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Linux 3.6-rc3
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945 41#include "drm_crtc_helper.h"
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d4906093
ML		 83static bool
84intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
d4906093
ML		 87static bool
88intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
79e53945 91
a4fc5ed6
KP		 92static bool
93intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
5eb08b69 96static bool
f2b115e6 97intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
a4fc5ed6 100
a0c4da24
JB		 101static bool
102intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
103 int target, int refclk, intel_clock_t *match_clock,
104 intel_clock_t *best_clock);
105
021357ac
CW		 106static inline u32 /* units of 100MHz */
107intel_fdi_link_freq(struct drm_device *dev)
108{
8b99e68c
CW		 109 if (IS_GEN5(dev)) {
110 struct drm_i915_private *dev_priv = dev->dev_private;
111 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
112 } else
113 return 27;
021357ac
CW		 114}
115
e4b36699 116static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 117 .dot = { .min = 25000, .max = 350000 },
118 .vco = { .min = 930000, .max = 1400000 },
119 .n = { .min = 3, .max = 16 },
120 .m = { .min = 96, .max = 140 },
121 .m1 = { .min = 18, .max = 26 },
122 .m2 = { .min = 6, .max = 16 },
123 .p = { .min = 4, .max = 128 },
124 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 125 .p2 = { .dot_limit = 165000,
126 .p2_slow = 4, .p2_fast = 2 },
d4906093 127 .find_pll = intel_find_best_PLL,
e4b36699
KP		 128};
129
130static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 131 .dot = { .min = 25000, .max = 350000 },
132 .vco = { .min = 930000, .max = 1400000 },
133 .n = { .min = 3, .max = 16 },
134 .m = { .min = 96, .max = 140 },
135 .m1 = { .min = 18, .max = 26 },
136 .m2 = { .min = 6, .max = 16 },
137 .p = { .min = 4, .max = 128 },
138 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 139 .p2 = { .dot_limit = 165000,
140 .p2_slow = 14, .p2_fast = 7 },
d4906093 141 .find_pll = intel_find_best_PLL,
e4b36699 142};
273e27ca 143
e4b36699 144static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
149 .m1 = { .min = 10, .max = 22 },
150 .m2 = { .min = 5, .max = 9 },
151 .p = { .min = 5, .max = 80 },
152 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 153 .p2 = { .dot_limit = 200000,
154 .p2_slow = 10, .p2_fast = 5 },
d4906093 155 .find_pll = intel_find_best_PLL,
e4b36699
KP		 156};
157
158static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 159 .dot = { .min = 20000, .max = 400000 },
160 .vco = { .min = 1400000, .max = 2800000 },
161 .n = { .min = 1, .max = 6 },
162 .m = { .min = 70, .max = 120 },
163 .m1 = { .min = 10, .max = 22 },
164 .m2 = { .min = 5, .max = 9 },
165 .p = { .min = 7, .max = 98 },
166 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 167 .p2 = { .dot_limit = 112000,
168 .p2_slow = 14, .p2_fast = 7 },
d4906093 169 .find_pll = intel_find_best_PLL,
e4b36699
KP		 170};
171
273e27ca 172
e4b36699 173static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 174 .dot = { .min = 25000, .max = 270000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 17, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 10, .max = 30 },
181 .p1 = { .min = 1, .max = 3},
182 .p2 = { .dot_limit = 270000,
183 .p2_slow = 10,
184 .p2_fast = 10
044c7c41 185 },
d4906093 186 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 187};
188
189static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 190 .dot = { .min = 22000, .max = 400000 },
191 .vco = { .min = 1750000, .max = 3500000},
192 .n = { .min = 1, .max = 4 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 16, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 5, .max = 80 },
197 .p1 = { .min = 1, .max = 8},
198 .p2 = { .dot_limit = 165000,
199 .p2_slow = 10, .p2_fast = 5 },
d4906093 200 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 201};
202
203static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 204 .dot = { .min = 20000, .max = 115000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 28, .max = 112 },
211 .p1 = { .min = 2, .max = 8 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 14, .p2_fast = 14
044c7c41 214 },
d4906093 215 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 216};
217
218static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 219 .dot = { .min = 80000, .max = 224000 },
220 .vco = { .min = 1750000, .max = 3500000 },
221 .n = { .min = 1, .max = 3 },
222 .m = { .min = 104, .max = 138 },
223 .m1 = { .min = 17, .max = 23 },
224 .m2 = { .min = 5, .max = 11 },
225 .p = { .min = 14, .max = 42 },
226 .p1 = { .min = 2, .max = 6 },
227 .p2 = { .dot_limit = 0,
228 .p2_slow = 7, .p2_fast = 7
044c7c41 229 },
d4906093 230 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 231};
232
233static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 234 .dot = { .min = 161670, .max = 227000 },
235 .vco = { .min = 1750000, .max = 3500000},
236 .n = { .min = 1, .max = 2 },
237 .m = { .min = 97, .max = 108 },
238 .m1 = { .min = 0x10, .max = 0x12 },
239 .m2 = { .min = 0x05, .max = 0x06 },
240 .p = { .min = 10, .max = 20 },
241 .p1 = { .min = 1, .max = 2},
242 .p2 = { .dot_limit = 0,
273e27ca 243 .p2_slow = 10, .p2_fast = 10 },
0206e353 244 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 245};
246
f2b115e6 247static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 248 .dot = { .min = 20000, .max = 400000},
249 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 250 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 251 .n = { .min = 3, .max = 6 },
252 .m = { .min = 2, .max = 256 },
273e27ca 253 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 254 .m1 = { .min = 0, .max = 0 },
255 .m2 = { .min = 0, .max = 254 },
256 .p = { .min = 5, .max = 80 },
257 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 258 .p2 = { .dot_limit = 200000,
259 .p2_slow = 10, .p2_fast = 5 },
6115707b 260 .find_pll = intel_find_best_PLL,
e4b36699
KP		 261};
262
f2b115e6 263static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 264 .dot = { .min = 20000, .max = 400000 },
265 .vco = { .min = 1700000, .max = 3500000 },
266 .n = { .min = 3, .max = 6 },
267 .m = { .min = 2, .max = 256 },
268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 7, .max = 112 },
271 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 272 .p2 = { .dot_limit = 112000,
273 .p2_slow = 14, .p2_fast = 14 },
6115707b 274 .find_pll = intel_find_best_PLL,
e4b36699
KP		 275};
276
273e27ca
EA		 277/* Ironlake / Sandybridge
278 *
279 * We calculate clock using (register_value + 2) for N/M1/M2, so here
280 * the range value for them is (actual_value - 2).
281 */
b91ad0ec 282static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 5 },
286 .m = { .min = 79, .max = 127 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 10, .p2_fast = 5 },
4547668a 293 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 294};
295
b91ad0ec 296static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 297 .dot = { .min = 25000, .max = 350000 },
298 .vco = { .min = 1760000, .max = 3510000 },
299 .n = { .min = 1, .max = 3 },
300 .m = { .min = 79, .max = 118 },
301 .m1 = { .min = 12, .max = 22 },
302 .m2 = { .min = 5, .max = 9 },
303 .p = { .min = 28, .max = 112 },
304 .p1 = { .min = 2, .max = 8 },
305 .p2 = { .dot_limit = 225000,
306 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 307 .find_pll = intel_g4x_find_best_PLL,
308};
309
310static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 3 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 14, .max = 56 },
318 .p1 = { .min = 2, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 321 .find_pll = intel_g4x_find_best_PLL,
322};
323
273e27ca 324/* LVDS 100mhz refclk limits. */
b91ad0ec 325static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 326 .dot = { .min = 25000, .max = 350000 },
327 .vco = { .min = 1760000, .max = 3510000 },
328 .n = { .min = 1, .max = 2 },
329 .m = { .min = 79, .max = 126 },
330 .m1 = { .min = 12, .max = 22 },
331 .m2 = { .min = 5, .max = 9 },
332 .p = { .min = 28, .max = 112 },
0206e353 333 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 334 .p2 = { .dot_limit = 225000,
335 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 336 .find_pll = intel_g4x_find_best_PLL,
337};
338
339static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 126 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 42 },
0206e353 347 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 350 .find_pll = intel_g4x_find_best_PLL,
351};
352
353static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000},
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 81, .max = 90 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 10, .max = 20 },
361 .p1 = { .min = 1, .max = 2},
362 .p2 = { .dot_limit = 0,
273e27ca 363 .p2_slow = 10, .p2_fast = 10 },
0206e353 364 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 365};
366
a0c4da24
JB		 367static const intel_limit_t intel_limits_vlv_dac = {
368 .dot = { .min = 25000, .max = 270000 },
369 .vco = { .min = 4000000, .max = 6000000 },
370 .n = { .min = 1, .max = 7 },
371 .m = { .min = 22, .max = 450 }, /* guess */
372 .m1 = { .min = 2, .max = 3 },
373 .m2 = { .min = 11, .max = 156 },
374 .p = { .min = 10, .max = 30 },
375 .p1 = { .min = 2, .max = 3 },
376 .p2 = { .dot_limit = 270000,
377 .p2_slow = 2, .p2_fast = 20 },
378 .find_pll = intel_vlv_find_best_pll,
379};
380
381static const intel_limit_t intel_limits_vlv_hdmi = {
382 .dot = { .min = 20000, .max = 165000 },
383 .vco = { .min = 5994000, .max = 4000000 },
384 .n = { .min = 1, .max = 7 },
385 .m = { .min = 60, .max = 300 }, /* guess */
386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
388 .p = { .min = 10, .max = 30 },
389 .p1 = { .min = 2, .max = 3 },
390 .p2 = { .dot_limit = 270000,
391 .p2_slow = 2, .p2_fast = 20 },
392 .find_pll = intel_vlv_find_best_pll,
393};
394
395static const intel_limit_t intel_limits_vlv_dp = {
396 .dot = { .min = 162000, .max = 270000 },
397 .vco = { .min = 5994000, .max = 4000000 },
398 .n = { .min = 1, .max = 7 },
399 .m = { .min = 60, .max = 300 }, /* guess */
400 .m1 = { .min = 2, .max = 3 },
401 .m2 = { .min = 11, .max = 156 },
402 .p = { .min = 10, .max = 30 },
403 .p1 = { .min = 2, .max = 3 },
404 .p2 = { .dot_limit = 270000,
405 .p2_slow = 2, .p2_fast = 20 },
406 .find_pll = intel_vlv_find_best_pll,
407};
408
57f350b6
JB		 409u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
410{
411 unsigned long flags;
412 u32 val = 0;
413
414 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
415 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
416 DRM_ERROR("DPIO idle wait timed out\n");
417 goto out_unlock;
418 }
419
420 I915_WRITE(DPIO_REG, reg);
421 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
422 DPIO_BYTE);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO read wait timed out\n");
425 goto out_unlock;
426 }
427 val = I915_READ(DPIO_DATA);
428
429out_unlock:
430 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
431 return val;
432}
433
a0c4da24
JB		 434static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
435 u32 val)
436{
437 unsigned long flags;
438
439 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
440 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
441 DRM_ERROR("DPIO idle wait timed out\n");
442 goto out_unlock;
443 }
444
445 I915_WRITE(DPIO_DATA, val);
446 I915_WRITE(DPIO_REG, reg);
447 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
448 DPIO_BYTE);
449 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
450 DRM_ERROR("DPIO write wait timed out\n");
451
452out_unlock:
453 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
454}
455
57f350b6
JB		 456static void vlv_init_dpio(struct drm_device *dev)
457{
458 struct drm_i915_private *dev_priv = dev->dev_private;
459
460 /* Reset the DPIO config */
461 I915_WRITE(DPIO_CTL, 0);
462 POSTING_READ(DPIO_CTL);
463 I915_WRITE(DPIO_CTL, 1);
464 POSTING_READ(DPIO_CTL);
465}
466
618563e3
DV		 467static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
468{
469 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
470 return 1;
471}
472
473static const struct dmi_system_id intel_dual_link_lvds[] = {
474 {
475 .callback = intel_dual_link_lvds_callback,
476 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
477 .matches = {
478 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
479 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
480 },
481 },
482 { } /* terminating entry */
483};
484
b0354385
TI		 485static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
486 unsigned int reg)
487{
488 unsigned int val;
489
121d527a
TI		 490 /* use the module option value if specified */
491 if (i915_lvds_channel_mode > 0)
492 return i915_lvds_channel_mode == 2;
493
618563e3
DV		 494 if (dmi_check_system(intel_dual_link_lvds))
495 return true;
496
b0354385
TI		 497 if (dev_priv->lvds_val)
498 val = dev_priv->lvds_val;
499 else {
500 /* BIOS should set the proper LVDS register value at boot, but
501 * in reality, it doesn't set the value when the lid is closed;
502 * we need to check "the value to be set" in VBT when LVDS
503 * register is uninitialized.
504 */
505 val = I915_READ(reg);
14d94a3d 506 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
b0354385
TI		 507 val = dev_priv->bios_lvds_val;
508 dev_priv->lvds_val = val;
509 }
510 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
511}
512
1b894b59
CW		 513static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
514 int refclk)
2c07245f 515{
b91ad0ec
ZW		 516 struct drm_device *dev = crtc->dev;
517 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 518 const intel_limit_t *limit;
b91ad0ec
ZW		 519
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 521 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 522 /* LVDS dual channel */
1b894b59 523 if (refclk == 100000)
b91ad0ec
ZW		 524 limit = &intel_limits_ironlake_dual_lvds_100m;
525 else
526 limit = &intel_limits_ironlake_dual_lvds;
527 } else {
1b894b59 528 if (refclk == 100000)
b91ad0ec
ZW		 529 limit = &intel_limits_ironlake_single_lvds_100m;
530 else
531 limit = &intel_limits_ironlake_single_lvds;
532 }
533 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 534 HAS_eDP)
535 limit = &intel_limits_ironlake_display_port;
2c07245f 536 else
b91ad0ec 537 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 538
539 return limit;
540}
541
044c7c41
ML		 542static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
543{
544 struct drm_device *dev = crtc->dev;
545 struct drm_i915_private *dev_priv = dev->dev_private;
546 const intel_limit_t *limit;
547
548 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 549 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 550 /* LVDS with dual channel */
e4b36699 551 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 552 else
553 /* LVDS with dual channel */
e4b36699 554 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 555 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
556 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 557 limit = &intel_limits_g4x_hdmi;
044c7c41 558 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 559 limit = &intel_limits_g4x_sdvo;
0206e353 560 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 561 limit = &intel_limits_g4x_display_port;
044c7c41 562 } else /* The option is for other outputs */
e4b36699 563 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 564
565 return limit;
566}
567
1b894b59 568static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 569{
570 struct drm_device *dev = crtc->dev;
571 const intel_limit_t *limit;
572
bad720ff 573 if (HAS_PCH_SPLIT(dev))
1b894b59 574 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 575 else if (IS_G4X(dev)) {
044c7c41 576 limit = intel_g4x_limit(crtc);
f2b115e6 577 } else if (IS_PINEVIEW(dev)) {
2177832f 578 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 579 limit = &intel_limits_pineview_lvds;
2177832f 580 else
f2b115e6 581 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 582 } else if (IS_VALLEYVIEW(dev)) {
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
584 limit = &intel_limits_vlv_dac;
585 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
586 limit = &intel_limits_vlv_hdmi;
587 else
588 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 589 } else if (!IS_GEN2(dev)) {
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
591 limit = &intel_limits_i9xx_lvds;
592 else
593 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 594 } else {
595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 596 limit = &intel_limits_i8xx_lvds;
79e53945 597 else
e4b36699 598 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 599 }
600 return limit;
601}
602
f2b115e6
AJ		 603/* m1 is reserved as 0 in Pineview, n is a ring counter */
604static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 605{
2177832f
SL		 606 clock->m = clock->m2 + 2;
607 clock->p = clock->p1 * clock->p2;
608 clock->vco = refclk * clock->m / clock->n;
609 clock->dot = clock->vco / clock->p;
610}
611
612static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
613{
f2b115e6
AJ		 614 if (IS_PINEVIEW(dev)) {
615 pineview_clock(refclk, clock);
2177832f
SL		 616 return;
617 }
79e53945
JB		 618 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
619 clock->p = clock->p1 * clock->p2;
620 clock->vco = refclk * clock->m / (clock->n + 2);
621 clock->dot = clock->vco / clock->p;
622}
623
79e53945
JB		 624/**
625 * Returns whether any output on the specified pipe is of the specified type
626 */
4ef69c7a 627bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 628{
4ef69c7a 629 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 630 struct intel_encoder *encoder;
631
6c2b7c12
DV		 632 for_each_encoder_on_crtc(dev, crtc, encoder)
633 if (encoder->type == type)
4ef69c7a
CW		 634 return true;
635
636 return false;
79e53945
JB		 637}
638
7c04d1d9 639#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 640/**
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
643 */
644
1b894b59
CW		 645static bool intel_PLL_is_valid(struct drm_device *dev,
646 const intel_limit_t *limit,
647 const intel_clock_t *clock)
79e53945 648{
79e53945 649 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 650 INTELPllInvalid("p1 out of range\n");
79e53945 651 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 652 INTELPllInvalid("p out of range\n");
79e53945 653 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 654 INTELPllInvalid("m2 out of range\n");
79e53945 655 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 656 INTELPllInvalid("m1 out of range\n");
f2b115e6 657 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 658 INTELPllInvalid("m1 <= m2\n");
79e53945 659 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 660 INTELPllInvalid("m out of range\n");
79e53945 661 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 662 INTELPllInvalid("n out of range\n");
79e53945 663 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 664 INTELPllInvalid("vco out of range\n");
79e53945
JB		 665 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
666 * connector, etc., rather than just a single range.
667 */
668 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 669 INTELPllInvalid("dot out of range\n");
79e53945
JB		 670
671 return true;
672}
673
d4906093
ML		 674static bool
675intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
d4906093 678
79e53945
JB		 679{
680 struct drm_device *dev = crtc->dev;
681 struct drm_i915_private *dev_priv = dev->dev_private;
682 intel_clock_t clock;
79e53945
JB		 683 int err = target;
684
bc5e5718 685 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 686 (I915_READ(LVDS)) != 0) {
79e53945
JB		 687 /*
688 * For LVDS, if the panel is on, just rely on its current
689 * settings for dual-channel. We haven't figured out how to
690 * reliably set up different single/dual channel state, if we
691 * even can.
692 */
b0354385 693 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 694 clock.p2 = limit->p2.p2_fast;
695 else
696 clock.p2 = limit->p2.p2_slow;
697 } else {
698 if (target < limit->p2.dot_limit)
699 clock.p2 = limit->p2.p2_slow;
700 else
701 clock.p2 = limit->p2.p2_fast;
702 }
703
0206e353 704 memset(best_clock, 0, sizeof(*best_clock));
79e53945 705
42158660
ZY		 706 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
707 clock.m1++) {
708 for (clock.m2 = limit->m2.min;
709 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 710 /* m1 is always 0 in Pineview */
711 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 712 break;
713 for (clock.n = limit->n.min;
714 clock.n <= limit->n.max; clock.n++) {
715 for (clock.p1 = limit->p1.min;
716 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 717 int this_err;
718
2177832f 719 intel_clock(dev, refclk, &clock);
1b894b59
CW		 720 if (!intel_PLL_is_valid(dev, limit,
721 &clock))
79e53945 722 continue;
cec2f356
SP		 723 if (match_clock &&
724 clock.p != match_clock->p)
725 continue;
79e53945
JB		 726
727 this_err = abs(clock.dot - target);
728 if (this_err < err) {
729 *best_clock = clock;
730 err = this_err;
731 }
732 }
733 }
734 }
735 }
736
737 return (err != target);
738}
739
d4906093
ML		 740static bool
741intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 742 int target, int refclk, intel_clock_t *match_clock,
743 intel_clock_t *best_clock)
d4906093
ML		 744{
745 struct drm_device *dev = crtc->dev;
746 struct drm_i915_private *dev_priv = dev->dev_private;
747 intel_clock_t clock;
748 int max_n;
749 bool found;
6ba770dc
AJ		 750 /* approximately equals target * 0.00585 */
751 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 752 found = false;
753
754 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 755 int lvds_reg;
756
c619eed4 757 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 758 lvds_reg = PCH_LVDS;
759 else
760 lvds_reg = LVDS;
761 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 762 LVDS_CLKB_POWER_UP)
763 clock.p2 = limit->p2.p2_fast;
764 else
765 clock.p2 = limit->p2.p2_slow;
766 } else {
767 if (target < limit->p2.dot_limit)
768 clock.p2 = limit->p2.p2_slow;
769 else
770 clock.p2 = limit->p2.p2_fast;
771 }
772
773 memset(best_clock, 0, sizeof(*best_clock));
774 max_n = limit->n.max;
f77f13e2 775 /* based on hardware requirement, prefer smaller n to precision */
d4906093 776 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 777 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 778 for (clock.m1 = limit->m1.max;
779 clock.m1 >= limit->m1.min; clock.m1--) {
780 for (clock.m2 = limit->m2.max;
781 clock.m2 >= limit->m2.min; clock.m2--) {
782 for (clock.p1 = limit->p1.max;
783 clock.p1 >= limit->p1.min; clock.p1--) {
784 int this_err;
785
2177832f 786 intel_clock(dev, refclk, &clock);
1b894b59
CW		 787 if (!intel_PLL_is_valid(dev, limit,
788 &clock))
d4906093 789 continue;
cec2f356
SP		 790 if (match_clock &&
791 clock.p != match_clock->p)
792 continue;
1b894b59
CW		 793
794 this_err = abs(clock.dot - target);
d4906093
ML		 795 if (this_err < err_most) {
796 *best_clock = clock;
797 err_most = this_err;
798 max_n = clock.n;
799 found = true;
800 }
801 }
802 }
803 }
804 }
2c07245f
ZW		 805 return found;
806}
807
5eb08b69 808static bool
f2b115e6 809intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
5eb08b69
ZW		 812{
813 struct drm_device *dev = crtc->dev;
814 intel_clock_t clock;
4547668a 815
5eb08b69
ZW		 816 if (target < 200000) {
817 clock.n = 1;
818 clock.p1 = 2;
819 clock.p2 = 10;
820 clock.m1 = 12;
821 clock.m2 = 9;
822 } else {
823 clock.n = 2;
824 clock.p1 = 1;
825 clock.p2 = 10;
826 clock.m1 = 14;
827 clock.m2 = 8;
828 }
829 intel_clock(dev, refclk, &clock);
830 memcpy(best_clock, &clock, sizeof(intel_clock_t));
831 return true;
832}
833
a4fc5ed6
KP		 834/* DisplayPort has only two frequencies, 162MHz and 270MHz */
835static bool
836intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
a4fc5ed6 839{
5eddb70b
CW		 840 intel_clock_t clock;
841 if (target < 200000) {
842 clock.p1 = 2;
843 clock.p2 = 10;
844 clock.n = 2;
845 clock.m1 = 23;
846 clock.m2 = 8;
847 } else {
848 clock.p1 = 1;
849 clock.p2 = 10;
850 clock.n = 1;
851 clock.m1 = 14;
852 clock.m2 = 2;
853 }
854 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
855 clock.p = (clock.p1 * clock.p2);
856 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
857 clock.vco = 0;
858 memcpy(best_clock, &clock, sizeof(intel_clock_t));
859 return true;
a4fc5ed6 860}
a0c4da24
JB		 861static bool
862intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
865{
866 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
867 u32 m, n, fastclk;
868 u32 updrate, minupdate, fracbits, p;
869 unsigned long bestppm, ppm, absppm;
870 int dotclk, flag;
871
af447bd3 872 flag = 0;
a0c4da24
JB		 873 dotclk = target * 1000;
874 bestppm = 1000000;
875 ppm = absppm = 0;
876 fastclk = dotclk / (2*100);
877 updrate = 0;
878 minupdate = 19200;
879 fracbits = 1;
880 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
881 bestm1 = bestm2 = bestp1 = bestp2 = 0;
882
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
885 updrate = refclk / n;
886 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
887 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
888 if (p2 > 10)
889 p2 = p2 - 1;
890 p = p1 * p2;
891 /* based on hardware requirement, prefer bigger m1,m2 values */
892 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
893 m2 = (((2*(fastclk * p * n / m1 )) +
894 refclk) / (2*refclk));
895 m = m1 * m2;
896 vco = updrate * m;
897 if (vco >= limit->vco.min && vco < limit->vco.max) {
898 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
899 absppm = (ppm > 0) ? ppm : (-ppm);
900 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
901 bestppm = 0;
902 flag = 1;
903 }
904 if (absppm < bestppm - 10) {
905 bestppm = absppm;
906 flag = 1;
907 }
908 if (flag) {
909 bestn = n;
910 bestm1 = m1;
911 bestm2 = m2;
912 bestp1 = p1;
913 bestp2 = p2;
914 flag = 0;
915 }
916 }
917 }
918 }
919 }
920 }
921 best_clock->n = bestn;
922 best_clock->m1 = bestm1;
923 best_clock->m2 = bestm2;
924 best_clock->p1 = bestp1;
925 best_clock->p2 = bestp2;
926
927 return true;
928}
a4fc5ed6 929
a928d536
PZ		 930static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
931{
932 struct drm_i915_private *dev_priv = dev->dev_private;
933 u32 frame, frame_reg = PIPEFRAME(pipe);
934
935 frame = I915_READ(frame_reg);
936
937 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
938 DRM_DEBUG_KMS("vblank wait timed out\n");
939}
940
9d0498a2
JB		 941/**
942 * intel_wait_for_vblank - wait for vblank on a given pipe
943 * @dev: drm device
944 * @pipe: pipe to wait for
945 *
946 * Wait for vblank to occur on a given pipe. Needed for various bits of
947 * mode setting code.
948 */
949void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 950{
9d0498a2 951 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 952 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 953
a928d536
PZ		 954 if (INTEL_INFO(dev)->gen >= 5) {
955 ironlake_wait_for_vblank(dev, pipe);
956 return;
957 }
958
300387c0
CW		 959 /* Clear existing vblank status. Note this will clear any other
960 * sticky status fields as well.
961 *
962 * This races with i915_driver_irq_handler() with the result
963 * that either function could miss a vblank event. Here it is not
964 * fatal, as we will either wait upon the next vblank interrupt or
965 * timeout. Generally speaking intel_wait_for_vblank() is only
966 * called during modeset at which time the GPU should be idle and
967 * should *not* be performing page flips and thus not waiting on
968 * vblanks...
969 * Currently, the result of us stealing a vblank from the irq
970 * handler is that a single frame will be skipped during swapbuffers.
971 */
972 I915_WRITE(pipestat_reg,
973 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
974
9d0498a2 975 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 976 if (wait_for(I915_READ(pipestat_reg) &
977 PIPE_VBLANK_INTERRUPT_STATUS,
978 50))
9d0498a2
JB		 979 DRM_DEBUG_KMS("vblank wait timed out\n");
980}
981
ab7ad7f6
KP		 982/*
983 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 984 * @dev: drm device
985 * @pipe: pipe to wait for
986 *
987 * After disabling a pipe, we can't wait for vblank in the usual way,
988 * spinning on the vblank interrupt status bit, since we won't actually
989 * see an interrupt when the pipe is disabled.
990 *
ab7ad7f6
KP		 991 * On Gen4 and above:
992 * wait for the pipe register state bit to turn off
993 *
994 * Otherwise:
995 * wait for the display line value to settle (it usually
996 * ends up stopping at the start of the next frame).
58e10eb9 997 *
9d0498a2 998 */
58e10eb9 999void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 1000{
1001 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 1002
1003 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 1004 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 1005
1006 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1007 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1008 100))
ab7ad7f6
KP		 1009 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1010 } else {
837ba00f 1011 u32 last_line, line_mask;
58e10eb9 1012 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 1013 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1014
837ba00f
PZ		 1015 if (IS_GEN2(dev))
1016 line_mask = DSL_LINEMASK_GEN2;
1017 else
1018 line_mask = DSL_LINEMASK_GEN3;
1019
ab7ad7f6
KP		 1020 /* Wait for the display line to settle */
1021 do {
837ba00f 1022 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 1023 mdelay(5);
837ba00f 1024 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 1025 time_after(timeout, jiffies));
1026 if (time_after(jiffies, timeout))
1027 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1028 }
79e53945
JB		 1029}
1030
b24e7179
JB		 1031static const char *state_string(bool enabled)
1032{
1033 return enabled ? "on" : "off";
1034}
1035
1036/* Only for pre-ILK configs */
1037static void assert_pll(struct drm_i915_private *dev_priv,
1038 enum pipe pipe, bool state)
1039{
1040 int reg;
1041 u32 val;
1042 bool cur_state;
1043
1044 reg = DPLL(pipe);
1045 val = I915_READ(reg);
1046 cur_state = !!(val & DPLL_VCO_ENABLE);
1047 WARN(cur_state != state,
1048 "PLL state assertion failure (expected %s, current %s)\n",
1049 state_string(state), state_string(cur_state));
1050}
1051#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1053
040484af
JB		 1054/* For ILK+ */
1055static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1056 struct intel_pch_pll *pll,
1057 struct intel_crtc *crtc,
1058 bool state)
040484af 1059{
040484af
JB		 1060 u32 val;
1061 bool cur_state;
1062
9d82aa17
ED		 1063 if (HAS_PCH_LPT(dev_priv->dev)) {
1064 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1065 return;
1066 }
1067
92b27b08
CW		 1068 if (WARN (!pll,
1069 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1070 return;
ee7b9f93 1071
92b27b08
CW		 1072 val = I915_READ(pll->pll_reg);
1073 cur_state = !!(val & DPLL_VCO_ENABLE);
1074 WARN(cur_state != state,
1075 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076 pll->pll_reg, state_string(state), state_string(cur_state), val);
1077
1078 /* Make sure the selected PLL is correctly attached to the transcoder */
1079 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1080 u32 pch_dpll;
1081
1082 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1083 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085 "PLL[%d] not attached to this transcoder %d: %08x\n",
1086 cur_state, crtc->pipe, pch_dpll)) {
1087 cur_state = !!(val >> (4*crtc->pipe + 3));
1088 WARN(cur_state != state,
1089 "PLL[%d] not %s on this transcoder %d: %08x\n",
1090 pll->pll_reg == _PCH_DPLL_B,
1091 state_string(state),
1092 crtc->pipe,
1093 val);
1094 }
d3ccbe86 1095 }
040484af 1096}
92b27b08
CW		 1097#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1099
1100static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
1102{
1103 int reg;
1104 u32 val;
1105 bool cur_state;
1106
bf507ef7
ED		 1107 if (IS_HASWELL(dev_priv->dev)) {
1108 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109 reg = DDI_FUNC_CTL(pipe);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1112 } else {
1113 reg = FDI_TX_CTL(pipe);
1114 val = I915_READ(reg);
1115 cur_state = !!(val & FDI_TX_ENABLE);
1116 }
040484af
JB		 1117 WARN(cur_state != state,
1118 "FDI TX state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1120}
1121#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123
1124static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125 enum pipe pipe, bool state)
1126{
1127 int reg;
1128 u32 val;
1129 bool cur_state;
1130
59c859d6
ED		 1131 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1133 return;
1134 } else {
1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
1138 }
040484af
JB		 1139 WARN(cur_state != state,
1140 "FDI RX state assertion failure (expected %s, current %s)\n",
1141 state_string(state), state_string(cur_state));
1142}
1143#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147 enum pipe pipe)
1148{
1149 int reg;
1150 u32 val;
1151
1152 /* ILK FDI PLL is always enabled */
1153 if (dev_priv->info->gen == 5)
1154 return;
1155
bf507ef7
ED		 1156 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157 if (IS_HASWELL(dev_priv->dev))
1158 return;
1159
040484af
JB		 1160 reg = FDI_TX_CTL(pipe);
1161 val = I915_READ(reg);
1162 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163}
1164
1165static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166 enum pipe pipe)
1167{
1168 int reg;
1169 u32 val;
1170
59c859d6
ED		 1171 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1173 return;
1174 }
040484af
JB		 1175 reg = FDI_RX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1178}
1179
ea0760cf
JB		 1180static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1181 enum pipe pipe)
1182{
1183 int pp_reg, lvds_reg;
1184 u32 val;
1185 enum pipe panel_pipe = PIPE_A;
0de3b485 1186 bool locked = true;
ea0760cf
JB		 1187
1188 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189 pp_reg = PCH_PP_CONTROL;
1190 lvds_reg = PCH_LVDS;
1191 } else {
1192 pp_reg = PP_CONTROL;
1193 lvds_reg = LVDS;
1194 }
1195
1196 val = I915_READ(pp_reg);
1197 if (!(val & PANEL_POWER_ON) ||
1198 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1199 locked = false;
1200
1201 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202 panel_pipe = PIPE_B;
1203
1204 WARN(panel_pipe == pipe && locked,
1205 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1206 pipe_name(pipe));
ea0760cf
JB		 1207}
1208
b840d907
JB		 1209void assert_pipe(struct drm_i915_private *dev_priv,
1210 enum pipe pipe, bool state)
b24e7179
JB		 1211{
1212 int reg;
1213 u32 val;
63d7bbe9 1214 bool cur_state;
b24e7179 1215
8e636784
DV		 1216 /* if we need the pipe A quirk it must be always on */
1217 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218 state = true;
1219
b24e7179
JB		 1220 reg = PIPECONF(pipe);
1221 val = I915_READ(reg);
63d7bbe9
JB		 1222 cur_state = !!(val & PIPECONF_ENABLE);
1223 WARN(cur_state != state,
1224 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1225 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1226}
1227
931872fc
CW		 1228static void assert_plane(struct drm_i915_private *dev_priv,
1229 enum plane plane, bool state)
b24e7179
JB		 1230{
1231 int reg;
1232 u32 val;
931872fc 1233 bool cur_state;
b24e7179
JB		 1234
1235 reg = DSPCNTR(plane);
1236 val = I915_READ(reg);
931872fc
CW		 1237 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238 WARN(cur_state != state,
1239 "plane %c assertion failure (expected %s, current %s)\n",
1240 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1241}
1242
931872fc
CW		 1243#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245
b24e7179
JB		 1246static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247 enum pipe pipe)
1248{
1249 int reg, i;
1250 u32 val;
1251 int cur_pipe;
1252
19ec1358 1253 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1254 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255 reg = DSPCNTR(pipe);
1256 val = I915_READ(reg);
1257 WARN((val & DISPLAY_PLANE_ENABLE),
1258 "plane %c assertion failure, should be disabled but not\n",
1259 plane_name(pipe));
19ec1358 1260 return;
28c05794 1261 }
19ec1358 1262
b24e7179
JB		 1263 /* Need to check both planes against the pipe */
1264 for (i = 0; i < 2; i++) {
1265 reg = DSPCNTR(i);
1266 val = I915_READ(reg);
1267 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268 DISPPLANE_SEL_PIPE_SHIFT;
1269 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1270 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1272 }
1273}
1274
92f2584a
JB		 1275static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276{
1277 u32 val;
1278 bool enabled;
1279
9d82aa17
ED		 1280 if (HAS_PCH_LPT(dev_priv->dev)) {
1281 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282 return;
1283 }
1284
92f2584a
JB		 1285 val = I915_READ(PCH_DREF_CONTROL);
1286 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287 DREF_SUPERSPREAD_SOURCE_MASK));
1288 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289}
1290
1291static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293{
1294 int reg;
1295 u32 val;
1296 bool enabled;
1297
1298 reg = TRANSCONF(pipe);
1299 val = I915_READ(reg);
1300 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1301 WARN(enabled,
1302 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303 pipe_name(pipe));
92f2584a
JB		 1304}
1305
4e634389
KP		 1306static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1308{
1309 if ((val & DP_PORT_EN) == 0)
1310 return false;
1311
1312 if (HAS_PCH_CPT(dev_priv->dev)) {
1313 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316 return false;
1317 } else {
1318 if ((val & DP_PIPE_MASK) != (pipe << 30))
1319 return false;
1320 }
1321 return true;
1322}
1323
1519b995
KP		 1324static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325 enum pipe pipe, u32 val)
1326{
1327 if ((val & PORT_ENABLE) == 0)
1328 return false;
1329
1330 if (HAS_PCH_CPT(dev_priv->dev)) {
1331 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332 return false;
1333 } else {
1334 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335 return false;
1336 }
1337 return true;
1338}
1339
1340static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1342{
1343 if ((val & LVDS_PORT_EN) == 0)
1344 return false;
1345
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
1347 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348 return false;
1349 } else {
1350 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351 return false;
1352 }
1353 return true;
1354}
1355
1356static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1358{
1359 if ((val & ADPA_DAC_ENABLE) == 0)
1360 return false;
1361 if (HAS_PCH_CPT(dev_priv->dev)) {
1362 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363 return false;
1364 } else {
1365 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366 return false;
1367 }
1368 return true;
1369}
1370
291906f1 1371static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1372 enum pipe pipe, int reg, u32 port_sel)
291906f1 1373{
47a05eca 1374 u32 val = I915_READ(reg);
4e634389 1375 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1377 reg, pipe_name(pipe));
de9a35ab
DV		 1378
1379 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1380 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1381}
1382
1383static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1384 enum pipe pipe, int reg)
1385{
47a05eca 1386 u32 val = I915_READ(reg);
1519b995 1387 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
23c99e77 1388 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1389 reg, pipe_name(pipe));
de9a35ab
DV		 1390
1391 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1392 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1393}
1394
1395static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1396 enum pipe pipe)
1397{
1398 int reg;
1399 u32 val;
291906f1 1400
f0575e92
KP		 1401 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1402 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1403 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1404
1405 reg = PCH_ADPA;
1406 val = I915_READ(reg);
1519b995 1407 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
291906f1 1408 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1409 pipe_name(pipe));
291906f1
JB		 1410
1411 reg = PCH_LVDS;
1412 val = I915_READ(reg);
1519b995 1413 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
291906f1 1414 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1415 pipe_name(pipe));
291906f1
JB		 1416
1417 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1418 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1419 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1420}
1421
63d7bbe9
JB		 1422/**
1423 * intel_enable_pll - enable a PLL
1424 * @dev_priv: i915 private structure
1425 * @pipe: pipe PLL to enable
1426 *
1427 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1428 * make sure the PLL reg is writable first though, since the panel write
1429 * protect mechanism may be enabled.
1430 *
1431 * Note! This is for pre-ILK only.
1432 */
1433static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1434{
1435 int reg;
1436 u32 val;
1437
1438 /* No really, not for ILK+ */
a0c4da24 1439 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1440
1441 /* PLL is protected by panel, make sure we can write it */
1442 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1443 assert_panel_unlocked(dev_priv, pipe);
1444
1445 reg = DPLL(pipe);
1446 val = I915_READ(reg);
1447 val |= DPLL_VCO_ENABLE;
1448
1449 /* We do this three times for luck */
1450 I915_WRITE(reg, val);
1451 POSTING_READ(reg);
1452 udelay(150); /* wait for warmup */
1453 I915_WRITE(reg, val);
1454 POSTING_READ(reg);
1455 udelay(150); /* wait for warmup */
1456 I915_WRITE(reg, val);
1457 POSTING_READ(reg);
1458 udelay(150); /* wait for warmup */
1459}
1460
1461/**
1462 * intel_disable_pll - disable a PLL
1463 * @dev_priv: i915 private structure
1464 * @pipe: pipe PLL to disable
1465 *
1466 * Disable the PLL for @pipe, making sure the pipe is off first.
1467 *
1468 * Note! This is for pre-ILK only.
1469 */
1470static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1471{
1472 int reg;
1473 u32 val;
1474
1475 /* Don't disable pipe A or pipe A PLLs if needed */
1476 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1477 return;
1478
1479 /* Make sure the pipe isn't still relying on us */
1480 assert_pipe_disabled(dev_priv, pipe);
1481
1482 reg = DPLL(pipe);
1483 val = I915_READ(reg);
1484 val &= ~DPLL_VCO_ENABLE;
1485 I915_WRITE(reg, val);
1486 POSTING_READ(reg);
1487}
1488
a416edef
ED		 1489/* SBI access */
1490static void
1491intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1492{
1493 unsigned long flags;
1494
1495 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1496 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1497 100)) {
1498 DRM_ERROR("timeout waiting for SBI to become ready\n");
1499 goto out_unlock;
1500 }
1501
1502 I915_WRITE(SBI_ADDR,
1503 (reg << 16));
1504 I915_WRITE(SBI_DATA,
1505 value);
1506 I915_WRITE(SBI_CTL_STAT,
1507 SBI_BUSY |
1508 SBI_CTL_OP_CRWR);
1509
39fb50f6 1510 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1511 100)) {
1512 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1513 goto out_unlock;
1514 }
1515
1516out_unlock:
1517 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1518}
1519
1520static u32
1521intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1522{
1523 unsigned long flags;
39fb50f6 1524 u32 value = 0;
a416edef
ED		 1525
1526 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1527 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1528 100)) {
1529 DRM_ERROR("timeout waiting for SBI to become ready\n");
1530 goto out_unlock;
1531 }
1532
1533 I915_WRITE(SBI_ADDR,
1534 (reg << 16));
1535 I915_WRITE(SBI_CTL_STAT,
1536 SBI_BUSY |
1537 SBI_CTL_OP_CRRD);
1538
39fb50f6 1539 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1540 100)) {
1541 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1542 goto out_unlock;
1543 }
1544
1545 value = I915_READ(SBI_DATA);
1546
1547out_unlock:
1548 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1549 return value;
1550}
1551
92f2584a
JB		 1552/**
1553 * intel_enable_pch_pll - enable PCH PLL
1554 * @dev_priv: i915 private structure
1555 * @pipe: pipe PLL to enable
1556 *
1557 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1558 * drives the transcoder clock.
1559 */
ee7b9f93 1560static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1561{
ee7b9f93 1562 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1563 struct intel_pch_pll *pll;
92f2584a
JB		 1564 int reg;
1565 u32 val;
1566
48da64a8 1567 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1568 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1569 pll = intel_crtc->pch_pll;
1570 if (pll == NULL)
1571 return;
1572
1573 if (WARN_ON(pll->refcount == 0))
1574 return;
ee7b9f93
JB		 1575
1576 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1577 pll->pll_reg, pll->active, pll->on,
1578 intel_crtc->base.base.id);
92f2584a
JB		 1579
1580 /* PCH refclock must be enabled first */
1581 assert_pch_refclk_enabled(dev_priv);
1582
ee7b9f93 1583 if (pll->active++ && pll->on) {
92b27b08 1584 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1585 return;
1586 }
1587
1588 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1589
1590 reg = pll->pll_reg;
92f2584a
JB		 1591 val = I915_READ(reg);
1592 val |= DPLL_VCO_ENABLE;
1593 I915_WRITE(reg, val);
1594 POSTING_READ(reg);
1595 udelay(200);
ee7b9f93
JB		 1596
1597 pll->on = true;
92f2584a
JB		 1598}
1599
ee7b9f93 1600static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1601{
ee7b9f93
JB		 1602 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1603 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1604 int reg;
ee7b9f93 1605 u32 val;
4c609cb8 1606
92f2584a
JB		 1607 /* PCH only available on ILK+ */
1608 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1609 if (pll == NULL)
1610 return;
92f2584a 1611
48da64a8
CW		 1612 if (WARN_ON(pll->refcount == 0))
1613 return;
7a419866 1614
ee7b9f93
JB		 1615 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1616 pll->pll_reg, pll->active, pll->on,
1617 intel_crtc->base.base.id);
7a419866 1618
48da64a8 1619 if (WARN_ON(pll->active == 0)) {
92b27b08 1620 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1621 return;
1622 }
1623
ee7b9f93 1624 if (--pll->active) {
92b27b08 1625 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1626 return;
ee7b9f93
JB		 1627 }
1628
1629 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1630
1631 /* Make sure transcoder isn't still depending on us */
1632 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1633
ee7b9f93 1634 reg = pll->pll_reg;
92f2584a
JB		 1635 val = I915_READ(reg);
1636 val &= ~DPLL_VCO_ENABLE;
1637 I915_WRITE(reg, val);
1638 POSTING_READ(reg);
1639 udelay(200);
ee7b9f93
JB		 1640
1641 pll->on = false;
92f2584a
JB		 1642}
1643
040484af
JB		 1644static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1645 enum pipe pipe)
1646{
1647 int reg;
5f7f726d 1648 u32 val, pipeconf_val;
7c26e5c6 1649 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1650
1651 /* PCH only available on ILK+ */
1652 BUG_ON(dev_priv->info->gen < 5);
1653
1654 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1655 assert_pch_pll_enabled(dev_priv,
1656 to_intel_crtc(crtc)->pch_pll,
1657 to_intel_crtc(crtc));
040484af
JB		 1658
1659 /* FDI must be feeding us bits for PCH ports */
1660 assert_fdi_tx_enabled(dev_priv, pipe);
1661 assert_fdi_rx_enabled(dev_priv, pipe);
1662
59c859d6
ED		 1663 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1664 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1665 return;
1666 }
040484af
JB		 1667 reg = TRANSCONF(pipe);
1668 val = I915_READ(reg);
5f7f726d 1669 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1670
1671 if (HAS_PCH_IBX(dev_priv->dev)) {
1672 /*
1673 * make the BPC in transcoder be consistent with
1674 * that in pipeconf reg.
1675 */
1676 val &= ~PIPE_BPC_MASK;
5f7f726d 1677 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1678 }
5f7f726d
PZ		 1679
1680 val &= ~TRANS_INTERLACE_MASK;
1681 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1682 if (HAS_PCH_IBX(dev_priv->dev) &&
1683 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1684 val |= TRANS_LEGACY_INTERLACED_ILK;
1685 else
1686 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1687 else
1688 val |= TRANS_PROGRESSIVE;
1689
040484af
JB		 1690 I915_WRITE(reg, val | TRANS_ENABLE);
1691 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1692 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1693}
1694
1695static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1696 enum pipe pipe)
1697{
1698 int reg;
1699 u32 val;
1700
1701 /* FDI relies on the transcoder */
1702 assert_fdi_tx_disabled(dev_priv, pipe);
1703 assert_fdi_rx_disabled(dev_priv, pipe);
1704
291906f1
JB		 1705 /* Ports must be off as well */
1706 assert_pch_ports_disabled(dev_priv, pipe);
1707
040484af
JB		 1708 reg = TRANSCONF(pipe);
1709 val = I915_READ(reg);
1710 val &= ~TRANS_ENABLE;
1711 I915_WRITE(reg, val);
1712 /* wait for PCH transcoder off, transcoder state */
1713 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1714 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1715}
1716
b24e7179 1717/**
309cfea8 1718 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1719 * @dev_priv: i915 private structure
1720 * @pipe: pipe to enable
040484af 1721 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1722 *
1723 * Enable @pipe, making sure that various hardware specific requirements
1724 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1725 *
1726 * @pipe should be %PIPE_A or %PIPE_B.
1727 *
1728 * Will wait until the pipe is actually running (i.e. first vblank) before
1729 * returning.
1730 */
040484af
JB		 1731static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1732 bool pch_port)
b24e7179
JB		 1733{
1734 int reg;
1735 u32 val;
1736
1737 /*
1738 * A pipe without a PLL won't actually be able to drive bits from
1739 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1740 * need the check.
1741 */
1742 if (!HAS_PCH_SPLIT(dev_priv->dev))
1743 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1744 else {
1745 if (pch_port) {
1746 /* if driving the PCH, we need FDI enabled */
1747 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1748 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1749 }
1750 /* FIXME: assert CPU port conditions for SNB+ */
1751 }
b24e7179
JB		 1752
1753 reg = PIPECONF(pipe);
1754 val = I915_READ(reg);
00d70b15
CW		 1755 if (val & PIPECONF_ENABLE)
1756 return;
1757
1758 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1759 intel_wait_for_vblank(dev_priv->dev, pipe);
1760}
1761
1762/**
309cfea8 1763 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1764 * @dev_priv: i915 private structure
1765 * @pipe: pipe to disable
1766 *
1767 * Disable @pipe, making sure that various hardware specific requirements
1768 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1769 *
1770 * @pipe should be %PIPE_A or %PIPE_B.
1771 *
1772 * Will wait until the pipe has shut down before returning.
1773 */
1774static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1775 enum pipe pipe)
1776{
1777 int reg;
1778 u32 val;
1779
1780 /*
1781 * Make sure planes won't keep trying to pump pixels to us,
1782 * or we might hang the display.
1783 */
1784 assert_planes_disabled(dev_priv, pipe);
1785
1786 /* Don't disable pipe A or pipe A PLLs if needed */
1787 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1788 return;
1789
1790 reg = PIPECONF(pipe);
1791 val = I915_READ(reg);
00d70b15
CW		 1792 if ((val & PIPECONF_ENABLE) == 0)
1793 return;
1794
1795 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1796 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1797}
1798
d74362c9
KP		 1799/*
1800 * Plane regs are double buffered, going from enabled->disabled needs a
1801 * trigger in order to latch. The display address reg provides this.
1802 */
6f1d69b0 1803void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1804 enum plane plane)
1805{
1806 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1807 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1808}
1809
b24e7179
JB		 1810/**
1811 * intel_enable_plane - enable a display plane on a given pipe
1812 * @dev_priv: i915 private structure
1813 * @plane: plane to enable
1814 * @pipe: pipe being fed
1815 *
1816 * Enable @plane on @pipe, making sure that @pipe is running first.
1817 */
1818static void intel_enable_plane(struct drm_i915_private *dev_priv,
1819 enum plane plane, enum pipe pipe)
1820{
1821 int reg;
1822 u32 val;
1823
1824 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1825 assert_pipe_enabled(dev_priv, pipe);
1826
1827 reg = DSPCNTR(plane);
1828 val = I915_READ(reg);
00d70b15
CW		 1829 if (val & DISPLAY_PLANE_ENABLE)
1830 return;
1831
1832 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1833 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1834 intel_wait_for_vblank(dev_priv->dev, pipe);
1835}
1836
b24e7179
JB		 1837/**
1838 * intel_disable_plane - disable a display plane
1839 * @dev_priv: i915 private structure
1840 * @plane: plane to disable
1841 * @pipe: pipe consuming the data
1842 *
1843 * Disable @plane; should be an independent operation.
1844 */
1845static void intel_disable_plane(struct drm_i915_private *dev_priv,
1846 enum plane plane, enum pipe pipe)
1847{
1848 int reg;
1849 u32 val;
1850
1851 reg = DSPCNTR(plane);
1852 val = I915_READ(reg);
00d70b15
CW		 1853 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1854 return;
1855
1856 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1857 intel_flush_display_plane(dev_priv, plane);
1858 intel_wait_for_vblank(dev_priv->dev, pipe);
1859}
1860
47a05eca 1861static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1862 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1863{
1864 u32 val = I915_READ(reg);
4e634389 1865 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
f0575e92 1866 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1867 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1868 }
47a05eca
JB		 1869}
1870
1871static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1872 enum pipe pipe, int reg)
1873{
1874 u32 val = I915_READ(reg);
1519b995 1875 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
f0575e92
KP		 1876 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1877 reg, pipe);
47a05eca 1878 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1879 }
47a05eca
JB		 1880}
1881
1882/* Disable any ports connected to this transcoder */
1883static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1884 enum pipe pipe)
1885{
1886 u32 reg, val;
1887
1888 val = I915_READ(PCH_PP_CONTROL);
1889 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1890
f0575e92
KP		 1891 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1892 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1893 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1894
1895 reg = PCH_ADPA;
1896 val = I915_READ(reg);
1519b995 1897 if (adpa_pipe_enabled(dev_priv, val, pipe))
47a05eca
JB		 1898 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1899
1900 reg = PCH_LVDS;
1901 val = I915_READ(reg);
1519b995
KP		 1902 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1903 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
47a05eca
JB		 1904 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1905 POSTING_READ(reg);
1906 udelay(100);
1907 }
1908
1909 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1910 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1911 disable_pch_hdmi(dev_priv, pipe, HDMID);
1912}
1913
127bd2ac 1914int
48b956c5 1915intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1916 struct drm_i915_gem_object *obj,
919926ae 1917 struct intel_ring_buffer *pipelined)
6b95a207 1918{
ce453d81 1919 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1920 u32 alignment;
1921 int ret;
1922
05394f39 1923 switch (obj->tiling_mode) {
6b95a207 1924 case I915_TILING_NONE:
534843da
CW		 1925 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1926 alignment = 128 * 1024;
a6c45cf0 1927 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1928 alignment = 4 * 1024;
1929 else
1930 alignment = 64 * 1024;
6b95a207
KH		 1931 break;
1932 case I915_TILING_X:
1933 /* pin() will align the object as required by fence */
1934 alignment = 0;
1935 break;
1936 case I915_TILING_Y:
1937 /* FIXME: Is this true? */
1938 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1939 return -EINVAL;
1940 default:
1941 BUG();
1942 }
1943
ce453d81 1944 dev_priv->mm.interruptible = false;
2da3b9b9 1945 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1946 if (ret)
ce453d81 1947 goto err_interruptible;
6b95a207
KH		 1948
1949 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1950 * fence, whereas 965+ only requires a fence if using
1951 * framebuffer compression. For simplicity, we always install
1952 * a fence as the cost is not that onerous.
1953 */
06d98131 1954 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1955 if (ret)
1956 goto err_unpin;
1690e1eb 1957
9a5a53b3 1958 i915_gem_object_pin_fence(obj);
6b95a207 1959
ce453d81 1960 dev_priv->mm.interruptible = true;
6b95a207 1961 return 0;
48b956c5
CW		 1962
1963err_unpin:
1964 i915_gem_object_unpin(obj);
ce453d81
CW		 1965err_interruptible:
1966 dev_priv->mm.interruptible = true;
48b956c5 1967 return ret;
6b95a207
KH		 1968}
1969
1690e1eb
CW		 1970void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1971{
1972 i915_gem_object_unpin_fence(obj);
1973 i915_gem_object_unpin(obj);
1974}
1975
c2c75131
DV		 1976/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1977 * is assumed to be a power-of-two. */
1978static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1979 unsigned int bpp,
1980 unsigned int pitch)
1981{
1982 int tile_rows, tiles;
1983
1984 tile_rows = *y / 8;
1985 *y %= 8;
1986 tiles = *x / (512/bpp);
1987 *x %= 512/bpp;
1988
1989 return tile_rows * pitch * 8 + tiles * 4096;
1990}
1991
17638cd6
JB		 1992static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1993 int x, int y)
81255565
JB		 1994{
1995 struct drm_device *dev = crtc->dev;
1996 struct drm_i915_private *dev_priv = dev->dev_private;
1997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1998 struct intel_framebuffer *intel_fb;
05394f39 1999 struct drm_i915_gem_object *obj;
81255565 2000 int plane = intel_crtc->plane;
e506a0c6 2001 unsigned long linear_offset;
81255565 2002 u32 dspcntr;
5eddb70b 2003 u32 reg;
81255565
JB		 2004
2005 switch (plane) {
2006 case 0:
2007 case 1:
2008 break;
2009 default:
2010 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2011 return -EINVAL;
2012 }
2013
2014 intel_fb = to_intel_framebuffer(fb);
2015 obj = intel_fb->obj;
81255565 2016
5eddb70b
CW		 2017 reg = DSPCNTR(plane);
2018 dspcntr = I915_READ(reg);
81255565
JB		 2019 /* Mask out pixel format bits in case we change it */
2020 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2021 switch (fb->bits_per_pixel) {
2022 case 8:
2023 dspcntr |= DISPPLANE_8BPP;
2024 break;
2025 case 16:
2026 if (fb->depth == 15)
2027 dspcntr |= DISPPLANE_15_16BPP;
2028 else
2029 dspcntr |= DISPPLANE_16BPP;
2030 break;
2031 case 24:
2032 case 32:
2033 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2034 break;
2035 default:
17638cd6 2036 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 2037 return -EINVAL;
2038 }
a6c45cf0 2039 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2040 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2041 dspcntr |= DISPPLANE_TILED;
2042 else
2043 dspcntr &= ~DISPPLANE_TILED;
2044 }
2045
5eddb70b 2046 I915_WRITE(reg, dspcntr);
81255565 2047
e506a0c6 2048 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2049
c2c75131
DV		 2050 if (INTEL_INFO(dev)->gen >= 4) {
2051 intel_crtc->dspaddr_offset =
2052 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2053 fb->bits_per_pixel / 8,
2054 fb->pitches[0]);
2055 linear_offset -= intel_crtc->dspaddr_offset;
2056 } else {
e506a0c6 2057 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2058 }
e506a0c6
DV		 2059
2060 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2061 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2062 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2063 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2064 I915_MODIFY_DISPBASE(DSPSURF(plane),
2065 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2066 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2067 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2068 } else
e506a0c6 2069 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2070 POSTING_READ(reg);
81255565 2071
17638cd6
JB		 2072 return 0;
2073}
2074
2075static int ironlake_update_plane(struct drm_crtc *crtc,
2076 struct drm_framebuffer *fb, int x, int y)
2077{
2078 struct drm_device *dev = crtc->dev;
2079 struct drm_i915_private *dev_priv = dev->dev_private;
2080 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2081 struct intel_framebuffer *intel_fb;
2082 struct drm_i915_gem_object *obj;
2083 int plane = intel_crtc->plane;
e506a0c6 2084 unsigned long linear_offset;
17638cd6
JB		 2085 u32 dspcntr;
2086 u32 reg;
2087
2088 switch (plane) {
2089 case 0:
2090 case 1:
27f8227b 2091 case 2:
17638cd6
JB		 2092 break;
2093 default:
2094 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2095 return -EINVAL;
2096 }
2097
2098 intel_fb = to_intel_framebuffer(fb);
2099 obj = intel_fb->obj;
2100
2101 reg = DSPCNTR(plane);
2102 dspcntr = I915_READ(reg);
2103 /* Mask out pixel format bits in case we change it */
2104 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2105 switch (fb->bits_per_pixel) {
2106 case 8:
2107 dspcntr |= DISPPLANE_8BPP;
2108 break;
2109 case 16:
2110 if (fb->depth != 16)
2111 return -EINVAL;
2112
2113 dspcntr |= DISPPLANE_16BPP;
2114 break;
2115 case 24:
2116 case 32:
2117 if (fb->depth == 24)
2118 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2119 else if (fb->depth == 30)
2120 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2121 else
2122 return -EINVAL;
2123 break;
2124 default:
2125 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2126 return -EINVAL;
2127 }
2128
2129 if (obj->tiling_mode != I915_TILING_NONE)
2130 dspcntr |= DISPPLANE_TILED;
2131 else
2132 dspcntr &= ~DISPPLANE_TILED;
2133
2134 /* must disable */
2135 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2136
2137 I915_WRITE(reg, dspcntr);
2138
e506a0c6 2139 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131
DV		 2140 intel_crtc->dspaddr_offset =
2141 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2142 fb->bits_per_pixel / 8,
2143 fb->pitches[0]);
2144 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2145
e506a0c6
DV		 2146 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2147 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2148 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2149 I915_MODIFY_DISPBASE(DSPSURF(plane),
2150 obj->gtt_offset + intel_crtc->dspaddr_offset);
17638cd6 2151 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2152 I915_WRITE(DSPLINOFF(plane), linear_offset);
17638cd6
JB		 2153 POSTING_READ(reg);
2154
2155 return 0;
2156}
2157
2158/* Assume fb object is pinned & idle & fenced and just update base pointers */
2159static int
2160intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2161 int x, int y, enum mode_set_atomic state)
2162{
2163 struct drm_device *dev = crtc->dev;
2164 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2165
6b8e6ed0
CW		 2166 if (dev_priv->display.disable_fbc)
2167 dev_priv->display.disable_fbc(dev);
3dec0095 2168 intel_increase_pllclock(crtc);
81255565 2169
6b8e6ed0 2170 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2171}
2172
14667a4b
CW		 2173static int
2174intel_finish_fb(struct drm_framebuffer *old_fb)
2175{
2176 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2177 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2178 bool was_interruptible = dev_priv->mm.interruptible;
2179 int ret;
2180
2181 wait_event(dev_priv->pending_flip_queue,
2182 atomic_read(&dev_priv->mm.wedged) ||
2183 atomic_read(&obj->pending_flip) == 0);
2184
2185 /* Big Hammer, we also need to ensure that any pending
2186 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2187 * current scanout is retired before unpinning the old
2188 * framebuffer.
2189 *
2190 * This should only fail upon a hung GPU, in which case we
2191 * can safely continue.
2192 */
2193 dev_priv->mm.interruptible = false;
2194 ret = i915_gem_object_finish_gpu(obj);
2195 dev_priv->mm.interruptible = was_interruptible;
2196
2197 return ret;
2198}
2199
5c3b82e2 2200static int
3c4fdcfb
KH		 2201intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2202 struct drm_framebuffer *old_fb)
79e53945
JB		 2203{
2204 struct drm_device *dev = crtc->dev;
6b8e6ed0 2205 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 2206 struct drm_i915_master_private *master_priv;
2207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 2208 int ret;
79e53945
JB		 2209
2210 /* no fb bound */
2211 if (!crtc->fb) {
a5071c2f 2212 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2213 return 0;
2214 }
2215
5826eca5
ED		 2216 if(intel_crtc->plane > dev_priv->num_pipe) {
2217 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2218 intel_crtc->plane,
2219 dev_priv->num_pipe);
5c3b82e2 2220 return -EINVAL;
79e53945
JB		 2221 }
2222
5c3b82e2 2223 mutex_lock(&dev->struct_mutex);
265db958
CW		 2224 ret = intel_pin_and_fence_fb_obj(dev,
2225 to_intel_framebuffer(crtc->fb)->obj,
919926ae 2226 NULL);
5c3b82e2
CW		 2227 if (ret != 0) {
2228 mutex_unlock(&dev->struct_mutex);
a5071c2f 2229 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2230 return ret;
2231 }
79e53945 2232
14667a4b
CW		 2233 if (old_fb)
2234 intel_finish_fb(old_fb);
265db958 2235
6b8e6ed0 2236 ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
4e6cfefc 2237 if (ret) {
1690e1eb 2238 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2239 mutex_unlock(&dev->struct_mutex);
a5071c2f 2240 DRM_ERROR("failed to update base address\n");
4e6cfefc 2241 return ret;
79e53945 2242 }
3c4fdcfb 2243
b7f1de28
CW		 2244 if (old_fb) {
2245 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2246 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2247 }
652c393a 2248
6b8e6ed0 2249 intel_update_fbc(dev);
5c3b82e2 2250 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2251
2252 if (!dev->primary->master)
5c3b82e2 2253 return 0;
79e53945
JB		 2254
2255 master_priv = dev->primary->master->driver_priv;
2256 if (!master_priv->sarea_priv)
5c3b82e2 2257 return 0;
79e53945 2258
265db958 2259 if (intel_crtc->pipe) {
79e53945
JB		 2260 master_priv->sarea_priv->pipeB_x = x;
2261 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2262 } else {
2263 master_priv->sarea_priv->pipeA_x = x;
2264 master_priv->sarea_priv->pipeA_y = y;
79e53945 2265 }
5c3b82e2
CW		 2266
2267 return 0;
79e53945
JB		 2268}
2269
5eddb70b 2270static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2271{
2272 struct drm_device *dev = crtc->dev;
2273 struct drm_i915_private *dev_priv = dev->dev_private;
2274 u32 dpa_ctl;
2275
28c97730 2276 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2277 dpa_ctl = I915_READ(DP_A);
2278 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2279
2280 if (clock < 200000) {
2281 u32 temp;
2282 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2283 /* workaround for 160Mhz:
2284 1) program 0x4600c bits 15:0 = 0x8124
2285 2) program 0x46010 bit 0 = 1
2286 3) program 0x46034 bit 24 = 1
2287 4) program 0x64000 bit 14 = 1
2288 */
2289 temp = I915_READ(0x4600c);
2290 temp &= 0xffff0000;
2291 I915_WRITE(0x4600c, temp | 0x8124);
2292
2293 temp = I915_READ(0x46010);
2294 I915_WRITE(0x46010, temp | 1);
2295
2296 temp = I915_READ(0x46034);
2297 I915_WRITE(0x46034, temp | (1 << 24));
2298 } else {
2299 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2300 }
2301 I915_WRITE(DP_A, dpa_ctl);
2302
5eddb70b 2303 POSTING_READ(DP_A);
32f9d658
ZW		 2304 udelay(500);
2305}
2306
5e84e1a4
ZW		 2307static void intel_fdi_normal_train(struct drm_crtc *crtc)
2308{
2309 struct drm_device *dev = crtc->dev;
2310 struct drm_i915_private *dev_priv = dev->dev_private;
2311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2312 int pipe = intel_crtc->pipe;
2313 u32 reg, temp;
2314
2315 /* enable normal train */
2316 reg = FDI_TX_CTL(pipe);
2317 temp = I915_READ(reg);
61e499bf 2318 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2319 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2320 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2321 } else {
2322 temp &= ~FDI_LINK_TRAIN_NONE;
2323 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2324 }
5e84e1a4
ZW		 2325 I915_WRITE(reg, temp);
2326
2327 reg = FDI_RX_CTL(pipe);
2328 temp = I915_READ(reg);
2329 if (HAS_PCH_CPT(dev)) {
2330 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2331 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2332 } else {
2333 temp &= ~FDI_LINK_TRAIN_NONE;
2334 temp |= FDI_LINK_TRAIN_NONE;
2335 }
2336 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2337
2338 /* wait one idle pattern time */
2339 POSTING_READ(reg);
2340 udelay(1000);
357555c0
JB		 2341
2342 /* IVB wants error correction enabled */
2343 if (IS_IVYBRIDGE(dev))
2344 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2345 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2346}
2347
291427f5
JB		 2348static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2349{
2350 struct drm_i915_private *dev_priv = dev->dev_private;
2351 u32 flags = I915_READ(SOUTH_CHICKEN1);
2352
2353 flags |= FDI_PHASE_SYNC_OVR(pipe);
2354 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2355 flags |= FDI_PHASE_SYNC_EN(pipe);
2356 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2357 POSTING_READ(SOUTH_CHICKEN1);
2358}
2359
8db9d77b
ZW		 2360/* The FDI link training functions for ILK/Ibexpeak. */
2361static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2362{
2363 struct drm_device *dev = crtc->dev;
2364 struct drm_i915_private *dev_priv = dev->dev_private;
2365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2366 int pipe = intel_crtc->pipe;
0fc932b8 2367 int plane = intel_crtc->plane;
5eddb70b 2368 u32 reg, temp, tries;
8db9d77b 2369
0fc932b8
JB		 2370 /* FDI needs bits from pipe & plane first */
2371 assert_pipe_enabled(dev_priv, pipe);
2372 assert_plane_enabled(dev_priv, plane);
2373
e1a44743
AJ		 2374 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2375 for train result */
5eddb70b
CW		 2376 reg = FDI_RX_IMR(pipe);
2377 temp = I915_READ(reg);
e1a44743
AJ		 2378 temp &= ~FDI_RX_SYMBOL_LOCK;
2379 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2380 I915_WRITE(reg, temp);
2381 I915_READ(reg);
e1a44743
AJ		 2382 udelay(150);
2383
8db9d77b 2384 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2385 reg = FDI_TX_CTL(pipe);
2386 temp = I915_READ(reg);
77ffb597
AJ		 2387 temp &= ~(7 << 19);
2388 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2389 temp &= ~FDI_LINK_TRAIN_NONE;
2390 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2391 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2392
5eddb70b
CW		 2393 reg = FDI_RX_CTL(pipe);
2394 temp = I915_READ(reg);
8db9d77b
ZW		 2395 temp &= ~FDI_LINK_TRAIN_NONE;
2396 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2397 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2398
2399 POSTING_READ(reg);
8db9d77b
ZW		 2400 udelay(150);
2401
5b2adf89 2402 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2403 if (HAS_PCH_IBX(dev)) {
2404 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2405 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2406 FDI_RX_PHASE_SYNC_POINTER_EN);
2407 }
5b2adf89 2408
5eddb70b 2409 reg = FDI_RX_IIR(pipe);
e1a44743 2410 for (tries = 0; tries < 5; tries++) {
5eddb70b 2411 temp = I915_READ(reg);
8db9d77b
ZW		 2412 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2413
2414 if ((temp & FDI_RX_BIT_LOCK)) {
2415 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2416 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2417 break;
2418 }
8db9d77b 2419 }
e1a44743 2420 if (tries == 5)
5eddb70b 2421 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2422
2423 /* Train 2 */
5eddb70b
CW		 2424 reg = FDI_TX_CTL(pipe);
2425 temp = I915_READ(reg);
8db9d77b
ZW		 2426 temp &= ~FDI_LINK_TRAIN_NONE;
2427 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2428 I915_WRITE(reg, temp);
8db9d77b 2429
5eddb70b
CW		 2430 reg = FDI_RX_CTL(pipe);
2431 temp = I915_READ(reg);
8db9d77b
ZW		 2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2434 I915_WRITE(reg, temp);
8db9d77b 2435
5eddb70b
CW		 2436 POSTING_READ(reg);
2437 udelay(150);
8db9d77b 2438
5eddb70b 2439 reg = FDI_RX_IIR(pipe);
e1a44743 2440 for (tries = 0; tries < 5; tries++) {
5eddb70b 2441 temp = I915_READ(reg);
8db9d77b
ZW		 2442 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2443
2444 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2445 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2446 DRM_DEBUG_KMS("FDI train 2 done.\n");
2447 break;
2448 }
8db9d77b 2449 }
e1a44743 2450 if (tries == 5)
5eddb70b 2451 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2452
2453 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2454
8db9d77b
ZW		 2455}
2456
0206e353 2457static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2458 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2459 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2460 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2461 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2462};
2463
2464/* The FDI link training functions for SNB/Cougarpoint. */
2465static void gen6_fdi_link_train(struct drm_crtc *crtc)
2466{
2467 struct drm_device *dev = crtc->dev;
2468 struct drm_i915_private *dev_priv = dev->dev_private;
2469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2470 int pipe = intel_crtc->pipe;
fa37d39e 2471 u32 reg, temp, i, retry;
8db9d77b 2472
e1a44743
AJ		 2473 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2474 for train result */
5eddb70b
CW		 2475 reg = FDI_RX_IMR(pipe);
2476 temp = I915_READ(reg);
e1a44743
AJ		 2477 temp &= ~FDI_RX_SYMBOL_LOCK;
2478 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2479 I915_WRITE(reg, temp);
2480
2481 POSTING_READ(reg);
e1a44743
AJ		 2482 udelay(150);
2483
8db9d77b 2484 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2485 reg = FDI_TX_CTL(pipe);
2486 temp = I915_READ(reg);
77ffb597
AJ		 2487 temp &= ~(7 << 19);
2488 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2489 temp &= ~FDI_LINK_TRAIN_NONE;
2490 temp |= FDI_LINK_TRAIN_PATTERN_1;
2491 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2492 /* SNB-B */
2493 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2494 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2495
5eddb70b
CW		 2496 reg = FDI_RX_CTL(pipe);
2497 temp = I915_READ(reg);
8db9d77b
ZW		 2498 if (HAS_PCH_CPT(dev)) {
2499 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2500 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2501 } else {
2502 temp &= ~FDI_LINK_TRAIN_NONE;
2503 temp |= FDI_LINK_TRAIN_PATTERN_1;
2504 }
5eddb70b
CW		 2505 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2506
2507 POSTING_READ(reg);
8db9d77b
ZW		 2508 udelay(150);
2509
291427f5
JB		 2510 if (HAS_PCH_CPT(dev))
2511 cpt_phase_pointer_enable(dev, pipe);
2512
0206e353 2513 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2514 reg = FDI_TX_CTL(pipe);
2515 temp = I915_READ(reg);
8db9d77b
ZW		 2516 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2517 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2518 I915_WRITE(reg, temp);
2519
2520 POSTING_READ(reg);
8db9d77b
ZW		 2521 udelay(500);
2522
fa37d39e
SP		 2523 for (retry = 0; retry < 5; retry++) {
2524 reg = FDI_RX_IIR(pipe);
2525 temp = I915_READ(reg);
2526 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2527 if (temp & FDI_RX_BIT_LOCK) {
2528 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2529 DRM_DEBUG_KMS("FDI train 1 done.\n");
2530 break;
2531 }
2532 udelay(50);
8db9d77b 2533 }
fa37d39e
SP		 2534 if (retry < 5)
2535 break;
8db9d77b
ZW		 2536 }
2537 if (i == 4)
5eddb70b 2538 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2539
2540 /* Train 2 */
5eddb70b
CW		 2541 reg = FDI_TX_CTL(pipe);
2542 temp = I915_READ(reg);
8db9d77b
ZW		 2543 temp &= ~FDI_LINK_TRAIN_NONE;
2544 temp |= FDI_LINK_TRAIN_PATTERN_2;
2545 if (IS_GEN6(dev)) {
2546 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2547 /* SNB-B */
2548 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2549 }
5eddb70b 2550 I915_WRITE(reg, temp);
8db9d77b 2551
5eddb70b
CW		 2552 reg = FDI_RX_CTL(pipe);
2553 temp = I915_READ(reg);
8db9d77b
ZW		 2554 if (HAS_PCH_CPT(dev)) {
2555 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2556 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2557 } else {
2558 temp &= ~FDI_LINK_TRAIN_NONE;
2559 temp |= FDI_LINK_TRAIN_PATTERN_2;
2560 }
5eddb70b
CW		 2561 I915_WRITE(reg, temp);
2562
2563 POSTING_READ(reg);
8db9d77b
ZW		 2564 udelay(150);
2565
0206e353 2566 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2567 reg = FDI_TX_CTL(pipe);
2568 temp = I915_READ(reg);
8db9d77b
ZW		 2569 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2570 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2571 I915_WRITE(reg, temp);
2572
2573 POSTING_READ(reg);
8db9d77b
ZW		 2574 udelay(500);
2575
fa37d39e
SP		 2576 for (retry = 0; retry < 5; retry++) {
2577 reg = FDI_RX_IIR(pipe);
2578 temp = I915_READ(reg);
2579 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2580 if (temp & FDI_RX_SYMBOL_LOCK) {
2581 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2582 DRM_DEBUG_KMS("FDI train 2 done.\n");
2583 break;
2584 }
2585 udelay(50);
8db9d77b 2586 }
fa37d39e
SP		 2587 if (retry < 5)
2588 break;
8db9d77b
ZW		 2589 }
2590 if (i == 4)
5eddb70b 2591 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2592
2593 DRM_DEBUG_KMS("FDI train done.\n");
2594}
2595
357555c0
JB		 2596/* Manual link training for Ivy Bridge A0 parts */
2597static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2598{
2599 struct drm_device *dev = crtc->dev;
2600 struct drm_i915_private *dev_priv = dev->dev_private;
2601 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2602 int pipe = intel_crtc->pipe;
2603 u32 reg, temp, i;
2604
2605 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2606 for train result */
2607 reg = FDI_RX_IMR(pipe);
2608 temp = I915_READ(reg);
2609 temp &= ~FDI_RX_SYMBOL_LOCK;
2610 temp &= ~FDI_RX_BIT_LOCK;
2611 I915_WRITE(reg, temp);
2612
2613 POSTING_READ(reg);
2614 udelay(150);
2615
2616 /* enable CPU FDI TX and PCH FDI RX */
2617 reg = FDI_TX_CTL(pipe);
2618 temp = I915_READ(reg);
2619 temp &= ~(7 << 19);
2620 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2621 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2622 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2623 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2624 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2625 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2626 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2627
2628 reg = FDI_RX_CTL(pipe);
2629 temp = I915_READ(reg);
2630 temp &= ~FDI_LINK_TRAIN_AUTO;
2631 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2632 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2633 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2634 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2635
2636 POSTING_READ(reg);
2637 udelay(150);
2638
291427f5
JB		 2639 if (HAS_PCH_CPT(dev))
2640 cpt_phase_pointer_enable(dev, pipe);
2641
0206e353 2642 for (i = 0; i < 4; i++) {
357555c0
JB		 2643 reg = FDI_TX_CTL(pipe);
2644 temp = I915_READ(reg);
2645 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2646 temp |= snb_b_fdi_train_param[i];
2647 I915_WRITE(reg, temp);
2648
2649 POSTING_READ(reg);
2650 udelay(500);
2651
2652 reg = FDI_RX_IIR(pipe);
2653 temp = I915_READ(reg);
2654 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2655
2656 if (temp & FDI_RX_BIT_LOCK ||
2657 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2658 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2659 DRM_DEBUG_KMS("FDI train 1 done.\n");
2660 break;
2661 }
2662 }
2663 if (i == 4)
2664 DRM_ERROR("FDI train 1 fail!\n");
2665
2666 /* Train 2 */
2667 reg = FDI_TX_CTL(pipe);
2668 temp = I915_READ(reg);
2669 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2670 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2671 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2672 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2673 I915_WRITE(reg, temp);
2674
2675 reg = FDI_RX_CTL(pipe);
2676 temp = I915_READ(reg);
2677 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2678 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2679 I915_WRITE(reg, temp);
2680
2681 POSTING_READ(reg);
2682 udelay(150);
2683
0206e353 2684 for (i = 0; i < 4; i++) {
357555c0
JB		 2685 reg = FDI_TX_CTL(pipe);
2686 temp = I915_READ(reg);
2687 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2688 temp |= snb_b_fdi_train_param[i];
2689 I915_WRITE(reg, temp);
2690
2691 POSTING_READ(reg);
2692 udelay(500);
2693
2694 reg = FDI_RX_IIR(pipe);
2695 temp = I915_READ(reg);
2696 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2697
2698 if (temp & FDI_RX_SYMBOL_LOCK) {
2699 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2700 DRM_DEBUG_KMS("FDI train 2 done.\n");
2701 break;
2702 }
2703 }
2704 if (i == 4)
2705 DRM_ERROR("FDI train 2 fail!\n");
2706
2707 DRM_DEBUG_KMS("FDI train done.\n");
2708}
2709
2710static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2711{
2712 struct drm_device *dev = crtc->dev;
2713 struct drm_i915_private *dev_priv = dev->dev_private;
2714 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2715 int pipe = intel_crtc->pipe;
5eddb70b 2716 u32 reg, temp;
79e53945 2717
c64e311e 2718 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2719 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2720 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2721
c98e9dcf 2722 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2723 reg = FDI_RX_CTL(pipe);
2724 temp = I915_READ(reg);
2725 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2726 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2727 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2728 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2729
2730 POSTING_READ(reg);
c98e9dcf
JB		 2731 udelay(200);
2732
2733 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2734 temp = I915_READ(reg);
2735 I915_WRITE(reg, temp | FDI_PCDCLK);
2736
2737 POSTING_READ(reg);
c98e9dcf
JB		 2738 udelay(200);
2739
bf507ef7
ED		 2740 /* On Haswell, the PLL configuration for ports and pipes is handled
2741 * separately, as part of DDI setup */
2742 if (!IS_HASWELL(dev)) {
2743 /* Enable CPU FDI TX PLL, always on for Ironlake */
2744 reg = FDI_TX_CTL(pipe);
2745 temp = I915_READ(reg);
2746 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2747 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2748
bf507ef7
ED		 2749 POSTING_READ(reg);
2750 udelay(100);
2751 }
6be4a607 2752 }
0e23b99d
JB		 2753}
2754
291427f5
JB		 2755static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2756{
2757 struct drm_i915_private *dev_priv = dev->dev_private;
2758 u32 flags = I915_READ(SOUTH_CHICKEN1);
2759
2760 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2761 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2762 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2763 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2764 POSTING_READ(SOUTH_CHICKEN1);
2765}
0fc932b8
JB		 2766static void ironlake_fdi_disable(struct drm_crtc *crtc)
2767{
2768 struct drm_device *dev = crtc->dev;
2769 struct drm_i915_private *dev_priv = dev->dev_private;
2770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2771 int pipe = intel_crtc->pipe;
2772 u32 reg, temp;
2773
2774 /* disable CPU FDI tx and PCH FDI rx */
2775 reg = FDI_TX_CTL(pipe);
2776 temp = I915_READ(reg);
2777 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2778 POSTING_READ(reg);
2779
2780 reg = FDI_RX_CTL(pipe);
2781 temp = I915_READ(reg);
2782 temp &= ~(0x7 << 16);
2783 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2784 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2785
2786 POSTING_READ(reg);
2787 udelay(100);
2788
2789 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2790 if (HAS_PCH_IBX(dev)) {
2791 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2792 I915_WRITE(FDI_RX_CHICKEN(pipe),
2793 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2794 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2795 } else if (HAS_PCH_CPT(dev)) {
2796 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2797 }
0fc932b8
JB		 2798
2799 /* still set train pattern 1 */
2800 reg = FDI_TX_CTL(pipe);
2801 temp = I915_READ(reg);
2802 temp &= ~FDI_LINK_TRAIN_NONE;
2803 temp |= FDI_LINK_TRAIN_PATTERN_1;
2804 I915_WRITE(reg, temp);
2805
2806 reg = FDI_RX_CTL(pipe);
2807 temp = I915_READ(reg);
2808 if (HAS_PCH_CPT(dev)) {
2809 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2810 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2811 } else {
2812 temp &= ~FDI_LINK_TRAIN_NONE;
2813 temp |= FDI_LINK_TRAIN_PATTERN_1;
2814 }
2815 /* BPC in FDI rx is consistent with that in PIPECONF */
2816 temp &= ~(0x07 << 16);
2817 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2818 I915_WRITE(reg, temp);
2819
2820 POSTING_READ(reg);
2821 udelay(100);
2822}
2823
e6c3a2a6
CW		 2824static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2825{
0f91128d 2826 struct drm_device *dev = crtc->dev;
e6c3a2a6
CW		 2827
2828 if (crtc->fb == NULL)
2829 return;
2830
0f91128d
CW		 2831 mutex_lock(&dev->struct_mutex);
2832 intel_finish_fb(crtc->fb);
2833 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2834}
2835
040484af
JB		 2836static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2837{
2838 struct drm_device *dev = crtc->dev;
040484af
JB		 2839 struct intel_encoder *encoder;
2840
2841 /*
2842 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2843 * must be driven by its own crtc; no sharing is possible.
2844 */
6c2b7c12 2845 for_each_encoder_on_crtc(dev, crtc, encoder) {
040484af 2846
6ee8bab0
ED		 2847 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2848 * CPU handles all others */
2849 if (IS_HASWELL(dev)) {
2850 /* It is still unclear how this will work on PPT, so throw up a warning */
2851 WARN_ON(!HAS_PCH_LPT(dev));
2852
2853 if (encoder->type == DRM_MODE_ENCODER_DAC) {
2854 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2855 return true;
2856 } else {
2857 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2858 encoder->type);
2859 return false;
2860 }
2861 }
2862
040484af
JB		 2863 switch (encoder->type) {
2864 case INTEL_OUTPUT_EDP:
2865 if (!intel_encoder_is_pch_edp(&encoder->base))
2866 return false;
2867 continue;
2868 }
2869 }
2870
2871 return true;
2872}
2873
e615efe4
ED		 2874/* Program iCLKIP clock to the desired frequency */
2875static void lpt_program_iclkip(struct drm_crtc *crtc)
2876{
2877 struct drm_device *dev = crtc->dev;
2878 struct drm_i915_private *dev_priv = dev->dev_private;
2879 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2880 u32 temp;
2881
2882 /* It is necessary to ungate the pixclk gate prior to programming
2883 * the divisors, and gate it back when it is done.
2884 */
2885 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2886
2887 /* Disable SSCCTL */
2888 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2889 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2890 SBI_SSCCTL_DISABLE);
2891
2892 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2893 if (crtc->mode.clock == 20000) {
2894 auxdiv = 1;
2895 divsel = 0x41;
2896 phaseinc = 0x20;
2897 } else {
2898 /* The iCLK virtual clock root frequency is in MHz,
2899 * but the crtc->mode.clock in in KHz. To get the divisors,
2900 * it is necessary to divide one by another, so we
2901 * convert the virtual clock precision to KHz here for higher
2902 * precision.
2903 */
2904 u32 iclk_virtual_root_freq = 172800 * 1000;
2905 u32 iclk_pi_range = 64;
2906 u32 desired_divisor, msb_divisor_value, pi_value;
2907
2908 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2909 msb_divisor_value = desired_divisor / iclk_pi_range;
2910 pi_value = desired_divisor % iclk_pi_range;
2911
2912 auxdiv = 0;
2913 divsel = msb_divisor_value - 2;
2914 phaseinc = pi_value;
2915 }
2916
2917 /* This should not happen with any sane values */
2918 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2919 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2920 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2921 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2922
2923 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2924 crtc->mode.clock,
2925 auxdiv,
2926 divsel,
2927 phasedir,
2928 phaseinc);
2929
2930 /* Program SSCDIVINTPHASE6 */
2931 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2932 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2933 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2934 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2935 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2936 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2937 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2938
2939 intel_sbi_write(dev_priv,
2940 SBI_SSCDIVINTPHASE6,
2941 temp);
2942
2943 /* Program SSCAUXDIV */
2944 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2945 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2946 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2947 intel_sbi_write(dev_priv,
2948 SBI_SSCAUXDIV6,
2949 temp);
2950
2951
2952 /* Enable modulator and associated divider */
2953 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2954 temp &= ~SBI_SSCCTL_DISABLE;
2955 intel_sbi_write(dev_priv,
2956 SBI_SSCCTL6,
2957 temp);
2958
2959 /* Wait for initialization time */
2960 udelay(24);
2961
2962 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2963}
2964
f67a559d
JB		 2965/*
2966 * Enable PCH resources required for PCH ports:
2967 * - PCH PLLs
2968 * - FDI training & RX/TX
2969 * - update transcoder timings
2970 * - DP transcoding bits
2971 * - transcoder
2972 */
2973static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2974{
2975 struct drm_device *dev = crtc->dev;
2976 struct drm_i915_private *dev_priv = dev->dev_private;
2977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2978 int pipe = intel_crtc->pipe;
ee7b9f93 2979 u32 reg, temp;
2c07245f 2980
e7e164db
CW		 2981 assert_transcoder_disabled(dev_priv, pipe);
2982
c98e9dcf 2983 /* For PCH output, training FDI link */
674cf967 2984 dev_priv->display.fdi_link_train(crtc);
2c07245f 2985
6f13b7b5
CW		 2986 intel_enable_pch_pll(intel_crtc);
2987
e615efe4
ED		 2988 if (HAS_PCH_LPT(dev)) {
2989 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2990 lpt_program_iclkip(crtc);
2991 } else if (HAS_PCH_CPT(dev)) {
ee7b9f93 2992 u32 sel;
4b645f14 2993
c98e9dcf 2994 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 2995 switch (pipe) {
2996 default:
2997 case 0:
2998 temp |= TRANSA_DPLL_ENABLE;
2999 sel = TRANSA_DPLLB_SEL;
3000 break;
3001 case 1:
3002 temp |= TRANSB_DPLL_ENABLE;
3003 sel = TRANSB_DPLLB_SEL;
3004 break;
3005 case 2:
3006 temp |= TRANSC_DPLL_ENABLE;
3007 sel = TRANSC_DPLLB_SEL;
3008 break;
d64311ab 3009 }
ee7b9f93
JB		 3010 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3011 temp |= sel;
3012 else
3013 temp &= ~sel;
c98e9dcf 3014 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3015 }
5eddb70b 3016
d9b6cb56
JB		 3017 /* set transcoder timing, panel must allow it */
3018 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3019 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3020 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3021 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3022
5eddb70b
CW		 3023 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3024 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3025 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3026 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3027
f57e1e3a
ED		 3028 if (!IS_HASWELL(dev))
3029 intel_fdi_normal_train(crtc);
5e84e1a4 3030
c98e9dcf
JB		 3031 /* For PCH DP, enable TRANS_DP_CTL */
3032 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3033 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3034 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3035 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3036 reg = TRANS_DP_CTL(pipe);
3037 temp = I915_READ(reg);
3038 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3039 TRANS_DP_SYNC_MASK |
3040 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3041 temp |= (TRANS_DP_OUTPUT_ENABLE |
3042 TRANS_DP_ENH_FRAMING);
9325c9f0 3043 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3044
3045 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3046 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3047 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3048 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3049
3050 switch (intel_trans_dp_port_sel(crtc)) {
3051 case PCH_DP_B:
5eddb70b 3052 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3053 break;
3054 case PCH_DP_C:
5eddb70b 3055 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3056 break;
3057 case PCH_DP_D:
5eddb70b 3058 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3059 break;
3060 default:
3061 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 3062 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 3063 break;
32f9d658 3064 }
2c07245f 3065
5eddb70b 3066 I915_WRITE(reg, temp);
6be4a607 3067 }
b52eb4dc 3068
040484af 3069 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 3070}
3071
ee7b9f93
JB		 3072static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3073{
3074 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3075
3076 if (pll == NULL)
3077 return;
3078
3079 if (pll->refcount == 0) {
3080 WARN(1, "bad PCH PLL refcount\n");
3081 return;
3082 }
3083
3084 --pll->refcount;
3085 intel_crtc->pch_pll = NULL;
3086}
3087
3088static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3089{
3090 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3091 struct intel_pch_pll *pll;
3092 int i;
3093
3094 pll = intel_crtc->pch_pll;
3095 if (pll) {
3096 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3097 intel_crtc->base.base.id, pll->pll_reg);
3098 goto prepare;
3099 }
3100
98b6bd99
DV		 3101 if (HAS_PCH_IBX(dev_priv->dev)) {
3102 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3103 i = intel_crtc->pipe;
3104 pll = &dev_priv->pch_plls[i];
3105
3106 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3107 intel_crtc->base.base.id, pll->pll_reg);
3108
3109 goto found;
3110 }
3111
ee7b9f93
JB		 3112 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3113 pll = &dev_priv->pch_plls[i];
3114
3115 /* Only want to check enabled timings first */
3116 if (pll->refcount == 0)
3117 continue;
3118
3119 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3120 fp == I915_READ(pll->fp0_reg)) {
3121 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3122 intel_crtc->base.base.id,
3123 pll->pll_reg, pll->refcount, pll->active);
3124
3125 goto found;
3126 }
3127 }
3128
3129 /* Ok no matching timings, maybe there's a free one? */
3130 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3131 pll = &dev_priv->pch_plls[i];
3132 if (pll->refcount == 0) {
3133 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3134 intel_crtc->base.base.id, pll->pll_reg);
3135 goto found;
3136 }
3137 }
3138
3139 return NULL;
3140
3141found:
3142 intel_crtc->pch_pll = pll;
3143 pll->refcount++;
3144 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3145prepare: /* separate function? */
3146 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3147
e04c7350
CW		 3148 /* Wait for the clocks to stabilize before rewriting the regs */
3149 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3150 POSTING_READ(pll->pll_reg);
3151 udelay(150);
e04c7350
CW		 3152
3153 I915_WRITE(pll->fp0_reg, fp);
3154 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3155 pll->on = false;
3156 return pll;
3157}
3158
d4270e57
JB		 3159void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3160{
3161 struct drm_i915_private *dev_priv = dev->dev_private;
3162 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3163 u32 temp;
3164
3165 temp = I915_READ(dslreg);
3166 udelay(500);
3167 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3168 /* Without this, mode sets may fail silently on FDI */
3169 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3170 udelay(250);
3171 I915_WRITE(tc2reg, 0);
3172 if (wait_for(I915_READ(dslreg) != temp, 5))
3173 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3174 }
3175}
3176
f67a559d
JB		 3177static void ironlake_crtc_enable(struct drm_crtc *crtc)
3178{
3179 struct drm_device *dev = crtc->dev;
3180 struct drm_i915_private *dev_priv = dev->dev_private;
3181 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3182 int pipe = intel_crtc->pipe;
3183 int plane = intel_crtc->plane;
3184 u32 temp;
3185 bool is_pch_port;
3186
3187 if (intel_crtc->active)
3188 return;
3189
3190 intel_crtc->active = true;
3191 intel_update_watermarks(dev);
3192
3193 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3194 temp = I915_READ(PCH_LVDS);
3195 if ((temp & LVDS_PORT_EN) == 0)
3196 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3197 }
3198
3199 is_pch_port = intel_crtc_driving_pch(crtc);
3200
3201 if (is_pch_port)
357555c0 3202 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 3203 else
3204 ironlake_fdi_disable(crtc);
3205
3206 /* Enable panel fitting for LVDS */
3207 if (dev_priv->pch_pf_size &&
3208 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3209 /* Force use of hard-coded filter coefficients
3210 * as some pre-programmed values are broken,
3211 * e.g. x201.
3212 */
9db4a9c7
JB		 3213 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3214 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3215 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3216 }
3217
9c54c0dd
JB		 3218 /*
3219 * On ILK+ LUT must be loaded before the pipe is running but with
3220 * clocks enabled
3221 */
3222 intel_crtc_load_lut(crtc);
3223
f67a559d
JB		 3224 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3225 intel_enable_plane(dev_priv, plane, pipe);
3226
3227 if (is_pch_port)
3228 ironlake_pch_enable(crtc);
c98e9dcf 3229
d1ebd816 3230 mutex_lock(&dev->struct_mutex);
bed4a673 3231 intel_update_fbc(dev);
d1ebd816
BW		 3232 mutex_unlock(&dev->struct_mutex);
3233
6b383a7f 3234 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 3235}
3236
3237static void ironlake_crtc_disable(struct drm_crtc *crtc)
3238{
3239 struct drm_device *dev = crtc->dev;
3240 struct drm_i915_private *dev_priv = dev->dev_private;
3241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3242 int pipe = intel_crtc->pipe;
3243 int plane = intel_crtc->plane;
5eddb70b 3244 u32 reg, temp;
b52eb4dc 3245
f7abfe8b
CW		 3246 if (!intel_crtc->active)
3247 return;
3248
e6c3a2a6 3249 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3250 drm_vblank_off(dev, pipe);
6b383a7f 3251 intel_crtc_update_cursor(crtc, false);
5eddb70b 3252
b24e7179 3253 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3254
973d04f9
CW		 3255 if (dev_priv->cfb_plane == plane)
3256 intel_disable_fbc(dev);
2c07245f 3257
b24e7179 3258 intel_disable_pipe(dev_priv, pipe);
32f9d658 3259
6be4a607 3260 /* Disable PF */
9db4a9c7
JB		 3261 I915_WRITE(PF_CTL(pipe), 0);
3262 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3263
0fc932b8 3264 ironlake_fdi_disable(crtc);
2c07245f 3265
47a05eca
JB		 3266 /* This is a horrible layering violation; we should be doing this in
3267 * the connector/encoder ->prepare instead, but we don't always have
3268 * enough information there about the config to know whether it will
3269 * actually be necessary or just cause undesired flicker.
3270 */
3271 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 3272
040484af 3273 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3274
6be4a607
JB		 3275 if (HAS_PCH_CPT(dev)) {
3276 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3277 reg = TRANS_DP_CTL(pipe);
3278 temp = I915_READ(reg);
3279 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3280 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3281 I915_WRITE(reg, temp);
6be4a607
JB		 3282
3283 /* disable DPLL_SEL */
3284 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3285 switch (pipe) {
3286 case 0:
d64311ab 3287 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3288 break;
3289 case 1:
6be4a607 3290 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3291 break;
3292 case 2:
4b645f14 3293 /* C shares PLL A or B */
d64311ab 3294 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3295 break;
3296 default:
3297 BUG(); /* wtf */
3298 }
6be4a607 3299 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3300 }
e3421a18 3301
6be4a607 3302 /* disable PCH DPLL */
ee7b9f93 3303 intel_disable_pch_pll(intel_crtc);
8db9d77b 3304
6be4a607 3305 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 3306 reg = FDI_RX_CTL(pipe);
3307 temp = I915_READ(reg);
3308 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 3309
6be4a607 3310 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 3311 reg = FDI_TX_CTL(pipe);
3312 temp = I915_READ(reg);
3313 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3314
3315 POSTING_READ(reg);
6be4a607 3316 udelay(100);
8db9d77b 3317
5eddb70b
CW		 3318 reg = FDI_RX_CTL(pipe);
3319 temp = I915_READ(reg);
3320 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 3321
6be4a607 3322 /* Wait for the clocks to turn off. */
5eddb70b 3323 POSTING_READ(reg);
6be4a607 3324 udelay(100);
6b383a7f 3325
f7abfe8b 3326 intel_crtc->active = false;
6b383a7f 3327 intel_update_watermarks(dev);
d1ebd816
BW		 3328
3329 mutex_lock(&dev->struct_mutex);
6b383a7f 3330 intel_update_fbc(dev);
d1ebd816 3331 mutex_unlock(&dev->struct_mutex);
6be4a607 3332}
1b3c7a47 3333
6be4a607
JB		 3334static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3335{
3336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3337 int pipe = intel_crtc->pipe;
3338 int plane = intel_crtc->plane;
8db9d77b 3339
6be4a607
JB		 3340 /* XXX: When our outputs are all unaware of DPMS modes other than off
3341 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3342 */
3343 switch (mode) {
3344 case DRM_MODE_DPMS_ON:
3345 case DRM_MODE_DPMS_STANDBY:
3346 case DRM_MODE_DPMS_SUSPEND:
3347 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3348 ironlake_crtc_enable(crtc);
3349 break;
1b3c7a47 3350
6be4a607
JB		 3351 case DRM_MODE_DPMS_OFF:
3352 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3353 ironlake_crtc_disable(crtc);
2c07245f
ZW		 3354 break;
3355 }
3356}
3357
ee7b9f93
JB		 3358static void ironlake_crtc_off(struct drm_crtc *crtc)
3359{
3360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3361 intel_put_pch_pll(intel_crtc);
3362}
3363
02e792fb
DV		 3364static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3365{
02e792fb 3366 if (!enable && intel_crtc->overlay) {
23f09ce3 3367 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3368 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3369
23f09ce3 3370 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3371 dev_priv->mm.interruptible = false;
3372 (void) intel_overlay_switch_off(intel_crtc->overlay);
3373 dev_priv->mm.interruptible = true;
23f09ce3 3374 mutex_unlock(&dev->struct_mutex);
02e792fb 3375 }
02e792fb 3376
5dcdbcb0
CW		 3377 /* Let userspace switch the overlay on again. In most cases userspace
3378 * has to recompute where to put it anyway.
3379 */
02e792fb
DV		 3380}
3381
0b8765c6 3382static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3383{
3384 struct drm_device *dev = crtc->dev;
79e53945
JB		 3385 struct drm_i915_private *dev_priv = dev->dev_private;
3386 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3387 int pipe = intel_crtc->pipe;
80824003 3388 int plane = intel_crtc->plane;
79e53945 3389
f7abfe8b
CW		 3390 if (intel_crtc->active)
3391 return;
3392
3393 intel_crtc->active = true;
6b383a7f
CW		 3394 intel_update_watermarks(dev);
3395
63d7bbe9 3396 intel_enable_pll(dev_priv, pipe);
040484af 3397 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3398 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3399
0b8765c6 3400 intel_crtc_load_lut(crtc);
bed4a673 3401 intel_update_fbc(dev);
79e53945 3402
0b8765c6
JB		 3403 /* Give the overlay scaler a chance to enable if it's on this pipe */
3404 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3405 intel_crtc_update_cursor(crtc, true);
0b8765c6 3406}
79e53945 3407
0b8765c6
JB		 3408static void i9xx_crtc_disable(struct drm_crtc *crtc)
3409{
3410 struct drm_device *dev = crtc->dev;
3411 struct drm_i915_private *dev_priv = dev->dev_private;
3412 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3413 int pipe = intel_crtc->pipe;
3414 int plane = intel_crtc->plane;
b690e96c 3415
f7abfe8b
CW		 3416 if (!intel_crtc->active)
3417 return;
3418
0b8765c6 3419 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3420 intel_crtc_wait_for_pending_flips(crtc);
3421 drm_vblank_off(dev, pipe);
0b8765c6 3422 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3423 intel_crtc_update_cursor(crtc, false);
0b8765c6 3424
973d04f9
CW		 3425 if (dev_priv->cfb_plane == plane)
3426 intel_disable_fbc(dev);
79e53945 3427
b24e7179 3428 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3429 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3430 intel_disable_pll(dev_priv, pipe);
0b8765c6 3431
f7abfe8b 3432 intel_crtc->active = false;
6b383a7f
CW		 3433 intel_update_fbc(dev);
3434 intel_update_watermarks(dev);
0b8765c6
JB		 3435}
3436
3437static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3438{
3439 /* XXX: When our outputs are all unaware of DPMS modes other than off
3440 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3441 */
3442 switch (mode) {
3443 case DRM_MODE_DPMS_ON:
3444 case DRM_MODE_DPMS_STANDBY:
3445 case DRM_MODE_DPMS_SUSPEND:
3446 i9xx_crtc_enable(crtc);
3447 break;
3448 case DRM_MODE_DPMS_OFF:
3449 i9xx_crtc_disable(crtc);
79e53945
JB		 3450 break;
3451 }
2c07245f
ZW		 3452}
3453
ee7b9f93
JB		 3454static void i9xx_crtc_off(struct drm_crtc *crtc)
3455{
3456}
3457
2c07245f
ZW		 3458/**
3459 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 3460 */
3461static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3462{
3463 struct drm_device *dev = crtc->dev;
e70236a8 3464 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 3465 struct drm_i915_master_private *master_priv;
3466 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3467 int pipe = intel_crtc->pipe;
3468 bool enabled;
3469
032d2a0d
CW		 3470 if (intel_crtc->dpms_mode == mode)
3471 return;
3472
65655d4a 3473 intel_crtc->dpms_mode = mode;
debcaddc 3474
e70236a8 3475 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 3476
3477 if (!dev->primary->master)
3478 return;
3479
3480 master_priv = dev->primary->master->driver_priv;
3481 if (!master_priv->sarea_priv)
3482 return;
3483
3484 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3485
3486 switch (pipe) {
3487 case 0:
3488 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3489 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3490 break;
3491 case 1:
3492 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3493 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3494 break;
3495 default:
9db4a9c7 3496 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3497 break;
3498 }
79e53945
JB		 3499}
3500
cdd59983
CW		 3501static void intel_crtc_disable(struct drm_crtc *crtc)
3502{
3503 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3504 struct drm_device *dev = crtc->dev;
ee7b9f93 3505 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983
CW		 3506
3507 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
ee7b9f93
JB		 3508 dev_priv->display.off(crtc);
3509
931872fc
CW		 3510 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3511 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3512
3513 if (crtc->fb) {
3514 mutex_lock(&dev->struct_mutex);
1690e1eb 3515 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983
CW		 3516 mutex_unlock(&dev->struct_mutex);
3517 }
3518}
3519
7e7d76c3
JB		 3520/* Prepare for a mode set.
3521 *
3522 * Note we could be a lot smarter here. We need to figure out which outputs
3523 * will be enabled, which disabled (in short, how the config will changes)
3524 * and perform the minimum necessary steps to accomplish that, e.g. updating
3525 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3526 * panel fitting is in the proper state, etc.
3527 */
3528static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 3529{
7e7d76c3 3530 i9xx_crtc_disable(crtc);
79e53945
JB		 3531}
3532
7e7d76c3 3533static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3534{
7e7d76c3 3535 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3536}
3537
3538static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3539{
7e7d76c3 3540 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3541}
3542
3543static void ironlake_crtc_commit(struct drm_crtc *crtc)
3544{
7e7d76c3 3545 ironlake_crtc_enable(crtc);
79e53945
JB		 3546}
3547
0206e353 3548void intel_encoder_prepare(struct drm_encoder *encoder)
79e53945
JB		 3549{
3550 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3551 /* lvds has its own version of prepare see intel_lvds_prepare */
3552 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3553}
3554
0206e353 3555void intel_encoder_commit(struct drm_encoder *encoder)
79e53945
JB		 3556{
3557 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
d4270e57 3558 struct drm_device *dev = encoder->dev;
d47d7cb8 3559 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
d4270e57 3560
79e53945
JB		 3561 /* lvds has its own version of commit see intel_lvds_commit */
3562 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
d4270e57
JB		 3563
3564 if (HAS_PCH_CPT(dev))
3565 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
79e53945
JB		 3566}
3567
ea5b213a
CW		 3568void intel_encoder_destroy(struct drm_encoder *encoder)
3569{
4ef69c7a 3570 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3571
ea5b213a
CW		 3572 drm_encoder_cleanup(encoder);
3573 kfree(intel_encoder);
3574}
3575
79e53945 3576static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3577 const struct drm_display_mode *mode,
79e53945
JB		 3578 struct drm_display_mode *adjusted_mode)
3579{
2c07245f 3580 struct drm_device *dev = crtc->dev;
89749350 3581
bad720ff 3582 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3583 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3584 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3585 return false;
2c07245f 3586 }
89749350 3587
f9bef081
DV		 3588 /* All interlaced capable intel hw wants timings in frames. Note though
3589 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3590 * timings, so we need to be careful not to clobber these.*/
3591 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3592 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3593
79e53945
JB		 3594 return true;
3595}
3596
25eb05fc
JB		 3597static int valleyview_get_display_clock_speed(struct drm_device *dev)
3598{
3599 return 400000; /* FIXME */
3600}
3601
e70236a8
JB		 3602static int i945_get_display_clock_speed(struct drm_device *dev)
3603{
3604 return 400000;
3605}
79e53945 3606
e70236a8 3607static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3608{
e70236a8
JB		 3609 return 333000;
3610}
79e53945 3611
e70236a8
JB		 3612static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3613{
3614 return 200000;
3615}
79e53945 3616
e70236a8
JB		 3617static int i915gm_get_display_clock_speed(struct drm_device *dev)
3618{
3619 u16 gcfgc = 0;
79e53945 3620
e70236a8
JB		 3621 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3622
3623 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3624 return 133000;
3625 else {
3626 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3627 case GC_DISPLAY_CLOCK_333_MHZ:
3628 return 333000;
3629 default:
3630 case GC_DISPLAY_CLOCK_190_200_MHZ:
3631 return 190000;
79e53945 3632 }
e70236a8
JB		 3633 }
3634}
3635
3636static int i865_get_display_clock_speed(struct drm_device *dev)
3637{
3638 return 266000;
3639}
3640
3641static int i855_get_display_clock_speed(struct drm_device *dev)
3642{
3643 u16 hpllcc = 0;
3644 /* Assume that the hardware is in the high speed state. This
3645 * should be the default.
3646 */
3647 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3648 case GC_CLOCK_133_200:
3649 case GC_CLOCK_100_200:
3650 return 200000;
3651 case GC_CLOCK_166_250:
3652 return 250000;
3653 case GC_CLOCK_100_133:
79e53945 3654 return 133000;
e70236a8 3655 }
79e53945 3656
e70236a8
JB		 3657 /* Shouldn't happen */
3658 return 0;
3659}
79e53945 3660
e70236a8
JB		 3661static int i830_get_display_clock_speed(struct drm_device *dev)
3662{
3663 return 133000;
79e53945
JB		 3664}
3665
2c07245f
ZW		 3666struct fdi_m_n {
3667 u32 tu;
3668 u32 gmch_m;
3669 u32 gmch_n;
3670 u32 link_m;
3671 u32 link_n;
3672};
3673
3674static void
3675fdi_reduce_ratio(u32 *num, u32 *den)
3676{
3677 while (*num > 0xffffff || *den > 0xffffff) {
3678 *num >>= 1;
3679 *den >>= 1;
3680 }
3681}
3682
2c07245f 3683static void
f2b115e6
AJ		 3684ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3685 int link_clock, struct fdi_m_n *m_n)
2c07245f 3686{
2c07245f
ZW		 3687 m_n->tu = 64; /* default size */
3688
22ed1113
CW		 3689 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3690 m_n->gmch_m = bits_per_pixel * pixel_clock;
3691 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3692 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3693
22ed1113
CW		 3694 m_n->link_m = pixel_clock;
3695 m_n->link_n = link_clock;
2c07245f
ZW		 3696 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3697}
3698
a7615030
CW		 3699static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3700{
72bbe58c
KP		 3701 if (i915_panel_use_ssc >= 0)
3702 return i915_panel_use_ssc != 0;
3703 return dev_priv->lvds_use_ssc
435793df 3704 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 3705}
3706
5a354204
JB		 3707/**
3708 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3709 * @crtc: CRTC structure
3b5c78a3 3710 * @mode: requested mode
5a354204
JB		 3711 *
3712 * A pipe may be connected to one or more outputs. Based on the depth of the
3713 * attached framebuffer, choose a good color depth to use on the pipe.
3714 *
3715 * If possible, match the pipe depth to the fb depth. In some cases, this
3716 * isn't ideal, because the connected output supports a lesser or restricted
3717 * set of depths. Resolve that here:
3718 * LVDS typically supports only 6bpc, so clamp down in that case
3719 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3720 * Displays may support a restricted set as well, check EDID and clamp as
3721 * appropriate.
3b5c78a3 3722 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 3723 *
3724 * RETURNS:
3725 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3726 * true if they don't match).
3727 */
3728static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3b5c78a3
AJ		 3729 unsigned int *pipe_bpp,
3730 struct drm_display_mode *mode)
5a354204
JB		 3731{
3732 struct drm_device *dev = crtc->dev;
3733 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 3734 struct drm_connector *connector;
6c2b7c12 3735 struct intel_encoder *intel_encoder;
5a354204
JB		 3736 unsigned int display_bpc = UINT_MAX, bpc;
3737
3738 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 3739 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 3740
3741 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3742 unsigned int lvds_bpc;
3743
3744 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3745 LVDS_A3_POWER_UP)
3746 lvds_bpc = 8;
3747 else
3748 lvds_bpc = 6;
3749
3750 if (lvds_bpc < display_bpc) {
82820490 3751 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 3752 display_bpc = lvds_bpc;
3753 }
3754 continue;
3755 }
3756
5a354204
JB		 3757 /* Not one of the known troublemakers, check the EDID */
3758 list_for_each_entry(connector, &dev->mode_config.connector_list,
3759 head) {
6c2b7c12 3760 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 3761 continue;
3762
62ac41a6
JB		 3763 /* Don't use an invalid EDID bpc value */
3764 if (connector->display_info.bpc &&
3765 connector->display_info.bpc < display_bpc) {
82820490 3766 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 3767 display_bpc = connector->display_info.bpc;
3768 }
3769 }
3770
3771 /*
3772 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3773 * through, clamp it down. (Note: >12bpc will be caught below.)
3774 */
3775 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3776 if (display_bpc > 8 && display_bpc < 12) {
82820490 3777 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 3778 display_bpc = 12;
3779 } else {
82820490 3780 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 3781 display_bpc = 8;
3782 }
3783 }
3784 }
3785
3b5c78a3
AJ		 3786 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3787 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3788 display_bpc = 6;
3789 }
3790
5a354204
JB		 3791 /*
3792 * We could just drive the pipe at the highest bpc all the time and
3793 * enable dithering as needed, but that costs bandwidth. So choose
3794 * the minimum value that expresses the full color range of the fb but
3795 * also stays within the max display bpc discovered above.
3796 */
3797
3798 switch (crtc->fb->depth) {
3799 case 8:
3800 bpc = 8; /* since we go through a colormap */
3801 break;
3802 case 15:
3803 case 16:
3804 bpc = 6; /* min is 18bpp */
3805 break;
3806 case 24:
578393cd 3807 bpc = 8;
5a354204
JB		 3808 break;
3809 case 30:
578393cd 3810 bpc = 10;
5a354204
JB		 3811 break;
3812 case 48:
578393cd 3813 bpc = 12;
5a354204
JB		 3814 break;
3815 default:
3816 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3817 bpc = min((unsigned int)8, display_bpc);
3818 break;
3819 }
3820
578393cd
KP		 3821 display_bpc = min(display_bpc, bpc);
3822
82820490
AJ		 3823 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3824 bpc, display_bpc);
5a354204 3825
578393cd 3826 *pipe_bpp = display_bpc * 3;
5a354204
JB		 3827
3828 return display_bpc != bpc;
3829}
3830
a0c4da24
JB		 3831static int vlv_get_refclk(struct drm_crtc *crtc)
3832{
3833 struct drm_device *dev = crtc->dev;
3834 struct drm_i915_private *dev_priv = dev->dev_private;
3835 int refclk = 27000; /* for DP & HDMI */
3836
3837 return 100000; /* only one validated so far */
3838
3839 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3840 refclk = 96000;
3841 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3842 if (intel_panel_use_ssc(dev_priv))
3843 refclk = 100000;
3844 else
3845 refclk = 96000;
3846 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3847 refclk = 100000;
3848 }
3849
3850 return refclk;
3851}
3852
c65d77d8
JB		 3853static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3854{
3855 struct drm_device *dev = crtc->dev;
3856 struct drm_i915_private *dev_priv = dev->dev_private;
3857 int refclk;
3858
a0c4da24
JB		 3859 if (IS_VALLEYVIEW(dev)) {
3860 refclk = vlv_get_refclk(crtc);
3861 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 3862 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3863 refclk = dev_priv->lvds_ssc_freq * 1000;
3864 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3865 refclk / 1000);
3866 } else if (!IS_GEN2(dev)) {
3867 refclk = 96000;
3868 } else {
3869 refclk = 48000;
3870 }
3871
3872 return refclk;
3873}
3874
3875static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3876 intel_clock_t *clock)
3877{
3878 /* SDVO TV has fixed PLL values depend on its clock range,
3879 this mirrors vbios setting. */
3880 if (adjusted_mode->clock >= 100000
3881 && adjusted_mode->clock < 140500) {
3882 clock->p1 = 2;
3883 clock->p2 = 10;
3884 clock->n = 3;
3885 clock->m1 = 16;
3886 clock->m2 = 8;
3887 } else if (adjusted_mode->clock >= 140500
3888 && adjusted_mode->clock <= 200000) {
3889 clock->p1 = 1;
3890 clock->p2 = 10;
3891 clock->n = 6;
3892 clock->m1 = 12;
3893 clock->m2 = 8;
3894 }
3895}
3896
a7516a05
JB		 3897static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3898 intel_clock_t *clock,
3899 intel_clock_t *reduced_clock)
3900{
3901 struct drm_device *dev = crtc->dev;
3902 struct drm_i915_private *dev_priv = dev->dev_private;
3903 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3904 int pipe = intel_crtc->pipe;
3905 u32 fp, fp2 = 0;
3906
3907 if (IS_PINEVIEW(dev)) {
3908 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3909 if (reduced_clock)
3910 fp2 = (1 << reduced_clock->n) << 16 |
3911 reduced_clock->m1 << 8 | reduced_clock->m2;
3912 } else {
3913 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3914 if (reduced_clock)
3915 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3916 reduced_clock->m2;
3917 }
3918
3919 I915_WRITE(FP0(pipe), fp);
3920
3921 intel_crtc->lowfreq_avail = false;
3922 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3923 reduced_clock && i915_powersave) {
3924 I915_WRITE(FP1(pipe), fp2);
3925 intel_crtc->lowfreq_avail = true;
3926 } else {
3927 I915_WRITE(FP1(pipe), fp);
3928 }
3929}
3930
93e537a1
DV		 3931static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3932 struct drm_display_mode *adjusted_mode)
3933{
3934 struct drm_device *dev = crtc->dev;
3935 struct drm_i915_private *dev_priv = dev->dev_private;
3936 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3937 int pipe = intel_crtc->pipe;
284d5df5 3938 u32 temp;
93e537a1
DV		 3939
3940 temp = I915_READ(LVDS);
3941 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3942 if (pipe == 1) {
3943 temp |= LVDS_PIPEB_SELECT;
3944 } else {
3945 temp &= ~LVDS_PIPEB_SELECT;
3946 }
3947 /* set the corresponsding LVDS_BORDER bit */
3948 temp |= dev_priv->lvds_border_bits;
3949 /* Set the B0-B3 data pairs corresponding to whether we're going to
3950 * set the DPLLs for dual-channel mode or not.
3951 */
3952 if (clock->p2 == 7)
3953 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3954 else
3955 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3956
3957 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3958 * appropriately here, but we need to look more thoroughly into how
3959 * panels behave in the two modes.
3960 */
3961 /* set the dithering flag on LVDS as needed */
3962 if (INTEL_INFO(dev)->gen >= 4) {
3963 if (dev_priv->lvds_dither)
3964 temp |= LVDS_ENABLE_DITHER;
3965 else
3966 temp &= ~LVDS_ENABLE_DITHER;
3967 }
284d5df5 3968 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 3969 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 3970 temp |= LVDS_HSYNC_POLARITY;
93e537a1 3971 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 3972 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 3973 I915_WRITE(LVDS, temp);
3974}
3975
a0c4da24
JB		 3976static void vlv_update_pll(struct drm_crtc *crtc,
3977 struct drm_display_mode *mode,
3978 struct drm_display_mode *adjusted_mode,
3979 intel_clock_t *clock, intel_clock_t *reduced_clock,
3980 int refclk, int num_connectors)
3981{
3982 struct drm_device *dev = crtc->dev;
3983 struct drm_i915_private *dev_priv = dev->dev_private;
3984 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3985 int pipe = intel_crtc->pipe;
3986 u32 dpll, mdiv, pdiv;
3987 u32 bestn, bestm1, bestm2, bestp1, bestp2;
3988 bool is_hdmi;
3989
3990 is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
3991
3992 bestn = clock->n;
3993 bestm1 = clock->m1;
3994 bestm2 = clock->m2;
3995 bestp1 = clock->p1;
3996 bestp2 = clock->p2;
3997
3998 /* Enable DPIO clock input */
3999 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4000 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4001 I915_WRITE(DPLL(pipe), dpll);
4002 POSTING_READ(DPLL(pipe));
4003
4004 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4005 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4006 mdiv |= ((bestn << DPIO_N_SHIFT));
4007 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4008 mdiv |= (1 << DPIO_K_SHIFT);
4009 mdiv |= DPIO_ENABLE_CALIBRATION;
4010 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4011
4012 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4013
4014 pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
4015 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4016 (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4017 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4018
4019 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
4020
4021 dpll |= DPLL_VCO_ENABLE;
4022 I915_WRITE(DPLL(pipe), dpll);
4023 POSTING_READ(DPLL(pipe));
4024 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4025 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4026
4027 if (is_hdmi) {
4028 u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4029
4030 if (temp > 1)
4031 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4032 else
4033 temp = 0;
4034
4035 I915_WRITE(DPLL_MD(pipe), temp);
4036 POSTING_READ(DPLL_MD(pipe));
4037 }
4038
4039 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
4040}
4041
eb1cbe48
DV		 4042static void i9xx_update_pll(struct drm_crtc *crtc,
4043 struct drm_display_mode *mode,
4044 struct drm_display_mode *adjusted_mode,
4045 intel_clock_t *clock, intel_clock_t *reduced_clock,
4046 int num_connectors)
4047{
4048 struct drm_device *dev = crtc->dev;
4049 struct drm_i915_private *dev_priv = dev->dev_private;
4050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4051 int pipe = intel_crtc->pipe;
4052 u32 dpll;
4053 bool is_sdvo;
4054
4055 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4056 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4057
4058 dpll = DPLL_VGA_MODE_DIS;
4059
4060 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4061 dpll |= DPLLB_MODE_LVDS;
4062 else
4063 dpll |= DPLLB_MODE_DAC_SERIAL;
4064 if (is_sdvo) {
4065 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4066 if (pixel_multiplier > 1) {
4067 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4068 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4069 }
4070 dpll |= DPLL_DVO_HIGH_SPEED;
4071 }
4072 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4073 dpll |= DPLL_DVO_HIGH_SPEED;
4074
4075 /* compute bitmask from p1 value */
4076 if (IS_PINEVIEW(dev))
4077 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4078 else {
4079 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4080 if (IS_G4X(dev) && reduced_clock)
4081 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4082 }
4083 switch (clock->p2) {
4084 case 5:
4085 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4086 break;
4087 case 7:
4088 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4089 break;
4090 case 10:
4091 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4092 break;
4093 case 14:
4094 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4095 break;
4096 }
4097 if (INTEL_INFO(dev)->gen >= 4)
4098 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4099
4100 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4101 dpll |= PLL_REF_INPUT_TVCLKINBC;
4102 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4103 /* XXX: just matching BIOS for now */
4104 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4105 dpll |= 3;
4106 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4107 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4108 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4109 else
4110 dpll |= PLL_REF_INPUT_DREFCLK;
4111
4112 dpll |= DPLL_VCO_ENABLE;
4113 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4114 POSTING_READ(DPLL(pipe));
4115 udelay(150);
4116
4117 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4118 * This is an exception to the general rule that mode_set doesn't turn
4119 * things on.
4120 */
4121 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4122 intel_update_lvds(crtc, clock, adjusted_mode);
4123
4124 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4125 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4126
4127 I915_WRITE(DPLL(pipe), dpll);
4128
4129 /* Wait for the clocks to stabilize. */
4130 POSTING_READ(DPLL(pipe));
4131 udelay(150);
4132
4133 if (INTEL_INFO(dev)->gen >= 4) {
4134 u32 temp = 0;
4135 if (is_sdvo) {
4136 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4137 if (temp > 1)
4138 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4139 else
4140 temp = 0;
4141 }
4142 I915_WRITE(DPLL_MD(pipe), temp);
4143 } else {
4144 /* The pixel multiplier can only be updated once the
4145 * DPLL is enabled and the clocks are stable.
4146 *
4147 * So write it again.
4148 */
4149 I915_WRITE(DPLL(pipe), dpll);
4150 }
4151}
4152
4153static void i8xx_update_pll(struct drm_crtc *crtc,
4154 struct drm_display_mode *adjusted_mode,
4155 intel_clock_t *clock,
4156 int num_connectors)
4157{
4158 struct drm_device *dev = crtc->dev;
4159 struct drm_i915_private *dev_priv = dev->dev_private;
4160 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4161 int pipe = intel_crtc->pipe;
4162 u32 dpll;
4163
4164 dpll = DPLL_VGA_MODE_DIS;
4165
4166 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4167 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4168 } else {
4169 if (clock->p1 == 2)
4170 dpll |= PLL_P1_DIVIDE_BY_TWO;
4171 else
4172 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4173 if (clock->p2 == 4)
4174 dpll |= PLL_P2_DIVIDE_BY_4;
4175 }
4176
4177 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4178 /* XXX: just matching BIOS for now */
4179 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4180 dpll |= 3;
4181 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4182 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4183 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4184 else
4185 dpll |= PLL_REF_INPUT_DREFCLK;
4186
4187 dpll |= DPLL_VCO_ENABLE;
4188 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4189 POSTING_READ(DPLL(pipe));
4190 udelay(150);
4191
4192 I915_WRITE(DPLL(pipe), dpll);
4193
4194 /* Wait for the clocks to stabilize. */
4195 POSTING_READ(DPLL(pipe));
4196 udelay(150);
4197
4198 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4199 * This is an exception to the general rule that mode_set doesn't turn
4200 * things on.
4201 */
4202 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4203 intel_update_lvds(crtc, clock, adjusted_mode);
4204
4205 /* The pixel multiplier can only be updated once the
4206 * DPLL is enabled and the clocks are stable.
4207 *
4208 * So write it again.
4209 */
4210 I915_WRITE(DPLL(pipe), dpll);
4211}
4212
f564048e
EA		 4213static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4214 struct drm_display_mode *mode,
4215 struct drm_display_mode *adjusted_mode,
4216 int x, int y,
4217 struct drm_framebuffer *old_fb)
79e53945
JB		 4218{
4219 struct drm_device *dev = crtc->dev;
4220 struct drm_i915_private *dev_priv = dev->dev_private;
4221 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4222 int pipe = intel_crtc->pipe;
80824003 4223 int plane = intel_crtc->plane;
c751ce4f 4224 int refclk, num_connectors = 0;
652c393a 4225 intel_clock_t clock, reduced_clock;
eb1cbe48
DV		 4226 u32 dspcntr, pipeconf, vsyncshift;
4227 bool ok, has_reduced_clock = false, is_sdvo = false;
4228 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4229 struct intel_encoder *encoder;
d4906093 4230 const intel_limit_t *limit;
5c3b82e2 4231 int ret;
79e53945 4232
6c2b7c12 4233 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4234 switch (encoder->type) {
79e53945
JB		 4235 case INTEL_OUTPUT_LVDS:
4236 is_lvds = true;
4237 break;
4238 case INTEL_OUTPUT_SDVO:
7d57382e 4239 case INTEL_OUTPUT_HDMI:
79e53945 4240 is_sdvo = true;
5eddb70b 4241 if (encoder->needs_tv_clock)
e2f0ba97 4242 is_tv = true;
79e53945 4243 break;
79e53945
JB		 4244 case INTEL_OUTPUT_TVOUT:
4245 is_tv = true;
4246 break;
a4fc5ed6
KP		 4247 case INTEL_OUTPUT_DISPLAYPORT:
4248 is_dp = true;
4249 break;
79e53945 4250 }
43565a06 4251
c751ce4f 4252 num_connectors++;
79e53945
JB		 4253 }
4254
c65d77d8 4255 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4256
d4906093
ML		 4257 /*
4258 * Returns a set of divisors for the desired target clock with the given
4259 * refclk, or FALSE. The returned values represent the clock equation:
4260 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4261 */
1b894b59 4262 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4263 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4264 &clock);
79e53945
JB		 4265 if (!ok) {
4266 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4267 return -EINVAL;
79e53945
JB		 4268 }
4269
cda4b7d3 4270 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4271 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4272
ddc9003c 4273 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4274 /*
4275 * Ensure we match the reduced clock's P to the target clock.
4276 * If the clocks don't match, we can't switch the display clock
4277 * by using the FP0/FP1. In such case we will disable the LVDS
4278 * downclock feature.
4279 */
ddc9003c 4280 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4281 dev_priv->lvds_downclock,
4282 refclk,
cec2f356 4283 &clock,
5eddb70b 4284 &reduced_clock);
7026d4ac
ZW		 4285 }
4286
c65d77d8
JB		 4287 if (is_sdvo && is_tv)
4288 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4289
a7516a05
JB		 4290 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4291 &reduced_clock : NULL);
79e53945 4292
eb1cbe48
DV		 4293 if (IS_GEN2(dev))
4294 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
a0c4da24
JB		 4295 else if (IS_VALLEYVIEW(dev))
4296 vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
4297 refclk, num_connectors);
79e53945 4298 else
eb1cbe48
DV		 4299 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4300 has_reduced_clock ? &reduced_clock : NULL,
4301 num_connectors);
79e53945
JB		 4302
4303 /* setup pipeconf */
5eddb70b 4304 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4305
4306 /* Set up the display plane register */
4307 dspcntr = DISPPLANE_GAMMA_ENABLE;
4308
929c77fb
EA		 4309 if (pipe == 0)
4310 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4311 else
4312 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4313
a6c45cf0 4314 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4315 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4316 * core speed.
4317 *
4318 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4319 * pipe == 0 check?
4320 */
e70236a8
JB		 4321 if (mode->clock >
4322 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4323 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4324 else
5eddb70b 4325 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4326 }
4327
3b5c78a3
AJ		 4328 /* default to 8bpc */
4329 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4330 if (is_dp) {
4331 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4332 pipeconf |= PIPECONF_BPP_6 |
4333 PIPECONF_DITHER_EN |
4334 PIPECONF_DITHER_TYPE_SP;
4335 }
4336 }
4337
28c97730 4338 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4339 drm_mode_debug_printmodeline(mode);
4340
a7516a05
JB		 4341 if (HAS_PIPE_CXSR(dev)) {
4342 if (intel_crtc->lowfreq_avail) {
28c97730 4343 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4344 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4345 } else {
28c97730 4346 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4347 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4348 }
4349 }
4350
617cf884 4351 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575
DV		 4352 if (!IS_GEN2(dev) &&
4353 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
734b4157
KH		 4354 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4355 /* the chip adds 2 halflines automatically */
734b4157 4356 adjusted_mode->crtc_vtotal -= 1;
734b4157 4357 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 4358 vsyncshift = adjusted_mode->crtc_hsync_start
4359 - adjusted_mode->crtc_htotal/2;
4360 } else {
617cf884 4361 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 4362 vsyncshift = 0;
4363 }
4364
4365 if (!IS_GEN3(dev))
4366 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
734b4157 4367
5eddb70b
CW		 4368 I915_WRITE(HTOTAL(pipe),
4369 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4370 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4371 I915_WRITE(HBLANK(pipe),
4372 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4373 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4374 I915_WRITE(HSYNC(pipe),
4375 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4376 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4377
4378 I915_WRITE(VTOTAL(pipe),
4379 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4380 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4381 I915_WRITE(VBLANK(pipe),
4382 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4383 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4384 I915_WRITE(VSYNC(pipe),
4385 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4386 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 4387
4388 /* pipesrc and dspsize control the size that is scaled from,
4389 * which should always be the user's requested size.
79e53945 4390 */
929c77fb
EA		 4391 I915_WRITE(DSPSIZE(plane),
4392 ((mode->vdisplay - 1) << 16) |
4393 (mode->hdisplay - 1));
4394 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 4395 I915_WRITE(PIPESRC(pipe),
4396 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4397
f564048e
EA		 4398 I915_WRITE(PIPECONF(pipe), pipeconf);
4399 POSTING_READ(PIPECONF(pipe));
929c77fb 4400 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4401
4402 intel_wait_for_vblank(dev, pipe);
4403
f564048e
EA		 4404 I915_WRITE(DSPCNTR(plane), dspcntr);
4405 POSTING_READ(DSPCNTR(plane));
4406
4407 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4408
4409 intel_update_watermarks(dev);
4410
f564048e
EA		 4411 return ret;
4412}
4413
9fb526db
KP		 4414/*
4415 * Initialize reference clocks when the driver loads
4416 */
4417void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4418{
4419 struct drm_i915_private *dev_priv = dev->dev_private;
4420 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4421 struct intel_encoder *encoder;
13d83a67
JB		 4422 u32 temp;
4423 bool has_lvds = false;
199e5d79
KP		 4424 bool has_cpu_edp = false;
4425 bool has_pch_edp = false;
4426 bool has_panel = false;
99eb6a01
KP		 4427 bool has_ck505 = false;
4428 bool can_ssc = false;
13d83a67
JB		 4429
4430 /* We need to take the global config into account */
199e5d79
KP		 4431 list_for_each_entry(encoder, &mode_config->encoder_list,
4432 base.head) {
4433 switch (encoder->type) {
4434 case INTEL_OUTPUT_LVDS:
4435 has_panel = true;
4436 has_lvds = true;
4437 break;
4438 case INTEL_OUTPUT_EDP:
4439 has_panel = true;
4440 if (intel_encoder_is_pch_edp(&encoder->base))
4441 has_pch_edp = true;
4442 else
4443 has_cpu_edp = true;
4444 break;
13d83a67
JB		 4445 }
4446 }
4447
99eb6a01
KP		 4448 if (HAS_PCH_IBX(dev)) {
4449 has_ck505 = dev_priv->display_clock_mode;
4450 can_ssc = has_ck505;
4451 } else {
4452 has_ck505 = false;
4453 can_ssc = true;
4454 }
4455
4456 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4457 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4458 has_ck505);
13d83a67
JB		 4459
4460 /* Ironlake: try to setup display ref clock before DPLL
4461 * enabling. This is only under driver's control after
4462 * PCH B stepping, previous chipset stepping should be
4463 * ignoring this setting.
4464 */
4465 temp = I915_READ(PCH_DREF_CONTROL);
4466 /* Always enable nonspread source */
4467 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4468
99eb6a01
KP		 4469 if (has_ck505)
4470 temp |= DREF_NONSPREAD_CK505_ENABLE;
4471 else
4472 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4473
199e5d79
KP		 4474 if (has_panel) {
4475 temp &= ~DREF_SSC_SOURCE_MASK;
4476 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4477
199e5d79 4478 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4479 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4480 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4481 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4482 } else
4483 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4484
4485 /* Get SSC going before enabling the outputs */
4486 I915_WRITE(PCH_DREF_CONTROL, temp);
4487 POSTING_READ(PCH_DREF_CONTROL);
4488 udelay(200);
4489
13d83a67
JB		 4490 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4491
4492 /* Enable CPU source on CPU attached eDP */
199e5d79 4493 if (has_cpu_edp) {
99eb6a01 4494 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4495 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4496 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4497 }
13d83a67
JB		 4498 else
4499 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4500 } else
4501 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4502
4503 I915_WRITE(PCH_DREF_CONTROL, temp);
4504 POSTING_READ(PCH_DREF_CONTROL);
4505 udelay(200);
4506 } else {
4507 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4508
4509 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4510
4511 /* Turn off CPU output */
4512 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4513
4514 I915_WRITE(PCH_DREF_CONTROL, temp);
4515 POSTING_READ(PCH_DREF_CONTROL);
4516 udelay(200);
4517
4518 /* Turn off the SSC source */
4519 temp &= ~DREF_SSC_SOURCE_MASK;
4520 temp |= DREF_SSC_SOURCE_DISABLE;
4521
4522 /* Turn off SSC1 */
4523 temp &= ~ DREF_SSC1_ENABLE;
4524
13d83a67
JB		 4525 I915_WRITE(PCH_DREF_CONTROL, temp);
4526 POSTING_READ(PCH_DREF_CONTROL);
4527 udelay(200);
4528 }
4529}
4530
d9d444cb
JB		 4531static int ironlake_get_refclk(struct drm_crtc *crtc)
4532{
4533 struct drm_device *dev = crtc->dev;
4534 struct drm_i915_private *dev_priv = dev->dev_private;
4535 struct intel_encoder *encoder;
d9d444cb
JB		 4536 struct intel_encoder *edp_encoder = NULL;
4537 int num_connectors = 0;
4538 bool is_lvds = false;
4539
6c2b7c12 4540 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 4541 switch (encoder->type) {
4542 case INTEL_OUTPUT_LVDS:
4543 is_lvds = true;
4544 break;
4545 case INTEL_OUTPUT_EDP:
4546 edp_encoder = encoder;
4547 break;
4548 }
4549 num_connectors++;
4550 }
4551
4552 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4553 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4554 dev_priv->lvds_ssc_freq);
4555 return dev_priv->lvds_ssc_freq * 1000;
4556 }
4557
4558 return 120000;
4559}
4560
f564048e
EA		 4561static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4562 struct drm_display_mode *mode,
4563 struct drm_display_mode *adjusted_mode,
4564 int x, int y,
4565 struct drm_framebuffer *old_fb)
79e53945
JB		 4566{
4567 struct drm_device *dev = crtc->dev;
4568 struct drm_i915_private *dev_priv = dev->dev_private;
4569 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4570 int pipe = intel_crtc->pipe;
80824003 4571 int plane = intel_crtc->plane;
c751ce4f 4572 int refclk, num_connectors = 0;
652c393a 4573 intel_clock_t clock, reduced_clock;
5eddb70b 4574 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 4575 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 4576 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
e3aef172 4577 struct intel_encoder *encoder, *edp_encoder = NULL;
d4906093 4578 const intel_limit_t *limit;
5c3b82e2 4579 int ret;
2c07245f 4580 struct fdi_m_n m_n = {0};
fae14981 4581 u32 temp;
5a354204
JB		 4582 int target_clock, pixel_multiplier, lane, link_bw, factor;
4583 unsigned int pipe_bpp;
4584 bool dither;
e3aef172 4585 bool is_cpu_edp = false, is_pch_edp = false;
79e53945 4586
6c2b7c12 4587 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4588 switch (encoder->type) {
79e53945
JB		 4589 case INTEL_OUTPUT_LVDS:
4590 is_lvds = true;
4591 break;
4592 case INTEL_OUTPUT_SDVO:
7d57382e 4593 case INTEL_OUTPUT_HDMI:
79e53945 4594 is_sdvo = true;
5eddb70b 4595 if (encoder->needs_tv_clock)
e2f0ba97 4596 is_tv = true;
79e53945 4597 break;
79e53945
JB		 4598 case INTEL_OUTPUT_TVOUT:
4599 is_tv = true;
4600 break;
4601 case INTEL_OUTPUT_ANALOG:
4602 is_crt = true;
4603 break;
a4fc5ed6
KP		 4604 case INTEL_OUTPUT_DISPLAYPORT:
4605 is_dp = true;
4606 break;
32f9d658 4607 case INTEL_OUTPUT_EDP:
e3aef172
JB		 4608 is_dp = true;
4609 if (intel_encoder_is_pch_edp(&encoder->base))
4610 is_pch_edp = true;
4611 else
4612 is_cpu_edp = true;
4613 edp_encoder = encoder;
32f9d658 4614 break;
79e53945 4615 }
43565a06 4616
c751ce4f 4617 num_connectors++;
79e53945
JB		 4618 }
4619
d9d444cb 4620 refclk = ironlake_get_refclk(crtc);
79e53945 4621
d4906093
ML		 4622 /*
4623 * Returns a set of divisors for the desired target clock with the given
4624 * refclk, or FALSE. The returned values represent the clock equation:
4625 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4626 */
1b894b59 4627 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4628 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4629 &clock);
79e53945
JB		 4630 if (!ok) {
4631 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4632 return -EINVAL;
79e53945
JB		 4633 }
4634
cda4b7d3 4635 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4636 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4637
ddc9003c 4638 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4639 /*
4640 * Ensure we match the reduced clock's P to the target clock.
4641 * If the clocks don't match, we can't switch the display clock
4642 * by using the FP0/FP1. In such case we will disable the LVDS
4643 * downclock feature.
4644 */
ddc9003c 4645 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4646 dev_priv->lvds_downclock,
4647 refclk,
cec2f356 4648 &clock,
5eddb70b 4649 &reduced_clock);
652c393a 4650 }
61e9653f
DV		 4651
4652 if (is_sdvo && is_tv)
4653 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4654
7026d4ac 4655
2c07245f 4656 /* FDI link */
8febb297
EA		 4657 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4658 lane = 0;
4659 /* CPU eDP doesn't require FDI link, so just set DP M/N
4660 according to current link config */
e3aef172 4661 if (is_cpu_edp) {
e3aef172 4662 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297 4663 } else {
8febb297
EA		 4664 /* FDI is a binary signal running at ~2.7GHz, encoding
4665 * each output octet as 10 bits. The actual frequency
4666 * is stored as a divider into a 100MHz clock, and the
4667 * mode pixel clock is stored in units of 1KHz.
4668 * Hence the bw of each lane in terms of the mode signal
4669 * is:
4670 */
4671 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4672 }
58a27471 4673
94bf2ced
DV		 4674 /* [e]DP over FDI requires target mode clock instead of link clock. */
4675 if (edp_encoder)
4676 target_clock = intel_edp_target_clock(edp_encoder, mode);
4677 else if (is_dp)
4678 target_clock = mode->clock;
4679 else
4680 target_clock = adjusted_mode->clock;
4681
8febb297
EA		 4682 /* determine panel color depth */
4683 temp = I915_READ(PIPECONF(pipe));
4684 temp &= ~PIPE_BPC_MASK;
3b5c78a3 4685 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5a354204
JB		 4686 switch (pipe_bpp) {
4687 case 18:
4688 temp |= PIPE_6BPC;
8febb297 4689 break;
5a354204
JB		 4690 case 24:
4691 temp |= PIPE_8BPC;
8febb297 4692 break;
5a354204
JB		 4693 case 30:
4694 temp |= PIPE_10BPC;
8febb297 4695 break;
5a354204
JB		 4696 case 36:
4697 temp |= PIPE_12BPC;
8febb297
EA		 4698 break;
4699 default:
62ac41a6
JB		 4700 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4701 pipe_bpp);
5a354204
JB		 4702 temp |= PIPE_8BPC;
4703 pipe_bpp = 24;
4704 break;
8febb297 4705 }
77ffb597 4706
5a354204
JB		 4707 intel_crtc->bpp = pipe_bpp;
4708 I915_WRITE(PIPECONF(pipe), temp);
4709
8febb297
EA		 4710 if (!lane) {
4711 /*
4712 * Account for spread spectrum to avoid
4713 * oversubscribing the link. Max center spread
4714 * is 2.5%; use 5% for safety's sake.
4715 */
5a354204 4716 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 4717 lane = bps / (link_bw * 8) + 1;
5eb08b69 4718 }
2c07245f 4719
8febb297
EA		 4720 intel_crtc->fdi_lanes = lane;
4721
4722 if (pixel_multiplier > 1)
4723 link_bw *= pixel_multiplier;
5a354204
JB		 4724 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4725 &m_n);
8febb297 4726
a07d6787
EA		 4727 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4728 if (has_reduced_clock)
4729 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4730 reduced_clock.m2;
79e53945 4731
c1858123 4732 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 4733 factor = 21;
4734 if (is_lvds) {
4735 if ((intel_panel_use_ssc(dev_priv) &&
4736 dev_priv->lvds_ssc_freq == 100) ||
4737 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4738 factor = 25;
4739 } else if (is_sdvo && is_tv)
4740 factor = 20;
c1858123 4741
cb0e0931 4742 if (clock.m < factor * clock.n)
8febb297 4743 fp |= FP_CB_TUNE;
2c07245f 4744
5eddb70b 4745 dpll = 0;
2c07245f 4746
a07d6787
EA		 4747 if (is_lvds)
4748 dpll |= DPLLB_MODE_LVDS;
4749 else
4750 dpll |= DPLLB_MODE_DAC_SERIAL;
4751 if (is_sdvo) {
4752 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4753 if (pixel_multiplier > 1) {
4754 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 4755 }
a07d6787
EA		 4756 dpll |= DPLL_DVO_HIGH_SPEED;
4757 }
e3aef172 4758 if (is_dp && !is_cpu_edp)
a07d6787 4759 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4760
a07d6787
EA		 4761 /* compute bitmask from p1 value */
4762 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4763 /* also FPA1 */
4764 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4765
4766 switch (clock.p2) {
4767 case 5:
4768 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4769 break;
4770 case 7:
4771 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4772 break;
4773 case 10:
4774 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4775 break;
4776 case 14:
4777 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4778 break;
79e53945
JB		 4779 }
4780
43565a06
KH		 4781 if (is_sdvo && is_tv)
4782 dpll |= PLL_REF_INPUT_TVCLKINBC;
4783 else if (is_tv)
79e53945 4784 /* XXX: just matching BIOS for now */
43565a06 4785 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4786 dpll |= 3;
a7615030 4787 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4788 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4789 else
4790 dpll |= PLL_REF_INPUT_DREFCLK;
4791
4792 /* setup pipeconf */
5eddb70b 4793 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4794
4795 /* Set up the display plane register */
4796 dspcntr = DISPPLANE_GAMMA_ENABLE;
4797
f7cb34d4 4798 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 4799 drm_mode_debug_printmodeline(mode);
4800
9d82aa17
ED		 4801 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4802 * pre-Haswell/LPT generation */
4803 if (HAS_PCH_LPT(dev)) {
4804 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4805 pipe);
4806 } else if (!is_cpu_edp) {
ee7b9f93 4807 struct intel_pch_pll *pll;
4b645f14 4808
ee7b9f93
JB		 4809 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4810 if (pll == NULL) {
4811 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4812 pipe);
4b645f14
JB		 4813 return -EINVAL;
4814 }
ee7b9f93
JB		 4815 } else
4816 intel_put_pch_pll(intel_crtc);
79e53945
JB		 4817
4818 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4819 * This is an exception to the general rule that mode_set doesn't turn
4820 * things on.
4821 */
4822 if (is_lvds) {
fae14981 4823 temp = I915_READ(PCH_LVDS);
5eddb70b 4824 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 4825 if (HAS_PCH_CPT(dev)) {
4826 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 4827 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 4828 } else {
4829 if (pipe == 1)
4830 temp |= LVDS_PIPEB_SELECT;
4831 else
4832 temp &= ~LVDS_PIPEB_SELECT;
4833 }
4b645f14 4834
a3e17eb8 4835 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 4836 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 4837 /* Set the B0-B3 data pairs corresponding to whether we're going to
4838 * set the DPLLs for dual-channel mode or not.
4839 */
4840 if (clock.p2 == 7)
5eddb70b 4841 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 4842 else
5eddb70b 4843 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 4844
4845 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4846 * appropriately here, but we need to look more thoroughly into how
4847 * panels behave in the two modes.
4848 */
284d5df5 4849 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 4850 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4851 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 4852 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4853 temp |= LVDS_VSYNC_POLARITY;
fae14981 4854 I915_WRITE(PCH_LVDS, temp);
79e53945 4855 }
434ed097 4856
8febb297
EA		 4857 pipeconf &= ~PIPECONF_DITHER_EN;
4858 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 4859 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297 4860 pipeconf |= PIPECONF_DITHER_EN;
f74974c7 4861 pipeconf |= PIPECONF_DITHER_TYPE_SP;
434ed097 4862 }
e3aef172 4863 if (is_dp && !is_cpu_edp) {
a4fc5ed6 4864 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 4865 } else {
8db9d77b 4866 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 4867 I915_WRITE(TRANSDATA_M1(pipe), 0);
4868 I915_WRITE(TRANSDATA_N1(pipe), 0);
4869 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4870 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 4871 }
79e53945 4872
ee7b9f93
JB		 4873 if (intel_crtc->pch_pll) {
4874 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 4875
32f9d658 4876 /* Wait for the clocks to stabilize. */
ee7b9f93 4877 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 4878 udelay(150);
4879
8febb297
EA		 4880 /* The pixel multiplier can only be updated once the
4881 * DPLL is enabled and the clocks are stable.
4882 *
4883 * So write it again.
4884 */
ee7b9f93 4885 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 4886 }
79e53945 4887
5eddb70b 4888 intel_crtc->lowfreq_avail = false;
ee7b9f93 4889 if (intel_crtc->pch_pll) {
4b645f14 4890 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 4891 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 4892 intel_crtc->lowfreq_avail = true;
4b645f14 4893 } else {
ee7b9f93 4894 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 4895 }
4896 }
4897
617cf884 4898 pipeconf &= ~PIPECONF_INTERLACE_MASK;
734b4157 4899 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5def474e 4900 pipeconf |= PIPECONF_INTERLACED_ILK;
734b4157 4901 /* the chip adds 2 halflines automatically */
734b4157 4902 adjusted_mode->crtc_vtotal -= 1;
734b4157 4903 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 4904 I915_WRITE(VSYNCSHIFT(pipe),
4905 adjusted_mode->crtc_hsync_start
4906 - adjusted_mode->crtc_htotal/2);
4907 } else {
617cf884 4908 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 4909 I915_WRITE(VSYNCSHIFT(pipe), 0);
4910 }
734b4157 4911
5eddb70b
CW		 4912 I915_WRITE(HTOTAL(pipe),
4913 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4914 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4915 I915_WRITE(HBLANK(pipe),
4916 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4917 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4918 I915_WRITE(HSYNC(pipe),
4919 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4920 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4921
4922 I915_WRITE(VTOTAL(pipe),
4923 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4924 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4925 I915_WRITE(VBLANK(pipe),
4926 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4927 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4928 I915_WRITE(VSYNC(pipe),
4929 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4930 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 4931
8febb297
EA		 4932 /* pipesrc controls the size that is scaled from, which should
4933 * always be the user's requested size.
79e53945 4934 */
5eddb70b
CW		 4935 I915_WRITE(PIPESRC(pipe),
4936 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4937
8febb297
EA		 4938 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4939 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4940 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4941 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 4942
e3aef172 4943 if (is_cpu_edp)
8febb297 4944 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 4945
5eddb70b
CW		 4946 I915_WRITE(PIPECONF(pipe), pipeconf);
4947 POSTING_READ(PIPECONF(pipe));
79e53945 4948
9d0498a2 4949 intel_wait_for_vblank(dev, pipe);
79e53945 4950
5eddb70b 4951 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 4952 POSTING_READ(DSPCNTR(plane));
79e53945 4953
5c3b82e2 4954 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 4955
4956 intel_update_watermarks(dev);
4957
1f8eeabf
ED		 4958 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
4959
1f803ee5 4960 return ret;
79e53945
JB		 4961}
4962
f564048e
EA		 4963static int intel_crtc_mode_set(struct drm_crtc *crtc,
4964 struct drm_display_mode *mode,
4965 struct drm_display_mode *adjusted_mode,
4966 int x, int y,
4967 struct drm_framebuffer *old_fb)
4968{
4969 struct drm_device *dev = crtc->dev;
4970 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 4971 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4972 int pipe = intel_crtc->pipe;
f564048e
EA		 4973 int ret;
4974
0b701d27 4975 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 4976
f564048e
EA		 4977 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4978 x, y, old_fb);
79e53945 4979 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 4980
d8e70a25
JB		 4981 if (ret)
4982 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4983 else
4984 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
120eced9 4985
1f803ee5 4986 return ret;
79e53945
JB		 4987}
4988
3a9627f4
WF		 4989static bool intel_eld_uptodate(struct drm_connector *connector,
4990 int reg_eldv, uint32_t bits_eldv,
4991 int reg_elda, uint32_t bits_elda,
4992 int reg_edid)
4993{
4994 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4995 uint8_t *eld = connector->eld;
4996 uint32_t i;
4997
4998 i = I915_READ(reg_eldv);
4999 i &= bits_eldv;
5000
5001 if (!eld[0])
5002 return !i;
5003
5004 if (!i)
5005 return false;
5006
5007 i = I915_READ(reg_elda);
5008 i &= ~bits_elda;
5009 I915_WRITE(reg_elda, i);
5010
5011 for (i = 0; i < eld[2]; i++)
5012 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5013 return false;
5014
5015 return true;
5016}
5017
e0dac65e
WF		 5018static void g4x_write_eld(struct drm_connector *connector,
5019 struct drm_crtc *crtc)
5020{
5021 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5022 uint8_t *eld = connector->eld;
5023 uint32_t eldv;
5024 uint32_t len;
5025 uint32_t i;
5026
5027 i = I915_READ(G4X_AUD_VID_DID);
5028
5029 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5030 eldv = G4X_ELDV_DEVCL_DEVBLC;
5031 else
5032 eldv = G4X_ELDV_DEVCTG;
5033
3a9627f4
WF		 5034 if (intel_eld_uptodate(connector,
5035 G4X_AUD_CNTL_ST, eldv,
5036 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5037 G4X_HDMIW_HDMIEDID))
5038 return;
5039
e0dac65e
WF		 5040 i = I915_READ(G4X_AUD_CNTL_ST);
5041 i &= ~(eldv | G4X_ELD_ADDR);
5042 len = (i >> 9) & 0x1f; /* ELD buffer size */
5043 I915_WRITE(G4X_AUD_CNTL_ST, i);
5044
5045 if (!eld[0])
5046 return;
5047
5048 len = min_t(uint8_t, eld[2], len);
5049 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5050 for (i = 0; i < len; i++)
5051 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5052
5053 i = I915_READ(G4X_AUD_CNTL_ST);
5054 i |= eldv;
5055 I915_WRITE(G4X_AUD_CNTL_ST, i);
5056}
5057
5058static void ironlake_write_eld(struct drm_connector *connector,
5059 struct drm_crtc *crtc)
5060{
5061 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5062 uint8_t *eld = connector->eld;
5063 uint32_t eldv;
5064 uint32_t i;
5065 int len;
5066 int hdmiw_hdmiedid;
b6daa025 5067 int aud_config;
e0dac65e
WF		 5068 int aud_cntl_st;
5069 int aud_cntrl_st2;
5070
b3f33cbf 5071 if (HAS_PCH_IBX(connector->dev)) {
1202b4c6 5072 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
b6daa025 5073 aud_config = IBX_AUD_CONFIG_A;
1202b4c6
WF		 5074 aud_cntl_st = IBX_AUD_CNTL_ST_A;
5075 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 5076 } else {
1202b4c6 5077 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
b6daa025 5078 aud_config = CPT_AUD_CONFIG_A;
1202b4c6
WF		 5079 aud_cntl_st = CPT_AUD_CNTL_ST_A;
5080 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 5081 }
5082
5083 i = to_intel_crtc(crtc)->pipe;
5084 hdmiw_hdmiedid += i * 0x100;
5085 aud_cntl_st += i * 0x100;
b6daa025 5086 aud_config += i * 0x100;
e0dac65e
WF		 5087
5088 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
5089
5090 i = I915_READ(aud_cntl_st);
5091 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
5092 if (!i) {
5093 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5094 /* operate blindly on all ports */
1202b4c6
WF		 5095 eldv = IBX_ELD_VALIDB;
5096 eldv |= IBX_ELD_VALIDB << 4;
5097 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 5098 } else {
5099 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 5100 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 5101 }
5102
3a9627f4
WF		 5103 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5104 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5105 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 5106 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5107 } else
5108 I915_WRITE(aud_config, 0);
e0dac65e 5109
3a9627f4
WF		 5110 if (intel_eld_uptodate(connector,
5111 aud_cntrl_st2, eldv,
5112 aud_cntl_st, IBX_ELD_ADDRESS,
5113 hdmiw_hdmiedid))
5114 return;
5115
e0dac65e
WF		 5116 i = I915_READ(aud_cntrl_st2);
5117 i &= ~eldv;
5118 I915_WRITE(aud_cntrl_st2, i);
5119
5120 if (!eld[0])
5121 return;
5122
e0dac65e 5123 i = I915_READ(aud_cntl_st);
1202b4c6 5124 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 5125 I915_WRITE(aud_cntl_st, i);
5126
5127 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5128 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5129 for (i = 0; i < len; i++)
5130 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5131
5132 i = I915_READ(aud_cntrl_st2);
5133 i |= eldv;
5134 I915_WRITE(aud_cntrl_st2, i);
5135}
5136
5137void intel_write_eld(struct drm_encoder *encoder,
5138 struct drm_display_mode *mode)
5139{
5140 struct drm_crtc *crtc = encoder->crtc;
5141 struct drm_connector *connector;
5142 struct drm_device *dev = encoder->dev;
5143 struct drm_i915_private *dev_priv = dev->dev_private;
5144
5145 connector = drm_select_eld(encoder, mode);
5146 if (!connector)
5147 return;
5148
5149 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5150 connector->base.id,
5151 drm_get_connector_name(connector),
5152 connector->encoder->base.id,
5153 drm_get_encoder_name(connector->encoder));
5154
5155 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5156
5157 if (dev_priv->display.write_eld)
5158 dev_priv->display.write_eld(connector, crtc);
5159}
5160
79e53945
JB		 5161/** Loads the palette/gamma unit for the CRTC with the prepared values */
5162void intel_crtc_load_lut(struct drm_crtc *crtc)
5163{
5164 struct drm_device *dev = crtc->dev;
5165 struct drm_i915_private *dev_priv = dev->dev_private;
5166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5167 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5168 int i;
5169
5170 /* The clocks have to be on to load the palette. */
aed3f09d 5171 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 5172 return;
5173
f2b115e6 5174 /* use legacy palette for Ironlake */
bad720ff 5175 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5176 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5177
79e53945
JB		 5178 for (i = 0; i < 256; i++) {
5179 I915_WRITE(palreg + 4 * i,
5180 (intel_crtc->lut_r[i] << 16) |
5181 (intel_crtc->lut_g[i] << 8) |
5182 intel_crtc->lut_b[i]);
5183 }
5184}
5185
560b85bb
CW		 5186static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5187{
5188 struct drm_device *dev = crtc->dev;
5189 struct drm_i915_private *dev_priv = dev->dev_private;
5190 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5191 bool visible = base != 0;
5192 u32 cntl;
5193
5194 if (intel_crtc->cursor_visible == visible)
5195 return;
5196
9db4a9c7 5197 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5198 if (visible) {
5199 /* On these chipsets we can only modify the base whilst
5200 * the cursor is disabled.
5201 */
9db4a9c7 5202 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5203
5204 cntl &= ~(CURSOR_FORMAT_MASK);
5205 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5206 cntl |= CURSOR_ENABLE |
5207 CURSOR_GAMMA_ENABLE |
5208 CURSOR_FORMAT_ARGB;
5209 } else
5210 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 5211 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 5212
5213 intel_crtc->cursor_visible = visible;
5214}
5215
5216static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5217{
5218 struct drm_device *dev = crtc->dev;
5219 struct drm_i915_private *dev_priv = dev->dev_private;
5220 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5221 int pipe = intel_crtc->pipe;
5222 bool visible = base != 0;
5223
5224 if (intel_crtc->cursor_visible != visible) {
548f245b 5225 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 5226 if (base) {
5227 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5228 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5229 cntl |= pipe << 28; /* Connect to correct pipe */
5230 } else {
5231 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5232 cntl |= CURSOR_MODE_DISABLE;
5233 }
9db4a9c7 5234 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 5235
5236 intel_crtc->cursor_visible = visible;
5237 }
5238 /* and commit changes on next vblank */
9db4a9c7 5239 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 5240}
5241
65a21cd6
JB		 5242static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5243{
5244 struct drm_device *dev = crtc->dev;
5245 struct drm_i915_private *dev_priv = dev->dev_private;
5246 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5247 int pipe = intel_crtc->pipe;
5248 bool visible = base != 0;
5249
5250 if (intel_crtc->cursor_visible != visible) {
5251 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5252 if (base) {
5253 cntl &= ~CURSOR_MODE;
5254 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5255 } else {
5256 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5257 cntl |= CURSOR_MODE_DISABLE;
5258 }
5259 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5260
5261 intel_crtc->cursor_visible = visible;
5262 }
5263 /* and commit changes on next vblank */
5264 I915_WRITE(CURBASE_IVB(pipe), base);
5265}
5266
cda4b7d3 5267/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5268static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5269 bool on)
cda4b7d3
CW		 5270{
5271 struct drm_device *dev = crtc->dev;
5272 struct drm_i915_private *dev_priv = dev->dev_private;
5273 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5274 int pipe = intel_crtc->pipe;
5275 int x = intel_crtc->cursor_x;
5276 int y = intel_crtc->cursor_y;
560b85bb 5277 u32 base, pos;
cda4b7d3
CW		 5278 bool visible;
5279
5280 pos = 0;
5281
6b383a7f 5282 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5283 base = intel_crtc->cursor_addr;
5284 if (x > (int) crtc->fb->width)
5285 base = 0;
5286
5287 if (y > (int) crtc->fb->height)
5288 base = 0;
5289 } else
5290 base = 0;
5291
5292 if (x < 0) {
5293 if (x + intel_crtc->cursor_width < 0)
5294 base = 0;
5295
5296 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5297 x = -x;
5298 }
5299 pos |= x << CURSOR_X_SHIFT;
5300
5301 if (y < 0) {
5302 if (y + intel_crtc->cursor_height < 0)
5303 base = 0;
5304
5305 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5306 y = -y;
5307 }
5308 pos |= y << CURSOR_Y_SHIFT;
5309
5310 visible = base != 0;
560b85bb 5311 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 5312 return;
5313
0cd83aa9 5314 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 5315 I915_WRITE(CURPOS_IVB(pipe), pos);
5316 ivb_update_cursor(crtc, base);
5317 } else {
5318 I915_WRITE(CURPOS(pipe), pos);
5319 if (IS_845G(dev) || IS_I865G(dev))
5320 i845_update_cursor(crtc, base);
5321 else
5322 i9xx_update_cursor(crtc, base);
5323 }
cda4b7d3
CW		 5324}
5325
79e53945 5326static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 5327 struct drm_file *file,
79e53945
JB		 5328 uint32_t handle,
5329 uint32_t width, uint32_t height)
5330{
5331 struct drm_device *dev = crtc->dev;
5332 struct drm_i915_private *dev_priv = dev->dev_private;
5333 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 5334 struct drm_i915_gem_object *obj;
cda4b7d3 5335 uint32_t addr;
3f8bc370 5336 int ret;
79e53945 5337
28c97730 5338 DRM_DEBUG_KMS("\n");
79e53945
JB		 5339
5340 /* if we want to turn off the cursor ignore width and height */
5341 if (!handle) {
28c97730 5342 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 5343 addr = 0;
05394f39 5344 obj = NULL;
5004417d 5345 mutex_lock(&dev->struct_mutex);
3f8bc370 5346 goto finish;
79e53945
JB		 5347 }
5348
5349 /* Currently we only support 64x64 cursors */
5350 if (width != 64 || height != 64) {
5351 DRM_ERROR("we currently only support 64x64 cursors\n");
5352 return -EINVAL;
5353 }
5354
05394f39 5355 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 5356 if (&obj->base == NULL)
79e53945
JB		 5357 return -ENOENT;
5358
05394f39 5359 if (obj->base.size < width * height * 4) {
79e53945 5360 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 5361 ret = -ENOMEM;
5362 goto fail;
79e53945
JB		 5363 }
5364
71acb5eb 5365 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 5366 mutex_lock(&dev->struct_mutex);
b295d1b6 5367 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 5368 if (obj->tiling_mode) {
5369 DRM_ERROR("cursor cannot be tiled\n");
5370 ret = -EINVAL;
5371 goto fail_locked;
5372 }
5373
2da3b9b9 5374 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 5375 if (ret) {
5376 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 5377 goto fail_locked;
e7b526bb
CW		 5378 }
5379
d9e86c0e
CW		 5380 ret = i915_gem_object_put_fence(obj);
5381 if (ret) {
2da3b9b9 5382 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 5383 goto fail_unpin;
5384 }
5385
05394f39 5386 addr = obj->gtt_offset;
71acb5eb 5387 } else {
6eeefaf3 5388 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 5389 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 5390 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5391 align);
71acb5eb
DA		 5392 if (ret) {
5393 DRM_ERROR("failed to attach phys object\n");
7f9872e0 5394 goto fail_locked;
71acb5eb 5395 }
05394f39 5396 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 5397 }
5398
a6c45cf0 5399 if (IS_GEN2(dev))
14b60391
JB		 5400 I915_WRITE(CURSIZE, (height << 12) | width);
5401
3f8bc370 5402 finish:
3f8bc370 5403 if (intel_crtc->cursor_bo) {
b295d1b6 5404 if (dev_priv->info->cursor_needs_physical) {
05394f39 5405 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 5406 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5407 } else
5408 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 5409 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 5410 }
80824003 5411
7f9872e0 5412 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 5413
5414 intel_crtc->cursor_addr = addr;
05394f39 5415 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 5416 intel_crtc->cursor_width = width;
5417 intel_crtc->cursor_height = height;
5418
6b383a7f 5419 intel_crtc_update_cursor(crtc, true);
3f8bc370 5420
79e53945 5421 return 0;
e7b526bb 5422fail_unpin:
05394f39 5423 i915_gem_object_unpin(obj);
7f9872e0 5424fail_locked:
34b8686e 5425 mutex_unlock(&dev->struct_mutex);
bc9025bd 5426fail:
05394f39 5427 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 5428 return ret;
79e53945
JB		 5429}
5430
5431static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5432{
79e53945 5433 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5434
cda4b7d3
CW		 5435 intel_crtc->cursor_x = x;
5436 intel_crtc->cursor_y = y;
652c393a 5437
6b383a7f 5438 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 5439
5440 return 0;
5441}
5442
5443/** Sets the color ramps on behalf of RandR */
5444void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5445 u16 blue, int regno)
5446{
5447 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5448
5449 intel_crtc->lut_r[regno] = red >> 8;
5450 intel_crtc->lut_g[regno] = green >> 8;
5451 intel_crtc->lut_b[regno] = blue >> 8;
5452}
5453
b8c00ac5
DA		 5454void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5455 u16 *blue, int regno)
5456{
5457 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5458
5459 *red = intel_crtc->lut_r[regno] << 8;
5460 *green = intel_crtc->lut_g[regno] << 8;
5461 *blue = intel_crtc->lut_b[regno] << 8;
5462}
5463
79e53945 5464static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 5465 u16 *blue, uint32_t start, uint32_t size)
79e53945 5466{
7203425a 5467 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 5468 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5469
7203425a 5470 for (i = start; i < end; i++) {
79e53945
JB		 5471 intel_crtc->lut_r[i] = red[i] >> 8;
5472 intel_crtc->lut_g[i] = green[i] >> 8;
5473 intel_crtc->lut_b[i] = blue[i] >> 8;
5474 }
5475
5476 intel_crtc_load_lut(crtc);
5477}
5478
5479/**
5480 * Get a pipe with a simple mode set on it for doing load-based monitor
5481 * detection.
5482 *
5483 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5484 * its requirements. The pipe will be connected to no other encoders.
79e53945 5485 *
c751ce4f 5486 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5487 * configured for it. In the future, it could choose to temporarily disable
5488 * some outputs to free up a pipe for its use.
5489 *
5490 * \return crtc, or NULL if no pipes are available.
5491 */
5492
5493/* VESA 640x480x72Hz mode to set on the pipe */
5494static struct drm_display_mode load_detect_mode = {
5495 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5496 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5497};
5498
d2dff872
CW		 5499static struct drm_framebuffer *
5500intel_framebuffer_create(struct drm_device *dev,
308e5bcb 5501 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 5502 struct drm_i915_gem_object *obj)
5503{
5504 struct intel_framebuffer *intel_fb;
5505 int ret;
5506
5507 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5508 if (!intel_fb) {
5509 drm_gem_object_unreference_unlocked(&obj->base);
5510 return ERR_PTR(-ENOMEM);
5511 }
5512
5513 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5514 if (ret) {
5515 drm_gem_object_unreference_unlocked(&obj->base);
5516 kfree(intel_fb);
5517 return ERR_PTR(ret);
5518 }
5519
5520 return &intel_fb->base;
5521}
5522
5523static u32
5524intel_framebuffer_pitch_for_width(int width, int bpp)
5525{
5526 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5527 return ALIGN(pitch, 64);
5528}
5529
5530static u32
5531intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5532{
5533 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5534 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5535}
5536
5537static struct drm_framebuffer *
5538intel_framebuffer_create_for_mode(struct drm_device *dev,
5539 struct drm_display_mode *mode,
5540 int depth, int bpp)
5541{
5542 struct drm_i915_gem_object *obj;
308e5bcb 5543 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 5544
5545 obj = i915_gem_alloc_object(dev,
5546 intel_framebuffer_size_for_mode(mode, bpp));
5547 if (obj == NULL)
5548 return ERR_PTR(-ENOMEM);
5549
5550 mode_cmd.width = mode->hdisplay;
5551 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 5552 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5553 bpp);
5ca0c34a 5554 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 5555
5556 return intel_framebuffer_create(dev, &mode_cmd, obj);
5557}
5558
5559static struct drm_framebuffer *
5560mode_fits_in_fbdev(struct drm_device *dev,
5561 struct drm_display_mode *mode)
5562{
5563 struct drm_i915_private *dev_priv = dev->dev_private;
5564 struct drm_i915_gem_object *obj;
5565 struct drm_framebuffer *fb;
5566
5567 if (dev_priv->fbdev == NULL)
5568 return NULL;
5569
5570 obj = dev_priv->fbdev->ifb.obj;
5571 if (obj == NULL)
5572 return NULL;
5573
5574 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 5575 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5576 fb->bits_per_pixel))
d2dff872
CW		 5577 return NULL;
5578
01f2c773 5579 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 5580 return NULL;
5581
5582 return fb;
5583}
5584
7173188d
CW		 5585bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5586 struct drm_connector *connector,
5587 struct drm_display_mode *mode,
8261b191 5588 struct intel_load_detect_pipe *old)
79e53945
JB		 5589{
5590 struct intel_crtc *intel_crtc;
5591 struct drm_crtc *possible_crtc;
4ef69c7a 5592 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5593 struct drm_crtc *crtc = NULL;
5594 struct drm_device *dev = encoder->dev;
d2dff872 5595 struct drm_framebuffer *old_fb;
79e53945
JB		 5596 int i = -1;
5597
d2dff872
CW		 5598 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5599 connector->base.id, drm_get_connector_name(connector),
5600 encoder->base.id, drm_get_encoder_name(encoder));
5601
79e53945
JB		 5602 /*
5603 * Algorithm gets a little messy:
7a5e4805 5604 *
79e53945
JB		 5605 * - if the connector already has an assigned crtc, use it (but make
5606 * sure it's on first)
7a5e4805 5607 *
79e53945
JB		 5608 * - try to find the first unused crtc that can drive this connector,
5609 * and use that if we find one
79e53945
JB		 5610 */
5611
5612 /* See if we already have a CRTC for this connector */
5613 if (encoder->crtc) {
5614 crtc = encoder->crtc;
8261b191 5615
79e53945 5616 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5617 old->dpms_mode = intel_crtc->dpms_mode;
5618 old->load_detect_temp = false;
5619
5620 /* Make sure the crtc and connector are running */
79e53945 5621 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 5622 struct drm_encoder_helper_funcs *encoder_funcs;
5623 struct drm_crtc_helper_funcs *crtc_funcs;
5624
79e53945
JB		 5625 crtc_funcs = crtc->helper_private;
5626 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 5627
5628 encoder_funcs = encoder->helper_private;
79e53945
JB		 5629 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5630 }
8261b191 5631
7173188d 5632 return true;
79e53945
JB		 5633 }
5634
5635 /* Find an unused one (if possible) */
5636 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5637 i++;
5638 if (!(encoder->possible_crtcs & (1 << i)))
5639 continue;
5640 if (!possible_crtc->enabled) {
5641 crtc = possible_crtc;
5642 break;
5643 }
79e53945
JB		 5644 }
5645
5646 /*
5647 * If we didn't find an unused CRTC, don't use any.
5648 */
5649 if (!crtc) {
7173188d
CW		 5650 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5651 return false;
79e53945
JB		 5652 }
5653
5654 encoder->crtc = crtc;
c1c43977 5655 connector->encoder = encoder;
79e53945
JB		 5656
5657 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5658 old->dpms_mode = intel_crtc->dpms_mode;
5659 old->load_detect_temp = true;
d2dff872 5660 old->release_fb = NULL;
79e53945 5661
6492711d
CW		 5662 if (!mode)
5663 mode = &load_detect_mode;
79e53945 5664
d2dff872
CW		 5665 old_fb = crtc->fb;
5666
5667 /* We need a framebuffer large enough to accommodate all accesses
5668 * that the plane may generate whilst we perform load detection.
5669 * We can not rely on the fbcon either being present (we get called
5670 * during its initialisation to detect all boot displays, or it may
5671 * not even exist) or that it is large enough to satisfy the
5672 * requested mode.
5673 */
5674 crtc->fb = mode_fits_in_fbdev(dev, mode);
5675 if (crtc->fb == NULL) {
5676 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5677 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5678 old->release_fb = crtc->fb;
5679 } else
5680 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5681 if (IS_ERR(crtc->fb)) {
5682 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5683 crtc->fb = old_fb;
5684 return false;
79e53945 5685 }
79e53945 5686
d2dff872 5687 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 5688 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 5689 if (old->release_fb)
5690 old->release_fb->funcs->destroy(old->release_fb);
5691 crtc->fb = old_fb;
6492711d 5692 return false;
79e53945 5693 }
7173188d 5694
79e53945 5695 /* let the connector get through one full cycle before testing */
9d0498a2 5696 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 5697
7173188d 5698 return true;
79e53945
JB		 5699}
5700
c1c43977 5701void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 5702 struct drm_connector *connector,
5703 struct intel_load_detect_pipe *old)
79e53945 5704{
4ef69c7a 5705 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5706 struct drm_device *dev = encoder->dev;
5707 struct drm_crtc *crtc = encoder->crtc;
5708 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5709 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5710
d2dff872
CW		 5711 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5712 connector->base.id, drm_get_connector_name(connector),
5713 encoder->base.id, drm_get_encoder_name(encoder));
5714
8261b191 5715 if (old->load_detect_temp) {
c1c43977 5716 connector->encoder = NULL;
79e53945 5717 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 5718
5719 if (old->release_fb)
5720 old->release_fb->funcs->destroy(old->release_fb);
5721
0622a53c 5722 return;
79e53945
JB		 5723 }
5724
c751ce4f 5725 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 5726 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5727 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 5728 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 5729 }
5730}
5731
5732/* Returns the clock of the currently programmed mode of the given pipe. */
5733static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5734{
5735 struct drm_i915_private *dev_priv = dev->dev_private;
5736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5737 int pipe = intel_crtc->pipe;
548f245b 5738 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 5739 u32 fp;
5740 intel_clock_t clock;
5741
5742 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 5743 fp = I915_READ(FP0(pipe));
79e53945 5744 else
39adb7a5 5745 fp = I915_READ(FP1(pipe));
79e53945
JB		 5746
5747 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 5748 if (IS_PINEVIEW(dev)) {
5749 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5750 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 5751 } else {
5752 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5753 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5754 }
5755
a6c45cf0 5756 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 5757 if (IS_PINEVIEW(dev))
5758 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5759 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 5760 else
5761 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 5762 DPLL_FPA01_P1_POST_DIV_SHIFT);
5763
5764 switch (dpll & DPLL_MODE_MASK) {
5765 case DPLLB_MODE_DAC_SERIAL:
5766 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5767 5 : 10;
5768 break;
5769 case DPLLB_MODE_LVDS:
5770 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5771 7 : 14;
5772 break;
5773 default:
28c97730 5774 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 5775 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5776 return 0;
5777 }
5778
5779 /* XXX: Handle the 100Mhz refclk */
2177832f 5780 intel_clock(dev, 96000, &clock);
79e53945
JB		 5781 } else {
5782 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5783
5784 if (is_lvds) {
5785 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5786 DPLL_FPA01_P1_POST_DIV_SHIFT);
5787 clock.p2 = 14;
5788
5789 if ((dpll & PLL_REF_INPUT_MASK) ==
5790 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5791 /* XXX: might not be 66MHz */
2177832f 5792 intel_clock(dev, 66000, &clock);
79e53945 5793 } else
2177832f 5794 intel_clock(dev, 48000, &clock);
79e53945
JB		 5795 } else {
5796 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5797 clock.p1 = 2;
5798 else {
5799 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5800 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5801 }
5802 if (dpll & PLL_P2_DIVIDE_BY_4)
5803 clock.p2 = 4;
5804 else
5805 clock.p2 = 2;
5806
2177832f 5807 intel_clock(dev, 48000, &clock);
79e53945
JB		 5808 }
5809 }
5810
5811 /* XXX: It would be nice to validate the clocks, but we can't reuse
5812 * i830PllIsValid() because it relies on the xf86_config connector
5813 * configuration being accurate, which it isn't necessarily.
5814 */
5815
5816 return clock.dot;
5817}
5818
5819/** Returns the currently programmed mode of the given pipe. */
5820struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5821 struct drm_crtc *crtc)
5822{
548f245b 5823 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 5824 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5825 int pipe = intel_crtc->pipe;
5826 struct drm_display_mode *mode;
548f245b
JB		 5827 int htot = I915_READ(HTOTAL(pipe));
5828 int hsync = I915_READ(HSYNC(pipe));
5829 int vtot = I915_READ(VTOTAL(pipe));
5830 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 5831
5832 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5833 if (!mode)
5834 return NULL;
5835
5836 mode->clock = intel_crtc_clock_get(dev, crtc);
5837 mode->hdisplay = (htot & 0xffff) + 1;
5838 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5839 mode->hsync_start = (hsync & 0xffff) + 1;
5840 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5841 mode->vdisplay = (vtot & 0xffff) + 1;
5842 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5843 mode->vsync_start = (vsync & 0xffff) + 1;
5844 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5845
5846 drm_mode_set_name(mode);
79e53945
JB		 5847
5848 return mode;
5849}
5850
652c393a
JB		 5851#define GPU_IDLE_TIMEOUT 500 /* ms */
5852
5853/* When this timer fires, we've been idle for awhile */
5854static void intel_gpu_idle_timer(unsigned long arg)
5855{
5856 struct drm_device *dev = (struct drm_device *)arg;
5857 drm_i915_private_t *dev_priv = dev->dev_private;
5858
ff7ea4c0
CW		 5859 if (!list_empty(&dev_priv->mm.active_list)) {
5860 /* Still processing requests, so just re-arm the timer. */
5861 mod_timer(&dev_priv->idle_timer, jiffies +
5862 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5863 return;
5864 }
652c393a 5865
ff7ea4c0 5866 dev_priv->busy = false;
01dfba93 5867 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5868}
5869
652c393a
JB		 5870#define CRTC_IDLE_TIMEOUT 1000 /* ms */
5871
5872static void intel_crtc_idle_timer(unsigned long arg)
5873{
5874 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5875 struct drm_crtc *crtc = &intel_crtc->base;
5876 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 5877 struct intel_framebuffer *intel_fb;
652c393a 5878
ff7ea4c0
CW		 5879 intel_fb = to_intel_framebuffer(crtc->fb);
5880 if (intel_fb && intel_fb->obj->active) {
5881 /* The framebuffer is still being accessed by the GPU. */
5882 mod_timer(&intel_crtc->idle_timer, jiffies +
5883 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5884 return;
5885 }
652c393a 5886
ff7ea4c0 5887 intel_crtc->busy = false;
01dfba93 5888 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5889}
5890
3dec0095 5891static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 5892{
5893 struct drm_device *dev = crtc->dev;
5894 drm_i915_private_t *dev_priv = dev->dev_private;
5895 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5896 int pipe = intel_crtc->pipe;
dbdc6479
JB		 5897 int dpll_reg = DPLL(pipe);
5898 int dpll;
652c393a 5899
bad720ff 5900 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5901 return;
5902
5903 if (!dev_priv->lvds_downclock_avail)
5904 return;
5905
dbdc6479 5906 dpll = I915_READ(dpll_reg);
652c393a 5907 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 5908 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 5909
8ac5a6d5 5910 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 5911
5912 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5913 I915_WRITE(dpll_reg, dpll);
9d0498a2 5914 intel_wait_for_vblank(dev, pipe);
dbdc6479 5915
652c393a
JB		 5916 dpll = I915_READ(dpll_reg);
5917 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 5918 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 5919 }
5920
5921 /* Schedule downclock */
3dec0095
DV		 5922 mod_timer(&intel_crtc->idle_timer, jiffies +
5923 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 5924}
5925
5926static void intel_decrease_pllclock(struct drm_crtc *crtc)
5927{
5928 struct drm_device *dev = crtc->dev;
5929 drm_i915_private_t *dev_priv = dev->dev_private;
5930 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 5931
bad720ff 5932 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5933 return;
5934
5935 if (!dev_priv->lvds_downclock_avail)
5936 return;
5937
5938 /*
5939 * Since this is called by a timer, we should never get here in
5940 * the manual case.
5941 */
5942 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 5943 int pipe = intel_crtc->pipe;
5944 int dpll_reg = DPLL(pipe);
5945 int dpll;
f6e5b160 5946
44d98a61 5947 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 5948
8ac5a6d5 5949 assert_panel_unlocked(dev_priv, pipe);
652c393a 5950
dc257cf1 5951 dpll = I915_READ(dpll_reg);
652c393a
JB		 5952 dpll |= DISPLAY_RATE_SELECT_FPA1;
5953 I915_WRITE(dpll_reg, dpll);
9d0498a2 5954 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 5955 dpll = I915_READ(dpll_reg);
5956 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 5957 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 5958 }
5959
5960}
5961
5962/**
5963 * intel_idle_update - adjust clocks for idleness
5964 * @work: work struct
5965 *
5966 * Either the GPU or display (or both) went idle. Check the busy status
5967 * here and adjust the CRTC and GPU clocks as necessary.
5968 */
5969static void intel_idle_update(struct work_struct *work)
5970{
5971 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5972 idle_work);
5973 struct drm_device *dev = dev_priv->dev;
5974 struct drm_crtc *crtc;
5975 struct intel_crtc *intel_crtc;
5976
5977 if (!i915_powersave)
5978 return;
5979
5980 mutex_lock(&dev->struct_mutex);
5981
7648fa99
JB		 5982 i915_update_gfx_val(dev_priv);
5983
652c393a
JB		 5984 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5985 /* Skip inactive CRTCs */
5986 if (!crtc->fb)
5987 continue;
5988
5989 intel_crtc = to_intel_crtc(crtc);
5990 if (!intel_crtc->busy)
5991 intel_decrease_pllclock(crtc);
5992 }
5993
45ac22c8 5994
652c393a
JB		 5995 mutex_unlock(&dev->struct_mutex);
5996}
5997
5998/**
5999 * intel_mark_busy - mark the GPU and possibly the display busy
6000 * @dev: drm device
6001 * @obj: object we're operating on
6002 *
6003 * Callers can use this function to indicate that the GPU is busy processing
6004 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6005 * buffer), we'll also mark the display as busy, so we know to increase its
6006 * clock frequency.
6007 */
05394f39 6008void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 6009{
6010 drm_i915_private_t *dev_priv = dev->dev_private;
6011 struct drm_crtc *crtc = NULL;
6012 struct intel_framebuffer *intel_fb;
6013 struct intel_crtc *intel_crtc;
6014
5e17ee74
ZW		 6015 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6016 return;
6017
9104183d
CW		 6018 if (!dev_priv->busy) {
6019 intel_sanitize_pm(dev);
28cf798f 6020 dev_priv->busy = true;
9104183d 6021 } else
28cf798f
CW		 6022 mod_timer(&dev_priv->idle_timer, jiffies +
6023 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a 6024
acb87dfb
CW		 6025 if (obj == NULL)
6026 return;
6027
652c393a
JB		 6028 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6029 if (!crtc->fb)
6030 continue;
6031
6032 intel_crtc = to_intel_crtc(crtc);
6033 intel_fb = to_intel_framebuffer(crtc->fb);
6034 if (intel_fb->obj == obj) {
6035 if (!intel_crtc->busy) {
6036 /* Non-busy -> busy, upclock */
3dec0095 6037 intel_increase_pllclock(crtc);
652c393a
JB		 6038 intel_crtc->busy = true;
6039 } else {
6040 /* Busy -> busy, put off timer */
6041 mod_timer(&intel_crtc->idle_timer, jiffies +
6042 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6043 }
6044 }
6045 }
6046}
6047
79e53945
JB		 6048static void intel_crtc_destroy(struct drm_crtc *crtc)
6049{
6050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6051 struct drm_device *dev = crtc->dev;
6052 struct intel_unpin_work *work;
6053 unsigned long flags;
6054
6055 spin_lock_irqsave(&dev->event_lock, flags);
6056 work = intel_crtc->unpin_work;
6057 intel_crtc->unpin_work = NULL;
6058 spin_unlock_irqrestore(&dev->event_lock, flags);
6059
6060 if (work) {
6061 cancel_work_sync(&work->work);
6062 kfree(work);
6063 }
79e53945
JB		 6064
6065 drm_crtc_cleanup(crtc);
67e77c5a 6066
79e53945
JB		 6067 kfree(intel_crtc);
6068}
6069
6b95a207
KH		 6070static void intel_unpin_work_fn(struct work_struct *__work)
6071{
6072 struct intel_unpin_work *work =
6073 container_of(__work, struct intel_unpin_work, work);
6074
6075 mutex_lock(&work->dev->struct_mutex);
1690e1eb 6076 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6077 drm_gem_object_unreference(&work->pending_flip_obj->base);
6078 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6079
7782de3b 6080 intel_update_fbc(work->dev);
6b95a207
KH		 6081 mutex_unlock(&work->dev->struct_mutex);
6082 kfree(work);
6083}
6084
1afe3e9d 6085static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6086 struct drm_crtc *crtc)
6b95a207
KH		 6087{
6088 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6090 struct intel_unpin_work *work;
05394f39 6091 struct drm_i915_gem_object *obj;
6b95a207 6092 struct drm_pending_vblank_event *e;
49b14a5c 6093 struct timeval tnow, tvbl;
6b95a207
KH		 6094 unsigned long flags;
6095
6096 /* Ignore early vblank irqs */
6097 if (intel_crtc == NULL)
6098 return;
6099
49b14a5c
MK		 6100 do_gettimeofday(&tnow);
6101
6b95a207
KH		 6102 spin_lock_irqsave(&dev->event_lock, flags);
6103 work = intel_crtc->unpin_work;
6104 if (work == NULL || !work->pending) {
6105 spin_unlock_irqrestore(&dev->event_lock, flags);
6106 return;
6107 }
6108
6109 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6110
6111 if (work->event) {
6112 e = work->event;
49b14a5c 6113 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 6114
6115 /* Called before vblank count and timestamps have
6116 * been updated for the vblank interval of flip
6117 * completion? Need to increment vblank count and
6118 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 6119 * to account for this. We assume this happened if we
6120 * get called over 0.9 frame durations after the last
6121 * timestamped vblank.
6122 *
6123 * This calculation can not be used with vrefresh rates
6124 * below 5Hz (10Hz to be on the safe side) without
6125 * promoting to 64 integers.
0af7e4df 6126 */
49b14a5c
MK		 6127 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6128 9 * crtc->framedur_ns) {
0af7e4df 6129 e->event.sequence++;
49b14a5c
MK		 6130 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6131 crtc->framedur_ns);
0af7e4df
MK		 6132 }
6133
49b14a5c
MK		 6134 e->event.tv_sec = tvbl.tv_sec;
6135 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6136
6b95a207
KH		 6137 list_add_tail(&e->base.link,
6138 &e->base.file_priv->event_list);
6139 wake_up_interruptible(&e->base.file_priv->event_wait);
6140 }
6141
0af7e4df
MK		 6142 drm_vblank_put(dev, intel_crtc->pipe);
6143
6b95a207
KH		 6144 spin_unlock_irqrestore(&dev->event_lock, flags);
6145
05394f39 6146 obj = work->old_fb_obj;
d9e86c0e 6147
e59f2bac 6148 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 6149 &obj->pending_flip.counter);
6150 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 6151 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 6152
6b95a207 6153 schedule_work(&work->work);
e5510fac
JB		 6154
6155 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6156}
6157
1afe3e9d
JB		 6158void intel_finish_page_flip(struct drm_device *dev, int pipe)
6159{
6160 drm_i915_private_t *dev_priv = dev->dev_private;
6161 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6162
49b14a5c 6163 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6164}
6165
6166void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6167{
6168 drm_i915_private_t *dev_priv = dev->dev_private;
6169 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6170
49b14a5c 6171 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6172}
6173
6b95a207
KH		 6174void intel_prepare_page_flip(struct drm_device *dev, int plane)
6175{
6176 drm_i915_private_t *dev_priv = dev->dev_private;
6177 struct intel_crtc *intel_crtc =
6178 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6179 unsigned long flags;
6180
6181 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6182 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6183 if ((++intel_crtc->unpin_work->pending) > 1)
6184 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6185 } else {
6186 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6187 }
6b95a207
KH		 6188 spin_unlock_irqrestore(&dev->event_lock, flags);
6189}
6190
8c9f3aaf
JB		 6191static int intel_gen2_queue_flip(struct drm_device *dev,
6192 struct drm_crtc *crtc,
6193 struct drm_framebuffer *fb,
6194 struct drm_i915_gem_object *obj)
6195{
6196 struct drm_i915_private *dev_priv = dev->dev_private;
6197 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6198 u32 flip_mask;
6d90c952 6199 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6200 int ret;
6201
6d90c952 6202 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6203 if (ret)
83d4092b 6204 goto err;
8c9f3aaf 6205
6d90c952 6206 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6207 if (ret)
83d4092b 6208 goto err_unpin;
8c9f3aaf
JB		 6209
6210 /* Can't queue multiple flips, so wait for the previous
6211 * one to finish before executing the next.
6212 */
6213 if (intel_crtc->plane)
6214 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6215 else
6216 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6217 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6218 intel_ring_emit(ring, MI_NOOP);
6219 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6220 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6221 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6222 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6223 intel_ring_emit(ring, 0); /* aux display base address, unused */
6224 intel_ring_advance(ring);
83d4092b
CW		 6225 return 0;
6226
6227err_unpin:
6228 intel_unpin_fb_obj(obj);
6229err:
8c9f3aaf
JB		 6230 return ret;
6231}
6232
6233static int intel_gen3_queue_flip(struct drm_device *dev,
6234 struct drm_crtc *crtc,
6235 struct drm_framebuffer *fb,
6236 struct drm_i915_gem_object *obj)
6237{
6238 struct drm_i915_private *dev_priv = dev->dev_private;
6239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6240 u32 flip_mask;
6d90c952 6241 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6242 int ret;
6243
6d90c952 6244 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6245 if (ret)
83d4092b 6246 goto err;
8c9f3aaf 6247
6d90c952 6248 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6249 if (ret)
83d4092b 6250 goto err_unpin;
8c9f3aaf
JB		 6251
6252 if (intel_crtc->plane)
6253 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6254 else
6255 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6256 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6257 intel_ring_emit(ring, MI_NOOP);
6258 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6259 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6260 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6261 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6262 intel_ring_emit(ring, MI_NOOP);
6263
6264 intel_ring_advance(ring);
83d4092b
CW		 6265 return 0;
6266
6267err_unpin:
6268 intel_unpin_fb_obj(obj);
6269err:
8c9f3aaf
JB		 6270 return ret;
6271}
6272
6273static int intel_gen4_queue_flip(struct drm_device *dev,
6274 struct drm_crtc *crtc,
6275 struct drm_framebuffer *fb,
6276 struct drm_i915_gem_object *obj)
6277{
6278 struct drm_i915_private *dev_priv = dev->dev_private;
6279 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6280 uint32_t pf, pipesrc;
6d90c952 6281 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6282 int ret;
6283
6d90c952 6284 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6285 if (ret)
83d4092b 6286 goto err;
8c9f3aaf 6287
6d90c952 6288 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6289 if (ret)
83d4092b 6290 goto err_unpin;
8c9f3aaf
JB		 6291
6292 /* i965+ uses the linear or tiled offsets from the
6293 * Display Registers (which do not change across a page-flip)
6294 * so we need only reprogram the base address.
6295 */
6d90c952
DV		 6296 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6297 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6298 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 6299 intel_ring_emit(ring,
6300 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6301 obj->tiling_mode);
8c9f3aaf
JB		 6302
6303 /* XXX Enabling the panel-fitter across page-flip is so far
6304 * untested on non-native modes, so ignore it for now.
6305 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6306 */
6307 pf = 0;
6308 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6309 intel_ring_emit(ring, pf | pipesrc);
6310 intel_ring_advance(ring);
83d4092b
CW		 6311 return 0;
6312
6313err_unpin:
6314 intel_unpin_fb_obj(obj);
6315err:
8c9f3aaf
JB		 6316 return ret;
6317}
6318
6319static int intel_gen6_queue_flip(struct drm_device *dev,
6320 struct drm_crtc *crtc,
6321 struct drm_framebuffer *fb,
6322 struct drm_i915_gem_object *obj)
6323{
6324 struct drm_i915_private *dev_priv = dev->dev_private;
6325 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 6326 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6327 uint32_t pf, pipesrc;
6328 int ret;
6329
6d90c952 6330 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6331 if (ret)
83d4092b 6332 goto err;
8c9f3aaf 6333
6d90c952 6334 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6335 if (ret)
83d4092b 6336 goto err_unpin;
8c9f3aaf 6337
6d90c952
DV		 6338 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6339 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6340 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 6341 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 6342
dc257cf1
DV		 6343 /* Contrary to the suggestions in the documentation,
6344 * "Enable Panel Fitter" does not seem to be required when page
6345 * flipping with a non-native mode, and worse causes a normal
6346 * modeset to fail.
6347 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6348 */
6349 pf = 0;
8c9f3aaf 6350 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6351 intel_ring_emit(ring, pf | pipesrc);
6352 intel_ring_advance(ring);
83d4092b
CW		 6353 return 0;
6354
6355err_unpin:
6356 intel_unpin_fb_obj(obj);
6357err:
8c9f3aaf
JB		 6358 return ret;
6359}
6360
7c9017e5
JB		 6361/*
6362 * On gen7 we currently use the blit ring because (in early silicon at least)
6363 * the render ring doesn't give us interrpts for page flip completion, which
6364 * means clients will hang after the first flip is queued. Fortunately the
6365 * blit ring generates interrupts properly, so use it instead.
6366 */
6367static int intel_gen7_queue_flip(struct drm_device *dev,
6368 struct drm_crtc *crtc,
6369 struct drm_framebuffer *fb,
6370 struct drm_i915_gem_object *obj)
6371{
6372 struct drm_i915_private *dev_priv = dev->dev_private;
6373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6374 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 6375 uint32_t plane_bit = 0;
7c9017e5
JB		 6376 int ret;
6377
6378 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6379 if (ret)
83d4092b 6380 goto err;
7c9017e5 6381
cb05d8de
DV		 6382 switch(intel_crtc->plane) {
6383 case PLANE_A:
6384 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6385 break;
6386 case PLANE_B:
6387 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6388 break;
6389 case PLANE_C:
6390 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6391 break;
6392 default:
6393 WARN_ONCE(1, "unknown plane in flip command\n");
6394 ret = -ENODEV;
6395 goto err;
6396 }
6397
7c9017e5
JB		 6398 ret = intel_ring_begin(ring, 4);
6399 if (ret)
83d4092b 6400 goto err_unpin;
7c9017e5 6401
cb05d8de 6402 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 6403 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 6404 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5
JB		 6405 intel_ring_emit(ring, (MI_NOOP));
6406 intel_ring_advance(ring);
83d4092b
CW		 6407 return 0;
6408
6409err_unpin:
6410 intel_unpin_fb_obj(obj);
6411err:
7c9017e5
JB		 6412 return ret;
6413}
6414
8c9f3aaf
JB		 6415static int intel_default_queue_flip(struct drm_device *dev,
6416 struct drm_crtc *crtc,
6417 struct drm_framebuffer *fb,
6418 struct drm_i915_gem_object *obj)
6419{
6420 return -ENODEV;
6421}
6422
6b95a207
KH		 6423static int intel_crtc_page_flip(struct drm_crtc *crtc,
6424 struct drm_framebuffer *fb,
6425 struct drm_pending_vblank_event *event)
6426{
6427 struct drm_device *dev = crtc->dev;
6428 struct drm_i915_private *dev_priv = dev->dev_private;
6429 struct intel_framebuffer *intel_fb;
05394f39 6430 struct drm_i915_gem_object *obj;
6b95a207
KH		 6431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6432 struct intel_unpin_work *work;
8c9f3aaf 6433 unsigned long flags;
52e68630 6434 int ret;
6b95a207 6435
e6a595d2
VS		 6436 /* Can't change pixel format via MI display flips. */
6437 if (fb->pixel_format != crtc->fb->pixel_format)
6438 return -EINVAL;
6439
6440 /*
6441 * TILEOFF/LINOFF registers can't be changed via MI display flips.
6442 * Note that pitch changes could also affect these register.
6443 */
6444 if (INTEL_INFO(dev)->gen > 3 &&
6445 (fb->offsets[0] != crtc->fb->offsets[0] ||
6446 fb->pitches[0] != crtc->fb->pitches[0]))
6447 return -EINVAL;
6448
6b95a207
KH		 6449 work = kzalloc(sizeof *work, GFP_KERNEL);
6450 if (work == NULL)
6451 return -ENOMEM;
6452
6b95a207
KH		 6453 work->event = event;
6454 work->dev = crtc->dev;
6455 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6456 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6457 INIT_WORK(&work->work, intel_unpin_work_fn);
6458
7317c75e
JB		 6459 ret = drm_vblank_get(dev, intel_crtc->pipe);
6460 if (ret)
6461 goto free_work;
6462
6b95a207
KH		 6463 /* We borrow the event spin lock for protecting unpin_work */
6464 spin_lock_irqsave(&dev->event_lock, flags);
6465 if (intel_crtc->unpin_work) {
6466 spin_unlock_irqrestore(&dev->event_lock, flags);
6467 kfree(work);
7317c75e 6468 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 6469
6470 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6471 return -EBUSY;
6472 }
6473 intel_crtc->unpin_work = work;
6474 spin_unlock_irqrestore(&dev->event_lock, flags);
6475
6476 intel_fb = to_intel_framebuffer(fb);
6477 obj = intel_fb->obj;
6478
79158103
CW		 6479 ret = i915_mutex_lock_interruptible(dev);
6480 if (ret)
6481 goto cleanup;
6b95a207 6482
75dfca80 6483 /* Reference the objects for the scheduled work. */
05394f39
CW		 6484 drm_gem_object_reference(&work->old_fb_obj->base);
6485 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6486
6487 crtc->fb = fb;
96b099fd 6488
e1f99ce6 6489 work->pending_flip_obj = obj;
e1f99ce6 6490
4e5359cd
SF		 6491 work->enable_stall_check = true;
6492
e1f99ce6
CW		 6493 /* Block clients from rendering to the new back buffer until
6494 * the flip occurs and the object is no longer visible.
6495 */
05394f39 6496 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 6497
8c9f3aaf
JB		 6498 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6499 if (ret)
6500 goto cleanup_pending;
6b95a207 6501
7782de3b 6502 intel_disable_fbc(dev);
acb87dfb 6503 intel_mark_busy(dev, obj);
6b95a207
KH		 6504 mutex_unlock(&dev->struct_mutex);
6505
e5510fac
JB		 6506 trace_i915_flip_request(intel_crtc->plane, obj);
6507
6b95a207 6508 return 0;
96b099fd 6509
8c9f3aaf
JB		 6510cleanup_pending:
6511 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 6512 drm_gem_object_unreference(&work->old_fb_obj->base);
6513 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6514 mutex_unlock(&dev->struct_mutex);
6515
79158103 6516cleanup:
96b099fd
CW		 6517 spin_lock_irqsave(&dev->event_lock, flags);
6518 intel_crtc->unpin_work = NULL;
6519 spin_unlock_irqrestore(&dev->event_lock, flags);
6520
7317c75e
JB		 6521 drm_vblank_put(dev, intel_crtc->pipe);
6522free_work:
96b099fd
CW		 6523 kfree(work);
6524
6525 return ret;
6b95a207
KH		 6526}
6527
47f1c6c9
CW		 6528static void intel_sanitize_modesetting(struct drm_device *dev,
6529 int pipe, int plane)
6530{
6531 struct drm_i915_private *dev_priv = dev->dev_private;
6532 u32 reg, val;
a9dcf84b 6533 int i;
47f1c6c9 6534
f47166d2 6535 /* Clear any frame start delays used for debugging left by the BIOS */
a9dcf84b
DV		 6536 for_each_pipe(i) {
6537 reg = PIPECONF(i);
f47166d2
CW		 6538 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6539 }
6540
47f1c6c9
CW		 6541 if (HAS_PCH_SPLIT(dev))
6542 return;
6543
6544 /* Who knows what state these registers were left in by the BIOS or
6545 * grub?
6546 *
6547 * If we leave the registers in a conflicting state (e.g. with the
6548 * display plane reading from the other pipe than the one we intend
6549 * to use) then when we attempt to teardown the active mode, we will
6550 * not disable the pipes and planes in the correct order -- leaving
6551 * a plane reading from a disabled pipe and possibly leading to
6552 * undefined behaviour.
6553 */
6554
6555 reg = DSPCNTR(plane);
6556 val = I915_READ(reg);
6557
6558 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6559 return;
6560 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6561 return;
6562
6563 /* This display plane is active and attached to the other CPU pipe. */
6564 pipe = !pipe;
6565
6566 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 6567 intel_disable_plane(dev_priv, plane, pipe);
6568 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 6569}
79e53945 6570
f6e5b160
CW		 6571static void intel_crtc_reset(struct drm_crtc *crtc)
6572{
6573 struct drm_device *dev = crtc->dev;
6574 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6575
6576 /* Reset flags back to the 'unknown' status so that they
6577 * will be correctly set on the initial modeset.
6578 */
6579 intel_crtc->dpms_mode = -1;
6580
6581 /* We need to fix up any BIOS configuration that conflicts with
6582 * our expectations.
6583 */
6584 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6585}
6586
6587static struct drm_crtc_helper_funcs intel_helper_funcs = {
6588 .dpms = intel_crtc_dpms,
6589 .mode_fixup = intel_crtc_mode_fixup,
6590 .mode_set = intel_crtc_mode_set,
6591 .mode_set_base = intel_pipe_set_base,
6592 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6593 .load_lut = intel_crtc_load_lut,
6594 .disable = intel_crtc_disable,
6595};
6596
6597static const struct drm_crtc_funcs intel_crtc_funcs = {
6598 .reset = intel_crtc_reset,
6599 .cursor_set = intel_crtc_cursor_set,
6600 .cursor_move = intel_crtc_cursor_move,
6601 .gamma_set = intel_crtc_gamma_set,
6602 .set_config = drm_crtc_helper_set_config,
6603 .destroy = intel_crtc_destroy,
6604 .page_flip = intel_crtc_page_flip,
6605};
6606
ee7b9f93
JB		 6607static void intel_pch_pll_init(struct drm_device *dev)
6608{
6609 drm_i915_private_t *dev_priv = dev->dev_private;
6610 int i;
6611
6612 if (dev_priv->num_pch_pll == 0) {
6613 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6614 return;
6615 }
6616
6617 for (i = 0; i < dev_priv->num_pch_pll; i++) {
6618 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6619 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6620 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6621 }
6622}
6623
b358d0a6 6624static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 6625{
22fd0fab 6626 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 6627 struct intel_crtc *intel_crtc;
6628 int i;
6629
6630 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6631 if (intel_crtc == NULL)
6632 return;
6633
6634 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6635
6636 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 6637 for (i = 0; i < 256; i++) {
6638 intel_crtc->lut_r[i] = i;
6639 intel_crtc->lut_g[i] = i;
6640 intel_crtc->lut_b[i] = i;
6641 }
6642
80824003
JB		 6643 /* Swap pipes & planes for FBC on pre-965 */
6644 intel_crtc->pipe = pipe;
6645 intel_crtc->plane = pipe;
e2e767ab 6646 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 6647 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 6648 intel_crtc->plane = !pipe;
80824003
JB		 6649 }
6650
22fd0fab
JB		 6651 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6652 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6653 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6654 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6655
5d1d0cc8 6656 intel_crtc_reset(&intel_crtc->base);
04dbff52 6657 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5a354204 6658 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3
JB		 6659
6660 if (HAS_PCH_SPLIT(dev)) {
6661 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6662 intel_helper_funcs.commit = ironlake_crtc_commit;
6663 } else {
6664 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6665 intel_helper_funcs.commit = i9xx_crtc_commit;
6666 }
6667
79e53945
JB		 6668 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6669
652c393a
JB		 6670 intel_crtc->busy = false;
6671
6672 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6673 (unsigned long)intel_crtc);
79e53945
JB		 6674}
6675
08d7b3d1 6676int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 6677 struct drm_file *file)
08d7b3d1 6678{
08d7b3d1 6679 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 6680 struct drm_mode_object *drmmode_obj;
6681 struct intel_crtc *crtc;
08d7b3d1 6682
1cff8f6b
DV		 6683 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6684 return -ENODEV;
08d7b3d1 6685
c05422d5
DV		 6686 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6687 DRM_MODE_OBJECT_CRTC);
08d7b3d1 6688
c05422d5 6689 if (!drmmode_obj) {
08d7b3d1
CW		 6690 DRM_ERROR("no such CRTC id\n");
6691 return -EINVAL;
6692 }
6693
c05422d5
DV		 6694 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6695 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 6696
c05422d5 6697 return 0;
08d7b3d1
CW		 6698}
6699
c5e4df33 6700static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 6701{
4ef69c7a 6702 struct intel_encoder *encoder;
79e53945 6703 int index_mask = 0;
79e53945
JB		 6704 int entry = 0;
6705
4ef69c7a
CW		 6706 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6707 if (type_mask & encoder->clone_mask)
79e53945
JB		 6708 index_mask |= (1 << entry);
6709 entry++;
6710 }
4ef69c7a 6711
79e53945
JB		 6712 return index_mask;
6713}
6714
4d302442
CW		 6715static bool has_edp_a(struct drm_device *dev)
6716{
6717 struct drm_i915_private *dev_priv = dev->dev_private;
6718
6719 if (!IS_MOBILE(dev))
6720 return false;
6721
6722 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6723 return false;
6724
6725 if (IS_GEN5(dev) &&
6726 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6727 return false;
6728
6729 return true;
6730}
6731
79e53945
JB		 6732static void intel_setup_outputs(struct drm_device *dev)
6733{
725e30ad 6734 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 6735 struct intel_encoder *encoder;
cb0953d7 6736 bool dpd_is_edp = false;
f3cfcba6 6737 bool has_lvds;
79e53945 6738
f3cfcba6 6739 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 6740 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6741 /* disable the panel fitter on everything but LVDS */
6742 I915_WRITE(PFIT_CONTROL, 0);
6743 }
79e53945 6744
bad720ff 6745 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 6746 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 6747
4d302442 6748 if (has_edp_a(dev))
32f9d658
ZW		 6749 intel_dp_init(dev, DP_A);
6750
cb0953d7
AJ		 6751 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6752 intel_dp_init(dev, PCH_DP_D);
6753 }
6754
6755 intel_crt_init(dev);
6756
0e72a5b5
ED		 6757 if (IS_HASWELL(dev)) {
6758 int found;
6759
6760 /* Haswell uses DDI functions to detect digital outputs */
6761 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
6762 /* DDI A only supports eDP */
6763 if (found)
6764 intel_ddi_init(dev, PORT_A);
6765
6766 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
6767 * register */
6768 found = I915_READ(SFUSE_STRAP);
6769
6770 if (found & SFUSE_STRAP_DDIB_DETECTED)
6771 intel_ddi_init(dev, PORT_B);
6772 if (found & SFUSE_STRAP_DDIC_DETECTED)
6773 intel_ddi_init(dev, PORT_C);
6774 if (found & SFUSE_STRAP_DDID_DETECTED)
6775 intel_ddi_init(dev, PORT_D);
6776 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7
AJ		 6777 int found;
6778
30ad48b7 6779 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 6780 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 6781 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7
ZW		 6782 if (!found)
6783 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 6784 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6785 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 6786 }
6787
6788 if (I915_READ(HDMIC) & PORT_DETECTED)
6789 intel_hdmi_init(dev, HDMIC);
6790
b708a1d5 6791 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
30ad48b7
ZW		 6792 intel_hdmi_init(dev, HDMID);
6793
5eb08b69
ZW		 6794 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6795 intel_dp_init(dev, PCH_DP_C);
6796
cb0953d7 6797 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69 6798 intel_dp_init(dev, PCH_DP_D);
4a87d65d
JB		 6799 } else if (IS_VALLEYVIEW(dev)) {
6800 int found;
6801
6802 if (I915_READ(SDVOB) & PORT_DETECTED) {
6803 /* SDVOB multiplex with HDMIB */
6804 found = intel_sdvo_init(dev, SDVOB, true);
6805 if (!found)
6806 intel_hdmi_init(dev, SDVOB);
6807 if (!found && (I915_READ(DP_B) & DP_DETECTED))
6808 intel_dp_init(dev, DP_B);
6809 }
6810
6811 if (I915_READ(SDVOC) & PORT_DETECTED)
6812 intel_hdmi_init(dev, SDVOC);
5eb08b69 6813
4a87d65d
JB		 6814 /* Shares lanes with HDMI on SDVOC */
6815 if (I915_READ(DP_C) & DP_DETECTED)
6816 intel_dp_init(dev, DP_C);
103a196f 6817 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 6818 bool found = false;
7d57382e 6819
725e30ad 6820 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 6821 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 6822 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 6823 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6824 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 6825 intel_hdmi_init(dev, SDVOB);
b01f2c3a 6826 }
27185ae1 6827
b01f2c3a
JB		 6828 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6829 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 6830 intel_dp_init(dev, DP_B);
b01f2c3a 6831 }
725e30ad 6832 }
13520b05
KH		 6833
6834 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 6835
b01f2c3a
JB		 6836 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6837 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 6838 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 6839 }
27185ae1
ML		 6840
6841 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6842
b01f2c3a
JB		 6843 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6844 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 6845 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 6846 }
6847 if (SUPPORTS_INTEGRATED_DP(dev)) {
6848 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 6849 intel_dp_init(dev, DP_C);
b01f2c3a 6850 }
725e30ad 6851 }
27185ae1 6852
b01f2c3a
JB		 6853 if (SUPPORTS_INTEGRATED_DP(dev) &&
6854 (I915_READ(DP_D) & DP_DETECTED)) {
6855 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 6856 intel_dp_init(dev, DP_D);
b01f2c3a 6857 }
bad720ff 6858 } else if (IS_GEN2(dev))
79e53945
JB		 6859 intel_dvo_init(dev);
6860
103a196f 6861 if (SUPPORTS_TV(dev))
79e53945
JB		 6862 intel_tv_init(dev);
6863
4ef69c7a
CW		 6864 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6865 encoder->base.possible_crtcs = encoder->crtc_mask;
6866 encoder->base.possible_clones =
6867 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 6868 }
47356eb6 6869
2c7111db
CW		 6870 /* disable all the possible outputs/crtcs before entering KMS mode */
6871 drm_helper_disable_unused_functions(dev);
9fb526db 6872
40579abe 6873 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9fb526db 6874 ironlake_init_pch_refclk(dev);
79e53945
JB		 6875}
6876
6877static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6878{
6879 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 6880
6881 drm_framebuffer_cleanup(fb);
05394f39 6882 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 6883
6884 kfree(intel_fb);
6885}
6886
6887static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 6888 struct drm_file *file,
79e53945
JB		 6889 unsigned int *handle)
6890{
6891 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 6892 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 6893
05394f39 6894 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 6895}
6896
6897static const struct drm_framebuffer_funcs intel_fb_funcs = {
6898 .destroy = intel_user_framebuffer_destroy,
6899 .create_handle = intel_user_framebuffer_create_handle,
6900};
6901
38651674
DA		 6902int intel_framebuffer_init(struct drm_device *dev,
6903 struct intel_framebuffer *intel_fb,
308e5bcb 6904 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 6905 struct drm_i915_gem_object *obj)
79e53945 6906{
79e53945
JB		 6907 int ret;
6908
05394f39 6909 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 6910 return -EINVAL;
6911
308e5bcb 6912 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 6913 return -EINVAL;
6914
308e5bcb 6915 switch (mode_cmd->pixel_format) {
04b3924d
VS		 6916 case DRM_FORMAT_RGB332:
6917 case DRM_FORMAT_RGB565:
6918 case DRM_FORMAT_XRGB8888:
b250da79 6919 case DRM_FORMAT_XBGR8888:
04b3924d
VS		 6920 case DRM_FORMAT_ARGB8888:
6921 case DRM_FORMAT_XRGB2101010:
6922 case DRM_FORMAT_ARGB2101010:
308e5bcb 6923 /* RGB formats are common across chipsets */
b5626747 6924 break;
04b3924d
VS		 6925 case DRM_FORMAT_YUYV:
6926 case DRM_FORMAT_UYVY:
6927 case DRM_FORMAT_YVYU:
6928 case DRM_FORMAT_VYUY:
57cd6508
CW		 6929 break;
6930 default:
aca25848
ED		 6931 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6932 mode_cmd->pixel_format);
57cd6508
CW		 6933 return -EINVAL;
6934 }
6935
79e53945
JB		 6936 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6937 if (ret) {
6938 DRM_ERROR("framebuffer init failed %d\n", ret);
6939 return ret;
6940 }
6941
6942 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 6943 intel_fb->obj = obj;
79e53945
JB		 6944 return 0;
6945}
6946
79e53945
JB		 6947static struct drm_framebuffer *
6948intel_user_framebuffer_create(struct drm_device *dev,
6949 struct drm_file *filp,
308e5bcb 6950 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 6951{
05394f39 6952 struct drm_i915_gem_object *obj;
79e53945 6953
308e5bcb
JB		 6954 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6955 mode_cmd->handles[0]));
c8725226 6956 if (&obj->base == NULL)
cce13ff7 6957 return ERR_PTR(-ENOENT);
79e53945 6958
d2dff872 6959 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 6960}
6961
79e53945 6962static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 6963 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 6964 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 6965};
6966
e70236a8
JB		 6967/* Set up chip specific display functions */
6968static void intel_init_display(struct drm_device *dev)
6969{
6970 struct drm_i915_private *dev_priv = dev->dev_private;
6971
6972 /* We always want a DPMS function */
f564048e 6973 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 6974 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e 6975 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
ee7b9f93 6976 dev_priv->display.off = ironlake_crtc_off;
17638cd6 6977 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 6978 } else {
e70236a8 6979 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e 6980 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
ee7b9f93 6981 dev_priv->display.off = i9xx_crtc_off;
17638cd6 6982 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 6983 }
e70236a8 6984
e70236a8 6985 /* Returns the core display clock speed */
25eb05fc
JB		 6986 if (IS_VALLEYVIEW(dev))
6987 dev_priv->display.get_display_clock_speed =
6988 valleyview_get_display_clock_speed;
6989 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 6990 dev_priv->display.get_display_clock_speed =
6991 i945_get_display_clock_speed;
6992 else if (IS_I915G(dev))
6993 dev_priv->display.get_display_clock_speed =
6994 i915_get_display_clock_speed;
f2b115e6 6995 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 6996 dev_priv->display.get_display_clock_speed =
6997 i9xx_misc_get_display_clock_speed;
6998 else if (IS_I915GM(dev))
6999 dev_priv->display.get_display_clock_speed =
7000 i915gm_get_display_clock_speed;
7001 else if (IS_I865G(dev))
7002 dev_priv->display.get_display_clock_speed =
7003 i865_get_display_clock_speed;
f0f8a9ce 7004 else if (IS_I85X(dev))
e70236a8
JB		 7005 dev_priv->display.get_display_clock_speed =
7006 i855_get_display_clock_speed;
7007 else /* 852, 830 */
7008 dev_priv->display.get_display_clock_speed =
7009 i830_get_display_clock_speed;
7010
7f8a8569 7011 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 7012 if (IS_GEN5(dev)) {
674cf967 7013 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 7014 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 7015 } else if (IS_GEN6(dev)) {
674cf967 7016 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 7017 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 7018 } else if (IS_IVYBRIDGE(dev)) {
7019 /* FIXME: detect B0+ stepping and use auto training */
7020 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 7021 dev_priv->display.write_eld = ironlake_write_eld;
c82e4d26
ED		 7022 } else if (IS_HASWELL(dev)) {
7023 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
4abb3c8c 7024 dev_priv->display.write_eld = ironlake_write_eld;
7f8a8569
ZW		 7025 } else
7026 dev_priv->display.update_wm = NULL;
6067aaea 7027 } else if (IS_G4X(dev)) {
e0dac65e 7028 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 7029 }
8c9f3aaf
JB		 7030
7031 /* Default just returns -ENODEV to indicate unsupported */
7032 dev_priv->display.queue_flip = intel_default_queue_flip;
7033
7034 switch (INTEL_INFO(dev)->gen) {
7035 case 2:
7036 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7037 break;
7038
7039 case 3:
7040 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7041 break;
7042
7043 case 4:
7044 case 5:
7045 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7046 break;
7047
7048 case 6:
7049 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7050 break;
7c9017e5
JB		 7051 case 7:
7052 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7053 break;
8c9f3aaf 7054 }
e70236a8
JB		 7055}
7056
b690e96c
JB		 7057/*
7058 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7059 * resume, or other times. This quirk makes sure that's the case for
7060 * affected systems.
7061 */
0206e353 7062static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 7063{
7064 struct drm_i915_private *dev_priv = dev->dev_private;
7065
7066 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 7067 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 7068}
7069
435793df
KP		 7070/*
7071 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7072 */
7073static void quirk_ssc_force_disable(struct drm_device *dev)
7074{
7075 struct drm_i915_private *dev_priv = dev->dev_private;
7076 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 7077 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 7078}
7079
4dca20ef 7080/*
5a15ab5b
CE		 7081 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7082 * brightness value
4dca20ef
CE		 7083 */
7084static void quirk_invert_brightness(struct drm_device *dev)
7085{
7086 struct drm_i915_private *dev_priv = dev->dev_private;
7087 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 7088 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 7089}
7090
b690e96c
JB		 7091struct intel_quirk {
7092 int device;
7093 int subsystem_vendor;
7094 int subsystem_device;
7095 void (*hook)(struct drm_device *dev);
7096};
7097
c43b5634 7098static struct intel_quirk intel_quirks[] = {
b690e96c 7099 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 7100 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c
JB		 7101
7102 /* Thinkpad R31 needs pipe A force quirk */
7103 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
7104 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7105 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7106
7107 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7108 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
7109 /* ThinkPad X40 needs pipe A force quirk */
7110
7111 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7112 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7113
7114 /* 855 & before need to leave pipe A & dpll A up */
7115 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7116 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 7117
7118 /* Lenovo U160 cannot use SSC on LVDS */
7119 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 7120
7121 /* Sony Vaio Y cannot use SSC on LVDS */
7122 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 7123
7124 /* Acer Aspire 5734Z must invert backlight brightness */
7125 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 7126};
7127
7128static void intel_init_quirks(struct drm_device *dev)
7129{
7130 struct pci_dev *d = dev->pdev;
7131 int i;
7132
7133 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7134 struct intel_quirk *q = &intel_quirks[i];
7135
7136 if (d->device == q->device &&
7137 (d->subsystem_vendor == q->subsystem_vendor ||
7138 q->subsystem_vendor == PCI_ANY_ID) &&
7139 (d->subsystem_device == q->subsystem_device ||
7140 q->subsystem_device == PCI_ANY_ID))
7141 q->hook(dev);
7142 }
7143}
7144
9cce37f4
JB		 7145/* Disable the VGA plane that we never use */
7146static void i915_disable_vga(struct drm_device *dev)
7147{
7148 struct drm_i915_private *dev_priv = dev->dev_private;
7149 u8 sr1;
7150 u32 vga_reg;
7151
7152 if (HAS_PCH_SPLIT(dev))
7153 vga_reg = CPU_VGACNTRL;
7154 else
7155 vga_reg = VGACNTRL;
7156
7157 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 7158 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 7159 sr1 = inb(VGA_SR_DATA);
7160 outb(sr1 | 1<<5, VGA_SR_DATA);
7161 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7162 udelay(300);
7163
7164 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7165 POSTING_READ(vga_reg);
7166}
7167
f817586c
DV		 7168void intel_modeset_init_hw(struct drm_device *dev)
7169{
0232e927
ED		 7170 /* We attempt to init the necessary power wells early in the initialization
7171 * time, so the subsystems that expect power to be enabled can work.
7172 */
7173 intel_init_power_wells(dev);
7174
a8f78b58
ED		 7175 intel_prepare_ddi(dev);
7176
f817586c
DV		 7177 intel_init_clock_gating(dev);
7178
79f5b2c7 7179 mutex_lock(&dev->struct_mutex);
8090c6b9 7180 intel_enable_gt_powersave(dev);
79f5b2c7 7181 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 7182}
7183
79e53945
JB		 7184void intel_modeset_init(struct drm_device *dev)
7185{
652c393a 7186 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 7187 int i, ret;
79e53945
JB		 7188
7189 drm_mode_config_init(dev);
7190
7191 dev->mode_config.min_width = 0;
7192 dev->mode_config.min_height = 0;
7193
019d96cb
DA		 7194 dev->mode_config.preferred_depth = 24;
7195 dev->mode_config.prefer_shadow = 1;
7196
e6ecefaa 7197 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 7198
b690e96c
JB		 7199 intel_init_quirks(dev);
7200
1fa61106
ED		 7201 intel_init_pm(dev);
7202
e70236a8
JB		 7203 intel_init_display(dev);
7204
a6c45cf0
CW		 7205 if (IS_GEN2(dev)) {
7206 dev->mode_config.max_width = 2048;
7207 dev->mode_config.max_height = 2048;
7208 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 7209 dev->mode_config.max_width = 4096;
7210 dev->mode_config.max_height = 4096;
79e53945 7211 } else {
a6c45cf0
CW		 7212 dev->mode_config.max_width = 8192;
7213 dev->mode_config.max_height = 8192;
79e53945 7214 }
dd2757f8 7215 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 7216
28c97730 7217 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 7218 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 7219
a3524f1b 7220 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 7221 intel_crtc_init(dev, i);
00c2064b
JB		 7222 ret = intel_plane_init(dev, i);
7223 if (ret)
7224 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 7225 }
7226
ee7b9f93
JB		 7227 intel_pch_pll_init(dev);
7228
9cce37f4
JB		 7229 /* Just disable it once at startup */
7230 i915_disable_vga(dev);
79e53945 7231 intel_setup_outputs(dev);
652c393a 7232
652c393a
JB		 7233 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
7234 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
7235 (unsigned long)dev);
2c7111db
CW		 7236}
7237
7238void intel_modeset_gem_init(struct drm_device *dev)
7239{
1833b134 7240 intel_modeset_init_hw(dev);
02e792fb
DV		 7241
7242 intel_setup_overlay(dev);
79e53945
JB		 7243}
7244
7245void intel_modeset_cleanup(struct drm_device *dev)
7246{
652c393a
JB		 7247 struct drm_i915_private *dev_priv = dev->dev_private;
7248 struct drm_crtc *crtc;
7249 struct intel_crtc *intel_crtc;
7250
f87ea761 7251 drm_kms_helper_poll_fini(dev);
652c393a
JB		 7252 mutex_lock(&dev->struct_mutex);
7253
723bfd70
JB		 7254 intel_unregister_dsm_handler();
7255
7256
652c393a
JB		 7257 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7258 /* Skip inactive CRTCs */
7259 if (!crtc->fb)
7260 continue;
7261
7262 intel_crtc = to_intel_crtc(crtc);
3dec0095 7263 intel_increase_pllclock(crtc);
652c393a
JB		 7264 }
7265
973d04f9 7266 intel_disable_fbc(dev);
e70236a8 7267
8090c6b9 7268 intel_disable_gt_powersave(dev);
0cdab21f 7269
930ebb46
DV		 7270 ironlake_teardown_rc6(dev);
7271
57f350b6
JB		 7272 if (IS_VALLEYVIEW(dev))
7273 vlv_init_dpio(dev);
7274
69341a5e
KH		 7275 mutex_unlock(&dev->struct_mutex);
7276
6c0d9350
DV		 7277 /* Disable the irq before mode object teardown, for the irq might
7278 * enqueue unpin/hotplug work. */
7279 drm_irq_uninstall(dev);
7280 cancel_work_sync(&dev_priv->hotplug_work);
6fdd4d98 7281 cancel_work_sync(&dev_priv->rps_work);
6c0d9350 7282
1630fe75
CW		 7283 /* flush any delayed tasks or pending work */
7284 flush_scheduled_work();
7285
3dec0095
DV		 7286 /* Shut off idle work before the crtcs get freed. */
7287 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7288 intel_crtc = to_intel_crtc(crtc);
7289 del_timer_sync(&intel_crtc->idle_timer);
7290 }
7291 del_timer_sync(&dev_priv->idle_timer);
7292 cancel_work_sync(&dev_priv->idle_work);
7293
79e53945
JB		 7294 drm_mode_config_cleanup(dev);
7295}
7296
f1c79df3
ZW		 7297/*
7298 * Return which encoder is currently attached for connector.
7299 */
df0e9248 7300struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 7301{
df0e9248
CW		 7302 return &intel_attached_encoder(connector)->base;
7303}
f1c79df3 7304
df0e9248
CW		 7305void intel_connector_attach_encoder(struct intel_connector *connector,
7306 struct intel_encoder *encoder)
7307{
7308 connector->encoder = encoder;
7309 drm_mode_connector_attach_encoder(&connector->base,
7310 &encoder->base);
79e53945 7311}
28d52043
DA		 7312
7313/*
7314 * set vga decode state - true == enable VGA decode
7315 */
7316int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7317{
7318 struct drm_i915_private *dev_priv = dev->dev_private;
7319 u16 gmch_ctrl;
7320
7321 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7322 if (state)
7323 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7324 else
7325 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7326 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7327 return 0;
7328}
c4a1d9e4
CW		 7329
7330#ifdef CONFIG_DEBUG_FS
7331#include <linux/seq_file.h>
7332
7333struct intel_display_error_state {
7334 struct intel_cursor_error_state {
7335 u32 control;
7336 u32 position;
7337 u32 base;
7338 u32 size;
7339 } cursor[2];
7340
7341 struct intel_pipe_error_state {
7342 u32 conf;
7343 u32 source;
7344
7345 u32 htotal;
7346 u32 hblank;
7347 u32 hsync;
7348 u32 vtotal;
7349 u32 vblank;
7350 u32 vsync;
7351 } pipe[2];
7352
7353 struct intel_plane_error_state {
7354 u32 control;
7355 u32 stride;
7356 u32 size;
7357 u32 pos;
7358 u32 addr;
7359 u32 surface;
7360 u32 tile_offset;
7361 } plane[2];
7362};
7363
7364struct intel_display_error_state *
7365intel_display_capture_error_state(struct drm_device *dev)
7366{
0206e353 7367 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 7368 struct intel_display_error_state *error;
7369 int i;
7370
7371 error = kmalloc(sizeof(*error), GFP_ATOMIC);
7372 if (error == NULL)
7373 return NULL;
7374
7375 for (i = 0; i < 2; i++) {
7376 error->cursor[i].control = I915_READ(CURCNTR(i));
7377 error->cursor[i].position = I915_READ(CURPOS(i));
7378 error->cursor[i].base = I915_READ(CURBASE(i));
7379
7380 error->plane[i].control = I915_READ(DSPCNTR(i));
7381 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7382 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 7383 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 7384 error->plane[i].addr = I915_READ(DSPADDR(i));
7385 if (INTEL_INFO(dev)->gen >= 4) {
7386 error->plane[i].surface = I915_READ(DSPSURF(i));
7387 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7388 }
7389
7390 error->pipe[i].conf = I915_READ(PIPECONF(i));
7391 error->pipe[i].source = I915_READ(PIPESRC(i));
7392 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7393 error->pipe[i].hblank = I915_READ(HBLANK(i));
7394 error->pipe[i].hsync = I915_READ(HSYNC(i));
7395 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7396 error->pipe[i].vblank = I915_READ(VBLANK(i));
7397 error->pipe[i].vsync = I915_READ(VSYNC(i));
7398 }
7399
7400 return error;
7401}
7402
7403void
7404intel_display_print_error_state(struct seq_file *m,
7405 struct drm_device *dev,
7406 struct intel_display_error_state *error)
7407{
7408 int i;
7409
7410 for (i = 0; i < 2; i++) {
7411 seq_printf(m, "Pipe [%d]:\n", i);
7412 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
7413 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
7414 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
7415 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
7416 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
7417 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
7418 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
7419 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
7420
7421 seq_printf(m, "Plane [%d]:\n", i);
7422 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
7423 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
7424 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
7425 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
7426 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
7427 if (INTEL_INFO(dev)->gen >= 4) {
7428 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
7429 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
7430 }
7431
7432 seq_printf(m, "Cursor [%d]:\n", i);
7433 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
7434 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
7435 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
7436 }
7437}
7438#endif
Linux kernel - Deliverables
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