Commit | Line | Data |
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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
2d1a8a48 | 30 | #include <linux/export.h> |
01527b31 CT |
31 | #include <linux/notifier.h> |
32 | #include <linux/reboot.h> | |
760285e7 | 33 | #include <drm/drmP.h> |
c6f95f27 | 34 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
35 | #include <drm/drm_crtc.h> |
36 | #include <drm/drm_crtc_helper.h> | |
37 | #include <drm/drm_edid.h> | |
a4fc5ed6 | 38 | #include "intel_drv.h" |
760285e7 | 39 | #include <drm/i915_drm.h> |
a4fc5ed6 | 40 | #include "i915_drv.h" |
a4fc5ed6 | 41 | |
a4fc5ed6 KP |
42 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
43 | ||
559be30c TP |
44 | /* Compliance test status bits */ |
45 | #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 | |
46 | #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
47 | #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
48 | #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
49 | ||
9dd4ffdf | 50 | struct dp_link_dpll { |
840b32b7 | 51 | int clock; |
9dd4ffdf CML |
52 | struct dpll dpll; |
53 | }; | |
54 | ||
55 | static const struct dp_link_dpll gen4_dpll[] = { | |
840b32b7 | 56 | { 162000, |
9dd4ffdf | 57 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, |
840b32b7 | 58 | { 270000, |
9dd4ffdf CML |
59 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } |
60 | }; | |
61 | ||
62 | static const struct dp_link_dpll pch_dpll[] = { | |
840b32b7 | 63 | { 162000, |
9dd4ffdf | 64 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, |
840b32b7 | 65 | { 270000, |
9dd4ffdf CML |
66 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } |
67 | }; | |
68 | ||
65ce4bf5 | 69 | static const struct dp_link_dpll vlv_dpll[] = { |
840b32b7 | 70 | { 162000, |
58f6e632 | 71 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
840b32b7 | 72 | { 270000, |
65ce4bf5 CML |
73 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
74 | }; | |
75 | ||
ef9348c8 CML |
76 | /* |
77 | * CHV supports eDP 1.4 that have more link rates. | |
78 | * Below only provides the fixed rate but exclude variable rate. | |
79 | */ | |
80 | static const struct dp_link_dpll chv_dpll[] = { | |
81 | /* | |
82 | * CHV requires to program fractional division for m2. | |
83 | * m2 is stored in fixed point format using formula below | |
84 | * (m2_int << 22) | m2_fraction | |
85 | */ | |
840b32b7 | 86 | { 162000, /* m2_int = 32, m2_fraction = 1677722 */ |
ef9348c8 | 87 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, |
840b32b7 | 88 | { 270000, /* m2_int = 27, m2_fraction = 0 */ |
ef9348c8 | 89 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, |
840b32b7 | 90 | { 540000, /* m2_int = 27, m2_fraction = 0 */ |
ef9348c8 CML |
91 | { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } |
92 | }; | |
637a9c63 | 93 | |
64987fc5 SJ |
94 | static const int bxt_rates[] = { 162000, 216000, 243000, 270000, |
95 | 324000, 432000, 540000 }; | |
637a9c63 | 96 | static const int skl_rates[] = { 162000, 216000, 270000, |
f4896f15 VS |
97 | 324000, 432000, 540000 }; |
98 | static const int default_rates[] = { 162000, 270000, 540000 }; | |
ef9348c8 | 99 | |
cfcb0fc9 JB |
100 | /** |
101 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) | |
102 | * @intel_dp: DP struct | |
103 | * | |
104 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
105 | * will return true, and false otherwise. | |
106 | */ | |
107 | static bool is_edp(struct intel_dp *intel_dp) | |
108 | { | |
da63a9f2 PZ |
109 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
110 | ||
111 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; | |
cfcb0fc9 JB |
112 | } |
113 | ||
68b4d824 | 114 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
cfcb0fc9 | 115 | { |
68b4d824 ID |
116 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
117 | ||
118 | return intel_dig_port->base.base.dev; | |
cfcb0fc9 JB |
119 | } |
120 | ||
df0e9248 CW |
121 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
122 | { | |
fa90ecef | 123 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
124 | } |
125 | ||
ea5b213a | 126 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
1e0560e0 | 127 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp); |
4be73780 | 128 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
093e3f13 | 129 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp); |
a8c3344e VS |
130 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
131 | enum pipe pipe); | |
f21a2198 | 132 | static void intel_dp_unset_edid(struct intel_dp *intel_dp); |
a4fc5ed6 | 133 | |
ed4e9c1d VS |
134 | static int |
135 | intel_dp_max_link_bw(struct intel_dp *intel_dp) | |
a4fc5ed6 | 136 | { |
7183dc29 | 137 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
a4fc5ed6 KP |
138 | |
139 | switch (max_link_bw) { | |
140 | case DP_LINK_BW_1_62: | |
141 | case DP_LINK_BW_2_7: | |
1db10e28 | 142 | case DP_LINK_BW_5_4: |
d4eead50 | 143 | break; |
a4fc5ed6 | 144 | default: |
d4eead50 ID |
145 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", |
146 | max_link_bw); | |
a4fc5ed6 KP |
147 | max_link_bw = DP_LINK_BW_1_62; |
148 | break; | |
149 | } | |
150 | return max_link_bw; | |
151 | } | |
152 | ||
eeb6324d PZ |
153 | static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) |
154 | { | |
155 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
eeb6324d PZ |
156 | u8 source_max, sink_max; |
157 | ||
ccb1a831 | 158 | source_max = intel_dig_port->max_lanes; |
eeb6324d PZ |
159 | sink_max = drm_dp_max_lane_count(intel_dp->dpcd); |
160 | ||
161 | return min(source_max, sink_max); | |
162 | } | |
163 | ||
cd9dde44 AJ |
164 | /* |
165 | * The units on the numbers in the next two are... bizarre. Examples will | |
166 | * make it clearer; this one parallels an example in the eDP spec. | |
167 | * | |
168 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: | |
169 | * | |
170 | * 270000 * 1 * 8 / 10 == 216000 | |
171 | * | |
172 | * The actual data capacity of that configuration is 2.16Gbit/s, so the | |
173 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - | |
174 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be | |
175 | * 119000. At 18bpp that's 2142000 kilobits per second. | |
176 | * | |
177 | * Thus the strange-looking division by 10 in intel_dp_link_required, to | |
178 | * get the result in decakilobits instead of kilobits. | |
179 | */ | |
180 | ||
a4fc5ed6 | 181 | static int |
c898261c | 182 | intel_dp_link_required(int pixel_clock, int bpp) |
a4fc5ed6 | 183 | { |
cd9dde44 | 184 | return (pixel_clock * bpp + 9) / 10; |
a4fc5ed6 KP |
185 | } |
186 | ||
fe27d53e DA |
187 | static int |
188 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) | |
189 | { | |
190 | return (max_link_clock * max_lanes * 8) / 10; | |
191 | } | |
192 | ||
c19de8eb | 193 | static enum drm_mode_status |
a4fc5ed6 KP |
194 | intel_dp_mode_valid(struct drm_connector *connector, |
195 | struct drm_display_mode *mode) | |
196 | { | |
df0e9248 | 197 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
dd06f90e JN |
198 | struct intel_connector *intel_connector = to_intel_connector(connector); |
199 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
36008365 DV |
200 | int target_clock = mode->clock; |
201 | int max_rate, mode_rate, max_lanes, max_link_clock; | |
799487f5 | 202 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
a4fc5ed6 | 203 | |
dd06f90e JN |
204 | if (is_edp(intel_dp) && fixed_mode) { |
205 | if (mode->hdisplay > fixed_mode->hdisplay) | |
7de56f43 ZY |
206 | return MODE_PANEL; |
207 | ||
dd06f90e | 208 | if (mode->vdisplay > fixed_mode->vdisplay) |
7de56f43 | 209 | return MODE_PANEL; |
03afc4a2 DV |
210 | |
211 | target_clock = fixed_mode->clock; | |
7de56f43 ZY |
212 | } |
213 | ||
50fec21a | 214 | max_link_clock = intel_dp_max_link_rate(intel_dp); |
eeb6324d | 215 | max_lanes = intel_dp_max_lane_count(intel_dp); |
36008365 DV |
216 | |
217 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); | |
218 | mode_rate = intel_dp_link_required(target_clock, 18); | |
219 | ||
799487f5 | 220 | if (mode_rate > max_rate || target_clock > max_dotclk) |
c4867936 | 221 | return MODE_CLOCK_HIGH; |
a4fc5ed6 KP |
222 | |
223 | if (mode->clock < 10000) | |
224 | return MODE_CLOCK_LOW; | |
225 | ||
0af78a2b DV |
226 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
227 | return MODE_H_ILLEGAL; | |
228 | ||
a4fc5ed6 KP |
229 | return MODE_OK; |
230 | } | |
231 | ||
a4f1289e | 232 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes) |
a4fc5ed6 KP |
233 | { |
234 | int i; | |
235 | uint32_t v = 0; | |
236 | ||
237 | if (src_bytes > 4) | |
238 | src_bytes = 4; | |
239 | for (i = 0; i < src_bytes; i++) | |
240 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
241 | return v; | |
242 | } | |
243 | ||
c2af70e2 | 244 | static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
a4fc5ed6 KP |
245 | { |
246 | int i; | |
247 | if (dst_bytes > 4) | |
248 | dst_bytes = 4; | |
249 | for (i = 0; i < dst_bytes; i++) | |
250 | dst[i] = src >> ((3-i) * 8); | |
251 | } | |
252 | ||
bf13e81b JN |
253 | static void |
254 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
36b5f425 | 255 | struct intel_dp *intel_dp); |
bf13e81b JN |
256 | static void |
257 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
36b5f425 | 258 | struct intel_dp *intel_dp); |
335f752b ID |
259 | static void |
260 | intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp); | |
bf13e81b | 261 | |
773538e8 VS |
262 | static void pps_lock(struct intel_dp *intel_dp) |
263 | { | |
264 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
265 | struct intel_encoder *encoder = &intel_dig_port->base; | |
266 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 267 | struct drm_i915_private *dev_priv = to_i915(dev); |
773538e8 VS |
268 | enum intel_display_power_domain power_domain; |
269 | ||
270 | /* | |
271 | * See vlv_power_sequencer_reset() why we need | |
272 | * a power domain reference here. | |
273 | */ | |
25f78f58 | 274 | power_domain = intel_display_port_aux_power_domain(encoder); |
773538e8 VS |
275 | intel_display_power_get(dev_priv, power_domain); |
276 | ||
277 | mutex_lock(&dev_priv->pps_mutex); | |
278 | } | |
279 | ||
280 | static void pps_unlock(struct intel_dp *intel_dp) | |
281 | { | |
282 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
283 | struct intel_encoder *encoder = &intel_dig_port->base; | |
284 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 285 | struct drm_i915_private *dev_priv = to_i915(dev); |
773538e8 VS |
286 | enum intel_display_power_domain power_domain; |
287 | ||
288 | mutex_unlock(&dev_priv->pps_mutex); | |
289 | ||
25f78f58 | 290 | power_domain = intel_display_port_aux_power_domain(encoder); |
773538e8 VS |
291 | intel_display_power_put(dev_priv, power_domain); |
292 | } | |
293 | ||
961a0db0 VS |
294 | static void |
295 | vlv_power_sequencer_kick(struct intel_dp *intel_dp) | |
296 | { | |
297 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
298 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 299 | struct drm_i915_private *dev_priv = to_i915(dev); |
961a0db0 | 300 | enum pipe pipe = intel_dp->pps_pipe; |
0047eedc VS |
301 | bool pll_enabled, release_cl_override = false; |
302 | enum dpio_phy phy = DPIO_PHY(pipe); | |
303 | enum dpio_channel ch = vlv_pipe_to_channel(pipe); | |
961a0db0 VS |
304 | uint32_t DP; |
305 | ||
306 | if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, | |
307 | "skipping pipe %c power seqeuncer kick due to port %c being active\n", | |
308 | pipe_name(pipe), port_name(intel_dig_port->port))) | |
309 | return; | |
310 | ||
311 | DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n", | |
312 | pipe_name(pipe), port_name(intel_dig_port->port)); | |
313 | ||
314 | /* Preserve the BIOS-computed detected bit. This is | |
315 | * supposed to be read-only. | |
316 | */ | |
317 | DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
318 | DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; | |
319 | DP |= DP_PORT_WIDTH(1); | |
320 | DP |= DP_LINK_TRAIN_PAT_1; | |
321 | ||
322 | if (IS_CHERRYVIEW(dev)) | |
323 | DP |= DP_PIPE_SELECT_CHV(pipe); | |
324 | else if (pipe == PIPE_B) | |
325 | DP |= DP_PIPEB_SELECT; | |
326 | ||
d288f65f VS |
327 | pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; |
328 | ||
329 | /* | |
330 | * The DPLL for the pipe must be enabled for this to work. | |
331 | * So enable temporarily it if it's not already enabled. | |
332 | */ | |
0047eedc VS |
333 | if (!pll_enabled) { |
334 | release_cl_override = IS_CHERRYVIEW(dev) && | |
335 | !chv_phy_powergate_ch(dev_priv, phy, ch, true); | |
336 | ||
3f36b937 TU |
337 | if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ? |
338 | &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) { | |
339 | DRM_ERROR("Failed to force on pll for pipe %c!\n", | |
340 | pipe_name(pipe)); | |
341 | return; | |
342 | } | |
0047eedc | 343 | } |
d288f65f | 344 | |
961a0db0 VS |
345 | /* |
346 | * Similar magic as in intel_dp_enable_port(). | |
347 | * We _must_ do this port enable + disable trick | |
348 | * to make this power seqeuencer lock onto the port. | |
349 | * Otherwise even VDD force bit won't work. | |
350 | */ | |
351 | I915_WRITE(intel_dp->output_reg, DP); | |
352 | POSTING_READ(intel_dp->output_reg); | |
353 | ||
354 | I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); | |
355 | POSTING_READ(intel_dp->output_reg); | |
356 | ||
357 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); | |
358 | POSTING_READ(intel_dp->output_reg); | |
d288f65f | 359 | |
0047eedc | 360 | if (!pll_enabled) { |
d288f65f | 361 | vlv_force_pll_off(dev, pipe); |
0047eedc VS |
362 | |
363 | if (release_cl_override) | |
364 | chv_phy_powergate_ch(dev_priv, phy, ch, false); | |
365 | } | |
961a0db0 VS |
366 | } |
367 | ||
bf13e81b JN |
368 | static enum pipe |
369 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) | |
370 | { | |
371 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
bf13e81b | 372 | struct drm_device *dev = intel_dig_port->base.base.dev; |
fac5e23e | 373 | struct drm_i915_private *dev_priv = to_i915(dev); |
a4a5d2f8 VS |
374 | struct intel_encoder *encoder; |
375 | unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); | |
a8c3344e | 376 | enum pipe pipe; |
bf13e81b | 377 | |
e39b999a | 378 | lockdep_assert_held(&dev_priv->pps_mutex); |
bf13e81b | 379 | |
a8c3344e VS |
380 | /* We should never land here with regular DP ports */ |
381 | WARN_ON(!is_edp(intel_dp)); | |
382 | ||
a4a5d2f8 VS |
383 | if (intel_dp->pps_pipe != INVALID_PIPE) |
384 | return intel_dp->pps_pipe; | |
385 | ||
386 | /* | |
387 | * We don't have power sequencer currently. | |
388 | * Pick one that's not used by other ports. | |
389 | */ | |
19c8054c | 390 | for_each_intel_encoder(dev, encoder) { |
a4a5d2f8 VS |
391 | struct intel_dp *tmp; |
392 | ||
393 | if (encoder->type != INTEL_OUTPUT_EDP) | |
394 | continue; | |
395 | ||
396 | tmp = enc_to_intel_dp(&encoder->base); | |
397 | ||
398 | if (tmp->pps_pipe != INVALID_PIPE) | |
399 | pipes &= ~(1 << tmp->pps_pipe); | |
400 | } | |
401 | ||
402 | /* | |
403 | * Didn't find one. This should not happen since there | |
404 | * are two power sequencers and up to two eDP ports. | |
405 | */ | |
406 | if (WARN_ON(pipes == 0)) | |
a8c3344e VS |
407 | pipe = PIPE_A; |
408 | else | |
409 | pipe = ffs(pipes) - 1; | |
a4a5d2f8 | 410 | |
a8c3344e VS |
411 | vlv_steal_power_sequencer(dev, pipe); |
412 | intel_dp->pps_pipe = pipe; | |
a4a5d2f8 VS |
413 | |
414 | DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n", | |
415 | pipe_name(intel_dp->pps_pipe), | |
416 | port_name(intel_dig_port->port)); | |
417 | ||
418 | /* init power sequencer on this pipe and port */ | |
36b5f425 VS |
419 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
420 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); | |
a4a5d2f8 | 421 | |
961a0db0 VS |
422 | /* |
423 | * Even vdd force doesn't work until we've made | |
424 | * the power sequencer lock in on the port. | |
425 | */ | |
426 | vlv_power_sequencer_kick(intel_dp); | |
a4a5d2f8 VS |
427 | |
428 | return intel_dp->pps_pipe; | |
429 | } | |
430 | ||
78597996 ID |
431 | static int |
432 | bxt_power_sequencer_idx(struct intel_dp *intel_dp) | |
433 | { | |
434 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
435 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 436 | struct drm_i915_private *dev_priv = to_i915(dev); |
78597996 ID |
437 | |
438 | lockdep_assert_held(&dev_priv->pps_mutex); | |
439 | ||
440 | /* We should never land here with regular DP ports */ | |
441 | WARN_ON(!is_edp(intel_dp)); | |
442 | ||
443 | /* | |
444 | * TODO: BXT has 2 PPS instances. The correct port->PPS instance | |
445 | * mapping needs to be retrieved from VBT, for now just hard-code to | |
446 | * use instance #0 always. | |
447 | */ | |
448 | if (!intel_dp->pps_reset) | |
449 | return 0; | |
450 | ||
451 | intel_dp->pps_reset = false; | |
452 | ||
453 | /* | |
454 | * Only the HW needs to be reprogrammed, the SW state is fixed and | |
455 | * has been setup during connector init. | |
456 | */ | |
457 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); | |
458 | ||
459 | return 0; | |
460 | } | |
461 | ||
6491ab27 VS |
462 | typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, |
463 | enum pipe pipe); | |
464 | ||
465 | static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, | |
466 | enum pipe pipe) | |
467 | { | |
44cb734c | 468 | return I915_READ(PP_STATUS(pipe)) & PP_ON; |
6491ab27 VS |
469 | } |
470 | ||
471 | static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, | |
472 | enum pipe pipe) | |
473 | { | |
44cb734c | 474 | return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD; |
6491ab27 VS |
475 | } |
476 | ||
477 | static bool vlv_pipe_any(struct drm_i915_private *dev_priv, | |
478 | enum pipe pipe) | |
479 | { | |
480 | return true; | |
481 | } | |
bf13e81b | 482 | |
a4a5d2f8 | 483 | static enum pipe |
6491ab27 VS |
484 | vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, |
485 | enum port port, | |
486 | vlv_pipe_check pipe_check) | |
a4a5d2f8 VS |
487 | { |
488 | enum pipe pipe; | |
bf13e81b | 489 | |
bf13e81b | 490 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
44cb734c | 491 | u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) & |
bf13e81b | 492 | PANEL_PORT_SELECT_MASK; |
a4a5d2f8 VS |
493 | |
494 | if (port_sel != PANEL_PORT_SELECT_VLV(port)) | |
495 | continue; | |
496 | ||
6491ab27 VS |
497 | if (!pipe_check(dev_priv, pipe)) |
498 | continue; | |
499 | ||
a4a5d2f8 | 500 | return pipe; |
bf13e81b JN |
501 | } |
502 | ||
a4a5d2f8 VS |
503 | return INVALID_PIPE; |
504 | } | |
505 | ||
506 | static void | |
507 | vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) | |
508 | { | |
509 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
510 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 511 | struct drm_i915_private *dev_priv = to_i915(dev); |
a4a5d2f8 VS |
512 | enum port port = intel_dig_port->port; |
513 | ||
514 | lockdep_assert_held(&dev_priv->pps_mutex); | |
515 | ||
516 | /* try to find a pipe with this port selected */ | |
6491ab27 VS |
517 | /* first pick one where the panel is on */ |
518 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
519 | vlv_pipe_has_pp_on); | |
520 | /* didn't find one? pick one where vdd is on */ | |
521 | if (intel_dp->pps_pipe == INVALID_PIPE) | |
522 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
523 | vlv_pipe_has_vdd_on); | |
524 | /* didn't find one? pick one with just the correct port */ | |
525 | if (intel_dp->pps_pipe == INVALID_PIPE) | |
526 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
527 | vlv_pipe_any); | |
a4a5d2f8 VS |
528 | |
529 | /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ | |
530 | if (intel_dp->pps_pipe == INVALID_PIPE) { | |
531 | DRM_DEBUG_KMS("no initial power sequencer for port %c\n", | |
532 | port_name(port)); | |
533 | return; | |
bf13e81b JN |
534 | } |
535 | ||
a4a5d2f8 VS |
536 | DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n", |
537 | port_name(port), pipe_name(intel_dp->pps_pipe)); | |
538 | ||
36b5f425 VS |
539 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
540 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); | |
bf13e81b JN |
541 | } |
542 | ||
78597996 | 543 | void intel_power_sequencer_reset(struct drm_i915_private *dev_priv) |
773538e8 | 544 | { |
91c8a326 | 545 | struct drm_device *dev = &dev_priv->drm; |
773538e8 VS |
546 | struct intel_encoder *encoder; |
547 | ||
78597996 ID |
548 | if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
549 | !IS_BROXTON(dev))) | |
773538e8 VS |
550 | return; |
551 | ||
552 | /* | |
553 | * We can't grab pps_mutex here due to deadlock with power_domain | |
554 | * mutex when power_domain functions are called while holding pps_mutex. | |
555 | * That also means that in order to use pps_pipe the code needs to | |
556 | * hold both a power domain reference and pps_mutex, and the power domain | |
557 | * reference get/put must be done while _not_ holding pps_mutex. | |
558 | * pps_{lock,unlock}() do these steps in the correct order, so one | |
559 | * should use them always. | |
560 | */ | |
561 | ||
19c8054c | 562 | for_each_intel_encoder(dev, encoder) { |
773538e8 VS |
563 | struct intel_dp *intel_dp; |
564 | ||
565 | if (encoder->type != INTEL_OUTPUT_EDP) | |
566 | continue; | |
567 | ||
568 | intel_dp = enc_to_intel_dp(&encoder->base); | |
78597996 ID |
569 | if (IS_BROXTON(dev)) |
570 | intel_dp->pps_reset = true; | |
571 | else | |
572 | intel_dp->pps_pipe = INVALID_PIPE; | |
773538e8 | 573 | } |
bf13e81b JN |
574 | } |
575 | ||
8e8232d5 ID |
576 | struct pps_registers { |
577 | i915_reg_t pp_ctrl; | |
578 | i915_reg_t pp_stat; | |
579 | i915_reg_t pp_on; | |
580 | i915_reg_t pp_off; | |
581 | i915_reg_t pp_div; | |
582 | }; | |
583 | ||
584 | static void intel_pps_get_registers(struct drm_i915_private *dev_priv, | |
585 | struct intel_dp *intel_dp, | |
586 | struct pps_registers *regs) | |
587 | { | |
44cb734c ID |
588 | int pps_idx = 0; |
589 | ||
8e8232d5 ID |
590 | memset(regs, 0, sizeof(*regs)); |
591 | ||
44cb734c ID |
592 | if (IS_BROXTON(dev_priv)) |
593 | pps_idx = bxt_power_sequencer_idx(intel_dp); | |
594 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
595 | pps_idx = vlv_power_sequencer_pipe(intel_dp); | |
8e8232d5 | 596 | |
44cb734c ID |
597 | regs->pp_ctrl = PP_CONTROL(pps_idx); |
598 | regs->pp_stat = PP_STATUS(pps_idx); | |
599 | regs->pp_on = PP_ON_DELAYS(pps_idx); | |
600 | regs->pp_off = PP_OFF_DELAYS(pps_idx); | |
601 | if (!IS_BROXTON(dev_priv)) | |
602 | regs->pp_div = PP_DIVISOR(pps_idx); | |
8e8232d5 ID |
603 | } |
604 | ||
f0f59a00 VS |
605 | static i915_reg_t |
606 | _pp_ctrl_reg(struct intel_dp *intel_dp) | |
bf13e81b | 607 | { |
8e8232d5 | 608 | struct pps_registers regs; |
bf13e81b | 609 | |
8e8232d5 ID |
610 | intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp, |
611 | ®s); | |
612 | ||
613 | return regs.pp_ctrl; | |
bf13e81b JN |
614 | } |
615 | ||
f0f59a00 VS |
616 | static i915_reg_t |
617 | _pp_stat_reg(struct intel_dp *intel_dp) | |
bf13e81b | 618 | { |
8e8232d5 | 619 | struct pps_registers regs; |
bf13e81b | 620 | |
8e8232d5 ID |
621 | intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp, |
622 | ®s); | |
623 | ||
624 | return regs.pp_stat; | |
bf13e81b JN |
625 | } |
626 | ||
01527b31 CT |
627 | /* Reboot notifier handler to shutdown panel power to guarantee T12 timing |
628 | This function only applicable when panel PM state is not to be tracked */ | |
629 | static int edp_notify_handler(struct notifier_block *this, unsigned long code, | |
630 | void *unused) | |
631 | { | |
632 | struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), | |
633 | edp_notifier); | |
634 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
fac5e23e | 635 | struct drm_i915_private *dev_priv = to_i915(dev); |
01527b31 CT |
636 | |
637 | if (!is_edp(intel_dp) || code != SYS_RESTART) | |
638 | return 0; | |
639 | ||
773538e8 | 640 | pps_lock(intel_dp); |
e39b999a | 641 | |
666a4537 | 642 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
e39b999a | 643 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
f0f59a00 | 644 | i915_reg_t pp_ctrl_reg, pp_div_reg; |
649636ef | 645 | u32 pp_div; |
e39b999a | 646 | |
44cb734c ID |
647 | pp_ctrl_reg = PP_CONTROL(pipe); |
648 | pp_div_reg = PP_DIVISOR(pipe); | |
01527b31 CT |
649 | pp_div = I915_READ(pp_div_reg); |
650 | pp_div &= PP_REFERENCE_DIVIDER_MASK; | |
651 | ||
652 | /* 0x1F write to PP_DIV_REG sets max cycle delay */ | |
653 | I915_WRITE(pp_div_reg, pp_div | 0x1F); | |
654 | I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); | |
655 | msleep(intel_dp->panel_power_cycle_delay); | |
656 | } | |
657 | ||
773538e8 | 658 | pps_unlock(intel_dp); |
e39b999a | 659 | |
01527b31 CT |
660 | return 0; |
661 | } | |
662 | ||
4be73780 | 663 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
ebf33b18 | 664 | { |
30add22d | 665 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 666 | struct drm_i915_private *dev_priv = to_i915(dev); |
ebf33b18 | 667 | |
e39b999a VS |
668 | lockdep_assert_held(&dev_priv->pps_mutex); |
669 | ||
666a4537 | 670 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
9a42356b VS |
671 | intel_dp->pps_pipe == INVALID_PIPE) |
672 | return false; | |
673 | ||
bf13e81b | 674 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
ebf33b18 KP |
675 | } |
676 | ||
4be73780 | 677 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
ebf33b18 | 678 | { |
30add22d | 679 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 680 | struct drm_i915_private *dev_priv = to_i915(dev); |
ebf33b18 | 681 | |
e39b999a VS |
682 | lockdep_assert_held(&dev_priv->pps_mutex); |
683 | ||
666a4537 | 684 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
9a42356b VS |
685 | intel_dp->pps_pipe == INVALID_PIPE) |
686 | return false; | |
687 | ||
773538e8 | 688 | return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; |
ebf33b18 KP |
689 | } |
690 | ||
9b984dae KP |
691 | static void |
692 | intel_dp_check_edp(struct intel_dp *intel_dp) | |
693 | { | |
30add22d | 694 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 695 | struct drm_i915_private *dev_priv = to_i915(dev); |
ebf33b18 | 696 | |
9b984dae KP |
697 | if (!is_edp(intel_dp)) |
698 | return; | |
453c5420 | 699 | |
4be73780 | 700 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
9b984dae KP |
701 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
702 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", | |
bf13e81b JN |
703 | I915_READ(_pp_stat_reg(intel_dp)), |
704 | I915_READ(_pp_ctrl_reg(intel_dp))); | |
9b984dae KP |
705 | } |
706 | } | |
707 | ||
9ee32fea DV |
708 | static uint32_t |
709 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) | |
710 | { | |
711 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
712 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 713 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 714 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
9ee32fea DV |
715 | uint32_t status; |
716 | bool done; | |
717 | ||
ef04f00d | 718 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
9ee32fea | 719 | if (has_aux_irq) |
b18ac466 | 720 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
3598706b | 721 | msecs_to_jiffies_timeout(10)); |
9ee32fea | 722 | else |
713a6b66 | 723 | done = wait_for(C, 10) == 0; |
9ee32fea DV |
724 | if (!done) |
725 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", | |
726 | has_aux_irq); | |
727 | #undef C | |
728 | ||
729 | return status; | |
730 | } | |
731 | ||
6ffb1be7 | 732 | static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
a4fc5ed6 | 733 | { |
174edf1f | 734 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
e7dc33f3 | 735 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
9ee32fea | 736 | |
a457f54b VS |
737 | if (index) |
738 | return 0; | |
739 | ||
ec5b01dd DL |
740 | /* |
741 | * The clock divider is based off the hrawclk, and would like to run at | |
a457f54b | 742 | * 2MHz. So, take the hrawclk value and divide by 2000 and use that |
a4fc5ed6 | 743 | */ |
a457f54b | 744 | return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); |
ec5b01dd DL |
745 | } |
746 | ||
747 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
748 | { | |
749 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
a457f54b | 750 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
ec5b01dd DL |
751 | |
752 | if (index) | |
753 | return 0; | |
754 | ||
a457f54b VS |
755 | /* |
756 | * The clock divider is based off the cdclk or PCH rawclk, and would | |
757 | * like to run at 2MHz. So, take the cdclk or PCH rawclk value and | |
758 | * divide by 2000 and use that | |
759 | */ | |
e7dc33f3 | 760 | if (intel_dig_port->port == PORT_A) |
fce18c4c | 761 | return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); |
e7dc33f3 VS |
762 | else |
763 | return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); | |
ec5b01dd DL |
764 | } |
765 | ||
766 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
767 | { | |
768 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
a457f54b | 769 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
ec5b01dd | 770 | |
a457f54b | 771 | if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) { |
2c55c336 | 772 | /* Workaround for non-ULT HSW */ |
bc86625a CW |
773 | switch (index) { |
774 | case 0: return 63; | |
775 | case 1: return 72; | |
776 | default: return 0; | |
777 | } | |
2c55c336 | 778 | } |
a457f54b VS |
779 | |
780 | return ilk_get_aux_clock_divider(intel_dp, index); | |
b84a1cf8 RV |
781 | } |
782 | ||
b6b5e383 DL |
783 | static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
784 | { | |
785 | /* | |
786 | * SKL doesn't need us to program the AUX clock divider (Hardware will | |
787 | * derive the clock from CDCLK automatically). We still implement the | |
788 | * get_aux_clock_divider vfunc to plug-in into the existing code. | |
789 | */ | |
790 | return index ? 0 : 1; | |
791 | } | |
792 | ||
6ffb1be7 VS |
793 | static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp, |
794 | bool has_aux_irq, | |
795 | int send_bytes, | |
796 | uint32_t aux_clock_divider) | |
5ed12a19 DL |
797 | { |
798 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
799 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
800 | uint32_t precharge, timeout; | |
801 | ||
802 | if (IS_GEN6(dev)) | |
803 | precharge = 3; | |
804 | else | |
805 | precharge = 5; | |
806 | ||
f3c6a3a7 | 807 | if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A) |
5ed12a19 DL |
808 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
809 | else | |
810 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; | |
811 | ||
812 | return DP_AUX_CH_CTL_SEND_BUSY | | |
788d4433 | 813 | DP_AUX_CH_CTL_DONE | |
5ed12a19 | 814 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
788d4433 | 815 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
5ed12a19 | 816 | timeout | |
788d4433 | 817 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
5ed12a19 DL |
818 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
819 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
788d4433 | 820 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
5ed12a19 DL |
821 | } |
822 | ||
b9ca5fad DL |
823 | static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, |
824 | bool has_aux_irq, | |
825 | int send_bytes, | |
826 | uint32_t unused) | |
827 | { | |
828 | return DP_AUX_CH_CTL_SEND_BUSY | | |
829 | DP_AUX_CH_CTL_DONE | | |
830 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | | |
831 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
832 | DP_AUX_CH_CTL_TIME_OUT_1600us | | |
833 | DP_AUX_CH_CTL_RECEIVE_ERROR | | |
834 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
d4dcbdce | 835 | DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | |
b9ca5fad DL |
836 | DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); |
837 | } | |
838 | ||
b84a1cf8 RV |
839 | static int |
840 | intel_dp_aux_ch(struct intel_dp *intel_dp, | |
bd9f74a5 | 841 | const uint8_t *send, int send_bytes, |
b84a1cf8 RV |
842 | uint8_t *recv, int recv_size) |
843 | { | |
844 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
845 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 846 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 847 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
bc86625a | 848 | uint32_t aux_clock_divider; |
b84a1cf8 RV |
849 | int i, ret, recv_bytes; |
850 | uint32_t status; | |
5ed12a19 | 851 | int try, clock = 0; |
4e6b788c | 852 | bool has_aux_irq = HAS_AUX_IRQ(dev); |
884f19e9 JN |
853 | bool vdd; |
854 | ||
773538e8 | 855 | pps_lock(intel_dp); |
e39b999a | 856 | |
72c3500a VS |
857 | /* |
858 | * We will be called with VDD already enabled for dpcd/edid/oui reads. | |
859 | * In such cases we want to leave VDD enabled and it's up to upper layers | |
860 | * to turn it off. But for eg. i2c-dev access we need to turn it on/off | |
861 | * ourselves. | |
862 | */ | |
1e0560e0 | 863 | vdd = edp_panel_vdd_on(intel_dp); |
b84a1cf8 RV |
864 | |
865 | /* dp aux is extremely sensitive to irq latency, hence request the | |
866 | * lowest possible wakeup latency and so prevent the cpu from going into | |
867 | * deep sleep states. | |
868 | */ | |
869 | pm_qos_update_request(&dev_priv->pm_qos, 0); | |
870 | ||
871 | intel_dp_check_edp(intel_dp); | |
5eb08b69 | 872 | |
11bee43e JB |
873 | /* Try to wait for any previous AUX channel activity */ |
874 | for (try = 0; try < 3; try++) { | |
ef04f00d | 875 | status = I915_READ_NOTRACE(ch_ctl); |
11bee43e JB |
876 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
877 | break; | |
878 | msleep(1); | |
879 | } | |
880 | ||
881 | if (try == 3) { | |
02196c77 MK |
882 | static u32 last_status = -1; |
883 | const u32 status = I915_READ(ch_ctl); | |
884 | ||
885 | if (status != last_status) { | |
886 | WARN(1, "dp_aux_ch not started status 0x%08x\n", | |
887 | status); | |
888 | last_status = status; | |
889 | } | |
890 | ||
9ee32fea DV |
891 | ret = -EBUSY; |
892 | goto out; | |
4f7f7b7e CW |
893 | } |
894 | ||
46a5ae9f PZ |
895 | /* Only 5 data registers! */ |
896 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { | |
897 | ret = -E2BIG; | |
898 | goto out; | |
899 | } | |
900 | ||
ec5b01dd | 901 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
153b1100 DL |
902 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
903 | has_aux_irq, | |
904 | send_bytes, | |
905 | aux_clock_divider); | |
5ed12a19 | 906 | |
bc86625a CW |
907 | /* Must try at least 3 times according to DP spec */ |
908 | for (try = 0; try < 5; try++) { | |
909 | /* Load the send data into the aux channel data registers */ | |
910 | for (i = 0; i < send_bytes; i += 4) | |
330e20ec | 911 | I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2], |
a4f1289e RV |
912 | intel_dp_pack_aux(send + i, |
913 | send_bytes - i)); | |
bc86625a CW |
914 | |
915 | /* Send the command and wait for it to complete */ | |
5ed12a19 | 916 | I915_WRITE(ch_ctl, send_ctl); |
bc86625a CW |
917 | |
918 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); | |
919 | ||
920 | /* Clear done status and any errors */ | |
921 | I915_WRITE(ch_ctl, | |
922 | status | | |
923 | DP_AUX_CH_CTL_DONE | | |
924 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
925 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
926 | ||
74ebf294 | 927 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) |
bc86625a | 928 | continue; |
74ebf294 TP |
929 | |
930 | /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 | |
931 | * 400us delay required for errors and timeouts | |
932 | * Timeout errors from the HW already meet this | |
933 | * requirement so skip to next iteration | |
934 | */ | |
935 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { | |
936 | usleep_range(400, 500); | |
bc86625a | 937 | continue; |
74ebf294 | 938 | } |
bc86625a | 939 | if (status & DP_AUX_CH_CTL_DONE) |
e058c945 | 940 | goto done; |
bc86625a | 941 | } |
a4fc5ed6 KP |
942 | } |
943 | ||
a4fc5ed6 | 944 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 945 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
9ee32fea DV |
946 | ret = -EBUSY; |
947 | goto out; | |
a4fc5ed6 KP |
948 | } |
949 | ||
e058c945 | 950 | done: |
a4fc5ed6 KP |
951 | /* Check for timeout or receive error. |
952 | * Timeouts occur when the sink is not connected | |
953 | */ | |
a5b3da54 | 954 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 955 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
9ee32fea DV |
956 | ret = -EIO; |
957 | goto out; | |
a5b3da54 | 958 | } |
1ae8c0a5 KP |
959 | |
960 | /* Timeouts occur when the device isn't connected, so they're | |
961 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 962 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
28c97730 | 963 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
9ee32fea DV |
964 | ret = -ETIMEDOUT; |
965 | goto out; | |
a4fc5ed6 KP |
966 | } |
967 | ||
968 | /* Unload any bytes sent back from the other side */ | |
969 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
970 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
14e01889 RV |
971 | |
972 | /* | |
973 | * By BSpec: "Message sizes of 0 or >20 are not allowed." | |
974 | * We have no idea of what happened so we return -EBUSY so | |
975 | * drm layer takes care for the necessary retries. | |
976 | */ | |
977 | if (recv_bytes == 0 || recv_bytes > 20) { | |
978 | DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n", | |
979 | recv_bytes); | |
980 | /* | |
981 | * FIXME: This patch was created on top of a series that | |
982 | * organize the retries at drm level. There EBUSY should | |
983 | * also take care for 1ms wait before retrying. | |
984 | * That aux retries re-org is still needed and after that is | |
985 | * merged we remove this sleep from here. | |
986 | */ | |
987 | usleep_range(1000, 1500); | |
988 | ret = -EBUSY; | |
989 | goto out; | |
990 | } | |
991 | ||
a4fc5ed6 KP |
992 | if (recv_bytes > recv_size) |
993 | recv_bytes = recv_size; | |
0206e353 | 994 | |
4f7f7b7e | 995 | for (i = 0; i < recv_bytes; i += 4) |
330e20ec | 996 | intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]), |
a4f1289e | 997 | recv + i, recv_bytes - i); |
a4fc5ed6 | 998 | |
9ee32fea DV |
999 | ret = recv_bytes; |
1000 | out: | |
1001 | pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); | |
1002 | ||
884f19e9 JN |
1003 | if (vdd) |
1004 | edp_panel_vdd_off(intel_dp, false); | |
1005 | ||
773538e8 | 1006 | pps_unlock(intel_dp); |
e39b999a | 1007 | |
9ee32fea | 1008 | return ret; |
a4fc5ed6 KP |
1009 | } |
1010 | ||
a6c8aff0 JN |
1011 | #define BARE_ADDRESS_SIZE 3 |
1012 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) | |
9d1a1031 JN |
1013 | static ssize_t |
1014 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) | |
a4fc5ed6 | 1015 | { |
9d1a1031 JN |
1016 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
1017 | uint8_t txbuf[20], rxbuf[20]; | |
1018 | size_t txsize, rxsize; | |
a4fc5ed6 | 1019 | int ret; |
a4fc5ed6 | 1020 | |
d2d9cbbd VS |
1021 | txbuf[0] = (msg->request << 4) | |
1022 | ((msg->address >> 16) & 0xf); | |
1023 | txbuf[1] = (msg->address >> 8) & 0xff; | |
9d1a1031 JN |
1024 | txbuf[2] = msg->address & 0xff; |
1025 | txbuf[3] = msg->size - 1; | |
46a5ae9f | 1026 | |
9d1a1031 JN |
1027 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
1028 | case DP_AUX_NATIVE_WRITE: | |
1029 | case DP_AUX_I2C_WRITE: | |
c1e74122 | 1030 | case DP_AUX_I2C_WRITE_STATUS_UPDATE: |
a6c8aff0 | 1031 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
a1ddefd8 | 1032 | rxsize = 2; /* 0 or 1 data bytes */ |
f51a44b9 | 1033 | |
9d1a1031 JN |
1034 | if (WARN_ON(txsize > 20)) |
1035 | return -E2BIG; | |
a4fc5ed6 | 1036 | |
dd788090 VS |
1037 | WARN_ON(!msg->buffer != !msg->size); |
1038 | ||
d81a67cc ID |
1039 | if (msg->buffer) |
1040 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); | |
a4fc5ed6 | 1041 | |
9d1a1031 JN |
1042 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
1043 | if (ret > 0) { | |
1044 | msg->reply = rxbuf[0] >> 4; | |
a4fc5ed6 | 1045 | |
a1ddefd8 JN |
1046 | if (ret > 1) { |
1047 | /* Number of bytes written in a short write. */ | |
1048 | ret = clamp_t(int, rxbuf[1], 0, msg->size); | |
1049 | } else { | |
1050 | /* Return payload size. */ | |
1051 | ret = msg->size; | |
1052 | } | |
9d1a1031 JN |
1053 | } |
1054 | break; | |
46a5ae9f | 1055 | |
9d1a1031 JN |
1056 | case DP_AUX_NATIVE_READ: |
1057 | case DP_AUX_I2C_READ: | |
a6c8aff0 | 1058 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
9d1a1031 | 1059 | rxsize = msg->size + 1; |
a4fc5ed6 | 1060 | |
9d1a1031 JN |
1061 | if (WARN_ON(rxsize > 20)) |
1062 | return -E2BIG; | |
a4fc5ed6 | 1063 | |
9d1a1031 JN |
1064 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
1065 | if (ret > 0) { | |
1066 | msg->reply = rxbuf[0] >> 4; | |
1067 | /* | |
1068 | * Assume happy day, and copy the data. The caller is | |
1069 | * expected to check msg->reply before touching it. | |
1070 | * | |
1071 | * Return payload size. | |
1072 | */ | |
1073 | ret--; | |
1074 | memcpy(msg->buffer, rxbuf + 1, ret); | |
a4fc5ed6 | 1075 | } |
9d1a1031 JN |
1076 | break; |
1077 | ||
1078 | default: | |
1079 | ret = -EINVAL; | |
1080 | break; | |
a4fc5ed6 | 1081 | } |
f51a44b9 | 1082 | |
9d1a1031 | 1083 | return ret; |
a4fc5ed6 KP |
1084 | } |
1085 | ||
f0f59a00 VS |
1086 | static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv, |
1087 | enum port port) | |
da00bdcf VS |
1088 | { |
1089 | switch (port) { | |
1090 | case PORT_B: | |
1091 | case PORT_C: | |
1092 | case PORT_D: | |
1093 | return DP_AUX_CH_CTL(port); | |
1094 | default: | |
1095 | MISSING_CASE(port); | |
1096 | return DP_AUX_CH_CTL(PORT_B); | |
1097 | } | |
1098 | } | |
1099 | ||
f0f59a00 VS |
1100 | static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv, |
1101 | enum port port, int index) | |
330e20ec VS |
1102 | { |
1103 | switch (port) { | |
1104 | case PORT_B: | |
1105 | case PORT_C: | |
1106 | case PORT_D: | |
1107 | return DP_AUX_CH_DATA(port, index); | |
1108 | default: | |
1109 | MISSING_CASE(port); | |
1110 | return DP_AUX_CH_DATA(PORT_B, index); | |
1111 | } | |
1112 | } | |
1113 | ||
f0f59a00 VS |
1114 | static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv, |
1115 | enum port port) | |
da00bdcf VS |
1116 | { |
1117 | switch (port) { | |
1118 | case PORT_A: | |
1119 | return DP_AUX_CH_CTL(port); | |
1120 | case PORT_B: | |
1121 | case PORT_C: | |
1122 | case PORT_D: | |
1123 | return PCH_DP_AUX_CH_CTL(port); | |
1124 | default: | |
1125 | MISSING_CASE(port); | |
1126 | return DP_AUX_CH_CTL(PORT_A); | |
1127 | } | |
1128 | } | |
1129 | ||
f0f59a00 VS |
1130 | static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv, |
1131 | enum port port, int index) | |
330e20ec VS |
1132 | { |
1133 | switch (port) { | |
1134 | case PORT_A: | |
1135 | return DP_AUX_CH_DATA(port, index); | |
1136 | case PORT_B: | |
1137 | case PORT_C: | |
1138 | case PORT_D: | |
1139 | return PCH_DP_AUX_CH_DATA(port, index); | |
1140 | default: | |
1141 | MISSING_CASE(port); | |
1142 | return DP_AUX_CH_DATA(PORT_A, index); | |
1143 | } | |
1144 | } | |
1145 | ||
da00bdcf VS |
1146 | /* |
1147 | * On SKL we don't have Aux for port E so we rely | |
1148 | * on VBT to set a proper alternate aux channel. | |
1149 | */ | |
1150 | static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv) | |
1151 | { | |
1152 | const struct ddi_vbt_port_info *info = | |
1153 | &dev_priv->vbt.ddi_port_info[PORT_E]; | |
1154 | ||
1155 | switch (info->alternate_aux_channel) { | |
1156 | case DP_AUX_A: | |
1157 | return PORT_A; | |
1158 | case DP_AUX_B: | |
1159 | return PORT_B; | |
1160 | case DP_AUX_C: | |
1161 | return PORT_C; | |
1162 | case DP_AUX_D: | |
1163 | return PORT_D; | |
1164 | default: | |
1165 | MISSING_CASE(info->alternate_aux_channel); | |
1166 | return PORT_A; | |
1167 | } | |
1168 | } | |
1169 | ||
f0f59a00 VS |
1170 | static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv, |
1171 | enum port port) | |
da00bdcf VS |
1172 | { |
1173 | if (port == PORT_E) | |
1174 | port = skl_porte_aux_port(dev_priv); | |
1175 | ||
1176 | switch (port) { | |
1177 | case PORT_A: | |
1178 | case PORT_B: | |
1179 | case PORT_C: | |
1180 | case PORT_D: | |
1181 | return DP_AUX_CH_CTL(port); | |
1182 | default: | |
1183 | MISSING_CASE(port); | |
1184 | return DP_AUX_CH_CTL(PORT_A); | |
1185 | } | |
1186 | } | |
1187 | ||
f0f59a00 VS |
1188 | static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv, |
1189 | enum port port, int index) | |
330e20ec VS |
1190 | { |
1191 | if (port == PORT_E) | |
1192 | port = skl_porte_aux_port(dev_priv); | |
1193 | ||
1194 | switch (port) { | |
1195 | case PORT_A: | |
1196 | case PORT_B: | |
1197 | case PORT_C: | |
1198 | case PORT_D: | |
1199 | return DP_AUX_CH_DATA(port, index); | |
1200 | default: | |
1201 | MISSING_CASE(port); | |
1202 | return DP_AUX_CH_DATA(PORT_A, index); | |
1203 | } | |
1204 | } | |
1205 | ||
f0f59a00 VS |
1206 | static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv, |
1207 | enum port port) | |
330e20ec VS |
1208 | { |
1209 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
1210 | return skl_aux_ctl_reg(dev_priv, port); | |
1211 | else if (HAS_PCH_SPLIT(dev_priv)) | |
1212 | return ilk_aux_ctl_reg(dev_priv, port); | |
1213 | else | |
1214 | return g4x_aux_ctl_reg(dev_priv, port); | |
1215 | } | |
1216 | ||
f0f59a00 VS |
1217 | static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv, |
1218 | enum port port, int index) | |
330e20ec VS |
1219 | { |
1220 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
1221 | return skl_aux_data_reg(dev_priv, port, index); | |
1222 | else if (HAS_PCH_SPLIT(dev_priv)) | |
1223 | return ilk_aux_data_reg(dev_priv, port, index); | |
1224 | else | |
1225 | return g4x_aux_data_reg(dev_priv, port, index); | |
1226 | } | |
1227 | ||
1228 | static void intel_aux_reg_init(struct intel_dp *intel_dp) | |
1229 | { | |
1230 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); | |
1231 | enum port port = dp_to_dig_port(intel_dp)->port; | |
1232 | int i; | |
1233 | ||
1234 | intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port); | |
1235 | for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++) | |
1236 | intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i); | |
1237 | } | |
1238 | ||
9d1a1031 | 1239 | static void |
a121f4e5 VS |
1240 | intel_dp_aux_fini(struct intel_dp *intel_dp) |
1241 | { | |
a121f4e5 VS |
1242 | kfree(intel_dp->aux.name); |
1243 | } | |
1244 | ||
7a418e34 | 1245 | static void |
9d1a1031 JN |
1246 | intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) |
1247 | { | |
33ad6626 JN |
1248 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1249 | enum port port = intel_dig_port->port; | |
ab2c0672 | 1250 | |
330e20ec | 1251 | intel_aux_reg_init(intel_dp); |
7a418e34 | 1252 | drm_dp_aux_init(&intel_dp->aux); |
8316f337 | 1253 | |
7a418e34 | 1254 | /* Failure to allocate our preferred name is not critical */ |
a121f4e5 | 1255 | intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port)); |
9d1a1031 | 1256 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
a4fc5ed6 KP |
1257 | } |
1258 | ||
fc0f8e25 | 1259 | static int |
12f6a2e2 | 1260 | intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates) |
fc0f8e25 | 1261 | { |
94ca719e VS |
1262 | if (intel_dp->num_sink_rates) { |
1263 | *sink_rates = intel_dp->sink_rates; | |
1264 | return intel_dp->num_sink_rates; | |
fc0f8e25 | 1265 | } |
12f6a2e2 VS |
1266 | |
1267 | *sink_rates = default_rates; | |
1268 | ||
1269 | return (intel_dp_max_link_bw(intel_dp) >> 3) + 1; | |
fc0f8e25 SJ |
1270 | } |
1271 | ||
e588fa18 | 1272 | bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) |
ed63baaf | 1273 | { |
e588fa18 ACO |
1274 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1275 | struct drm_device *dev = dig_port->base.base.dev; | |
1276 | ||
ed63baaf | 1277 | /* WaDisableHBR2:skl */ |
e87a005d | 1278 | if (IS_SKL_REVID(dev, 0, SKL_REVID_B0)) |
ed63baaf TS |
1279 | return false; |
1280 | ||
1281 | if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) || | |
1282 | (INTEL_INFO(dev)->gen >= 9)) | |
1283 | return true; | |
1284 | else | |
1285 | return false; | |
1286 | } | |
1287 | ||
a8f3ef61 | 1288 | static int |
e588fa18 | 1289 | intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates) |
a8f3ef61 | 1290 | { |
e588fa18 ACO |
1291 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1292 | struct drm_device *dev = dig_port->base.base.dev; | |
af7080f5 TS |
1293 | int size; |
1294 | ||
64987fc5 SJ |
1295 | if (IS_BROXTON(dev)) { |
1296 | *source_rates = bxt_rates; | |
af7080f5 | 1297 | size = ARRAY_SIZE(bxt_rates); |
ef11bdb3 | 1298 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
637a9c63 | 1299 | *source_rates = skl_rates; |
af7080f5 TS |
1300 | size = ARRAY_SIZE(skl_rates); |
1301 | } else { | |
1302 | *source_rates = default_rates; | |
1303 | size = ARRAY_SIZE(default_rates); | |
a8f3ef61 | 1304 | } |
636280ba | 1305 | |
ed63baaf | 1306 | /* This depends on the fact that 5.4 is last value in the array */ |
e588fa18 | 1307 | if (!intel_dp_source_supports_hbr2(intel_dp)) |
af7080f5 | 1308 | size--; |
636280ba | 1309 | |
af7080f5 | 1310 | return size; |
a8f3ef61 SJ |
1311 | } |
1312 | ||
c6bb3538 DV |
1313 | static void |
1314 | intel_dp_set_clock(struct intel_encoder *encoder, | |
840b32b7 | 1315 | struct intel_crtc_state *pipe_config) |
c6bb3538 DV |
1316 | { |
1317 | struct drm_device *dev = encoder->base.dev; | |
9dd4ffdf CML |
1318 | const struct dp_link_dpll *divisor = NULL; |
1319 | int i, count = 0; | |
c6bb3538 DV |
1320 | |
1321 | if (IS_G4X(dev)) { | |
9dd4ffdf CML |
1322 | divisor = gen4_dpll; |
1323 | count = ARRAY_SIZE(gen4_dpll); | |
c6bb3538 | 1324 | } else if (HAS_PCH_SPLIT(dev)) { |
9dd4ffdf CML |
1325 | divisor = pch_dpll; |
1326 | count = ARRAY_SIZE(pch_dpll); | |
ef9348c8 CML |
1327 | } else if (IS_CHERRYVIEW(dev)) { |
1328 | divisor = chv_dpll; | |
1329 | count = ARRAY_SIZE(chv_dpll); | |
c6bb3538 | 1330 | } else if (IS_VALLEYVIEW(dev)) { |
65ce4bf5 CML |
1331 | divisor = vlv_dpll; |
1332 | count = ARRAY_SIZE(vlv_dpll); | |
c6bb3538 | 1333 | } |
9dd4ffdf CML |
1334 | |
1335 | if (divisor && count) { | |
1336 | for (i = 0; i < count; i++) { | |
840b32b7 | 1337 | if (pipe_config->port_clock == divisor[i].clock) { |
9dd4ffdf CML |
1338 | pipe_config->dpll = divisor[i].dpll; |
1339 | pipe_config->clock_set = true; | |
1340 | break; | |
1341 | } | |
1342 | } | |
c6bb3538 DV |
1343 | } |
1344 | } | |
1345 | ||
2ecae76a VS |
1346 | static int intersect_rates(const int *source_rates, int source_len, |
1347 | const int *sink_rates, int sink_len, | |
94ca719e | 1348 | int *common_rates) |
a8f3ef61 SJ |
1349 | { |
1350 | int i = 0, j = 0, k = 0; | |
1351 | ||
a8f3ef61 SJ |
1352 | while (i < source_len && j < sink_len) { |
1353 | if (source_rates[i] == sink_rates[j]) { | |
e6bda3e4 VS |
1354 | if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) |
1355 | return k; | |
94ca719e | 1356 | common_rates[k] = source_rates[i]; |
a8f3ef61 SJ |
1357 | ++k; |
1358 | ++i; | |
1359 | ++j; | |
1360 | } else if (source_rates[i] < sink_rates[j]) { | |
1361 | ++i; | |
1362 | } else { | |
1363 | ++j; | |
1364 | } | |
1365 | } | |
1366 | return k; | |
1367 | } | |
1368 | ||
94ca719e VS |
1369 | static int intel_dp_common_rates(struct intel_dp *intel_dp, |
1370 | int *common_rates) | |
2ecae76a | 1371 | { |
2ecae76a VS |
1372 | const int *source_rates, *sink_rates; |
1373 | int source_len, sink_len; | |
1374 | ||
1375 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); | |
e588fa18 | 1376 | source_len = intel_dp_source_rates(intel_dp, &source_rates); |
2ecae76a VS |
1377 | |
1378 | return intersect_rates(source_rates, source_len, | |
1379 | sink_rates, sink_len, | |
94ca719e | 1380 | common_rates); |
2ecae76a VS |
1381 | } |
1382 | ||
0336400e VS |
1383 | static void snprintf_int_array(char *str, size_t len, |
1384 | const int *array, int nelem) | |
1385 | { | |
1386 | int i; | |
1387 | ||
1388 | str[0] = '\0'; | |
1389 | ||
1390 | for (i = 0; i < nelem; i++) { | |
b2f505be | 1391 | int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); |
0336400e VS |
1392 | if (r >= len) |
1393 | return; | |
1394 | str += r; | |
1395 | len -= r; | |
1396 | } | |
1397 | } | |
1398 | ||
1399 | static void intel_dp_print_rates(struct intel_dp *intel_dp) | |
1400 | { | |
0336400e | 1401 | const int *source_rates, *sink_rates; |
94ca719e VS |
1402 | int source_len, sink_len, common_len; |
1403 | int common_rates[DP_MAX_SUPPORTED_RATES]; | |
0336400e VS |
1404 | char str[128]; /* FIXME: too big for stack? */ |
1405 | ||
1406 | if ((drm_debug & DRM_UT_KMS) == 0) | |
1407 | return; | |
1408 | ||
e588fa18 | 1409 | source_len = intel_dp_source_rates(intel_dp, &source_rates); |
0336400e VS |
1410 | snprintf_int_array(str, sizeof(str), source_rates, source_len); |
1411 | DRM_DEBUG_KMS("source rates: %s\n", str); | |
1412 | ||
1413 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); | |
1414 | snprintf_int_array(str, sizeof(str), sink_rates, sink_len); | |
1415 | DRM_DEBUG_KMS("sink rates: %s\n", str); | |
1416 | ||
94ca719e VS |
1417 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
1418 | snprintf_int_array(str, sizeof(str), common_rates, common_len); | |
1419 | DRM_DEBUG_KMS("common rates: %s\n", str); | |
0336400e VS |
1420 | } |
1421 | ||
f4896f15 | 1422 | static int rate_to_index(int find, const int *rates) |
a8f3ef61 SJ |
1423 | { |
1424 | int i = 0; | |
1425 | ||
1426 | for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) | |
1427 | if (find == rates[i]) | |
1428 | break; | |
1429 | ||
1430 | return i; | |
1431 | } | |
1432 | ||
50fec21a VS |
1433 | int |
1434 | intel_dp_max_link_rate(struct intel_dp *intel_dp) | |
1435 | { | |
1436 | int rates[DP_MAX_SUPPORTED_RATES] = {}; | |
1437 | int len; | |
1438 | ||
94ca719e | 1439 | len = intel_dp_common_rates(intel_dp, rates); |
50fec21a VS |
1440 | if (WARN_ON(len <= 0)) |
1441 | return 162000; | |
1442 | ||
1354f734 | 1443 | return rates[len - 1]; |
50fec21a VS |
1444 | } |
1445 | ||
ed4e9c1d VS |
1446 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) |
1447 | { | |
94ca719e | 1448 | return rate_to_index(rate, intel_dp->sink_rates); |
ed4e9c1d VS |
1449 | } |
1450 | ||
94223d04 ACO |
1451 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, |
1452 | uint8_t *link_bw, uint8_t *rate_select) | |
04a60f9f VS |
1453 | { |
1454 | if (intel_dp->num_sink_rates) { | |
1455 | *link_bw = 0; | |
1456 | *rate_select = | |
1457 | intel_dp_rate_select(intel_dp, port_clock); | |
1458 | } else { | |
1459 | *link_bw = drm_dp_link_rate_to_bw_code(port_clock); | |
1460 | *rate_select = 0; | |
1461 | } | |
1462 | } | |
1463 | ||
00c09d70 | 1464 | bool |
5bfe2ac0 | 1465 | intel_dp_compute_config(struct intel_encoder *encoder, |
5cec258b | 1466 | struct intel_crtc_state *pipe_config) |
a4fc5ed6 | 1467 | { |
5bfe2ac0 | 1468 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1469 | struct drm_i915_private *dev_priv = to_i915(dev); |
2d112de7 | 1470 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
5bfe2ac0 | 1471 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1472 | enum port port = dp_to_dig_port(intel_dp)->port; |
84556d58 | 1473 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
dd06f90e | 1474 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
a4fc5ed6 | 1475 | int lane_count, clock; |
56071a20 | 1476 | int min_lane_count = 1; |
eeb6324d | 1477 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
06ea66b6 | 1478 | /* Conveniently, the link BW constants become indices with a shift...*/ |
56071a20 | 1479 | int min_clock = 0; |
a8f3ef61 | 1480 | int max_clock; |
083f9560 | 1481 | int bpp, mode_rate; |
ff9a6750 | 1482 | int link_avail, link_clock; |
94ca719e VS |
1483 | int common_rates[DP_MAX_SUPPORTED_RATES] = {}; |
1484 | int common_len; | |
04a60f9f | 1485 | uint8_t link_bw, rate_select; |
a8f3ef61 | 1486 | |
94ca719e | 1487 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
a8f3ef61 SJ |
1488 | |
1489 | /* No common link rates between source and sink */ | |
94ca719e | 1490 | WARN_ON(common_len <= 0); |
a8f3ef61 | 1491 | |
94ca719e | 1492 | max_clock = common_len - 1; |
a4fc5ed6 | 1493 | |
bc7d38a4 | 1494 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) |
5bfe2ac0 DV |
1495 | pipe_config->has_pch_encoder = true; |
1496 | ||
f769cd24 | 1497 | pipe_config->has_drrs = false; |
9fcb1704 | 1498 | pipe_config->has_audio = intel_dp->has_audio && port != PORT_A; |
a4fc5ed6 | 1499 | |
dd06f90e JN |
1500 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
1501 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, | |
1502 | adjusted_mode); | |
a1b2278e CK |
1503 | |
1504 | if (INTEL_INFO(dev)->gen >= 9) { | |
1505 | int ret; | |
e435d6e5 | 1506 | ret = skl_update_scaler_crtc(pipe_config); |
a1b2278e CK |
1507 | if (ret) |
1508 | return ret; | |
1509 | } | |
1510 | ||
b5667627 | 1511 | if (HAS_GMCH_DISPLAY(dev)) |
2dd24552 JB |
1512 | intel_gmch_panel_fitting(intel_crtc, pipe_config, |
1513 | intel_connector->panel.fitting_mode); | |
1514 | else | |
b074cec8 JB |
1515 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
1516 | intel_connector->panel.fitting_mode); | |
0d3a1bee ZY |
1517 | } |
1518 | ||
cb1793ce | 1519 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
0af78a2b DV |
1520 | return false; |
1521 | ||
083f9560 | 1522 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
a8f3ef61 | 1523 | "max bw %d pixel clock %iKHz\n", |
94ca719e | 1524 | max_lane_count, common_rates[max_clock], |
241bfc38 | 1525 | adjusted_mode->crtc_clock); |
083f9560 | 1526 | |
36008365 DV |
1527 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
1528 | * bpc in between. */ | |
3e7ca985 | 1529 | bpp = pipe_config->pipe_bpp; |
56071a20 | 1530 | if (is_edp(intel_dp)) { |
22ce5628 TS |
1531 | |
1532 | /* Get bpp from vbt only for panels that dont have bpp in edid */ | |
1533 | if (intel_connector->base.display_info.bpc == 0 && | |
6aa23e65 | 1534 | (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) { |
56071a20 | 1535 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
6aa23e65 JN |
1536 | dev_priv->vbt.edp.bpp); |
1537 | bpp = dev_priv->vbt.edp.bpp; | |
56071a20 JN |
1538 | } |
1539 | ||
344c5bbc JN |
1540 | /* |
1541 | * Use the maximum clock and number of lanes the eDP panel | |
1542 | * advertizes being capable of. The panels are generally | |
1543 | * designed to support only a single clock and lane | |
1544 | * configuration, and typically these values correspond to the | |
1545 | * native resolution of the panel. | |
1546 | */ | |
1547 | min_lane_count = max_lane_count; | |
1548 | min_clock = max_clock; | |
7984211e | 1549 | } |
657445fe | 1550 | |
36008365 | 1551 | for (; bpp >= 6*3; bpp -= 2*3) { |
241bfc38 DL |
1552 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
1553 | bpp); | |
36008365 | 1554 | |
c6930992 | 1555 | for (clock = min_clock; clock <= max_clock; clock++) { |
a8f3ef61 SJ |
1556 | for (lane_count = min_lane_count; |
1557 | lane_count <= max_lane_count; | |
1558 | lane_count <<= 1) { | |
1559 | ||
94ca719e | 1560 | link_clock = common_rates[clock]; |
36008365 DV |
1561 | link_avail = intel_dp_max_data_rate(link_clock, |
1562 | lane_count); | |
1563 | ||
1564 | if (mode_rate <= link_avail) { | |
1565 | goto found; | |
1566 | } | |
1567 | } | |
1568 | } | |
1569 | } | |
c4867936 | 1570 | |
36008365 | 1571 | return false; |
3685a8f3 | 1572 | |
36008365 | 1573 | found: |
55bc60db VS |
1574 | if (intel_dp->color_range_auto) { |
1575 | /* | |
1576 | * See: | |
1577 | * CEA-861-E - 5.1 Default Encoding Parameters | |
1578 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry | |
1579 | */ | |
0f2a2a75 VS |
1580 | pipe_config->limited_color_range = |
1581 | bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1; | |
1582 | } else { | |
1583 | pipe_config->limited_color_range = | |
1584 | intel_dp->limited_color_range; | |
55bc60db VS |
1585 | } |
1586 | ||
90a6b7b0 | 1587 | pipe_config->lane_count = lane_count; |
a8f3ef61 | 1588 | |
657445fe | 1589 | pipe_config->pipe_bpp = bpp; |
94ca719e | 1590 | pipe_config->port_clock = common_rates[clock]; |
a4fc5ed6 | 1591 | |
04a60f9f VS |
1592 | intel_dp_compute_rate(intel_dp, pipe_config->port_clock, |
1593 | &link_bw, &rate_select); | |
1594 | ||
1595 | DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n", | |
1596 | link_bw, rate_select, pipe_config->lane_count, | |
ff9a6750 | 1597 | pipe_config->port_clock, bpp); |
36008365 DV |
1598 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
1599 | mode_rate, link_avail); | |
a4fc5ed6 | 1600 | |
03afc4a2 | 1601 | intel_link_compute_m_n(bpp, lane_count, |
241bfc38 DL |
1602 | adjusted_mode->crtc_clock, |
1603 | pipe_config->port_clock, | |
03afc4a2 | 1604 | &pipe_config->dp_m_n); |
9d1a455b | 1605 | |
439d7ac0 | 1606 | if (intel_connector->panel.downclock_mode != NULL && |
96178eeb | 1607 | dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { |
f769cd24 | 1608 | pipe_config->has_drrs = true; |
439d7ac0 PB |
1609 | intel_link_compute_m_n(bpp, lane_count, |
1610 | intel_connector->panel.downclock_mode->clock, | |
1611 | pipe_config->port_clock, | |
1612 | &pipe_config->dp_m2_n2); | |
1613 | } | |
1614 | ||
14d41b3b VS |
1615 | /* |
1616 | * DPLL0 VCO may need to be adjusted to get the correct | |
1617 | * clock for eDP. This will affect cdclk as well. | |
1618 | */ | |
1619 | if (is_edp(intel_dp) && | |
1620 | (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) { | |
1621 | int vco; | |
1622 | ||
1623 | switch (pipe_config->port_clock / 2) { | |
1624 | case 108000: | |
1625 | case 216000: | |
63911d72 | 1626 | vco = 8640000; |
14d41b3b VS |
1627 | break; |
1628 | default: | |
63911d72 | 1629 | vco = 8100000; |
14d41b3b VS |
1630 | break; |
1631 | } | |
1632 | ||
1633 | to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco; | |
1634 | } | |
1635 | ||
a3c988ea | 1636 | if (!HAS_DDI(dev)) |
840b32b7 | 1637 | intel_dp_set_clock(encoder, pipe_config); |
c6bb3538 | 1638 | |
03afc4a2 | 1639 | return true; |
a4fc5ed6 KP |
1640 | } |
1641 | ||
901c2daf VS |
1642 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
1643 | const struct intel_crtc_state *pipe_config) | |
1644 | { | |
1645 | intel_dp->link_rate = pipe_config->port_clock; | |
1646 | intel_dp->lane_count = pipe_config->lane_count; | |
64ee2fd2 | 1647 | intel_dp->link_mst = intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST); |
901c2daf VS |
1648 | } |
1649 | ||
8ac33ed3 | 1650 | static void intel_dp_prepare(struct intel_encoder *encoder) |
a4fc5ed6 | 1651 | { |
b934223d | 1652 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1653 | struct drm_i915_private *dev_priv = to_i915(dev); |
b934223d | 1654 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1655 | enum port port = dp_to_dig_port(intel_dp)->port; |
b934223d | 1656 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
7c5f93b0 | 1657 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
a4fc5ed6 | 1658 | |
901c2daf VS |
1659 | intel_dp_set_link_params(intel_dp, crtc->config); |
1660 | ||
417e822d | 1661 | /* |
1a2eb460 | 1662 | * There are four kinds of DP registers: |
417e822d KP |
1663 | * |
1664 | * IBX PCH | |
1a2eb460 KP |
1665 | * SNB CPU |
1666 | * IVB CPU | |
417e822d KP |
1667 | * CPT PCH |
1668 | * | |
1669 | * IBX PCH and CPU are the same for almost everything, | |
1670 | * except that the CPU DP PLL is configured in this | |
1671 | * register | |
1672 | * | |
1673 | * CPT PCH is quite different, having many bits moved | |
1674 | * to the TRANS_DP_CTL register instead. That | |
1675 | * configuration happens (oddly) in ironlake_pch_enable | |
1676 | */ | |
9c9e7927 | 1677 | |
417e822d KP |
1678 | /* Preserve the BIOS-computed detected bit. This is |
1679 | * supposed to be read-only. | |
1680 | */ | |
1681 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
a4fc5ed6 | 1682 | |
417e822d | 1683 | /* Handle DP bits in common between all three register formats */ |
417e822d | 1684 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
90a6b7b0 | 1685 | intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count); |
a4fc5ed6 | 1686 | |
417e822d | 1687 | /* Split out the IBX/CPU vs CPT settings */ |
32f9d658 | 1688 | |
39e5fa88 | 1689 | if (IS_GEN7(dev) && port == PORT_A) { |
1a2eb460 KP |
1690 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
1691 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
1692 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
1693 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
1694 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
1695 | ||
6aba5b6c | 1696 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1a2eb460 KP |
1697 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1698 | ||
7c62a164 | 1699 | intel_dp->DP |= crtc->pipe << 29; |
39e5fa88 | 1700 | } else if (HAS_PCH_CPT(dev) && port != PORT_A) { |
e3ef4479 VS |
1701 | u32 trans_dp; |
1702 | ||
39e5fa88 | 1703 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
e3ef4479 VS |
1704 | |
1705 | trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); | |
1706 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) | |
1707 | trans_dp |= TRANS_DP_ENH_FRAMING; | |
1708 | else | |
1709 | trans_dp &= ~TRANS_DP_ENH_FRAMING; | |
1710 | I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); | |
39e5fa88 | 1711 | } else { |
0f2a2a75 | 1712 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && |
666a4537 | 1713 | !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range) |
0f2a2a75 | 1714 | intel_dp->DP |= DP_COLOR_RANGE_16_235; |
417e822d KP |
1715 | |
1716 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
1717 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
1718 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
1719 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
1720 | intel_dp->DP |= DP_LINK_TRAIN_OFF; | |
1721 | ||
6aba5b6c | 1722 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
417e822d KP |
1723 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1724 | ||
39e5fa88 | 1725 | if (IS_CHERRYVIEW(dev)) |
44f37d1f | 1726 | intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); |
39e5fa88 VS |
1727 | else if (crtc->pipe == PIPE_B) |
1728 | intel_dp->DP |= DP_PIPEB_SELECT; | |
32f9d658 | 1729 | } |
a4fc5ed6 KP |
1730 | } |
1731 | ||
ffd6749d PZ |
1732 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
1733 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) | |
99ea7127 | 1734 | |
1a5ef5b7 PZ |
1735 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
1736 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) | |
99ea7127 | 1737 | |
ffd6749d PZ |
1738 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
1739 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) | |
99ea7127 | 1740 | |
de9c1b6b ID |
1741 | static void intel_pps_verify_state(struct drm_i915_private *dev_priv, |
1742 | struct intel_dp *intel_dp); | |
1743 | ||
4be73780 | 1744 | static void wait_panel_status(struct intel_dp *intel_dp, |
99ea7127 KP |
1745 | u32 mask, |
1746 | u32 value) | |
bd943159 | 1747 | { |
30add22d | 1748 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 1749 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 1750 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
453c5420 | 1751 | |
e39b999a VS |
1752 | lockdep_assert_held(&dev_priv->pps_mutex); |
1753 | ||
de9c1b6b ID |
1754 | intel_pps_verify_state(dev_priv, intel_dp); |
1755 | ||
bf13e81b JN |
1756 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1757 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
32ce697c | 1758 | |
99ea7127 | 1759 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
453c5420 JB |
1760 | mask, value, |
1761 | I915_READ(pp_stat_reg), | |
1762 | I915_READ(pp_ctrl_reg)); | |
32ce697c | 1763 | |
9036ff06 CW |
1764 | if (intel_wait_for_register(dev_priv, |
1765 | pp_stat_reg, mask, value, | |
1766 | 5000)) | |
99ea7127 | 1767 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
453c5420 JB |
1768 | I915_READ(pp_stat_reg), |
1769 | I915_READ(pp_ctrl_reg)); | |
54c136d4 CW |
1770 | |
1771 | DRM_DEBUG_KMS("Wait complete\n"); | |
99ea7127 | 1772 | } |
32ce697c | 1773 | |
4be73780 | 1774 | static void wait_panel_on(struct intel_dp *intel_dp) |
99ea7127 KP |
1775 | { |
1776 | DRM_DEBUG_KMS("Wait for panel power on\n"); | |
4be73780 | 1777 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
bd943159 KP |
1778 | } |
1779 | ||
4be73780 | 1780 | static void wait_panel_off(struct intel_dp *intel_dp) |
99ea7127 KP |
1781 | { |
1782 | DRM_DEBUG_KMS("Wait for panel power off time\n"); | |
4be73780 | 1783 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
99ea7127 KP |
1784 | } |
1785 | ||
4be73780 | 1786 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
99ea7127 | 1787 | { |
d28d4731 AK |
1788 | ktime_t panel_power_on_time; |
1789 | s64 panel_power_off_duration; | |
1790 | ||
99ea7127 | 1791 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
dce56b3c | 1792 | |
d28d4731 AK |
1793 | /* take the difference of currrent time and panel power off time |
1794 | * and then make panel wait for t11_t12 if needed. */ | |
1795 | panel_power_on_time = ktime_get_boottime(); | |
1796 | panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time); | |
1797 | ||
dce56b3c PZ |
1798 | /* When we disable the VDD override bit last we have to do the manual |
1799 | * wait. */ | |
d28d4731 AK |
1800 | if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay) |
1801 | wait_remaining_ms_from_jiffies(jiffies, | |
1802 | intel_dp->panel_power_cycle_delay - panel_power_off_duration); | |
dce56b3c | 1803 | |
4be73780 | 1804 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
99ea7127 KP |
1805 | } |
1806 | ||
4be73780 | 1807 | static void wait_backlight_on(struct intel_dp *intel_dp) |
dce56b3c PZ |
1808 | { |
1809 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, | |
1810 | intel_dp->backlight_on_delay); | |
1811 | } | |
1812 | ||
4be73780 | 1813 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
dce56b3c PZ |
1814 | { |
1815 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, | |
1816 | intel_dp->backlight_off_delay); | |
1817 | } | |
99ea7127 | 1818 | |
832dd3c1 KP |
1819 | /* Read the current pp_control value, unlocking the register if it |
1820 | * is locked | |
1821 | */ | |
1822 | ||
453c5420 | 1823 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
832dd3c1 | 1824 | { |
453c5420 | 1825 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 1826 | struct drm_i915_private *dev_priv = to_i915(dev); |
453c5420 | 1827 | u32 control; |
832dd3c1 | 1828 | |
e39b999a VS |
1829 | lockdep_assert_held(&dev_priv->pps_mutex); |
1830 | ||
bf13e81b | 1831 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
8090ba8c ID |
1832 | if (WARN_ON(!HAS_DDI(dev_priv) && |
1833 | (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) { | |
b0a08bec VK |
1834 | control &= ~PANEL_UNLOCK_MASK; |
1835 | control |= PANEL_UNLOCK_REGS; | |
1836 | } | |
832dd3c1 | 1837 | return control; |
bd943159 KP |
1838 | } |
1839 | ||
951468f3 VS |
1840 | /* |
1841 | * Must be paired with edp_panel_vdd_off(). | |
1842 | * Must hold pps_mutex around the whole on/off sequence. | |
1843 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. | |
1844 | */ | |
1e0560e0 | 1845 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp) |
5d613501 | 1846 | { |
30add22d | 1847 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
4e6e1a54 ID |
1848 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1849 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
fac5e23e | 1850 | struct drm_i915_private *dev_priv = to_i915(dev); |
4e6e1a54 | 1851 | enum intel_display_power_domain power_domain; |
5d613501 | 1852 | u32 pp; |
f0f59a00 | 1853 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
adddaaf4 | 1854 | bool need_to_disable = !intel_dp->want_panel_vdd; |
5d613501 | 1855 | |
e39b999a VS |
1856 | lockdep_assert_held(&dev_priv->pps_mutex); |
1857 | ||
97af61f5 | 1858 | if (!is_edp(intel_dp)) |
adddaaf4 | 1859 | return false; |
bd943159 | 1860 | |
2c623c11 | 1861 | cancel_delayed_work(&intel_dp->panel_vdd_work); |
bd943159 | 1862 | intel_dp->want_panel_vdd = true; |
99ea7127 | 1863 | |
4be73780 | 1864 | if (edp_have_panel_vdd(intel_dp)) |
adddaaf4 | 1865 | return need_to_disable; |
b0665d57 | 1866 | |
25f78f58 | 1867 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4e6e1a54 | 1868 | intel_display_power_get(dev_priv, power_domain); |
e9cb81a2 | 1869 | |
3936fcf4 VS |
1870 | DRM_DEBUG_KMS("Turning eDP port %c VDD on\n", |
1871 | port_name(intel_dig_port->port)); | |
bd943159 | 1872 | |
4be73780 DV |
1873 | if (!edp_have_panel_power(intel_dp)) |
1874 | wait_panel_power_cycle(intel_dp); | |
99ea7127 | 1875 | |
453c5420 | 1876 | pp = ironlake_get_pp_control(intel_dp); |
5d613501 | 1877 | pp |= EDP_FORCE_VDD; |
ebf33b18 | 1878 | |
bf13e81b JN |
1879 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1880 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
453c5420 JB |
1881 | |
1882 | I915_WRITE(pp_ctrl_reg, pp); | |
1883 | POSTING_READ(pp_ctrl_reg); | |
1884 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
1885 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
ebf33b18 KP |
1886 | /* |
1887 | * If the panel wasn't on, delay before accessing aux channel | |
1888 | */ | |
4be73780 | 1889 | if (!edp_have_panel_power(intel_dp)) { |
3936fcf4 VS |
1890 | DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n", |
1891 | port_name(intel_dig_port->port)); | |
f01eca2e | 1892 | msleep(intel_dp->panel_power_up_delay); |
f01eca2e | 1893 | } |
adddaaf4 JN |
1894 | |
1895 | return need_to_disable; | |
1896 | } | |
1897 | ||
951468f3 VS |
1898 | /* |
1899 | * Must be paired with intel_edp_panel_vdd_off() or | |
1900 | * intel_edp_panel_off(). | |
1901 | * Nested calls to these functions are not allowed since | |
1902 | * we drop the lock. Caller must use some higher level | |
1903 | * locking to prevent nested calls from other threads. | |
1904 | */ | |
b80d6c78 | 1905 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
adddaaf4 | 1906 | { |
c695b6b6 | 1907 | bool vdd; |
adddaaf4 | 1908 | |
c695b6b6 VS |
1909 | if (!is_edp(intel_dp)) |
1910 | return; | |
1911 | ||
773538e8 | 1912 | pps_lock(intel_dp); |
c695b6b6 | 1913 | vdd = edp_panel_vdd_on(intel_dp); |
773538e8 | 1914 | pps_unlock(intel_dp); |
c695b6b6 | 1915 | |
e2c719b7 | 1916 | I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n", |
3936fcf4 | 1917 | port_name(dp_to_dig_port(intel_dp)->port)); |
5d613501 JB |
1918 | } |
1919 | ||
4be73780 | 1920 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
5d613501 | 1921 | { |
30add22d | 1922 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 1923 | struct drm_i915_private *dev_priv = to_i915(dev); |
be2c9196 VS |
1924 | struct intel_digital_port *intel_dig_port = |
1925 | dp_to_dig_port(intel_dp); | |
1926 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
1927 | enum intel_display_power_domain power_domain; | |
5d613501 | 1928 | u32 pp; |
f0f59a00 | 1929 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
5d613501 | 1930 | |
e39b999a | 1931 | lockdep_assert_held(&dev_priv->pps_mutex); |
a0e99e68 | 1932 | |
15e899a0 | 1933 | WARN_ON(intel_dp->want_panel_vdd); |
4e6e1a54 | 1934 | |
15e899a0 | 1935 | if (!edp_have_panel_vdd(intel_dp)) |
be2c9196 | 1936 | return; |
b0665d57 | 1937 | |
3936fcf4 VS |
1938 | DRM_DEBUG_KMS("Turning eDP port %c VDD off\n", |
1939 | port_name(intel_dig_port->port)); | |
bd943159 | 1940 | |
be2c9196 VS |
1941 | pp = ironlake_get_pp_control(intel_dp); |
1942 | pp &= ~EDP_FORCE_VDD; | |
453c5420 | 1943 | |
be2c9196 VS |
1944 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1945 | pp_stat_reg = _pp_stat_reg(intel_dp); | |
99ea7127 | 1946 | |
be2c9196 VS |
1947 | I915_WRITE(pp_ctrl_reg, pp); |
1948 | POSTING_READ(pp_ctrl_reg); | |
90791a5c | 1949 | |
be2c9196 VS |
1950 | /* Make sure sequencer is idle before allowing subsequent activity */ |
1951 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
1952 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
e9cb81a2 | 1953 | |
5a162e22 | 1954 | if ((pp & PANEL_POWER_ON) == 0) |
d28d4731 | 1955 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
e9cb81a2 | 1956 | |
25f78f58 | 1957 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
be2c9196 | 1958 | intel_display_power_put(dev_priv, power_domain); |
bd943159 | 1959 | } |
5d613501 | 1960 | |
4be73780 | 1961 | static void edp_panel_vdd_work(struct work_struct *__work) |
bd943159 KP |
1962 | { |
1963 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), | |
1964 | struct intel_dp, panel_vdd_work); | |
bd943159 | 1965 | |
773538e8 | 1966 | pps_lock(intel_dp); |
15e899a0 VS |
1967 | if (!intel_dp->want_panel_vdd) |
1968 | edp_panel_vdd_off_sync(intel_dp); | |
773538e8 | 1969 | pps_unlock(intel_dp); |
bd943159 KP |
1970 | } |
1971 | ||
aba86890 ID |
1972 | static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
1973 | { | |
1974 | unsigned long delay; | |
1975 | ||
1976 | /* | |
1977 | * Queue the timer to fire a long time from now (relative to the power | |
1978 | * down delay) to keep the panel power up across a sequence of | |
1979 | * operations. | |
1980 | */ | |
1981 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); | |
1982 | schedule_delayed_work(&intel_dp->panel_vdd_work, delay); | |
1983 | } | |
1984 | ||
951468f3 VS |
1985 | /* |
1986 | * Must be paired with edp_panel_vdd_on(). | |
1987 | * Must hold pps_mutex around the whole on/off sequence. | |
1988 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. | |
1989 | */ | |
4be73780 | 1990 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
bd943159 | 1991 | { |
fac5e23e | 1992 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
e39b999a VS |
1993 | |
1994 | lockdep_assert_held(&dev_priv->pps_mutex); | |
1995 | ||
97af61f5 KP |
1996 | if (!is_edp(intel_dp)) |
1997 | return; | |
5d613501 | 1998 | |
e2c719b7 | 1999 | I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on", |
3936fcf4 | 2000 | port_name(dp_to_dig_port(intel_dp)->port)); |
f2e8b18a | 2001 | |
bd943159 KP |
2002 | intel_dp->want_panel_vdd = false; |
2003 | ||
aba86890 | 2004 | if (sync) |
4be73780 | 2005 | edp_panel_vdd_off_sync(intel_dp); |
aba86890 ID |
2006 | else |
2007 | edp_panel_vdd_schedule_off(intel_dp); | |
5d613501 JB |
2008 | } |
2009 | ||
9f0fb5be | 2010 | static void edp_panel_on(struct intel_dp *intel_dp) |
9934c132 | 2011 | { |
30add22d | 2012 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2013 | struct drm_i915_private *dev_priv = to_i915(dev); |
99ea7127 | 2014 | u32 pp; |
f0f59a00 | 2015 | i915_reg_t pp_ctrl_reg; |
9934c132 | 2016 | |
9f0fb5be VS |
2017 | lockdep_assert_held(&dev_priv->pps_mutex); |
2018 | ||
97af61f5 | 2019 | if (!is_edp(intel_dp)) |
bd943159 | 2020 | return; |
99ea7127 | 2021 | |
3936fcf4 VS |
2022 | DRM_DEBUG_KMS("Turn eDP port %c panel power on\n", |
2023 | port_name(dp_to_dig_port(intel_dp)->port)); | |
e39b999a | 2024 | |
e7a89ace VS |
2025 | if (WARN(edp_have_panel_power(intel_dp), |
2026 | "eDP port %c panel power already on\n", | |
2027 | port_name(dp_to_dig_port(intel_dp)->port))) | |
9f0fb5be | 2028 | return; |
9934c132 | 2029 | |
4be73780 | 2030 | wait_panel_power_cycle(intel_dp); |
37c6c9b0 | 2031 | |
bf13e81b | 2032 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 2033 | pp = ironlake_get_pp_control(intel_dp); |
05ce1a49 KP |
2034 | if (IS_GEN5(dev)) { |
2035 | /* ILK workaround: disable reset around power sequence */ | |
2036 | pp &= ~PANEL_POWER_RESET; | |
bf13e81b JN |
2037 | I915_WRITE(pp_ctrl_reg, pp); |
2038 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 2039 | } |
37c6c9b0 | 2040 | |
5a162e22 | 2041 | pp |= PANEL_POWER_ON; |
99ea7127 KP |
2042 | if (!IS_GEN5(dev)) |
2043 | pp |= PANEL_POWER_RESET; | |
2044 | ||
453c5420 JB |
2045 | I915_WRITE(pp_ctrl_reg, pp); |
2046 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 2047 | |
4be73780 | 2048 | wait_panel_on(intel_dp); |
dce56b3c | 2049 | intel_dp->last_power_on = jiffies; |
9934c132 | 2050 | |
05ce1a49 KP |
2051 | if (IS_GEN5(dev)) { |
2052 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ | |
bf13e81b JN |
2053 | I915_WRITE(pp_ctrl_reg, pp); |
2054 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 2055 | } |
9f0fb5be | 2056 | } |
e39b999a | 2057 | |
9f0fb5be VS |
2058 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
2059 | { | |
2060 | if (!is_edp(intel_dp)) | |
2061 | return; | |
2062 | ||
2063 | pps_lock(intel_dp); | |
2064 | edp_panel_on(intel_dp); | |
773538e8 | 2065 | pps_unlock(intel_dp); |
9934c132 JB |
2066 | } |
2067 | ||
9f0fb5be VS |
2068 | |
2069 | static void edp_panel_off(struct intel_dp *intel_dp) | |
9934c132 | 2070 | { |
4e6e1a54 ID |
2071 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2072 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
30add22d | 2073 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2074 | struct drm_i915_private *dev_priv = to_i915(dev); |
4e6e1a54 | 2075 | enum intel_display_power_domain power_domain; |
99ea7127 | 2076 | u32 pp; |
f0f59a00 | 2077 | i915_reg_t pp_ctrl_reg; |
9934c132 | 2078 | |
9f0fb5be VS |
2079 | lockdep_assert_held(&dev_priv->pps_mutex); |
2080 | ||
97af61f5 KP |
2081 | if (!is_edp(intel_dp)) |
2082 | return; | |
37c6c9b0 | 2083 | |
3936fcf4 VS |
2084 | DRM_DEBUG_KMS("Turn eDP port %c panel power off\n", |
2085 | port_name(dp_to_dig_port(intel_dp)->port)); | |
37c6c9b0 | 2086 | |
3936fcf4 VS |
2087 | WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n", |
2088 | port_name(dp_to_dig_port(intel_dp)->port)); | |
24f3e092 | 2089 | |
453c5420 | 2090 | pp = ironlake_get_pp_control(intel_dp); |
35a38556 DV |
2091 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
2092 | * panels get very unhappy and cease to work. */ | |
5a162e22 | 2093 | pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
b3064154 | 2094 | EDP_BLC_ENABLE); |
453c5420 | 2095 | |
bf13e81b | 2096 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 2097 | |
849e39f5 PZ |
2098 | intel_dp->want_panel_vdd = false; |
2099 | ||
453c5420 JB |
2100 | I915_WRITE(pp_ctrl_reg, pp); |
2101 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 2102 | |
d28d4731 | 2103 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
4be73780 | 2104 | wait_panel_off(intel_dp); |
849e39f5 PZ |
2105 | |
2106 | /* We got a reference when we enabled the VDD. */ | |
25f78f58 | 2107 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4e6e1a54 | 2108 | intel_display_power_put(dev_priv, power_domain); |
9f0fb5be | 2109 | } |
e39b999a | 2110 | |
9f0fb5be VS |
2111 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
2112 | { | |
2113 | if (!is_edp(intel_dp)) | |
2114 | return; | |
e39b999a | 2115 | |
9f0fb5be VS |
2116 | pps_lock(intel_dp); |
2117 | edp_panel_off(intel_dp); | |
773538e8 | 2118 | pps_unlock(intel_dp); |
9934c132 JB |
2119 | } |
2120 | ||
1250d107 JN |
2121 | /* Enable backlight in the panel power control. */ |
2122 | static void _intel_edp_backlight_on(struct intel_dp *intel_dp) | |
32f9d658 | 2123 | { |
da63a9f2 PZ |
2124 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2125 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 2126 | struct drm_i915_private *dev_priv = to_i915(dev); |
32f9d658 | 2127 | u32 pp; |
f0f59a00 | 2128 | i915_reg_t pp_ctrl_reg; |
32f9d658 | 2129 | |
01cb9ea6 JB |
2130 | /* |
2131 | * If we enable the backlight right away following a panel power | |
2132 | * on, we may see slight flicker as the panel syncs with the eDP | |
2133 | * link. So delay a bit to make sure the image is solid before | |
2134 | * allowing it to appear. | |
2135 | */ | |
4be73780 | 2136 | wait_backlight_on(intel_dp); |
e39b999a | 2137 | |
773538e8 | 2138 | pps_lock(intel_dp); |
e39b999a | 2139 | |
453c5420 | 2140 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 2141 | pp |= EDP_BLC_ENABLE; |
453c5420 | 2142 | |
bf13e81b | 2143 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
2144 | |
2145 | I915_WRITE(pp_ctrl_reg, pp); | |
2146 | POSTING_READ(pp_ctrl_reg); | |
e39b999a | 2147 | |
773538e8 | 2148 | pps_unlock(intel_dp); |
32f9d658 ZW |
2149 | } |
2150 | ||
1250d107 JN |
2151 | /* Enable backlight PWM and backlight PP control. */ |
2152 | void intel_edp_backlight_on(struct intel_dp *intel_dp) | |
2153 | { | |
2154 | if (!is_edp(intel_dp)) | |
2155 | return; | |
2156 | ||
2157 | DRM_DEBUG_KMS("\n"); | |
2158 | ||
2159 | intel_panel_enable_backlight(intel_dp->attached_connector); | |
2160 | _intel_edp_backlight_on(intel_dp); | |
2161 | } | |
2162 | ||
2163 | /* Disable backlight in the panel power control. */ | |
2164 | static void _intel_edp_backlight_off(struct intel_dp *intel_dp) | |
32f9d658 | 2165 | { |
30add22d | 2166 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2167 | struct drm_i915_private *dev_priv = to_i915(dev); |
32f9d658 | 2168 | u32 pp; |
f0f59a00 | 2169 | i915_reg_t pp_ctrl_reg; |
32f9d658 | 2170 | |
f01eca2e KP |
2171 | if (!is_edp(intel_dp)) |
2172 | return; | |
2173 | ||
773538e8 | 2174 | pps_lock(intel_dp); |
e39b999a | 2175 | |
453c5420 | 2176 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 2177 | pp &= ~EDP_BLC_ENABLE; |
453c5420 | 2178 | |
bf13e81b | 2179 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
2180 | |
2181 | I915_WRITE(pp_ctrl_reg, pp); | |
2182 | POSTING_READ(pp_ctrl_reg); | |
f7d2323c | 2183 | |
773538e8 | 2184 | pps_unlock(intel_dp); |
e39b999a VS |
2185 | |
2186 | intel_dp->last_backlight_off = jiffies; | |
f7d2323c | 2187 | edp_wait_backlight_off(intel_dp); |
1250d107 | 2188 | } |
f7d2323c | 2189 | |
1250d107 JN |
2190 | /* Disable backlight PP control and backlight PWM. */ |
2191 | void intel_edp_backlight_off(struct intel_dp *intel_dp) | |
2192 | { | |
2193 | if (!is_edp(intel_dp)) | |
2194 | return; | |
2195 | ||
2196 | DRM_DEBUG_KMS("\n"); | |
f7d2323c | 2197 | |
1250d107 | 2198 | _intel_edp_backlight_off(intel_dp); |
f7d2323c | 2199 | intel_panel_disable_backlight(intel_dp->attached_connector); |
32f9d658 | 2200 | } |
a4fc5ed6 | 2201 | |
73580fb7 JN |
2202 | /* |
2203 | * Hook for controlling the panel power control backlight through the bl_power | |
2204 | * sysfs attribute. Take care to handle multiple calls. | |
2205 | */ | |
2206 | static void intel_edp_backlight_power(struct intel_connector *connector, | |
2207 | bool enable) | |
2208 | { | |
2209 | struct intel_dp *intel_dp = intel_attached_dp(&connector->base); | |
e39b999a VS |
2210 | bool is_enabled; |
2211 | ||
773538e8 | 2212 | pps_lock(intel_dp); |
e39b999a | 2213 | is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE; |
773538e8 | 2214 | pps_unlock(intel_dp); |
73580fb7 JN |
2215 | |
2216 | if (is_enabled == enable) | |
2217 | return; | |
2218 | ||
23ba9373 JN |
2219 | DRM_DEBUG_KMS("panel power control backlight %s\n", |
2220 | enable ? "enable" : "disable"); | |
73580fb7 JN |
2221 | |
2222 | if (enable) | |
2223 | _intel_edp_backlight_on(intel_dp); | |
2224 | else | |
2225 | _intel_edp_backlight_off(intel_dp); | |
2226 | } | |
2227 | ||
64e1077a VS |
2228 | static void assert_dp_port(struct intel_dp *intel_dp, bool state) |
2229 | { | |
2230 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
2231 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
2232 | bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN; | |
2233 | ||
2234 | I915_STATE_WARN(cur_state != state, | |
2235 | "DP port %c state assertion failure (expected %s, current %s)\n", | |
2236 | port_name(dig_port->port), | |
87ad3212 | 2237 | onoff(state), onoff(cur_state)); |
64e1077a VS |
2238 | } |
2239 | #define assert_dp_port_disabled(d) assert_dp_port((d), false) | |
2240 | ||
2241 | static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) | |
2242 | { | |
2243 | bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE; | |
2244 | ||
2245 | I915_STATE_WARN(cur_state != state, | |
2246 | "eDP PLL state assertion failure (expected %s, current %s)\n", | |
87ad3212 | 2247 | onoff(state), onoff(cur_state)); |
64e1077a VS |
2248 | } |
2249 | #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) | |
2250 | #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) | |
2251 | ||
2bd2ad64 | 2252 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp) |
d240f20f | 2253 | { |
da63a9f2 | 2254 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
64e1077a VS |
2255 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
2256 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
d240f20f | 2257 | |
64e1077a VS |
2258 | assert_pipe_disabled(dev_priv, crtc->pipe); |
2259 | assert_dp_port_disabled(intel_dp); | |
2260 | assert_edp_pll_disabled(dev_priv); | |
2bd2ad64 | 2261 | |
abfce949 VS |
2262 | DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n", |
2263 | crtc->config->port_clock); | |
2264 | ||
2265 | intel_dp->DP &= ~DP_PLL_FREQ_MASK; | |
2266 | ||
2267 | if (crtc->config->port_clock == 162000) | |
2268 | intel_dp->DP |= DP_PLL_FREQ_162MHZ; | |
2269 | else | |
2270 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; | |
2271 | ||
2272 | I915_WRITE(DP_A, intel_dp->DP); | |
2273 | POSTING_READ(DP_A); | |
2274 | udelay(500); | |
2275 | ||
6b23f3e8 VS |
2276 | /* |
2277 | * [DevILK] Work around required when enabling DP PLL | |
2278 | * while a pipe is enabled going to FDI: | |
2279 | * 1. Wait for the start of vertical blank on the enabled pipe going to FDI | |
2280 | * 2. Program DP PLL enable | |
2281 | */ | |
2282 | if (IS_GEN5(dev_priv)) | |
91c8a326 | 2283 | intel_wait_for_vblank_if_active(&dev_priv->drm, !crtc->pipe); |
6b23f3e8 | 2284 | |
0767935e | 2285 | intel_dp->DP |= DP_PLL_ENABLE; |
6fec7662 | 2286 | |
0767935e | 2287 | I915_WRITE(DP_A, intel_dp->DP); |
298b0b39 JB |
2288 | POSTING_READ(DP_A); |
2289 | udelay(200); | |
d240f20f JB |
2290 | } |
2291 | ||
2bd2ad64 | 2292 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
d240f20f | 2293 | { |
da63a9f2 | 2294 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
64e1077a VS |
2295 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
2296 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
d240f20f | 2297 | |
64e1077a VS |
2298 | assert_pipe_disabled(dev_priv, crtc->pipe); |
2299 | assert_dp_port_disabled(intel_dp); | |
2300 | assert_edp_pll_enabled(dev_priv); | |
2bd2ad64 | 2301 | |
abfce949 VS |
2302 | DRM_DEBUG_KMS("disabling eDP PLL\n"); |
2303 | ||
6fec7662 | 2304 | intel_dp->DP &= ~DP_PLL_ENABLE; |
0767935e | 2305 | |
6fec7662 | 2306 | I915_WRITE(DP_A, intel_dp->DP); |
1af5fa1b | 2307 | POSTING_READ(DP_A); |
d240f20f JB |
2308 | udelay(200); |
2309 | } | |
2310 | ||
c7ad3810 | 2311 | /* If the sink supports it, try to set the power state appropriately */ |
c19b0669 | 2312 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
c7ad3810 JB |
2313 | { |
2314 | int ret, i; | |
2315 | ||
2316 | /* Should have a valid DPCD by this point */ | |
2317 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
2318 | return; | |
2319 | ||
2320 | if (mode != DRM_MODE_DPMS_ON) { | |
9d1a1031 JN |
2321 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2322 | DP_SET_POWER_D3); | |
c7ad3810 JB |
2323 | } else { |
2324 | /* | |
2325 | * When turning on, we need to retry for 1ms to give the sink | |
2326 | * time to wake up. | |
2327 | */ | |
2328 | for (i = 0; i < 3; i++) { | |
9d1a1031 JN |
2329 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2330 | DP_SET_POWER_D0); | |
c7ad3810 JB |
2331 | if (ret == 1) |
2332 | break; | |
2333 | msleep(1); | |
2334 | } | |
2335 | } | |
f9cac721 JN |
2336 | |
2337 | if (ret != 1) | |
2338 | DRM_DEBUG_KMS("failed to %s sink power state\n", | |
2339 | mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); | |
c7ad3810 JB |
2340 | } |
2341 | ||
19d8fe15 DV |
2342 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
2343 | enum pipe *pipe) | |
d240f20f | 2344 | { |
19d8fe15 | 2345 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 2346 | enum port port = dp_to_dig_port(intel_dp)->port; |
19d8fe15 | 2347 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 2348 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d129bea ID |
2349 | enum intel_display_power_domain power_domain; |
2350 | u32 tmp; | |
6fa9a5ec | 2351 | bool ret; |
6d129bea ID |
2352 | |
2353 | power_domain = intel_display_port_power_domain(encoder); | |
6fa9a5ec | 2354 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
6d129bea ID |
2355 | return false; |
2356 | ||
6fa9a5ec ID |
2357 | ret = false; |
2358 | ||
6d129bea | 2359 | tmp = I915_READ(intel_dp->output_reg); |
19d8fe15 DV |
2360 | |
2361 | if (!(tmp & DP_PORT_EN)) | |
6fa9a5ec | 2362 | goto out; |
19d8fe15 | 2363 | |
39e5fa88 | 2364 | if (IS_GEN7(dev) && port == PORT_A) { |
19d8fe15 | 2365 | *pipe = PORT_TO_PIPE_CPT(tmp); |
39e5fa88 | 2366 | } else if (HAS_PCH_CPT(dev) && port != PORT_A) { |
adc289d7 | 2367 | enum pipe p; |
19d8fe15 | 2368 | |
adc289d7 VS |
2369 | for_each_pipe(dev_priv, p) { |
2370 | u32 trans_dp = I915_READ(TRANS_DP_CTL(p)); | |
2371 | if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) { | |
2372 | *pipe = p; | |
6fa9a5ec ID |
2373 | ret = true; |
2374 | ||
2375 | goto out; | |
19d8fe15 DV |
2376 | } |
2377 | } | |
19d8fe15 | 2378 | |
4a0833ec | 2379 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
f0f59a00 | 2380 | i915_mmio_reg_offset(intel_dp->output_reg)); |
39e5fa88 VS |
2381 | } else if (IS_CHERRYVIEW(dev)) { |
2382 | *pipe = DP_PORT_TO_PIPE_CHV(tmp); | |
2383 | } else { | |
2384 | *pipe = PORT_TO_PIPE(tmp); | |
4a0833ec | 2385 | } |
d240f20f | 2386 | |
6fa9a5ec ID |
2387 | ret = true; |
2388 | ||
2389 | out: | |
2390 | intel_display_power_put(dev_priv, power_domain); | |
2391 | ||
2392 | return ret; | |
19d8fe15 | 2393 | } |
d240f20f | 2394 | |
045ac3b5 | 2395 | static void intel_dp_get_config(struct intel_encoder *encoder, |
5cec258b | 2396 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
2397 | { |
2398 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
045ac3b5 | 2399 | u32 tmp, flags = 0; |
63000ef6 | 2400 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 2401 | struct drm_i915_private *dev_priv = to_i915(dev); |
63000ef6 XZ |
2402 | enum port port = dp_to_dig_port(intel_dp)->port; |
2403 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
045ac3b5 | 2404 | |
9ed109a7 | 2405 | tmp = I915_READ(intel_dp->output_reg); |
9fcb1704 JN |
2406 | |
2407 | pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; | |
9ed109a7 | 2408 | |
39e5fa88 | 2409 | if (HAS_PCH_CPT(dev) && port != PORT_A) { |
b81e34c2 VS |
2410 | u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
2411 | ||
2412 | if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) | |
63000ef6 XZ |
2413 | flags |= DRM_MODE_FLAG_PHSYNC; |
2414 | else | |
2415 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 2416 | |
b81e34c2 | 2417 | if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
63000ef6 XZ |
2418 | flags |= DRM_MODE_FLAG_PVSYNC; |
2419 | else | |
2420 | flags |= DRM_MODE_FLAG_NVSYNC; | |
2421 | } else { | |
39e5fa88 | 2422 | if (tmp & DP_SYNC_HS_HIGH) |
63000ef6 XZ |
2423 | flags |= DRM_MODE_FLAG_PHSYNC; |
2424 | else | |
2425 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 2426 | |
39e5fa88 | 2427 | if (tmp & DP_SYNC_VS_HIGH) |
63000ef6 XZ |
2428 | flags |= DRM_MODE_FLAG_PVSYNC; |
2429 | else | |
2430 | flags |= DRM_MODE_FLAG_NVSYNC; | |
2431 | } | |
045ac3b5 | 2432 | |
2d112de7 | 2433 | pipe_config->base.adjusted_mode.flags |= flags; |
f1f644dc | 2434 | |
8c875fca | 2435 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && |
666a4537 | 2436 | !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235) |
8c875fca VS |
2437 | pipe_config->limited_color_range = true; |
2438 | ||
90a6b7b0 VS |
2439 | pipe_config->lane_count = |
2440 | ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; | |
2441 | ||
eb14cb74 VS |
2442 | intel_dp_get_m_n(crtc, pipe_config); |
2443 | ||
18442d08 | 2444 | if (port == PORT_A) { |
b377e0df | 2445 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) |
f1f644dc JB |
2446 | pipe_config->port_clock = 162000; |
2447 | else | |
2448 | pipe_config->port_clock = 270000; | |
2449 | } | |
18442d08 | 2450 | |
e3b247da VS |
2451 | pipe_config->base.adjusted_mode.crtc_clock = |
2452 | intel_dotclock_calculate(pipe_config->port_clock, | |
2453 | &pipe_config->dp_m_n); | |
7f16e5c1 | 2454 | |
6aa23e65 JN |
2455 | if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp && |
2456 | pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { | |
c6cd2ee2 JN |
2457 | /* |
2458 | * This is a big fat ugly hack. | |
2459 | * | |
2460 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
2461 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
2462 | * unknown we fail to light up. Yet the same BIOS boots up with | |
2463 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
2464 | * max, not what it tells us to use. | |
2465 | * | |
2466 | * Note: This will still be broken if the eDP panel is not lit | |
2467 | * up by the BIOS, and thus we can't get the mode at module | |
2468 | * load. | |
2469 | */ | |
2470 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
6aa23e65 JN |
2471 | pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); |
2472 | dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; | |
c6cd2ee2 | 2473 | } |
045ac3b5 JB |
2474 | } |
2475 | ||
e8cb4558 | 2476 | static void intel_disable_dp(struct intel_encoder *encoder) |
d240f20f | 2477 | { |
e8cb4558 | 2478 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
982a3866 | 2479 | struct drm_device *dev = encoder->base.dev; |
495a5bb8 JN |
2480 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2481 | ||
6e3c9717 | 2482 | if (crtc->config->has_audio) |
495a5bb8 | 2483 | intel_audio_codec_disable(encoder); |
6cb49835 | 2484 | |
b32c6f48 RV |
2485 | if (HAS_PSR(dev) && !HAS_DDI(dev)) |
2486 | intel_psr_disable(intel_dp); | |
2487 | ||
6cb49835 DV |
2488 | /* Make sure the panel is off before trying to change the mode. But also |
2489 | * ensure that we have vdd while we switch off the panel. */ | |
24f3e092 | 2490 | intel_edp_panel_vdd_on(intel_dp); |
4be73780 | 2491 | intel_edp_backlight_off(intel_dp); |
fdbc3b1f | 2492 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
4be73780 | 2493 | intel_edp_panel_off(intel_dp); |
3739850b | 2494 | |
08aff3fe VS |
2495 | /* disable the port before the pipe on g4x */ |
2496 | if (INTEL_INFO(dev)->gen < 5) | |
3739850b | 2497 | intel_dp_link_down(intel_dp); |
d240f20f JB |
2498 | } |
2499 | ||
08aff3fe | 2500 | static void ilk_post_disable_dp(struct intel_encoder *encoder) |
d240f20f | 2501 | { |
2bd2ad64 | 2502 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
982a3866 | 2503 | enum port port = dp_to_dig_port(intel_dp)->port; |
2bd2ad64 | 2504 | |
49277c31 | 2505 | intel_dp_link_down(intel_dp); |
abfce949 VS |
2506 | |
2507 | /* Only ilk+ has port A */ | |
08aff3fe VS |
2508 | if (port == PORT_A) |
2509 | ironlake_edp_pll_off(intel_dp); | |
49277c31 VS |
2510 | } |
2511 | ||
2512 | static void vlv_post_disable_dp(struct intel_encoder *encoder) | |
2513 | { | |
2514 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
2515 | ||
2516 | intel_dp_link_down(intel_dp); | |
2bd2ad64 DV |
2517 | } |
2518 | ||
a8f327fb VS |
2519 | static void chv_post_disable_dp(struct intel_encoder *encoder) |
2520 | { | |
2521 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
2522 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 2523 | struct drm_i915_private *dev_priv = to_i915(dev); |
97fd4d5c | 2524 | |
a8f327fb VS |
2525 | intel_dp_link_down(intel_dp); |
2526 | ||
2527 | mutex_lock(&dev_priv->sb_lock); | |
2528 | ||
2529 | /* Assert data lane reset */ | |
2530 | chv_data_lane_soft_reset(encoder, true); | |
580d3811 | 2531 | |
a580516d | 2532 | mutex_unlock(&dev_priv->sb_lock); |
580d3811 VS |
2533 | } |
2534 | ||
7b13b58a VS |
2535 | static void |
2536 | _intel_dp_set_link_train(struct intel_dp *intel_dp, | |
2537 | uint32_t *DP, | |
2538 | uint8_t dp_train_pat) | |
2539 | { | |
2540 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2541 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 2542 | struct drm_i915_private *dev_priv = to_i915(dev); |
7b13b58a VS |
2543 | enum port port = intel_dig_port->port; |
2544 | ||
2545 | if (HAS_DDI(dev)) { | |
2546 | uint32_t temp = I915_READ(DP_TP_CTL(port)); | |
2547 | ||
2548 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) | |
2549 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; | |
2550 | else | |
2551 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; | |
2552 | ||
2553 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
2554 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2555 | case DP_TRAINING_PATTERN_DISABLE: | |
2556 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; | |
2557 | ||
2558 | break; | |
2559 | case DP_TRAINING_PATTERN_1: | |
2560 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
2561 | break; | |
2562 | case DP_TRAINING_PATTERN_2: | |
2563 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; | |
2564 | break; | |
2565 | case DP_TRAINING_PATTERN_3: | |
2566 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; | |
2567 | break; | |
2568 | } | |
2569 | I915_WRITE(DP_TP_CTL(port), temp); | |
2570 | ||
39e5fa88 VS |
2571 | } else if ((IS_GEN7(dev) && port == PORT_A) || |
2572 | (HAS_PCH_CPT(dev) && port != PORT_A)) { | |
7b13b58a VS |
2573 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
2574 | ||
2575 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2576 | case DP_TRAINING_PATTERN_DISABLE: | |
2577 | *DP |= DP_LINK_TRAIN_OFF_CPT; | |
2578 | break; | |
2579 | case DP_TRAINING_PATTERN_1: | |
2580 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; | |
2581 | break; | |
2582 | case DP_TRAINING_PATTERN_2: | |
2583 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; | |
2584 | break; | |
2585 | case DP_TRAINING_PATTERN_3: | |
2586 | DRM_ERROR("DP training pattern 3 not supported\n"); | |
2587 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; | |
2588 | break; | |
2589 | } | |
2590 | ||
2591 | } else { | |
2592 | if (IS_CHERRYVIEW(dev)) | |
2593 | *DP &= ~DP_LINK_TRAIN_MASK_CHV; | |
2594 | else | |
2595 | *DP &= ~DP_LINK_TRAIN_MASK; | |
2596 | ||
2597 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2598 | case DP_TRAINING_PATTERN_DISABLE: | |
2599 | *DP |= DP_LINK_TRAIN_OFF; | |
2600 | break; | |
2601 | case DP_TRAINING_PATTERN_1: | |
2602 | *DP |= DP_LINK_TRAIN_PAT_1; | |
2603 | break; | |
2604 | case DP_TRAINING_PATTERN_2: | |
2605 | *DP |= DP_LINK_TRAIN_PAT_2; | |
2606 | break; | |
2607 | case DP_TRAINING_PATTERN_3: | |
2608 | if (IS_CHERRYVIEW(dev)) { | |
2609 | *DP |= DP_LINK_TRAIN_PAT_3_CHV; | |
2610 | } else { | |
2611 | DRM_ERROR("DP training pattern 3 not supported\n"); | |
2612 | *DP |= DP_LINK_TRAIN_PAT_2; | |
2613 | } | |
2614 | break; | |
2615 | } | |
2616 | } | |
2617 | } | |
2618 | ||
2619 | static void intel_dp_enable_port(struct intel_dp *intel_dp) | |
2620 | { | |
2621 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
fac5e23e | 2622 | struct drm_i915_private *dev_priv = to_i915(dev); |
6fec7662 VS |
2623 | struct intel_crtc *crtc = |
2624 | to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc); | |
7b13b58a | 2625 | |
7b13b58a VS |
2626 | /* enable with pattern 1 (as per spec) */ |
2627 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, | |
2628 | DP_TRAINING_PATTERN_1); | |
2629 | ||
2630 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
2631 | POSTING_READ(intel_dp->output_reg); | |
7b713f50 VS |
2632 | |
2633 | /* | |
2634 | * Magic for VLV/CHV. We _must_ first set up the register | |
2635 | * without actually enabling the port, and then do another | |
2636 | * write to enable the port. Otherwise link training will | |
2637 | * fail when the power sequencer is freshly used for this port. | |
2638 | */ | |
2639 | intel_dp->DP |= DP_PORT_EN; | |
6fec7662 VS |
2640 | if (crtc->config->has_audio) |
2641 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; | |
7b713f50 VS |
2642 | |
2643 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
2644 | POSTING_READ(intel_dp->output_reg); | |
580d3811 VS |
2645 | } |
2646 | ||
e8cb4558 | 2647 | static void intel_enable_dp(struct intel_encoder *encoder) |
d240f20f | 2648 | { |
e8cb4558 DV |
2649 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2650 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 2651 | struct drm_i915_private *dev_priv = to_i915(dev); |
c1dec79a | 2652 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
e8cb4558 | 2653 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
d6fbdd15 | 2654 | enum pipe pipe = crtc->pipe; |
5d613501 | 2655 | |
0c33d8d7 DV |
2656 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
2657 | return; | |
5d613501 | 2658 | |
093e3f13 VS |
2659 | pps_lock(intel_dp); |
2660 | ||
666a4537 | 2661 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
093e3f13 VS |
2662 | vlv_init_panel_power_sequencer(intel_dp); |
2663 | ||
7b13b58a | 2664 | intel_dp_enable_port(intel_dp); |
093e3f13 VS |
2665 | |
2666 | edp_panel_vdd_on(intel_dp); | |
2667 | edp_panel_on(intel_dp); | |
2668 | edp_panel_vdd_off(intel_dp, true); | |
2669 | ||
2670 | pps_unlock(intel_dp); | |
2671 | ||
666a4537 | 2672 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
e0fce78f VS |
2673 | unsigned int lane_mask = 0x0; |
2674 | ||
2675 | if (IS_CHERRYVIEW(dev)) | |
2676 | lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count); | |
2677 | ||
9b6de0a1 VS |
2678 | vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), |
2679 | lane_mask); | |
e0fce78f | 2680 | } |
61234fa5 | 2681 | |
f01eca2e | 2682 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
33a34e4e | 2683 | intel_dp_start_link_train(intel_dp); |
3ab9c637 | 2684 | intel_dp_stop_link_train(intel_dp); |
c1dec79a | 2685 | |
6e3c9717 | 2686 | if (crtc->config->has_audio) { |
c1dec79a | 2687 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
d6fbdd15 | 2688 | pipe_name(pipe)); |
c1dec79a JN |
2689 | intel_audio_codec_enable(encoder); |
2690 | } | |
ab1f90f9 | 2691 | } |
89b667f8 | 2692 | |
ecff4f3b JN |
2693 | static void g4x_enable_dp(struct intel_encoder *encoder) |
2694 | { | |
828f5c6e JN |
2695 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2696 | ||
ecff4f3b | 2697 | intel_enable_dp(encoder); |
4be73780 | 2698 | intel_edp_backlight_on(intel_dp); |
ab1f90f9 | 2699 | } |
89b667f8 | 2700 | |
ab1f90f9 JN |
2701 | static void vlv_enable_dp(struct intel_encoder *encoder) |
2702 | { | |
828f5c6e JN |
2703 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2704 | ||
4be73780 | 2705 | intel_edp_backlight_on(intel_dp); |
b32c6f48 | 2706 | intel_psr_enable(intel_dp); |
d240f20f JB |
2707 | } |
2708 | ||
ecff4f3b | 2709 | static void g4x_pre_enable_dp(struct intel_encoder *encoder) |
ab1f90f9 JN |
2710 | { |
2711 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
d6fbdd15 | 2712 | enum port port = dp_to_dig_port(intel_dp)->port; |
ab1f90f9 | 2713 | |
8ac33ed3 DV |
2714 | intel_dp_prepare(encoder); |
2715 | ||
d41f1efb | 2716 | /* Only ilk+ has port A */ |
abfce949 | 2717 | if (port == PORT_A) |
ab1f90f9 JN |
2718 | ironlake_edp_pll_on(intel_dp); |
2719 | } | |
2720 | ||
83b84597 VS |
2721 | static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) |
2722 | { | |
2723 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
fac5e23e | 2724 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
83b84597 | 2725 | enum pipe pipe = intel_dp->pps_pipe; |
44cb734c | 2726 | i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe); |
83b84597 VS |
2727 | |
2728 | edp_panel_vdd_off_sync(intel_dp); | |
2729 | ||
2730 | /* | |
2731 | * VLV seems to get confused when multiple power seqeuencers | |
2732 | * have the same port selected (even if only one has power/vdd | |
2733 | * enabled). The failure manifests as vlv_wait_port_ready() failing | |
2734 | * CHV on the other hand doesn't seem to mind having the same port | |
2735 | * selected in multiple power seqeuencers, but let's clear the | |
2736 | * port select always when logically disconnecting a power sequencer | |
2737 | * from a port. | |
2738 | */ | |
2739 | DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n", | |
2740 | pipe_name(pipe), port_name(intel_dig_port->port)); | |
2741 | I915_WRITE(pp_on_reg, 0); | |
2742 | POSTING_READ(pp_on_reg); | |
2743 | ||
2744 | intel_dp->pps_pipe = INVALID_PIPE; | |
2745 | } | |
2746 | ||
a4a5d2f8 VS |
2747 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
2748 | enum pipe pipe) | |
2749 | { | |
fac5e23e | 2750 | struct drm_i915_private *dev_priv = to_i915(dev); |
a4a5d2f8 VS |
2751 | struct intel_encoder *encoder; |
2752 | ||
2753 | lockdep_assert_held(&dev_priv->pps_mutex); | |
2754 | ||
ac3c12e4 VS |
2755 | if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) |
2756 | return; | |
2757 | ||
19c8054c | 2758 | for_each_intel_encoder(dev, encoder) { |
a4a5d2f8 | 2759 | struct intel_dp *intel_dp; |
773538e8 | 2760 | enum port port; |
a4a5d2f8 VS |
2761 | |
2762 | if (encoder->type != INTEL_OUTPUT_EDP) | |
2763 | continue; | |
2764 | ||
2765 | intel_dp = enc_to_intel_dp(&encoder->base); | |
773538e8 | 2766 | port = dp_to_dig_port(intel_dp)->port; |
a4a5d2f8 VS |
2767 | |
2768 | if (intel_dp->pps_pipe != pipe) | |
2769 | continue; | |
2770 | ||
2771 | DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n", | |
773538e8 | 2772 | pipe_name(pipe), port_name(port)); |
a4a5d2f8 | 2773 | |
e02f9a06 | 2774 | WARN(encoder->base.crtc, |
034e43c6 VS |
2775 | "stealing pipe %c power sequencer from active eDP port %c\n", |
2776 | pipe_name(pipe), port_name(port)); | |
a4a5d2f8 | 2777 | |
a4a5d2f8 | 2778 | /* make sure vdd is off before we steal it */ |
83b84597 | 2779 | vlv_detach_power_sequencer(intel_dp); |
a4a5d2f8 VS |
2780 | } |
2781 | } | |
2782 | ||
2783 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp) | |
2784 | { | |
2785 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2786 | struct intel_encoder *encoder = &intel_dig_port->base; | |
2787 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 2788 | struct drm_i915_private *dev_priv = to_i915(dev); |
a4a5d2f8 | 2789 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
a4a5d2f8 VS |
2790 | |
2791 | lockdep_assert_held(&dev_priv->pps_mutex); | |
2792 | ||
093e3f13 VS |
2793 | if (!is_edp(intel_dp)) |
2794 | return; | |
2795 | ||
a4a5d2f8 VS |
2796 | if (intel_dp->pps_pipe == crtc->pipe) |
2797 | return; | |
2798 | ||
2799 | /* | |
2800 | * If another power sequencer was being used on this | |
2801 | * port previously make sure to turn off vdd there while | |
2802 | * we still have control of it. | |
2803 | */ | |
2804 | if (intel_dp->pps_pipe != INVALID_PIPE) | |
83b84597 | 2805 | vlv_detach_power_sequencer(intel_dp); |
a4a5d2f8 VS |
2806 | |
2807 | /* | |
2808 | * We may be stealing the power | |
2809 | * sequencer from another port. | |
2810 | */ | |
2811 | vlv_steal_power_sequencer(dev, crtc->pipe); | |
2812 | ||
2813 | /* now it's all ours */ | |
2814 | intel_dp->pps_pipe = crtc->pipe; | |
2815 | ||
2816 | DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n", | |
2817 | pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port)); | |
2818 | ||
2819 | /* init power sequencer on this pipe and port */ | |
36b5f425 VS |
2820 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
2821 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); | |
a4a5d2f8 VS |
2822 | } |
2823 | ||
ab1f90f9 | 2824 | static void vlv_pre_enable_dp(struct intel_encoder *encoder) |
a4fc5ed6 | 2825 | { |
5f68c275 | 2826 | vlv_phy_pre_encoder_enable(encoder); |
ab1f90f9 JN |
2827 | |
2828 | intel_enable_dp(encoder); | |
89b667f8 JB |
2829 | } |
2830 | ||
ecff4f3b | 2831 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) |
89b667f8 | 2832 | { |
8ac33ed3 DV |
2833 | intel_dp_prepare(encoder); |
2834 | ||
6da2e616 | 2835 | vlv_phy_pre_pll_enable(encoder); |
a4fc5ed6 KP |
2836 | } |
2837 | ||
e4a1d846 CML |
2838 | static void chv_pre_enable_dp(struct intel_encoder *encoder) |
2839 | { | |
e7d2a717 | 2840 | chv_phy_pre_encoder_enable(encoder); |
e4a1d846 | 2841 | |
e4a1d846 | 2842 | intel_enable_dp(encoder); |
b0b33846 VS |
2843 | |
2844 | /* Second common lane will stay alive on its own now */ | |
e7d2a717 | 2845 | chv_phy_release_cl2_override(encoder); |
e4a1d846 CML |
2846 | } |
2847 | ||
9197c88b VS |
2848 | static void chv_dp_pre_pll_enable(struct intel_encoder *encoder) |
2849 | { | |
625695f8 VS |
2850 | intel_dp_prepare(encoder); |
2851 | ||
419b1b7a | 2852 | chv_phy_pre_pll_enable(encoder); |
9197c88b VS |
2853 | } |
2854 | ||
d6db995f VS |
2855 | static void chv_dp_post_pll_disable(struct intel_encoder *encoder) |
2856 | { | |
204970b5 | 2857 | chv_phy_post_pll_disable(encoder); |
d6db995f VS |
2858 | } |
2859 | ||
a4fc5ed6 KP |
2860 | /* |
2861 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
2862 | * link status information | |
2863 | */ | |
94223d04 | 2864 | bool |
93f62dad | 2865 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 | 2866 | { |
9f085ebb L |
2867 | return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status, |
2868 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; | |
a4fc5ed6 KP |
2869 | } |
2870 | ||
1100244e | 2871 | /* These are source-specific values. */ |
94223d04 | 2872 | uint8_t |
1a2eb460 | 2873 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
a4fc5ed6 | 2874 | { |
30add22d | 2875 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2876 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc7d38a4 | 2877 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 2878 | |
9314726b VK |
2879 | if (IS_BROXTON(dev)) |
2880 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; | |
2881 | else if (INTEL_INFO(dev)->gen >= 9) { | |
06411f08 | 2882 | if (dev_priv->vbt.edp.low_vswing && port == PORT_A) |
7ad14a29 | 2883 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
5a9d1f1a | 2884 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
666a4537 | 2885 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
bd60018a | 2886 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
bc7d38a4 | 2887 | else if (IS_GEN7(dev) && port == PORT_A) |
bd60018a | 2888 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
bc7d38a4 | 2889 | else if (HAS_PCH_CPT(dev) && port != PORT_A) |
bd60018a | 2890 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
1a2eb460 | 2891 | else |
bd60018a | 2892 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
1a2eb460 KP |
2893 | } |
2894 | ||
94223d04 | 2895 | uint8_t |
1a2eb460 KP |
2896 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
2897 | { | |
30add22d | 2898 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
bc7d38a4 | 2899 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 2900 | |
5a9d1f1a DL |
2901 | if (INTEL_INFO(dev)->gen >= 9) { |
2902 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2903 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: | |
2904 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
2905 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
2906 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
2907 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
2908 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
7ad14a29 SJ |
2909 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
2910 | return DP_TRAIN_PRE_EMPH_LEVEL_0; | |
5a9d1f1a DL |
2911 | default: |
2912 | return DP_TRAIN_PRE_EMPH_LEVEL_0; | |
2913 | } | |
2914 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
d6c0d722 | 2915 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
2916 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
2917 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
2918 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
2919 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
2920 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
2921 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
2922 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
d6c0d722 | 2923 | default: |
bd60018a | 2924 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
d6c0d722 | 2925 | } |
666a4537 | 2926 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
e2fa6fba | 2927 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
2928 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
2929 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
2930 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
2931 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
2932 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
2933 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
2934 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
e2fa6fba | 2935 | default: |
bd60018a | 2936 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
e2fa6fba | 2937 | } |
bc7d38a4 | 2938 | } else if (IS_GEN7(dev) && port == PORT_A) { |
1a2eb460 | 2939 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
2940 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
2941 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
2942 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
2943 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
2944 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
1a2eb460 | 2945 | default: |
bd60018a | 2946 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
1a2eb460 KP |
2947 | } |
2948 | } else { | |
2949 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a SJ |
2950 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
2951 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
2952 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
2953 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
2954 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
2955 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
2956 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
1a2eb460 | 2957 | default: |
bd60018a | 2958 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
1a2eb460 | 2959 | } |
a4fc5ed6 KP |
2960 | } |
2961 | } | |
2962 | ||
5829975c | 2963 | static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) |
e2fa6fba | 2964 | { |
53d98725 | 2965 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
e2fa6fba P |
2966 | unsigned long demph_reg_value, preemph_reg_value, |
2967 | uniqtranscale_reg_value; | |
2968 | uint8_t train_set = intel_dp->train_set[0]; | |
e2fa6fba P |
2969 | |
2970 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
bd60018a | 2971 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
e2fa6fba P |
2972 | preemph_reg_value = 0x0004000; |
2973 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 2974 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
2975 | demph_reg_value = 0x2B405555; |
2976 | uniqtranscale_reg_value = 0x552AB83A; | |
2977 | break; | |
bd60018a | 2978 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
2979 | demph_reg_value = 0x2B404040; |
2980 | uniqtranscale_reg_value = 0x5548B83A; | |
2981 | break; | |
bd60018a | 2982 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e2fa6fba P |
2983 | demph_reg_value = 0x2B245555; |
2984 | uniqtranscale_reg_value = 0x5560B83A; | |
2985 | break; | |
bd60018a | 2986 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
e2fa6fba P |
2987 | demph_reg_value = 0x2B405555; |
2988 | uniqtranscale_reg_value = 0x5598DA3A; | |
2989 | break; | |
2990 | default: | |
2991 | return 0; | |
2992 | } | |
2993 | break; | |
bd60018a | 2994 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
e2fa6fba P |
2995 | preemph_reg_value = 0x0002000; |
2996 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 2997 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
2998 | demph_reg_value = 0x2B404040; |
2999 | uniqtranscale_reg_value = 0x5552B83A; | |
3000 | break; | |
bd60018a | 3001 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3002 | demph_reg_value = 0x2B404848; |
3003 | uniqtranscale_reg_value = 0x5580B83A; | |
3004 | break; | |
bd60018a | 3005 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e2fa6fba P |
3006 | demph_reg_value = 0x2B404040; |
3007 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3008 | break; | |
3009 | default: | |
3010 | return 0; | |
3011 | } | |
3012 | break; | |
bd60018a | 3013 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
e2fa6fba P |
3014 | preemph_reg_value = 0x0000000; |
3015 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3016 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3017 | demph_reg_value = 0x2B305555; |
3018 | uniqtranscale_reg_value = 0x5570B83A; | |
3019 | break; | |
bd60018a | 3020 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3021 | demph_reg_value = 0x2B2B4040; |
3022 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3023 | break; | |
3024 | default: | |
3025 | return 0; | |
3026 | } | |
3027 | break; | |
bd60018a | 3028 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
e2fa6fba P |
3029 | preemph_reg_value = 0x0006000; |
3030 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3031 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3032 | demph_reg_value = 0x1B405555; |
3033 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3034 | break; | |
3035 | default: | |
3036 | return 0; | |
3037 | } | |
3038 | break; | |
3039 | default: | |
3040 | return 0; | |
3041 | } | |
3042 | ||
53d98725 ACO |
3043 | vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value, |
3044 | uniqtranscale_reg_value, 0); | |
e2fa6fba P |
3045 | |
3046 | return 0; | |
3047 | } | |
3048 | ||
5829975c | 3049 | static uint32_t chv_signal_levels(struct intel_dp *intel_dp) |
e4a1d846 | 3050 | { |
b7fa22d8 ACO |
3051 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
3052 | u32 deemph_reg_value, margin_reg_value; | |
3053 | bool uniq_trans_scale = false; | |
e4a1d846 | 3054 | uint8_t train_set = intel_dp->train_set[0]; |
e4a1d846 CML |
3055 | |
3056 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
bd60018a | 3057 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
e4a1d846 | 3058 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3059 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3060 | deemph_reg_value = 128; |
3061 | margin_reg_value = 52; | |
3062 | break; | |
bd60018a | 3063 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3064 | deemph_reg_value = 128; |
3065 | margin_reg_value = 77; | |
3066 | break; | |
bd60018a | 3067 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e4a1d846 CML |
3068 | deemph_reg_value = 128; |
3069 | margin_reg_value = 102; | |
3070 | break; | |
bd60018a | 3071 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
e4a1d846 CML |
3072 | deemph_reg_value = 128; |
3073 | margin_reg_value = 154; | |
b7fa22d8 | 3074 | uniq_trans_scale = true; |
e4a1d846 CML |
3075 | break; |
3076 | default: | |
3077 | return 0; | |
3078 | } | |
3079 | break; | |
bd60018a | 3080 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
e4a1d846 | 3081 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3082 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3083 | deemph_reg_value = 85; |
3084 | margin_reg_value = 78; | |
3085 | break; | |
bd60018a | 3086 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3087 | deemph_reg_value = 85; |
3088 | margin_reg_value = 116; | |
3089 | break; | |
bd60018a | 3090 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e4a1d846 CML |
3091 | deemph_reg_value = 85; |
3092 | margin_reg_value = 154; | |
3093 | break; | |
3094 | default: | |
3095 | return 0; | |
3096 | } | |
3097 | break; | |
bd60018a | 3098 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
e4a1d846 | 3099 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3100 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3101 | deemph_reg_value = 64; |
3102 | margin_reg_value = 104; | |
3103 | break; | |
bd60018a | 3104 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3105 | deemph_reg_value = 64; |
3106 | margin_reg_value = 154; | |
3107 | break; | |
3108 | default: | |
3109 | return 0; | |
3110 | } | |
3111 | break; | |
bd60018a | 3112 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
e4a1d846 | 3113 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3114 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3115 | deemph_reg_value = 43; |
3116 | margin_reg_value = 154; | |
3117 | break; | |
3118 | default: | |
3119 | return 0; | |
3120 | } | |
3121 | break; | |
3122 | default: | |
3123 | return 0; | |
3124 | } | |
3125 | ||
b7fa22d8 ACO |
3126 | chv_set_phy_signal_level(encoder, deemph_reg_value, |
3127 | margin_reg_value, uniq_trans_scale); | |
e4a1d846 CML |
3128 | |
3129 | return 0; | |
3130 | } | |
3131 | ||
a4fc5ed6 | 3132 | static uint32_t |
5829975c | 3133 | gen4_signal_levels(uint8_t train_set) |
a4fc5ed6 | 3134 | { |
3cf2efb1 | 3135 | uint32_t signal_levels = 0; |
a4fc5ed6 | 3136 | |
3cf2efb1 | 3137 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3138 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
a4fc5ed6 KP |
3139 | default: |
3140 | signal_levels |= DP_VOLTAGE_0_4; | |
3141 | break; | |
bd60018a | 3142 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
a4fc5ed6 KP |
3143 | signal_levels |= DP_VOLTAGE_0_6; |
3144 | break; | |
bd60018a | 3145 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
a4fc5ed6 KP |
3146 | signal_levels |= DP_VOLTAGE_0_8; |
3147 | break; | |
bd60018a | 3148 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
a4fc5ed6 KP |
3149 | signal_levels |= DP_VOLTAGE_1_2; |
3150 | break; | |
3151 | } | |
3cf2efb1 | 3152 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
bd60018a | 3153 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
a4fc5ed6 KP |
3154 | default: |
3155 | signal_levels |= DP_PRE_EMPHASIS_0; | |
3156 | break; | |
bd60018a | 3157 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
a4fc5ed6 KP |
3158 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
3159 | break; | |
bd60018a | 3160 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
a4fc5ed6 KP |
3161 | signal_levels |= DP_PRE_EMPHASIS_6; |
3162 | break; | |
bd60018a | 3163 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
a4fc5ed6 KP |
3164 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
3165 | break; | |
3166 | } | |
3167 | return signal_levels; | |
3168 | } | |
3169 | ||
e3421a18 ZW |
3170 | /* Gen6's DP voltage swing and pre-emphasis control */ |
3171 | static uint32_t | |
5829975c | 3172 | gen6_edp_signal_levels(uint8_t train_set) |
e3421a18 | 3173 | { |
3c5a62b5 YL |
3174 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
3175 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
3176 | switch (signal_levels) { | |
bd60018a SJ |
3177 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3178 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
3c5a62b5 | 3179 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
bd60018a | 3180 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3c5a62b5 | 3181 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
bd60018a SJ |
3182 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
3183 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: | |
3c5a62b5 | 3184 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
bd60018a SJ |
3185 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3186 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: | |
3c5a62b5 | 3187 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
bd60018a SJ |
3188 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3189 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
3c5a62b5 | 3190 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
e3421a18 | 3191 | default: |
3c5a62b5 YL |
3192 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
3193 | "0x%x\n", signal_levels); | |
3194 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
e3421a18 ZW |
3195 | } |
3196 | } | |
3197 | ||
1a2eb460 KP |
3198 | /* Gen7's DP voltage swing and pre-emphasis control */ |
3199 | static uint32_t | |
5829975c | 3200 | gen7_edp_signal_levels(uint8_t train_set) |
1a2eb460 KP |
3201 | { |
3202 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | | |
3203 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
3204 | switch (signal_levels) { | |
bd60018a | 3205 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3206 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
bd60018a | 3207 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 | 3208 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
bd60018a | 3209 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
1a2eb460 KP |
3210 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
3211 | ||
bd60018a | 3212 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3213 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
bd60018a | 3214 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 KP |
3215 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
3216 | ||
bd60018a | 3217 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3218 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
bd60018a | 3219 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 KP |
3220 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
3221 | ||
3222 | default: | |
3223 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
3224 | "0x%x\n", signal_levels); | |
3225 | return EDP_LINK_TRAIN_500MV_0DB_IVB; | |
3226 | } | |
3227 | } | |
3228 | ||
94223d04 | 3229 | void |
f4eb692e | 3230 | intel_dp_set_signal_levels(struct intel_dp *intel_dp) |
f0a3424e PZ |
3231 | { |
3232 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
bc7d38a4 | 3233 | enum port port = intel_dig_port->port; |
f0a3424e | 3234 | struct drm_device *dev = intel_dig_port->base.base.dev; |
b905a915 | 3235 | struct drm_i915_private *dev_priv = to_i915(dev); |
f8896f5d | 3236 | uint32_t signal_levels, mask = 0; |
f0a3424e PZ |
3237 | uint8_t train_set = intel_dp->train_set[0]; |
3238 | ||
f8896f5d DW |
3239 | if (HAS_DDI(dev)) { |
3240 | signal_levels = ddi_signal_levels(intel_dp); | |
3241 | ||
3242 | if (IS_BROXTON(dev)) | |
3243 | signal_levels = 0; | |
3244 | else | |
3245 | mask = DDI_BUF_EMP_MASK; | |
e4a1d846 | 3246 | } else if (IS_CHERRYVIEW(dev)) { |
5829975c | 3247 | signal_levels = chv_signal_levels(intel_dp); |
e2fa6fba | 3248 | } else if (IS_VALLEYVIEW(dev)) { |
5829975c | 3249 | signal_levels = vlv_signal_levels(intel_dp); |
bc7d38a4 | 3250 | } else if (IS_GEN7(dev) && port == PORT_A) { |
5829975c | 3251 | signal_levels = gen7_edp_signal_levels(train_set); |
f0a3424e | 3252 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
bc7d38a4 | 3253 | } else if (IS_GEN6(dev) && port == PORT_A) { |
5829975c | 3254 | signal_levels = gen6_edp_signal_levels(train_set); |
f0a3424e PZ |
3255 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
3256 | } else { | |
5829975c | 3257 | signal_levels = gen4_signal_levels(train_set); |
f0a3424e PZ |
3258 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
3259 | } | |
3260 | ||
96fb9f9b VK |
3261 | if (mask) |
3262 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); | |
3263 | ||
3264 | DRM_DEBUG_KMS("Using vswing level %d\n", | |
3265 | train_set & DP_TRAIN_VOLTAGE_SWING_MASK); | |
3266 | DRM_DEBUG_KMS("Using pre-emphasis level %d\n", | |
3267 | (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> | |
3268 | DP_TRAIN_PRE_EMPHASIS_SHIFT); | |
f0a3424e | 3269 | |
f4eb692e | 3270 | intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels; |
b905a915 ACO |
3271 | |
3272 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
3273 | POSTING_READ(intel_dp->output_reg); | |
f0a3424e PZ |
3274 | } |
3275 | ||
94223d04 | 3276 | void |
e9c176d5 ACO |
3277 | intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, |
3278 | uint8_t dp_train_pat) | |
a4fc5ed6 | 3279 | { |
174edf1f | 3280 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
90a6b7b0 VS |
3281 | struct drm_i915_private *dev_priv = |
3282 | to_i915(intel_dig_port->base.base.dev); | |
a4fc5ed6 | 3283 | |
f4eb692e | 3284 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat); |
47ea7542 | 3285 | |
f4eb692e | 3286 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
ea5b213a | 3287 | POSTING_READ(intel_dp->output_reg); |
e9c176d5 ACO |
3288 | } |
3289 | ||
94223d04 | 3290 | void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
3ab9c637 ID |
3291 | { |
3292 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
3293 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 3294 | struct drm_i915_private *dev_priv = to_i915(dev); |
3ab9c637 ID |
3295 | enum port port = intel_dig_port->port; |
3296 | uint32_t val; | |
3297 | ||
3298 | if (!HAS_DDI(dev)) | |
3299 | return; | |
3300 | ||
3301 | val = I915_READ(DP_TP_CTL(port)); | |
3302 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
3303 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; | |
3304 | I915_WRITE(DP_TP_CTL(port), val); | |
3305 | ||
3306 | /* | |
3307 | * On PORT_A we can have only eDP in SST mode. There the only reason | |
3308 | * we need to set idle transmission mode is to work around a HW issue | |
3309 | * where we enable the pipe while not in idle link-training mode. | |
3310 | * In this case there is requirement to wait for a minimum number of | |
3311 | * idle patterns to be sent. | |
3312 | */ | |
3313 | if (port == PORT_A) | |
3314 | return; | |
3315 | ||
a767017f CW |
3316 | if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port), |
3317 | DP_TP_STATUS_IDLE_DONE, | |
3318 | DP_TP_STATUS_IDLE_DONE, | |
3319 | 1)) | |
3ab9c637 ID |
3320 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
3321 | } | |
3322 | ||
a4fc5ed6 | 3323 | static void |
ea5b213a | 3324 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 3325 | { |
da63a9f2 | 3326 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1612c8bd | 3327 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
bc7d38a4 | 3328 | enum port port = intel_dig_port->port; |
da63a9f2 | 3329 | struct drm_device *dev = intel_dig_port->base.base.dev; |
fac5e23e | 3330 | struct drm_i915_private *dev_priv = to_i915(dev); |
ea5b213a | 3331 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 3332 | |
bc76e320 | 3333 | if (WARN_ON(HAS_DDI(dev))) |
c19b0669 PZ |
3334 | return; |
3335 | ||
0c33d8d7 | 3336 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
1b39d6f3 CW |
3337 | return; |
3338 | ||
28c97730 | 3339 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 3340 | |
39e5fa88 VS |
3341 | if ((IS_GEN7(dev) && port == PORT_A) || |
3342 | (HAS_PCH_CPT(dev) && port != PORT_A)) { | |
e3421a18 | 3343 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
1612c8bd | 3344 | DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; |
e3421a18 | 3345 | } else { |
aad3d14d VS |
3346 | if (IS_CHERRYVIEW(dev)) |
3347 | DP &= ~DP_LINK_TRAIN_MASK_CHV; | |
3348 | else | |
3349 | DP &= ~DP_LINK_TRAIN_MASK; | |
1612c8bd | 3350 | DP |= DP_LINK_TRAIN_PAT_IDLE; |
e3421a18 | 3351 | } |
1612c8bd | 3352 | I915_WRITE(intel_dp->output_reg, DP); |
fe255d00 | 3353 | POSTING_READ(intel_dp->output_reg); |
5eb08b69 | 3354 | |
1612c8bd VS |
3355 | DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
3356 | I915_WRITE(intel_dp->output_reg, DP); | |
3357 | POSTING_READ(intel_dp->output_reg); | |
3358 | ||
3359 | /* | |
3360 | * HW workaround for IBX, we need to move the port | |
3361 | * to transcoder A after disabling it to allow the | |
3362 | * matching HDMI port to be enabled on transcoder A. | |
3363 | */ | |
3364 | if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) { | |
0c241d5b VS |
3365 | /* |
3366 | * We get CPU/PCH FIFO underruns on the other pipe when | |
3367 | * doing the workaround. Sweep them under the rug. | |
3368 | */ | |
3369 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
3370 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
3371 | ||
1612c8bd VS |
3372 | /* always enable with pattern 1 (as per spec) */ |
3373 | DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK); | |
3374 | DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1; | |
3375 | I915_WRITE(intel_dp->output_reg, DP); | |
3376 | POSTING_READ(intel_dp->output_reg); | |
3377 | ||
3378 | DP &= ~DP_PORT_EN; | |
5bddd17f | 3379 | I915_WRITE(intel_dp->output_reg, DP); |
0ca09685 | 3380 | POSTING_READ(intel_dp->output_reg); |
0c241d5b | 3381 | |
91c8a326 | 3382 | intel_wait_for_vblank_if_active(&dev_priv->drm, PIPE_A); |
0c241d5b VS |
3383 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
3384 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
5bddd17f EA |
3385 | } |
3386 | ||
f01eca2e | 3387 | msleep(intel_dp->panel_power_down_delay); |
6fec7662 VS |
3388 | |
3389 | intel_dp->DP = DP; | |
a4fc5ed6 KP |
3390 | } |
3391 | ||
26d61aad | 3392 | static bool |
fe5a66f9 | 3393 | intel_dp_read_dpcd(struct intel_dp *intel_dp) |
92fd8fd1 | 3394 | { |
9f085ebb L |
3395 | if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd, |
3396 | sizeof(intel_dp->dpcd)) < 0) | |
edb39244 | 3397 | return false; /* aux transfer failed */ |
92fd8fd1 | 3398 | |
a8e98153 | 3399 | DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); |
577c7a50 | 3400 | |
fe5a66f9 VS |
3401 | return intel_dp->dpcd[DP_DPCD_REV] != 0; |
3402 | } | |
edb39244 | 3403 | |
fe5a66f9 VS |
3404 | static bool |
3405 | intel_edp_init_dpcd(struct intel_dp *intel_dp) | |
3406 | { | |
3407 | struct drm_i915_private *dev_priv = | |
3408 | to_i915(dp_to_dig_port(intel_dp)->base.base.dev); | |
30d9aa42 | 3409 | |
fe5a66f9 VS |
3410 | /* this function is meant to be called only once */ |
3411 | WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0); | |
30d9aa42 | 3412 | |
fe5a66f9 | 3413 | if (!intel_dp_read_dpcd(intel_dp)) |
30d9aa42 SS |
3414 | return false; |
3415 | ||
fe5a66f9 VS |
3416 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
3417 | dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] & | |
3418 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; | |
474d1ec4 | 3419 | |
fe5a66f9 VS |
3420 | /* Check if the panel supports PSR */ |
3421 | drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, | |
3422 | intel_dp->psr_dpcd, | |
3423 | sizeof(intel_dp->psr_dpcd)); | |
3424 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { | |
3425 | dev_priv->psr.sink_support = true; | |
3426 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); | |
3427 | } | |
86ee27b5 | 3428 | |
fe5a66f9 VS |
3429 | if (INTEL_GEN(dev_priv) >= 9 && |
3430 | (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { | |
3431 | uint8_t frame_sync_cap; | |
3432 | ||
3433 | dev_priv->psr.sink_support = true; | |
3434 | drm_dp_dpcd_read(&intel_dp->aux, | |
3435 | DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, | |
3436 | &frame_sync_cap, 1); | |
3437 | dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; | |
3438 | /* PSR2 needs frame sync as well */ | |
3439 | dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; | |
3440 | DRM_DEBUG_KMS("PSR2 %s on sink", | |
3441 | dev_priv->psr.psr2_support ? "supported" : "not supported"); | |
50003939 JN |
3442 | } |
3443 | ||
fe5a66f9 VS |
3444 | /* Read the eDP Display control capabilities registers */ |
3445 | if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) && | |
3446 | drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, | |
3447 | intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd) == | |
3448 | sizeof(intel_dp->edp_dpcd))) | |
3449 | DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd), | |
3450 | intel_dp->edp_dpcd); | |
06ea66b6 | 3451 | |
fc0f8e25 | 3452 | /* Intermediate frequency support */ |
fe5a66f9 | 3453 | if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */ |
94ca719e | 3454 | __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; |
ea2d8a42 VS |
3455 | int i; |
3456 | ||
9f085ebb L |
3457 | drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, |
3458 | sink_rates, sizeof(sink_rates)); | |
ea2d8a42 | 3459 | |
94ca719e VS |
3460 | for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { |
3461 | int val = le16_to_cpu(sink_rates[i]); | |
ea2d8a42 VS |
3462 | |
3463 | if (val == 0) | |
3464 | break; | |
3465 | ||
af77b974 SJ |
3466 | /* Value read is in kHz while drm clock is saved in deca-kHz */ |
3467 | intel_dp->sink_rates[i] = (val * 200) / 10; | |
ea2d8a42 | 3468 | } |
94ca719e | 3469 | intel_dp->num_sink_rates = i; |
fc0f8e25 | 3470 | } |
0336400e | 3471 | |
fe5a66f9 VS |
3472 | return true; |
3473 | } | |
3474 | ||
3475 | ||
3476 | static bool | |
3477 | intel_dp_get_dpcd(struct intel_dp *intel_dp) | |
3478 | { | |
3479 | if (!intel_dp_read_dpcd(intel_dp)) | |
3480 | return false; | |
3481 | ||
3482 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT, | |
3483 | &intel_dp->sink_count, 1) < 0) | |
3484 | return false; | |
3485 | ||
3486 | /* | |
3487 | * Sink count can change between short pulse hpd hence | |
3488 | * a member variable in intel_dp will track any changes | |
3489 | * between short pulse interrupts. | |
3490 | */ | |
3491 | intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count); | |
3492 | ||
3493 | /* | |
3494 | * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that | |
3495 | * a dongle is present but no display. Unless we require to know | |
3496 | * if a dongle is present or not, we don't need to update | |
3497 | * downstream port information. So, an early return here saves | |
3498 | * time from performing other operations which are not required. | |
3499 | */ | |
3500 | if (!is_edp(intel_dp) && !intel_dp->sink_count) | |
3501 | return false; | |
0336400e | 3502 | |
edb39244 AJ |
3503 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
3504 | DP_DWN_STRM_PORT_PRESENT)) | |
3505 | return true; /* native DP sink */ | |
3506 | ||
3507 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) | |
3508 | return true; /* no per-port downstream info */ | |
3509 | ||
9f085ebb L |
3510 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
3511 | intel_dp->downstream_ports, | |
3512 | DP_MAX_DOWNSTREAM_PORTS) < 0) | |
edb39244 AJ |
3513 | return false; /* downstream port status fetch failed */ |
3514 | ||
3515 | return true; | |
92fd8fd1 KP |
3516 | } |
3517 | ||
0d198328 AJ |
3518 | static void |
3519 | intel_dp_probe_oui(struct intel_dp *intel_dp) | |
3520 | { | |
3521 | u8 buf[3]; | |
3522 | ||
3523 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) | |
3524 | return; | |
3525 | ||
9f085ebb | 3526 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) |
0d198328 AJ |
3527 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
3528 | buf[0], buf[1], buf[2]); | |
3529 | ||
9f085ebb | 3530 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) |
0d198328 AJ |
3531 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
3532 | buf[0], buf[1], buf[2]); | |
3533 | } | |
3534 | ||
0e32b39c | 3535 | static bool |
c4e3170a | 3536 | intel_dp_can_mst(struct intel_dp *intel_dp) |
0e32b39c DA |
3537 | { |
3538 | u8 buf[1]; | |
3539 | ||
7cc96139 NS |
3540 | if (!i915.enable_dp_mst) |
3541 | return false; | |
3542 | ||
0e32b39c DA |
3543 | if (!intel_dp->can_mst) |
3544 | return false; | |
3545 | ||
3546 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) | |
3547 | return false; | |
3548 | ||
c4e3170a VS |
3549 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1) != 1) |
3550 | return false; | |
0e32b39c | 3551 | |
c4e3170a VS |
3552 | return buf[0] & DP_MST_CAP; |
3553 | } | |
3554 | ||
3555 | static void | |
3556 | intel_dp_configure_mst(struct intel_dp *intel_dp) | |
3557 | { | |
3558 | if (!i915.enable_dp_mst) | |
3559 | return; | |
3560 | ||
3561 | if (!intel_dp->can_mst) | |
3562 | return; | |
3563 | ||
3564 | intel_dp->is_mst = intel_dp_can_mst(intel_dp); | |
3565 | ||
3566 | if (intel_dp->is_mst) | |
3567 | DRM_DEBUG_KMS("Sink is MST capable\n"); | |
3568 | else | |
3569 | DRM_DEBUG_KMS("Sink is not MST capable\n"); | |
3570 | ||
3571 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
3572 | intel_dp->is_mst); | |
0e32b39c DA |
3573 | } |
3574 | ||
e5a1cab5 | 3575 | static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp) |
d2e216d0 | 3576 | { |
082dcc7c | 3577 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
d72f9d91 | 3578 | struct drm_device *dev = dig_port->base.base.dev; |
082dcc7c | 3579 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
ad9dc91b | 3580 | u8 buf; |
e5a1cab5 | 3581 | int ret = 0; |
c6297843 RV |
3582 | int count = 0; |
3583 | int attempts = 10; | |
d2e216d0 | 3584 | |
082dcc7c RV |
3585 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) { |
3586 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); | |
e5a1cab5 RV |
3587 | ret = -EIO; |
3588 | goto out; | |
4373f0f2 PZ |
3589 | } |
3590 | ||
082dcc7c | 3591 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
e5a1cab5 | 3592 | buf & ~DP_TEST_SINK_START) < 0) { |
082dcc7c | 3593 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
e5a1cab5 RV |
3594 | ret = -EIO; |
3595 | goto out; | |
3596 | } | |
d2e216d0 | 3597 | |
c6297843 RV |
3598 | do { |
3599 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
3600 | ||
3601 | if (drm_dp_dpcd_readb(&intel_dp->aux, | |
3602 | DP_TEST_SINK_MISC, &buf) < 0) { | |
3603 | ret = -EIO; | |
3604 | goto out; | |
3605 | } | |
3606 | count = buf & DP_TEST_COUNT_MASK; | |
3607 | } while (--attempts && count); | |
3608 | ||
3609 | if (attempts == 0) { | |
dc5a9037 | 3610 | DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n"); |
c6297843 RV |
3611 | ret = -ETIMEDOUT; |
3612 | } | |
3613 | ||
e5a1cab5 | 3614 | out: |
082dcc7c | 3615 | hsw_enable_ips(intel_crtc); |
e5a1cab5 | 3616 | return ret; |
082dcc7c RV |
3617 | } |
3618 | ||
3619 | static int intel_dp_sink_crc_start(struct intel_dp *intel_dp) | |
3620 | { | |
3621 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
d72f9d91 | 3622 | struct drm_device *dev = dig_port->base.base.dev; |
082dcc7c RV |
3623 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
3624 | u8 buf; | |
e5a1cab5 RV |
3625 | int ret; |
3626 | ||
082dcc7c RV |
3627 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) |
3628 | return -EIO; | |
3629 | ||
3630 | if (!(buf & DP_TEST_CRC_SUPPORTED)) | |
3631 | return -ENOTTY; | |
3632 | ||
3633 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) | |
3634 | return -EIO; | |
3635 | ||
6d8175da RV |
3636 | if (buf & DP_TEST_SINK_START) { |
3637 | ret = intel_dp_sink_crc_stop(intel_dp); | |
3638 | if (ret) | |
3639 | return ret; | |
3640 | } | |
3641 | ||
082dcc7c | 3642 | hsw_disable_ips(intel_crtc); |
1dda5f93 | 3643 | |
9d1a1031 | 3644 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
082dcc7c RV |
3645 | buf | DP_TEST_SINK_START) < 0) { |
3646 | hsw_enable_ips(intel_crtc); | |
3647 | return -EIO; | |
4373f0f2 PZ |
3648 | } |
3649 | ||
d72f9d91 | 3650 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
082dcc7c RV |
3651 | return 0; |
3652 | } | |
3653 | ||
3654 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) | |
3655 | { | |
3656 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
3657 | struct drm_device *dev = dig_port->base.base.dev; | |
3658 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); | |
3659 | u8 buf; | |
621d4c76 | 3660 | int count, ret; |
082dcc7c | 3661 | int attempts = 6; |
082dcc7c RV |
3662 | |
3663 | ret = intel_dp_sink_crc_start(intel_dp); | |
3664 | if (ret) | |
3665 | return ret; | |
3666 | ||
ad9dc91b | 3667 | do { |
621d4c76 RV |
3668 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
3669 | ||
1dda5f93 | 3670 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
4373f0f2 PZ |
3671 | DP_TEST_SINK_MISC, &buf) < 0) { |
3672 | ret = -EIO; | |
afe0d67e | 3673 | goto stop; |
4373f0f2 | 3674 | } |
621d4c76 | 3675 | count = buf & DP_TEST_COUNT_MASK; |
aabc95dc | 3676 | |
7e38eeff | 3677 | } while (--attempts && count == 0); |
ad9dc91b RV |
3678 | |
3679 | if (attempts == 0) { | |
7e38eeff RV |
3680 | DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n"); |
3681 | ret = -ETIMEDOUT; | |
3682 | goto stop; | |
3683 | } | |
3684 | ||
3685 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) { | |
3686 | ret = -EIO; | |
3687 | goto stop; | |
ad9dc91b | 3688 | } |
d2e216d0 | 3689 | |
afe0d67e | 3690 | stop: |
082dcc7c | 3691 | intel_dp_sink_crc_stop(intel_dp); |
4373f0f2 | 3692 | return ret; |
d2e216d0 RV |
3693 | } |
3694 | ||
a60f0e38 JB |
3695 | static bool |
3696 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
3697 | { | |
9f085ebb | 3698 | return drm_dp_dpcd_read(&intel_dp->aux, |
9d1a1031 JN |
3699 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
3700 | sink_irq_vector, 1) == 1; | |
a60f0e38 JB |
3701 | } |
3702 | ||
0e32b39c DA |
3703 | static bool |
3704 | intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
3705 | { | |
3706 | int ret; | |
3707 | ||
9f085ebb | 3708 | ret = drm_dp_dpcd_read(&intel_dp->aux, |
0e32b39c DA |
3709 | DP_SINK_COUNT_ESI, |
3710 | sink_irq_vector, 14); | |
3711 | if (ret != 14) | |
3712 | return false; | |
3713 | ||
3714 | return true; | |
3715 | } | |
3716 | ||
c5d5ab7a TP |
3717 | static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) |
3718 | { | |
3719 | uint8_t test_result = DP_TEST_ACK; | |
3720 | return test_result; | |
3721 | } | |
3722 | ||
3723 | static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) | |
3724 | { | |
3725 | uint8_t test_result = DP_TEST_NAK; | |
3726 | return test_result; | |
3727 | } | |
3728 | ||
3729 | static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) | |
a60f0e38 | 3730 | { |
c5d5ab7a | 3731 | uint8_t test_result = DP_TEST_NAK; |
559be30c TP |
3732 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
3733 | struct drm_connector *connector = &intel_connector->base; | |
3734 | ||
3735 | if (intel_connector->detect_edid == NULL || | |
ac6f2e29 | 3736 | connector->edid_corrupt || |
559be30c TP |
3737 | intel_dp->aux.i2c_defer_count > 6) { |
3738 | /* Check EDID read for NACKs, DEFERs and corruption | |
3739 | * (DP CTS 1.2 Core r1.1) | |
3740 | * 4.2.2.4 : Failed EDID read, I2C_NAK | |
3741 | * 4.2.2.5 : Failed EDID read, I2C_DEFER | |
3742 | * 4.2.2.6 : EDID corruption detected | |
3743 | * Use failsafe mode for all cases | |
3744 | */ | |
3745 | if (intel_dp->aux.i2c_nack_count > 0 || | |
3746 | intel_dp->aux.i2c_defer_count > 0) | |
3747 | DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n", | |
3748 | intel_dp->aux.i2c_nack_count, | |
3749 | intel_dp->aux.i2c_defer_count); | |
3750 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE; | |
3751 | } else { | |
f79b468e TS |
3752 | struct edid *block = intel_connector->detect_edid; |
3753 | ||
3754 | /* We have to write the checksum | |
3755 | * of the last block read | |
3756 | */ | |
3757 | block += intel_connector->detect_edid->extensions; | |
3758 | ||
559be30c TP |
3759 | if (!drm_dp_dpcd_write(&intel_dp->aux, |
3760 | DP_TEST_EDID_CHECKSUM, | |
f79b468e | 3761 | &block->checksum, |
5a1cc655 | 3762 | 1)) |
559be30c TP |
3763 | DRM_DEBUG_KMS("Failed to write EDID checksum\n"); |
3764 | ||
3765 | test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; | |
3766 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD; | |
3767 | } | |
3768 | ||
3769 | /* Set test active flag here so userspace doesn't interrupt things */ | |
3770 | intel_dp->compliance_test_active = 1; | |
3771 | ||
c5d5ab7a TP |
3772 | return test_result; |
3773 | } | |
3774 | ||
3775 | static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) | |
a60f0e38 | 3776 | { |
c5d5ab7a TP |
3777 | uint8_t test_result = DP_TEST_NAK; |
3778 | return test_result; | |
3779 | } | |
3780 | ||
3781 | static void intel_dp_handle_test_request(struct intel_dp *intel_dp) | |
3782 | { | |
3783 | uint8_t response = DP_TEST_NAK; | |
3784 | uint8_t rxdata = 0; | |
3785 | int status = 0; | |
3786 | ||
c5d5ab7a TP |
3787 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1); |
3788 | if (status <= 0) { | |
3789 | DRM_DEBUG_KMS("Could not read test request from sink\n"); | |
3790 | goto update_status; | |
3791 | } | |
3792 | ||
3793 | switch (rxdata) { | |
3794 | case DP_TEST_LINK_TRAINING: | |
3795 | DRM_DEBUG_KMS("LINK_TRAINING test requested\n"); | |
3796 | intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING; | |
3797 | response = intel_dp_autotest_link_training(intel_dp); | |
3798 | break; | |
3799 | case DP_TEST_LINK_VIDEO_PATTERN: | |
3800 | DRM_DEBUG_KMS("TEST_PATTERN test requested\n"); | |
3801 | intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN; | |
3802 | response = intel_dp_autotest_video_pattern(intel_dp); | |
3803 | break; | |
3804 | case DP_TEST_LINK_EDID_READ: | |
3805 | DRM_DEBUG_KMS("EDID test requested\n"); | |
3806 | intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ; | |
3807 | response = intel_dp_autotest_edid(intel_dp); | |
3808 | break; | |
3809 | case DP_TEST_LINK_PHY_TEST_PATTERN: | |
3810 | DRM_DEBUG_KMS("PHY_PATTERN test requested\n"); | |
3811 | intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN; | |
3812 | response = intel_dp_autotest_phy_pattern(intel_dp); | |
3813 | break; | |
3814 | default: | |
3815 | DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata); | |
3816 | break; | |
3817 | } | |
3818 | ||
3819 | update_status: | |
3820 | status = drm_dp_dpcd_write(&intel_dp->aux, | |
3821 | DP_TEST_RESPONSE, | |
3822 | &response, 1); | |
3823 | if (status <= 0) | |
3824 | DRM_DEBUG_KMS("Could not write test response to sink\n"); | |
a60f0e38 JB |
3825 | } |
3826 | ||
0e32b39c DA |
3827 | static int |
3828 | intel_dp_check_mst_status(struct intel_dp *intel_dp) | |
3829 | { | |
3830 | bool bret; | |
3831 | ||
3832 | if (intel_dp->is_mst) { | |
3833 | u8 esi[16] = { 0 }; | |
3834 | int ret = 0; | |
3835 | int retry; | |
3836 | bool handled; | |
3837 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); | |
3838 | go_again: | |
3839 | if (bret == true) { | |
3840 | ||
3841 | /* check link status - esi[10] = 0x200c */ | |
19e0b4ca | 3842 | if (intel_dp->active_mst_links && |
901c2daf | 3843 | !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { |
0e32b39c DA |
3844 | DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); |
3845 | intel_dp_start_link_train(intel_dp); | |
0e32b39c DA |
3846 | intel_dp_stop_link_train(intel_dp); |
3847 | } | |
3848 | ||
6f34cc39 | 3849 | DRM_DEBUG_KMS("got esi %3ph\n", esi); |
0e32b39c DA |
3850 | ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); |
3851 | ||
3852 | if (handled) { | |
3853 | for (retry = 0; retry < 3; retry++) { | |
3854 | int wret; | |
3855 | wret = drm_dp_dpcd_write(&intel_dp->aux, | |
3856 | DP_SINK_COUNT_ESI+1, | |
3857 | &esi[1], 3); | |
3858 | if (wret == 3) { | |
3859 | break; | |
3860 | } | |
3861 | } | |
3862 | ||
3863 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); | |
3864 | if (bret == true) { | |
6f34cc39 | 3865 | DRM_DEBUG_KMS("got esi2 %3ph\n", esi); |
0e32b39c DA |
3866 | goto go_again; |
3867 | } | |
3868 | } else | |
3869 | ret = 0; | |
3870 | ||
3871 | return ret; | |
3872 | } else { | |
3873 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
3874 | DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); | |
3875 | intel_dp->is_mst = false; | |
3876 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); | |
3877 | /* send a hotplug event */ | |
3878 | drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); | |
3879 | } | |
3880 | } | |
3881 | return -EINVAL; | |
3882 | } | |
3883 | ||
5c9114d0 SS |
3884 | static void |
3885 | intel_dp_check_link_status(struct intel_dp *intel_dp) | |
3886 | { | |
3887 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; | |
3888 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
3889 | u8 link_status[DP_LINK_STATUS_SIZE]; | |
3890 | ||
3891 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); | |
3892 | ||
3893 | if (!intel_dp_get_link_status(intel_dp, link_status)) { | |
3894 | DRM_ERROR("Failed to get link status\n"); | |
3895 | return; | |
3896 | } | |
3897 | ||
3898 | if (!intel_encoder->base.crtc) | |
3899 | return; | |
3900 | ||
3901 | if (!to_intel_crtc(intel_encoder->base.crtc)->active) | |
3902 | return; | |
3903 | ||
3904 | /* if link training is requested we should perform it always */ | |
3905 | if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) || | |
3906 | (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) { | |
3907 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", | |
3908 | intel_encoder->base.name); | |
3909 | intel_dp_start_link_train(intel_dp); | |
3910 | intel_dp_stop_link_train(intel_dp); | |
3911 | } | |
3912 | } | |
3913 | ||
a4fc5ed6 KP |
3914 | /* |
3915 | * According to DP spec | |
3916 | * 5.1.2: | |
3917 | * 1. Read DPCD | |
3918 | * 2. Configure link according to Receiver Capabilities | |
3919 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
3920 | * 4. Check link status on receipt of hot-plug interrupt | |
39ff747b SS |
3921 | * |
3922 | * intel_dp_short_pulse - handles short pulse interrupts | |
3923 | * when full detection is not required. | |
3924 | * Returns %true if short pulse is handled and full detection | |
3925 | * is NOT required and %false otherwise. | |
a4fc5ed6 | 3926 | */ |
39ff747b | 3927 | static bool |
5c9114d0 | 3928 | intel_dp_short_pulse(struct intel_dp *intel_dp) |
a4fc5ed6 | 3929 | { |
5b215bcf | 3930 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
65fbb4e7 | 3931 | u8 sink_irq_vector = 0; |
39ff747b SS |
3932 | u8 old_sink_count = intel_dp->sink_count; |
3933 | bool ret; | |
5b215bcf | 3934 | |
4df6960e SS |
3935 | /* |
3936 | * Clearing compliance test variables to allow capturing | |
3937 | * of values for next automated test request. | |
3938 | */ | |
3939 | intel_dp->compliance_test_active = 0; | |
3940 | intel_dp->compliance_test_type = 0; | |
3941 | intel_dp->compliance_test_data = 0; | |
3942 | ||
39ff747b SS |
3943 | /* |
3944 | * Now read the DPCD to see if it's actually running | |
3945 | * If the current value of sink count doesn't match with | |
3946 | * the value that was stored earlier or dpcd read failed | |
3947 | * we need to do full detection | |
3948 | */ | |
3949 | ret = intel_dp_get_dpcd(intel_dp); | |
3950 | ||
3951 | if ((old_sink_count != intel_dp->sink_count) || !ret) { | |
3952 | /* No need to proceed if we are going to do full detect */ | |
3953 | return false; | |
59cd09e1 JB |
3954 | } |
3955 | ||
a60f0e38 JB |
3956 | /* Try to read the source of the interrupt */ |
3957 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
65fbb4e7 VS |
3958 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) && |
3959 | sink_irq_vector != 0) { | |
a60f0e38 | 3960 | /* Clear interrupt source */ |
9d1a1031 JN |
3961 | drm_dp_dpcd_writeb(&intel_dp->aux, |
3962 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
3963 | sink_irq_vector); | |
a60f0e38 JB |
3964 | |
3965 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
09b1eb13 | 3966 | DRM_DEBUG_DRIVER("Test request in short pulse not handled\n"); |
a60f0e38 JB |
3967 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
3968 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
3969 | } | |
3970 | ||
5c9114d0 SS |
3971 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
3972 | intel_dp_check_link_status(intel_dp); | |
3973 | drm_modeset_unlock(&dev->mode_config.connection_mutex); | |
39ff747b SS |
3974 | |
3975 | return true; | |
a4fc5ed6 | 3976 | } |
a4fc5ed6 | 3977 | |
caf9ab24 | 3978 | /* XXX this is probably wrong for multiple downstream ports */ |
71ba9000 | 3979 | static enum drm_connector_status |
26d61aad | 3980 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
71ba9000 | 3981 | { |
caf9ab24 | 3982 | uint8_t *dpcd = intel_dp->dpcd; |
caf9ab24 AJ |
3983 | uint8_t type; |
3984 | ||
3985 | if (!intel_dp_get_dpcd(intel_dp)) | |
3986 | return connector_status_disconnected; | |
3987 | ||
1034ce70 SS |
3988 | if (is_edp(intel_dp)) |
3989 | return connector_status_connected; | |
3990 | ||
caf9ab24 AJ |
3991 | /* if there's no downstream port, we're done */ |
3992 | if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) | |
26d61aad | 3993 | return connector_status_connected; |
caf9ab24 AJ |
3994 | |
3995 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ | |
c9ff160b JN |
3996 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
3997 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { | |
9d1a1031 | 3998 | |
30d9aa42 SS |
3999 | return intel_dp->sink_count ? |
4000 | connector_status_connected : connector_status_disconnected; | |
caf9ab24 AJ |
4001 | } |
4002 | ||
c4e3170a VS |
4003 | if (intel_dp_can_mst(intel_dp)) |
4004 | return connector_status_connected; | |
4005 | ||
caf9ab24 | 4006 | /* If no HPD, poke DDC gently */ |
0b99836f | 4007 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
26d61aad | 4008 | return connector_status_connected; |
caf9ab24 AJ |
4009 | |
4010 | /* Well we tried, say unknown for unreliable port types */ | |
c9ff160b JN |
4011 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
4012 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; | |
4013 | if (type == DP_DS_PORT_TYPE_VGA || | |
4014 | type == DP_DS_PORT_TYPE_NON_EDID) | |
4015 | return connector_status_unknown; | |
4016 | } else { | |
4017 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & | |
4018 | DP_DWN_STRM_PORT_TYPE_MASK; | |
4019 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || | |
4020 | type == DP_DWN_STRM_PORT_TYPE_OTHER) | |
4021 | return connector_status_unknown; | |
4022 | } | |
caf9ab24 AJ |
4023 | |
4024 | /* Anything else is out of spec, warn and ignore */ | |
4025 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); | |
26d61aad | 4026 | return connector_status_disconnected; |
71ba9000 AJ |
4027 | } |
4028 | ||
d410b56d CW |
4029 | static enum drm_connector_status |
4030 | edp_detect(struct intel_dp *intel_dp) | |
4031 | { | |
4032 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
4033 | enum drm_connector_status status; | |
4034 | ||
4035 | status = intel_panel_detect(dev); | |
4036 | if (status == connector_status_unknown) | |
4037 | status = connector_status_connected; | |
4038 | ||
4039 | return status; | |
4040 | } | |
4041 | ||
b93433cc JN |
4042 | static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
4043 | struct intel_digital_port *port) | |
5eb08b69 | 4044 | { |
b93433cc | 4045 | u32 bit; |
01cb9ea6 | 4046 | |
0df53b77 JN |
4047 | switch (port->port) { |
4048 | case PORT_A: | |
4049 | return true; | |
4050 | case PORT_B: | |
4051 | bit = SDE_PORTB_HOTPLUG; | |
4052 | break; | |
4053 | case PORT_C: | |
4054 | bit = SDE_PORTC_HOTPLUG; | |
4055 | break; | |
4056 | case PORT_D: | |
4057 | bit = SDE_PORTD_HOTPLUG; | |
4058 | break; | |
4059 | default: | |
4060 | MISSING_CASE(port->port); | |
4061 | return false; | |
4062 | } | |
4063 | ||
4064 | return I915_READ(SDEISR) & bit; | |
4065 | } | |
4066 | ||
4067 | static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv, | |
4068 | struct intel_digital_port *port) | |
4069 | { | |
4070 | u32 bit; | |
4071 | ||
4072 | switch (port->port) { | |
4073 | case PORT_A: | |
4074 | return true; | |
4075 | case PORT_B: | |
4076 | bit = SDE_PORTB_HOTPLUG_CPT; | |
4077 | break; | |
4078 | case PORT_C: | |
4079 | bit = SDE_PORTC_HOTPLUG_CPT; | |
4080 | break; | |
4081 | case PORT_D: | |
4082 | bit = SDE_PORTD_HOTPLUG_CPT; | |
4083 | break; | |
a78695d3 JN |
4084 | case PORT_E: |
4085 | bit = SDE_PORTE_HOTPLUG_SPT; | |
4086 | break; | |
0df53b77 JN |
4087 | default: |
4088 | MISSING_CASE(port->port); | |
4089 | return false; | |
b93433cc | 4090 | } |
1b469639 | 4091 | |
b93433cc | 4092 | return I915_READ(SDEISR) & bit; |
5eb08b69 ZW |
4093 | } |
4094 | ||
7e66bcf2 | 4095 | static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv, |
1d245987 | 4096 | struct intel_digital_port *port) |
a4fc5ed6 | 4097 | { |
9642c81c | 4098 | u32 bit; |
5eb08b69 | 4099 | |
9642c81c JN |
4100 | switch (port->port) { |
4101 | case PORT_B: | |
4102 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; | |
4103 | break; | |
4104 | case PORT_C: | |
4105 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; | |
4106 | break; | |
4107 | case PORT_D: | |
4108 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; | |
4109 | break; | |
4110 | default: | |
4111 | MISSING_CASE(port->port); | |
4112 | return false; | |
4113 | } | |
4114 | ||
4115 | return I915_READ(PORT_HOTPLUG_STAT) & bit; | |
4116 | } | |
4117 | ||
0780cd36 VS |
4118 | static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv, |
4119 | struct intel_digital_port *port) | |
9642c81c JN |
4120 | { |
4121 | u32 bit; | |
4122 | ||
4123 | switch (port->port) { | |
4124 | case PORT_B: | |
0780cd36 | 4125 | bit = PORTB_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
4126 | break; |
4127 | case PORT_C: | |
0780cd36 | 4128 | bit = PORTC_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
4129 | break; |
4130 | case PORT_D: | |
0780cd36 | 4131 | bit = PORTD_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
4132 | break; |
4133 | default: | |
4134 | MISSING_CASE(port->port); | |
4135 | return false; | |
a4fc5ed6 KP |
4136 | } |
4137 | ||
1d245987 | 4138 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
2a592bec DA |
4139 | } |
4140 | ||
e464bfde | 4141 | static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv, |
e2ec35a5 | 4142 | struct intel_digital_port *intel_dig_port) |
e464bfde | 4143 | { |
e2ec35a5 SJ |
4144 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4145 | enum port port; | |
e464bfde JN |
4146 | u32 bit; |
4147 | ||
e2ec35a5 SJ |
4148 | intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port); |
4149 | switch (port) { | |
e464bfde JN |
4150 | case PORT_A: |
4151 | bit = BXT_DE_PORT_HP_DDIA; | |
4152 | break; | |
4153 | case PORT_B: | |
4154 | bit = BXT_DE_PORT_HP_DDIB; | |
4155 | break; | |
4156 | case PORT_C: | |
4157 | bit = BXT_DE_PORT_HP_DDIC; | |
4158 | break; | |
4159 | default: | |
e2ec35a5 | 4160 | MISSING_CASE(port); |
e464bfde JN |
4161 | return false; |
4162 | } | |
4163 | ||
4164 | return I915_READ(GEN8_DE_PORT_ISR) & bit; | |
4165 | } | |
4166 | ||
7e66bcf2 JN |
4167 | /* |
4168 | * intel_digital_port_connected - is the specified port connected? | |
4169 | * @dev_priv: i915 private structure | |
4170 | * @port: the port to test | |
4171 | * | |
4172 | * Return %true if @port is connected, %false otherwise. | |
4173 | */ | |
237ed86c | 4174 | bool intel_digital_port_connected(struct drm_i915_private *dev_priv, |
7e66bcf2 JN |
4175 | struct intel_digital_port *port) |
4176 | { | |
0df53b77 | 4177 | if (HAS_PCH_IBX(dev_priv)) |
7e66bcf2 | 4178 | return ibx_digital_port_connected(dev_priv, port); |
22824fac | 4179 | else if (HAS_PCH_SPLIT(dev_priv)) |
0df53b77 | 4180 | return cpt_digital_port_connected(dev_priv, port); |
e464bfde JN |
4181 | else if (IS_BROXTON(dev_priv)) |
4182 | return bxt_digital_port_connected(dev_priv, port); | |
0780cd36 VS |
4183 | else if (IS_GM45(dev_priv)) |
4184 | return gm45_digital_port_connected(dev_priv, port); | |
7e66bcf2 JN |
4185 | else |
4186 | return g4x_digital_port_connected(dev_priv, port); | |
4187 | } | |
4188 | ||
8c241fef | 4189 | static struct edid * |
beb60608 | 4190 | intel_dp_get_edid(struct intel_dp *intel_dp) |
8c241fef | 4191 | { |
beb60608 | 4192 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
d6f24d0f | 4193 | |
9cd300e0 JN |
4194 | /* use cached edid if we have one */ |
4195 | if (intel_connector->edid) { | |
9cd300e0 JN |
4196 | /* invalid edid */ |
4197 | if (IS_ERR(intel_connector->edid)) | |
d6f24d0f JB |
4198 | return NULL; |
4199 | ||
55e9edeb | 4200 | return drm_edid_duplicate(intel_connector->edid); |
beb60608 CW |
4201 | } else |
4202 | return drm_get_edid(&intel_connector->base, | |
4203 | &intel_dp->aux.ddc); | |
4204 | } | |
8c241fef | 4205 | |
beb60608 CW |
4206 | static void |
4207 | intel_dp_set_edid(struct intel_dp *intel_dp) | |
4208 | { | |
4209 | struct intel_connector *intel_connector = intel_dp->attached_connector; | |
4210 | struct edid *edid; | |
8c241fef | 4211 | |
f21a2198 | 4212 | intel_dp_unset_edid(intel_dp); |
beb60608 CW |
4213 | edid = intel_dp_get_edid(intel_dp); |
4214 | intel_connector->detect_edid = edid; | |
4215 | ||
4216 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) | |
4217 | intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON; | |
4218 | else | |
4219 | intel_dp->has_audio = drm_detect_monitor_audio(edid); | |
8c241fef KP |
4220 | } |
4221 | ||
beb60608 CW |
4222 | static void |
4223 | intel_dp_unset_edid(struct intel_dp *intel_dp) | |
8c241fef | 4224 | { |
beb60608 | 4225 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
8c241fef | 4226 | |
beb60608 CW |
4227 | kfree(intel_connector->detect_edid); |
4228 | intel_connector->detect_edid = NULL; | |
9cd300e0 | 4229 | |
beb60608 CW |
4230 | intel_dp->has_audio = false; |
4231 | } | |
d6f24d0f | 4232 | |
f21a2198 SS |
4233 | static void |
4234 | intel_dp_long_pulse(struct intel_connector *intel_connector) | |
a9756bb5 | 4235 | { |
f21a2198 | 4236 | struct drm_connector *connector = &intel_connector->base; |
a9756bb5 | 4237 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
d63885da PZ |
4238 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4239 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
fa90ecef | 4240 | struct drm_device *dev = connector->dev; |
a9756bb5 | 4241 | enum drm_connector_status status; |
671dedd2 | 4242 | enum intel_display_power_domain power_domain; |
65fbb4e7 | 4243 | u8 sink_irq_vector = 0; |
a9756bb5 | 4244 | |
25f78f58 VS |
4245 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4246 | intel_display_power_get(to_i915(dev), power_domain); | |
a9756bb5 | 4247 | |
d410b56d CW |
4248 | /* Can't disconnect eDP, but you can close the lid... */ |
4249 | if (is_edp(intel_dp)) | |
4250 | status = edp_detect(intel_dp); | |
c555a81d ACO |
4251 | else if (intel_digital_port_connected(to_i915(dev), |
4252 | dp_to_dig_port(intel_dp))) | |
4253 | status = intel_dp_detect_dpcd(intel_dp); | |
a9756bb5 | 4254 | else |
c555a81d ACO |
4255 | status = connector_status_disconnected; |
4256 | ||
4df6960e SS |
4257 | if (status != connector_status_connected) { |
4258 | intel_dp->compliance_test_active = 0; | |
4259 | intel_dp->compliance_test_type = 0; | |
4260 | intel_dp->compliance_test_data = 0; | |
4261 | ||
0e505a08 | 4262 | if (intel_dp->is_mst) { |
4263 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", | |
4264 | intel_dp->is_mst, | |
4265 | intel_dp->mst_mgr.mst_state); | |
4266 | intel_dp->is_mst = false; | |
4267 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
4268 | intel_dp->is_mst); | |
4269 | } | |
4270 | ||
c8c8fb33 | 4271 | goto out; |
4df6960e | 4272 | } |
a9756bb5 | 4273 | |
f21a2198 | 4274 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
cca0502b | 4275 | intel_encoder->type = INTEL_OUTPUT_DP; |
f21a2198 | 4276 | |
fe5a66f9 VS |
4277 | DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n", |
4278 | yesno(intel_dp_source_supports_hbr2(intel_dp)), | |
4279 | yesno(drm_dp_tps3_supported(intel_dp->dpcd))); | |
4280 | ||
4281 | intel_dp_print_rates(intel_dp); | |
4282 | ||
0d198328 AJ |
4283 | intel_dp_probe_oui(intel_dp); |
4284 | ||
c4e3170a VS |
4285 | intel_dp_configure_mst(intel_dp); |
4286 | ||
4287 | if (intel_dp->is_mst) { | |
f21a2198 SS |
4288 | /* |
4289 | * If we are in MST mode then this connector | |
4290 | * won't appear connected or have anything | |
4291 | * with EDID on it | |
4292 | */ | |
0e32b39c DA |
4293 | status = connector_status_disconnected; |
4294 | goto out; | |
7d23e3c3 SS |
4295 | } else if (connector->status == connector_status_connected) { |
4296 | /* | |
4297 | * If display was connected already and is still connected | |
4298 | * check links status, there has been known issues of | |
4299 | * link loss triggerring long pulse!!!! | |
4300 | */ | |
4301 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); | |
4302 | intel_dp_check_link_status(intel_dp); | |
4303 | drm_modeset_unlock(&dev->mode_config.connection_mutex); | |
4304 | goto out; | |
0e32b39c DA |
4305 | } |
4306 | ||
4df6960e SS |
4307 | /* |
4308 | * Clearing NACK and defer counts to get their exact values | |
4309 | * while reading EDID which are required by Compliance tests | |
4310 | * 4.2.2.4 and 4.2.2.5 | |
4311 | */ | |
4312 | intel_dp->aux.i2c_nack_count = 0; | |
4313 | intel_dp->aux.i2c_defer_count = 0; | |
4314 | ||
beb60608 | 4315 | intel_dp_set_edid(intel_dp); |
a9756bb5 | 4316 | |
c8c8fb33 | 4317 | status = connector_status_connected; |
7d23e3c3 | 4318 | intel_dp->detect_done = true; |
c8c8fb33 | 4319 | |
09b1eb13 TP |
4320 | /* Try to read the source of the interrupt */ |
4321 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
65fbb4e7 VS |
4322 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) && |
4323 | sink_irq_vector != 0) { | |
09b1eb13 TP |
4324 | /* Clear interrupt source */ |
4325 | drm_dp_dpcd_writeb(&intel_dp->aux, | |
4326 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
4327 | sink_irq_vector); | |
4328 | ||
4329 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
4330 | intel_dp_handle_test_request(intel_dp); | |
4331 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) | |
4332 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
4333 | } | |
4334 | ||
c8c8fb33 | 4335 | out: |
0e505a08 | 4336 | if ((status != connector_status_connected) && |
4337 | (intel_dp->is_mst == false)) | |
f21a2198 | 4338 | intel_dp_unset_edid(intel_dp); |
7d23e3c3 | 4339 | |
25f78f58 | 4340 | intel_display_power_put(to_i915(dev), power_domain); |
f21a2198 SS |
4341 | return; |
4342 | } | |
4343 | ||
4344 | static enum drm_connector_status | |
4345 | intel_dp_detect(struct drm_connector *connector, bool force) | |
4346 | { | |
4347 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
4348 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
4349 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
4350 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4351 | ||
4352 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
4353 | connector->base.id, connector->name); | |
4354 | ||
4355 | if (intel_dp->is_mst) { | |
4356 | /* MST devices are disconnected from a monitor POV */ | |
4357 | intel_dp_unset_edid(intel_dp); | |
4358 | if (intel_encoder->type != INTEL_OUTPUT_EDP) | |
cca0502b | 4359 | intel_encoder->type = INTEL_OUTPUT_DP; |
f21a2198 SS |
4360 | return connector_status_disconnected; |
4361 | } | |
4362 | ||
7d23e3c3 SS |
4363 | /* If full detect is not performed yet, do a full detect */ |
4364 | if (!intel_dp->detect_done) | |
4365 | intel_dp_long_pulse(intel_dp->attached_connector); | |
4366 | ||
4367 | intel_dp->detect_done = false; | |
f21a2198 | 4368 | |
1b7f2c8b | 4369 | if (is_edp(intel_dp) || intel_connector->detect_edid) |
f21a2198 SS |
4370 | return connector_status_connected; |
4371 | else | |
4372 | return connector_status_disconnected; | |
a4fc5ed6 KP |
4373 | } |
4374 | ||
beb60608 CW |
4375 | static void |
4376 | intel_dp_force(struct drm_connector *connector) | |
a4fc5ed6 | 4377 | { |
df0e9248 | 4378 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
beb60608 | 4379 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
25f78f58 | 4380 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
671dedd2 | 4381 | enum intel_display_power_domain power_domain; |
a4fc5ed6 | 4382 | |
beb60608 CW |
4383 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
4384 | connector->base.id, connector->name); | |
4385 | intel_dp_unset_edid(intel_dp); | |
a4fc5ed6 | 4386 | |
beb60608 CW |
4387 | if (connector->status != connector_status_connected) |
4388 | return; | |
671dedd2 | 4389 | |
25f78f58 VS |
4390 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4391 | intel_display_power_get(dev_priv, power_domain); | |
beb60608 CW |
4392 | |
4393 | intel_dp_set_edid(intel_dp); | |
4394 | ||
25f78f58 | 4395 | intel_display_power_put(dev_priv, power_domain); |
beb60608 CW |
4396 | |
4397 | if (intel_encoder->type != INTEL_OUTPUT_EDP) | |
cca0502b | 4398 | intel_encoder->type = INTEL_OUTPUT_DP; |
beb60608 CW |
4399 | } |
4400 | ||
4401 | static int intel_dp_get_modes(struct drm_connector *connector) | |
4402 | { | |
4403 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4404 | struct edid *edid; | |
4405 | ||
4406 | edid = intel_connector->detect_edid; | |
4407 | if (edid) { | |
4408 | int ret = intel_connector_update_modes(connector, edid); | |
4409 | if (ret) | |
4410 | return ret; | |
4411 | } | |
32f9d658 | 4412 | |
f8779fda | 4413 | /* if eDP has no EDID, fall back to fixed mode */ |
beb60608 CW |
4414 | if (is_edp(intel_attached_dp(connector)) && |
4415 | intel_connector->panel.fixed_mode) { | |
f8779fda | 4416 | struct drm_display_mode *mode; |
beb60608 CW |
4417 | |
4418 | mode = drm_mode_duplicate(connector->dev, | |
dd06f90e | 4419 | intel_connector->panel.fixed_mode); |
f8779fda | 4420 | if (mode) { |
32f9d658 ZW |
4421 | drm_mode_probed_add(connector, mode); |
4422 | return 1; | |
4423 | } | |
4424 | } | |
beb60608 | 4425 | |
32f9d658 | 4426 | return 0; |
a4fc5ed6 KP |
4427 | } |
4428 | ||
1aad7ac0 CW |
4429 | static bool |
4430 | intel_dp_detect_audio(struct drm_connector *connector) | |
4431 | { | |
1aad7ac0 | 4432 | bool has_audio = false; |
beb60608 | 4433 | struct edid *edid; |
1aad7ac0 | 4434 | |
beb60608 CW |
4435 | edid = to_intel_connector(connector)->detect_edid; |
4436 | if (edid) | |
1aad7ac0 | 4437 | has_audio = drm_detect_monitor_audio(edid); |
671dedd2 | 4438 | |
1aad7ac0 CW |
4439 | return has_audio; |
4440 | } | |
4441 | ||
f684960e CW |
4442 | static int |
4443 | intel_dp_set_property(struct drm_connector *connector, | |
4444 | struct drm_property *property, | |
4445 | uint64_t val) | |
4446 | { | |
fac5e23e | 4447 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
53b41837 | 4448 | struct intel_connector *intel_connector = to_intel_connector(connector); |
da63a9f2 PZ |
4449 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
4450 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
f684960e CW |
4451 | int ret; |
4452 | ||
662595df | 4453 | ret = drm_object_property_set_value(&connector->base, property, val); |
f684960e CW |
4454 | if (ret) |
4455 | return ret; | |
4456 | ||
3f43c48d | 4457 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
4458 | int i = val; |
4459 | bool has_audio; | |
4460 | ||
4461 | if (i == intel_dp->force_audio) | |
f684960e CW |
4462 | return 0; |
4463 | ||
1aad7ac0 | 4464 | intel_dp->force_audio = i; |
f684960e | 4465 | |
c3e5f67b | 4466 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
4467 | has_audio = intel_dp_detect_audio(connector); |
4468 | else | |
c3e5f67b | 4469 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 CW |
4470 | |
4471 | if (has_audio == intel_dp->has_audio) | |
f684960e CW |
4472 | return 0; |
4473 | ||
1aad7ac0 | 4474 | intel_dp->has_audio = has_audio; |
f684960e CW |
4475 | goto done; |
4476 | } | |
4477 | ||
e953fd7b | 4478 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 | 4479 | bool old_auto = intel_dp->color_range_auto; |
0f2a2a75 | 4480 | bool old_range = intel_dp->limited_color_range; |
ae4edb80 | 4481 | |
55bc60db VS |
4482 | switch (val) { |
4483 | case INTEL_BROADCAST_RGB_AUTO: | |
4484 | intel_dp->color_range_auto = true; | |
4485 | break; | |
4486 | case INTEL_BROADCAST_RGB_FULL: | |
4487 | intel_dp->color_range_auto = false; | |
0f2a2a75 | 4488 | intel_dp->limited_color_range = false; |
55bc60db VS |
4489 | break; |
4490 | case INTEL_BROADCAST_RGB_LIMITED: | |
4491 | intel_dp->color_range_auto = false; | |
0f2a2a75 | 4492 | intel_dp->limited_color_range = true; |
55bc60db VS |
4493 | break; |
4494 | default: | |
4495 | return -EINVAL; | |
4496 | } | |
ae4edb80 DV |
4497 | |
4498 | if (old_auto == intel_dp->color_range_auto && | |
0f2a2a75 | 4499 | old_range == intel_dp->limited_color_range) |
ae4edb80 DV |
4500 | return 0; |
4501 | ||
e953fd7b CW |
4502 | goto done; |
4503 | } | |
4504 | ||
53b41837 YN |
4505 | if (is_edp(intel_dp) && |
4506 | property == connector->dev->mode_config.scaling_mode_property) { | |
4507 | if (val == DRM_MODE_SCALE_NONE) { | |
4508 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
4509 | return -EINVAL; | |
4510 | } | |
234126c6 VS |
4511 | if (HAS_GMCH_DISPLAY(dev_priv) && |
4512 | val == DRM_MODE_SCALE_CENTER) { | |
4513 | DRM_DEBUG_KMS("centering not supported\n"); | |
4514 | return -EINVAL; | |
4515 | } | |
53b41837 YN |
4516 | |
4517 | if (intel_connector->panel.fitting_mode == val) { | |
4518 | /* the eDP scaling property is not changed */ | |
4519 | return 0; | |
4520 | } | |
4521 | intel_connector->panel.fitting_mode = val; | |
4522 | ||
4523 | goto done; | |
4524 | } | |
4525 | ||
f684960e CW |
4526 | return -EINVAL; |
4527 | ||
4528 | done: | |
c0c36b94 CW |
4529 | if (intel_encoder->base.crtc) |
4530 | intel_crtc_restore_mode(intel_encoder->base.crtc); | |
f684960e CW |
4531 | |
4532 | return 0; | |
4533 | } | |
4534 | ||
7a418e34 CW |
4535 | static int |
4536 | intel_dp_connector_register(struct drm_connector *connector) | |
4537 | { | |
4538 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1ebaa0b9 CW |
4539 | int ret; |
4540 | ||
4541 | ret = intel_connector_register(connector); | |
4542 | if (ret) | |
4543 | return ret; | |
7a418e34 CW |
4544 | |
4545 | i915_debugfs_connector_add(connector); | |
4546 | ||
4547 | DRM_DEBUG_KMS("registering %s bus for %s\n", | |
4548 | intel_dp->aux.name, connector->kdev->kobj.name); | |
4549 | ||
4550 | intel_dp->aux.dev = connector->kdev; | |
4551 | return drm_dp_aux_register(&intel_dp->aux); | |
4552 | } | |
4553 | ||
c191eca1 CW |
4554 | static void |
4555 | intel_dp_connector_unregister(struct drm_connector *connector) | |
4556 | { | |
4557 | drm_dp_aux_unregister(&intel_attached_dp(connector)->aux); | |
4558 | intel_connector_unregister(connector); | |
4559 | } | |
4560 | ||
a4fc5ed6 | 4561 | static void |
73845adf | 4562 | intel_dp_connector_destroy(struct drm_connector *connector) |
a4fc5ed6 | 4563 | { |
1d508706 | 4564 | struct intel_connector *intel_connector = to_intel_connector(connector); |
aaa6fd2a | 4565 | |
10e972d3 | 4566 | kfree(intel_connector->detect_edid); |
beb60608 | 4567 | |
9cd300e0 JN |
4568 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
4569 | kfree(intel_connector->edid); | |
4570 | ||
acd8db10 PZ |
4571 | /* Can't call is_edp() since the encoder may have been destroyed |
4572 | * already. */ | |
4573 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
1d508706 | 4574 | intel_panel_fini(&intel_connector->panel); |
aaa6fd2a | 4575 | |
a4fc5ed6 | 4576 | drm_connector_cleanup(connector); |
55f78c43 | 4577 | kfree(connector); |
a4fc5ed6 KP |
4578 | } |
4579 | ||
00c09d70 | 4580 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
24d05927 | 4581 | { |
da63a9f2 PZ |
4582 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
4583 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
24d05927 | 4584 | |
0e32b39c | 4585 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
bd943159 KP |
4586 | if (is_edp(intel_dp)) { |
4587 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
951468f3 VS |
4588 | /* |
4589 | * vdd might still be enabled do to the delayed vdd off. | |
4590 | * Make sure vdd is actually turned off here. | |
4591 | */ | |
773538e8 | 4592 | pps_lock(intel_dp); |
4be73780 | 4593 | edp_panel_vdd_off_sync(intel_dp); |
773538e8 VS |
4594 | pps_unlock(intel_dp); |
4595 | ||
01527b31 CT |
4596 | if (intel_dp->edp_notifier.notifier_call) { |
4597 | unregister_reboot_notifier(&intel_dp->edp_notifier); | |
4598 | intel_dp->edp_notifier.notifier_call = NULL; | |
4599 | } | |
bd943159 | 4600 | } |
99681886 CW |
4601 | |
4602 | intel_dp_aux_fini(intel_dp); | |
4603 | ||
c8bd0e49 | 4604 | drm_encoder_cleanup(encoder); |
da63a9f2 | 4605 | kfree(intel_dig_port); |
24d05927 DV |
4606 | } |
4607 | ||
bf93ba67 | 4608 | void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) |
07f9cd0b ID |
4609 | { |
4610 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
4611 | ||
4612 | if (!is_edp(intel_dp)) | |
4613 | return; | |
4614 | ||
951468f3 VS |
4615 | /* |
4616 | * vdd might still be enabled do to the delayed vdd off. | |
4617 | * Make sure vdd is actually turned off here. | |
4618 | */ | |
afa4e53a | 4619 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
773538e8 | 4620 | pps_lock(intel_dp); |
07f9cd0b | 4621 | edp_panel_vdd_off_sync(intel_dp); |
773538e8 | 4622 | pps_unlock(intel_dp); |
07f9cd0b ID |
4623 | } |
4624 | ||
49e6bc51 VS |
4625 | static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) |
4626 | { | |
4627 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
4628 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 4629 | struct drm_i915_private *dev_priv = to_i915(dev); |
49e6bc51 VS |
4630 | enum intel_display_power_domain power_domain; |
4631 | ||
4632 | lockdep_assert_held(&dev_priv->pps_mutex); | |
4633 | ||
4634 | if (!edp_have_panel_vdd(intel_dp)) | |
4635 | return; | |
4636 | ||
4637 | /* | |
4638 | * The VDD bit needs a power domain reference, so if the bit is | |
4639 | * already enabled when we boot or resume, grab this reference and | |
4640 | * schedule a vdd off, so we don't hold on to the reference | |
4641 | * indefinitely. | |
4642 | */ | |
4643 | DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); | |
25f78f58 | 4644 | power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base); |
49e6bc51 VS |
4645 | intel_display_power_get(dev_priv, power_domain); |
4646 | ||
4647 | edp_panel_vdd_schedule_off(intel_dp); | |
4648 | } | |
4649 | ||
bf93ba67 | 4650 | void intel_dp_encoder_reset(struct drm_encoder *encoder) |
6d93c0c4 | 4651 | { |
64989ca4 VS |
4652 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
4653 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
4654 | ||
4655 | if (!HAS_DDI(dev_priv)) | |
4656 | intel_dp->DP = I915_READ(intel_dp->output_reg); | |
49e6bc51 VS |
4657 | |
4658 | if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP) | |
4659 | return; | |
4660 | ||
49e6bc51 VS |
4661 | pps_lock(intel_dp); |
4662 | ||
335f752b ID |
4663 | /* Reinit the power sequencer, in case BIOS did something with it. */ |
4664 | intel_dp_pps_init(encoder->dev, intel_dp); | |
49e6bc51 VS |
4665 | intel_edp_panel_vdd_sanitize(intel_dp); |
4666 | ||
4667 | pps_unlock(intel_dp); | |
6d93c0c4 ID |
4668 | } |
4669 | ||
a4fc5ed6 | 4670 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
4d688a2a | 4671 | .dpms = drm_atomic_helper_connector_dpms, |
a4fc5ed6 | 4672 | .detect = intel_dp_detect, |
beb60608 | 4673 | .force = intel_dp_force, |
a4fc5ed6 | 4674 | .fill_modes = drm_helper_probe_single_connector_modes, |
f684960e | 4675 | .set_property = intel_dp_set_property, |
2545e4a6 | 4676 | .atomic_get_property = intel_connector_atomic_get_property, |
7a418e34 | 4677 | .late_register = intel_dp_connector_register, |
c191eca1 | 4678 | .early_unregister = intel_dp_connector_unregister, |
73845adf | 4679 | .destroy = intel_dp_connector_destroy, |
c6f95f27 | 4680 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 4681 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
a4fc5ed6 KP |
4682 | }; |
4683 | ||
4684 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
4685 | .get_modes = intel_dp_get_modes, | |
4686 | .mode_valid = intel_dp_mode_valid, | |
a4fc5ed6 KP |
4687 | }; |
4688 | ||
a4fc5ed6 | 4689 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
6d93c0c4 | 4690 | .reset = intel_dp_encoder_reset, |
24d05927 | 4691 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
4692 | }; |
4693 | ||
b2c5c181 | 4694 | enum irqreturn |
13cf5504 DA |
4695 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) |
4696 | { | |
4697 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
1c767b33 | 4698 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
0e32b39c | 4699 | struct drm_device *dev = intel_dig_port->base.base.dev; |
fac5e23e | 4700 | struct drm_i915_private *dev_priv = to_i915(dev); |
1c767b33 | 4701 | enum intel_display_power_domain power_domain; |
b2c5c181 | 4702 | enum irqreturn ret = IRQ_NONE; |
1c767b33 | 4703 | |
2540058f TI |
4704 | if (intel_dig_port->base.type != INTEL_OUTPUT_EDP && |
4705 | intel_dig_port->base.type != INTEL_OUTPUT_HDMI) | |
cca0502b | 4706 | intel_dig_port->base.type = INTEL_OUTPUT_DP; |
13cf5504 | 4707 | |
7a7f84cc VS |
4708 | if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) { |
4709 | /* | |
4710 | * vdd off can generate a long pulse on eDP which | |
4711 | * would require vdd on to handle it, and thus we | |
4712 | * would end up in an endless cycle of | |
4713 | * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..." | |
4714 | */ | |
4715 | DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n", | |
4716 | port_name(intel_dig_port->port)); | |
a8b3d52f | 4717 | return IRQ_HANDLED; |
7a7f84cc VS |
4718 | } |
4719 | ||
26fbb774 VS |
4720 | DRM_DEBUG_KMS("got hpd irq on port %c - %s\n", |
4721 | port_name(intel_dig_port->port), | |
0e32b39c | 4722 | long_hpd ? "long" : "short"); |
13cf5504 | 4723 | |
25f78f58 | 4724 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
1c767b33 ID |
4725 | intel_display_power_get(dev_priv, power_domain); |
4726 | ||
0e32b39c | 4727 | if (long_hpd) { |
7d23e3c3 SS |
4728 | intel_dp_long_pulse(intel_dp->attached_connector); |
4729 | if (intel_dp->is_mst) | |
4730 | ret = IRQ_HANDLED; | |
4731 | goto put_power; | |
0e32b39c | 4732 | |
0e32b39c DA |
4733 | } else { |
4734 | if (intel_dp->is_mst) { | |
7d23e3c3 SS |
4735 | if (intel_dp_check_mst_status(intel_dp) == -EINVAL) { |
4736 | /* | |
4737 | * If we were in MST mode, and device is not | |
4738 | * there, get out of MST mode | |
4739 | */ | |
4740 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", | |
4741 | intel_dp->is_mst, intel_dp->mst_mgr.mst_state); | |
4742 | intel_dp->is_mst = false; | |
4743 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
4744 | intel_dp->is_mst); | |
4745 | goto put_power; | |
4746 | } | |
0e32b39c DA |
4747 | } |
4748 | ||
39ff747b SS |
4749 | if (!intel_dp->is_mst) { |
4750 | if (!intel_dp_short_pulse(intel_dp)) { | |
4751 | intel_dp_long_pulse(intel_dp->attached_connector); | |
4752 | goto put_power; | |
4753 | } | |
4754 | } | |
0e32b39c | 4755 | } |
b2c5c181 DV |
4756 | |
4757 | ret = IRQ_HANDLED; | |
4758 | ||
1c767b33 ID |
4759 | put_power: |
4760 | intel_display_power_put(dev_priv, power_domain); | |
4761 | ||
4762 | return ret; | |
13cf5504 DA |
4763 | } |
4764 | ||
477ec328 | 4765 | /* check the VBT to see whether the eDP is on another port */ |
5d8a7752 | 4766 | bool intel_dp_is_edp(struct drm_device *dev, enum port port) |
36e83a18 | 4767 | { |
fac5e23e | 4768 | struct drm_i915_private *dev_priv = to_i915(dev); |
36e83a18 | 4769 | |
53ce81a7 VS |
4770 | /* |
4771 | * eDP not supported on g4x. so bail out early just | |
4772 | * for a bit extra safety in case the VBT is bonkers. | |
4773 | */ | |
4774 | if (INTEL_INFO(dev)->gen < 5) | |
4775 | return false; | |
4776 | ||
3b32a35b VS |
4777 | if (port == PORT_A) |
4778 | return true; | |
4779 | ||
951d9efe | 4780 | return intel_bios_is_port_edp(dev_priv, port); |
36e83a18 ZY |
4781 | } |
4782 | ||
0e32b39c | 4783 | void |
f684960e CW |
4784 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
4785 | { | |
53b41837 YN |
4786 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4787 | ||
3f43c48d | 4788 | intel_attach_force_audio_property(connector); |
e953fd7b | 4789 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 4790 | intel_dp->color_range_auto = true; |
53b41837 YN |
4791 | |
4792 | if (is_edp(intel_dp)) { | |
4793 | drm_mode_create_scaling_mode_property(connector->dev); | |
6de6d846 RC |
4794 | drm_object_attach_property( |
4795 | &connector->base, | |
53b41837 | 4796 | connector->dev->mode_config.scaling_mode_property, |
8e740cd1 YN |
4797 | DRM_MODE_SCALE_ASPECT); |
4798 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; | |
53b41837 | 4799 | } |
f684960e CW |
4800 | } |
4801 | ||
dada1a9f ID |
4802 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
4803 | { | |
d28d4731 | 4804 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
dada1a9f ID |
4805 | intel_dp->last_power_on = jiffies; |
4806 | intel_dp->last_backlight_off = jiffies; | |
4807 | } | |
4808 | ||
67a54566 | 4809 | static void |
54648618 ID |
4810 | intel_pps_readout_hw_state(struct drm_i915_private *dev_priv, |
4811 | struct intel_dp *intel_dp, struct edp_power_seq *seq) | |
67a54566 | 4812 | { |
b0a08bec | 4813 | u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; |
8e8232d5 | 4814 | struct pps_registers regs; |
453c5420 | 4815 | |
8e8232d5 | 4816 | intel_pps_get_registers(dev_priv, intel_dp, ®s); |
67a54566 DV |
4817 | |
4818 | /* Workaround: Need to write PP_CONTROL with the unlock key as | |
4819 | * the very first thing. */ | |
b0a08bec | 4820 | pp_ctl = ironlake_get_pp_control(intel_dp); |
67a54566 | 4821 | |
8e8232d5 ID |
4822 | pp_on = I915_READ(regs.pp_on); |
4823 | pp_off = I915_READ(regs.pp_off); | |
54648618 | 4824 | if (!IS_BROXTON(dev_priv)) { |
8e8232d5 ID |
4825 | I915_WRITE(regs.pp_ctrl, pp_ctl); |
4826 | pp_div = I915_READ(regs.pp_div); | |
b0a08bec | 4827 | } |
67a54566 DV |
4828 | |
4829 | /* Pull timing values out of registers */ | |
54648618 ID |
4830 | seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> |
4831 | PANEL_POWER_UP_DELAY_SHIFT; | |
67a54566 | 4832 | |
54648618 ID |
4833 | seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> |
4834 | PANEL_LIGHT_ON_DELAY_SHIFT; | |
67a54566 | 4835 | |
54648618 ID |
4836 | seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
4837 | PANEL_LIGHT_OFF_DELAY_SHIFT; | |
67a54566 | 4838 | |
54648618 ID |
4839 | seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> |
4840 | PANEL_POWER_DOWN_DELAY_SHIFT; | |
67a54566 | 4841 | |
54648618 | 4842 | if (IS_BROXTON(dev_priv)) { |
b0a08bec VK |
4843 | u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> |
4844 | BXT_POWER_CYCLE_DELAY_SHIFT; | |
4845 | if (tmp > 0) | |
54648618 | 4846 | seq->t11_t12 = (tmp - 1) * 1000; |
b0a08bec | 4847 | else |
54648618 | 4848 | seq->t11_t12 = 0; |
b0a08bec | 4849 | } else { |
54648618 | 4850 | seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> |
67a54566 | 4851 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
b0a08bec | 4852 | } |
54648618 ID |
4853 | } |
4854 | ||
de9c1b6b ID |
4855 | static void |
4856 | intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq) | |
4857 | { | |
4858 | DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
4859 | state_name, | |
4860 | seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); | |
4861 | } | |
4862 | ||
4863 | static void | |
4864 | intel_pps_verify_state(struct drm_i915_private *dev_priv, | |
4865 | struct intel_dp *intel_dp) | |
4866 | { | |
4867 | struct edp_power_seq hw; | |
4868 | struct edp_power_seq *sw = &intel_dp->pps_delays; | |
4869 | ||
4870 | intel_pps_readout_hw_state(dev_priv, intel_dp, &hw); | |
4871 | ||
4872 | if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 || | |
4873 | hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) { | |
4874 | DRM_ERROR("PPS state mismatch\n"); | |
4875 | intel_pps_dump_state("sw", sw); | |
4876 | intel_pps_dump_state("hw", &hw); | |
4877 | } | |
4878 | } | |
4879 | ||
54648618 ID |
4880 | static void |
4881 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
4882 | struct intel_dp *intel_dp) | |
4883 | { | |
fac5e23e | 4884 | struct drm_i915_private *dev_priv = to_i915(dev); |
54648618 ID |
4885 | struct edp_power_seq cur, vbt, spec, |
4886 | *final = &intel_dp->pps_delays; | |
4887 | ||
4888 | lockdep_assert_held(&dev_priv->pps_mutex); | |
4889 | ||
4890 | /* already initialized? */ | |
4891 | if (final->t11_t12 != 0) | |
4892 | return; | |
4893 | ||
4894 | intel_pps_readout_hw_state(dev_priv, intel_dp, &cur); | |
67a54566 | 4895 | |
de9c1b6b | 4896 | intel_pps_dump_state("cur", &cur); |
67a54566 | 4897 | |
6aa23e65 | 4898 | vbt = dev_priv->vbt.edp.pps; |
67a54566 DV |
4899 | |
4900 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of | |
4901 | * our hw here, which are all in 100usec. */ | |
4902 | spec.t1_t3 = 210 * 10; | |
4903 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ | |
4904 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ | |
4905 | spec.t10 = 500 * 10; | |
4906 | /* This one is special and actually in units of 100ms, but zero | |
4907 | * based in the hw (so we need to add 100 ms). But the sw vbt | |
4908 | * table multiplies it with 1000 to make it in units of 100usec, | |
4909 | * too. */ | |
4910 | spec.t11_t12 = (510 + 100) * 10; | |
4911 | ||
de9c1b6b | 4912 | intel_pps_dump_state("vbt", &vbt); |
67a54566 DV |
4913 | |
4914 | /* Use the max of the register settings and vbt. If both are | |
4915 | * unset, fall back to the spec limits. */ | |
36b5f425 | 4916 | #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ |
67a54566 DV |
4917 | spec.field : \ |
4918 | max(cur.field, vbt.field)) | |
4919 | assign_final(t1_t3); | |
4920 | assign_final(t8); | |
4921 | assign_final(t9); | |
4922 | assign_final(t10); | |
4923 | assign_final(t11_t12); | |
4924 | #undef assign_final | |
4925 | ||
36b5f425 | 4926 | #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) |
67a54566 DV |
4927 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
4928 | intel_dp->backlight_on_delay = get_delay(t8); | |
4929 | intel_dp->backlight_off_delay = get_delay(t9); | |
4930 | intel_dp->panel_power_down_delay = get_delay(t10); | |
4931 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); | |
4932 | #undef get_delay | |
4933 | ||
f30d26e4 JN |
4934 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
4935 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, | |
4936 | intel_dp->panel_power_cycle_delay); | |
4937 | ||
4938 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", | |
4939 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); | |
de9c1b6b ID |
4940 | |
4941 | /* | |
4942 | * We override the HW backlight delays to 1 because we do manual waits | |
4943 | * on them. For T8, even BSpec recommends doing it. For T9, if we | |
4944 | * don't do this, we'll end up waiting for the backlight off delay | |
4945 | * twice: once when we do the manual sleep, and once when we disable | |
4946 | * the panel and wait for the PP_STATUS bit to become zero. | |
4947 | */ | |
4948 | final->t8 = 1; | |
4949 | final->t9 = 1; | |
f30d26e4 JN |
4950 | } |
4951 | ||
4952 | static void | |
4953 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
36b5f425 | 4954 | struct intel_dp *intel_dp) |
f30d26e4 | 4955 | { |
fac5e23e | 4956 | struct drm_i915_private *dev_priv = to_i915(dev); |
453c5420 | 4957 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
e7dc33f3 | 4958 | int div = dev_priv->rawclk_freq / 1000; |
8e8232d5 | 4959 | struct pps_registers regs; |
ad933b56 | 4960 | enum port port = dp_to_dig_port(intel_dp)->port; |
36b5f425 | 4961 | const struct edp_power_seq *seq = &intel_dp->pps_delays; |
453c5420 | 4962 | |
e39b999a | 4963 | lockdep_assert_held(&dev_priv->pps_mutex); |
453c5420 | 4964 | |
8e8232d5 | 4965 | intel_pps_get_registers(dev_priv, intel_dp, ®s); |
453c5420 | 4966 | |
f30d26e4 | 4967 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
de9c1b6b ID |
4968 | (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT); |
4969 | pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | | |
f30d26e4 | 4970 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
67a54566 DV |
4971 | /* Compute the divisor for the pp clock, simply match the Bspec |
4972 | * formula. */ | |
b0a08bec | 4973 | if (IS_BROXTON(dev)) { |
8e8232d5 | 4974 | pp_div = I915_READ(regs.pp_ctrl); |
b0a08bec VK |
4975 | pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; |
4976 | pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000) | |
4977 | << BXT_POWER_CYCLE_DELAY_SHIFT); | |
4978 | } else { | |
4979 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; | |
4980 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) | |
4981 | << PANEL_POWER_CYCLE_DELAY_SHIFT); | |
4982 | } | |
67a54566 DV |
4983 | |
4984 | /* Haswell doesn't have any port selection bits for the panel | |
4985 | * power sequencer any more. */ | |
666a4537 | 4986 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
ad933b56 | 4987 | port_sel = PANEL_PORT_SELECT_VLV(port); |
bc7d38a4 | 4988 | } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
ad933b56 | 4989 | if (port == PORT_A) |
a24c144c | 4990 | port_sel = PANEL_PORT_SELECT_DPA; |
67a54566 | 4991 | else |
a24c144c | 4992 | port_sel = PANEL_PORT_SELECT_DPD; |
67a54566 DV |
4993 | } |
4994 | ||
453c5420 JB |
4995 | pp_on |= port_sel; |
4996 | ||
8e8232d5 ID |
4997 | I915_WRITE(regs.pp_on, pp_on); |
4998 | I915_WRITE(regs.pp_off, pp_off); | |
b0a08bec | 4999 | if (IS_BROXTON(dev)) |
8e8232d5 | 5000 | I915_WRITE(regs.pp_ctrl, pp_div); |
b0a08bec | 5001 | else |
8e8232d5 | 5002 | I915_WRITE(regs.pp_div, pp_div); |
67a54566 | 5003 | |
67a54566 | 5004 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
8e8232d5 ID |
5005 | I915_READ(regs.pp_on), |
5006 | I915_READ(regs.pp_off), | |
b0a08bec | 5007 | IS_BROXTON(dev) ? |
8e8232d5 ID |
5008 | (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) : |
5009 | I915_READ(regs.pp_div)); | |
f684960e CW |
5010 | } |
5011 | ||
335f752b ID |
5012 | static void intel_dp_pps_init(struct drm_device *dev, |
5013 | struct intel_dp *intel_dp) | |
5014 | { | |
5015 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { | |
5016 | vlv_initial_power_sequencer_setup(intel_dp); | |
5017 | } else { | |
5018 | intel_dp_init_panel_power_sequencer(dev, intel_dp); | |
5019 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); | |
5020 | } | |
5021 | } | |
5022 | ||
b33a2815 VK |
5023 | /** |
5024 | * intel_dp_set_drrs_state - program registers for RR switch to take effect | |
5025 | * @dev: DRM device | |
5026 | * @refresh_rate: RR to be programmed | |
5027 | * | |
5028 | * This function gets called when refresh rate (RR) has to be changed from | |
5029 | * one frequency to another. Switches can be between high and low RR | |
5030 | * supported by the panel or to any other RR based on media playback (in | |
5031 | * this case, RR value needs to be passed from user space). | |
5032 | * | |
5033 | * The caller of this function needs to take a lock on dev_priv->drrs. | |
5034 | */ | |
96178eeb | 5035 | static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) |
439d7ac0 | 5036 | { |
fac5e23e | 5037 | struct drm_i915_private *dev_priv = to_i915(dev); |
439d7ac0 | 5038 | struct intel_encoder *encoder; |
96178eeb VK |
5039 | struct intel_digital_port *dig_port = NULL; |
5040 | struct intel_dp *intel_dp = dev_priv->drrs.dp; | |
5cec258b | 5041 | struct intel_crtc_state *config = NULL; |
439d7ac0 | 5042 | struct intel_crtc *intel_crtc = NULL; |
96178eeb | 5043 | enum drrs_refresh_rate_type index = DRRS_HIGH_RR; |
439d7ac0 PB |
5044 | |
5045 | if (refresh_rate <= 0) { | |
5046 | DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); | |
5047 | return; | |
5048 | } | |
5049 | ||
96178eeb VK |
5050 | if (intel_dp == NULL) { |
5051 | DRM_DEBUG_KMS("DRRS not supported.\n"); | |
439d7ac0 PB |
5052 | return; |
5053 | } | |
5054 | ||
1fcc9d1c | 5055 | /* |
e4d59f6b RV |
5056 | * FIXME: This needs proper synchronization with psr state for some |
5057 | * platforms that cannot have PSR and DRRS enabled at the same time. | |
1fcc9d1c | 5058 | */ |
439d7ac0 | 5059 | |
96178eeb VK |
5060 | dig_port = dp_to_dig_port(intel_dp); |
5061 | encoder = &dig_port->base; | |
723f9aab | 5062 | intel_crtc = to_intel_crtc(encoder->base.crtc); |
439d7ac0 PB |
5063 | |
5064 | if (!intel_crtc) { | |
5065 | DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); | |
5066 | return; | |
5067 | } | |
5068 | ||
6e3c9717 | 5069 | config = intel_crtc->config; |
439d7ac0 | 5070 | |
96178eeb | 5071 | if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { |
439d7ac0 PB |
5072 | DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); |
5073 | return; | |
5074 | } | |
5075 | ||
96178eeb VK |
5076 | if (intel_dp->attached_connector->panel.downclock_mode->vrefresh == |
5077 | refresh_rate) | |
439d7ac0 PB |
5078 | index = DRRS_LOW_RR; |
5079 | ||
96178eeb | 5080 | if (index == dev_priv->drrs.refresh_rate_type) { |
439d7ac0 PB |
5081 | DRM_DEBUG_KMS( |
5082 | "DRRS requested for previously set RR...ignoring\n"); | |
5083 | return; | |
5084 | } | |
5085 | ||
5086 | if (!intel_crtc->active) { | |
5087 | DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); | |
5088 | return; | |
5089 | } | |
5090 | ||
44395bfe | 5091 | if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) { |
a4c30b1d VK |
5092 | switch (index) { |
5093 | case DRRS_HIGH_RR: | |
5094 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
5095 | break; | |
5096 | case DRRS_LOW_RR: | |
5097 | intel_dp_set_m_n(intel_crtc, M2_N2); | |
5098 | break; | |
5099 | case DRRS_MAX_RR: | |
5100 | default: | |
5101 | DRM_ERROR("Unsupported refreshrate type\n"); | |
5102 | } | |
5103 | } else if (INTEL_INFO(dev)->gen > 6) { | |
f0f59a00 | 5104 | i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder); |
649636ef | 5105 | u32 val; |
a4c30b1d | 5106 | |
649636ef | 5107 | val = I915_READ(reg); |
439d7ac0 | 5108 | if (index > DRRS_HIGH_RR) { |
666a4537 | 5109 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6fa7aec1 VK |
5110 | val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5111 | else | |
5112 | val |= PIPECONF_EDP_RR_MODE_SWITCH; | |
439d7ac0 | 5113 | } else { |
666a4537 | 5114 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6fa7aec1 VK |
5115 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5116 | else | |
5117 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; | |
439d7ac0 PB |
5118 | } |
5119 | I915_WRITE(reg, val); | |
5120 | } | |
5121 | ||
4e9ac947 VK |
5122 | dev_priv->drrs.refresh_rate_type = index; |
5123 | ||
5124 | DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); | |
5125 | } | |
5126 | ||
b33a2815 VK |
5127 | /** |
5128 | * intel_edp_drrs_enable - init drrs struct if supported | |
5129 | * @intel_dp: DP struct | |
5130 | * | |
5131 | * Initializes frontbuffer_bits and drrs.dp | |
5132 | */ | |
c395578e VK |
5133 | void intel_edp_drrs_enable(struct intel_dp *intel_dp) |
5134 | { | |
5135 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
fac5e23e | 5136 | struct drm_i915_private *dev_priv = to_i915(dev); |
c395578e VK |
5137 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
5138 | struct drm_crtc *crtc = dig_port->base.base.crtc; | |
5139 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5140 | ||
5141 | if (!intel_crtc->config->has_drrs) { | |
5142 | DRM_DEBUG_KMS("Panel doesn't support DRRS\n"); | |
5143 | return; | |
5144 | } | |
5145 | ||
5146 | mutex_lock(&dev_priv->drrs.mutex); | |
5147 | if (WARN_ON(dev_priv->drrs.dp)) { | |
5148 | DRM_ERROR("DRRS already enabled\n"); | |
5149 | goto unlock; | |
5150 | } | |
5151 | ||
5152 | dev_priv->drrs.busy_frontbuffer_bits = 0; | |
5153 | ||
5154 | dev_priv->drrs.dp = intel_dp; | |
5155 | ||
5156 | unlock: | |
5157 | mutex_unlock(&dev_priv->drrs.mutex); | |
5158 | } | |
5159 | ||
b33a2815 VK |
5160 | /** |
5161 | * intel_edp_drrs_disable - Disable DRRS | |
5162 | * @intel_dp: DP struct | |
5163 | * | |
5164 | */ | |
c395578e VK |
5165 | void intel_edp_drrs_disable(struct intel_dp *intel_dp) |
5166 | { | |
5167 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
fac5e23e | 5168 | struct drm_i915_private *dev_priv = to_i915(dev); |
c395578e VK |
5169 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
5170 | struct drm_crtc *crtc = dig_port->base.base.crtc; | |
5171 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5172 | ||
5173 | if (!intel_crtc->config->has_drrs) | |
5174 | return; | |
5175 | ||
5176 | mutex_lock(&dev_priv->drrs.mutex); | |
5177 | if (!dev_priv->drrs.dp) { | |
5178 | mutex_unlock(&dev_priv->drrs.mutex); | |
5179 | return; | |
5180 | } | |
5181 | ||
5182 | if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) | |
91c8a326 CW |
5183 | intel_dp_set_drrs_state(&dev_priv->drm, |
5184 | intel_dp->attached_connector->panel. | |
5185 | fixed_mode->vrefresh); | |
c395578e VK |
5186 | |
5187 | dev_priv->drrs.dp = NULL; | |
5188 | mutex_unlock(&dev_priv->drrs.mutex); | |
5189 | ||
5190 | cancel_delayed_work_sync(&dev_priv->drrs.work); | |
5191 | } | |
5192 | ||
4e9ac947 VK |
5193 | static void intel_edp_drrs_downclock_work(struct work_struct *work) |
5194 | { | |
5195 | struct drm_i915_private *dev_priv = | |
5196 | container_of(work, typeof(*dev_priv), drrs.work.work); | |
5197 | struct intel_dp *intel_dp; | |
5198 | ||
5199 | mutex_lock(&dev_priv->drrs.mutex); | |
5200 | ||
5201 | intel_dp = dev_priv->drrs.dp; | |
5202 | ||
5203 | if (!intel_dp) | |
5204 | goto unlock; | |
5205 | ||
439d7ac0 | 5206 | /* |
4e9ac947 VK |
5207 | * The delayed work can race with an invalidate hence we need to |
5208 | * recheck. | |
439d7ac0 PB |
5209 | */ |
5210 | ||
4e9ac947 VK |
5211 | if (dev_priv->drrs.busy_frontbuffer_bits) |
5212 | goto unlock; | |
439d7ac0 | 5213 | |
4e9ac947 | 5214 | if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) |
91c8a326 CW |
5215 | intel_dp_set_drrs_state(&dev_priv->drm, |
5216 | intel_dp->attached_connector->panel. | |
5217 | downclock_mode->vrefresh); | |
439d7ac0 | 5218 | |
4e9ac947 | 5219 | unlock: |
4e9ac947 | 5220 | mutex_unlock(&dev_priv->drrs.mutex); |
439d7ac0 PB |
5221 | } |
5222 | ||
b33a2815 | 5223 | /** |
0ddfd203 | 5224 | * intel_edp_drrs_invalidate - Disable Idleness DRRS |
5748b6a1 | 5225 | * @dev_priv: i915 device |
b33a2815 VK |
5226 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5227 | * | |
0ddfd203 R |
5228 | * This function gets called everytime rendering on the given planes start. |
5229 | * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). | |
b33a2815 VK |
5230 | * |
5231 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. | |
5232 | */ | |
5748b6a1 CW |
5233 | void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv, |
5234 | unsigned int frontbuffer_bits) | |
a93fad0f | 5235 | { |
a93fad0f VK |
5236 | struct drm_crtc *crtc; |
5237 | enum pipe pipe; | |
5238 | ||
9da7d693 | 5239 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
a93fad0f VK |
5240 | return; |
5241 | ||
88f933a8 | 5242 | cancel_delayed_work(&dev_priv->drrs.work); |
3954e733 | 5243 | |
a93fad0f | 5244 | mutex_lock(&dev_priv->drrs.mutex); |
9da7d693 DV |
5245 | if (!dev_priv->drrs.dp) { |
5246 | mutex_unlock(&dev_priv->drrs.mutex); | |
5247 | return; | |
5248 | } | |
5249 | ||
a93fad0f VK |
5250 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5251 | pipe = to_intel_crtc(crtc)->pipe; | |
5252 | ||
c1d038c6 DV |
5253 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
5254 | dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; | |
5255 | ||
0ddfd203 | 5256 | /* invalidate means busy screen hence upclock */ |
c1d038c6 | 5257 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
91c8a326 CW |
5258 | intel_dp_set_drrs_state(&dev_priv->drm, |
5259 | dev_priv->drrs.dp->attached_connector->panel. | |
5260 | fixed_mode->vrefresh); | |
a93fad0f | 5261 | |
a93fad0f VK |
5262 | mutex_unlock(&dev_priv->drrs.mutex); |
5263 | } | |
5264 | ||
b33a2815 | 5265 | /** |
0ddfd203 | 5266 | * intel_edp_drrs_flush - Restart Idleness DRRS |
5748b6a1 | 5267 | * @dev_priv: i915 device |
b33a2815 VK |
5268 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5269 | * | |
0ddfd203 R |
5270 | * This function gets called every time rendering on the given planes has |
5271 | * completed or flip on a crtc is completed. So DRRS should be upclocked | |
5272 | * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, | |
5273 | * if no other planes are dirty. | |
b33a2815 VK |
5274 | * |
5275 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. | |
5276 | */ | |
5748b6a1 CW |
5277 | void intel_edp_drrs_flush(struct drm_i915_private *dev_priv, |
5278 | unsigned int frontbuffer_bits) | |
a93fad0f | 5279 | { |
a93fad0f VK |
5280 | struct drm_crtc *crtc; |
5281 | enum pipe pipe; | |
5282 | ||
9da7d693 | 5283 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
a93fad0f VK |
5284 | return; |
5285 | ||
88f933a8 | 5286 | cancel_delayed_work(&dev_priv->drrs.work); |
3954e733 | 5287 | |
a93fad0f | 5288 | mutex_lock(&dev_priv->drrs.mutex); |
9da7d693 DV |
5289 | if (!dev_priv->drrs.dp) { |
5290 | mutex_unlock(&dev_priv->drrs.mutex); | |
5291 | return; | |
5292 | } | |
5293 | ||
a93fad0f VK |
5294 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5295 | pipe = to_intel_crtc(crtc)->pipe; | |
c1d038c6 DV |
5296 | |
5297 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); | |
a93fad0f VK |
5298 | dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; |
5299 | ||
0ddfd203 | 5300 | /* flush means busy screen hence upclock */ |
c1d038c6 | 5301 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
91c8a326 CW |
5302 | intel_dp_set_drrs_state(&dev_priv->drm, |
5303 | dev_priv->drrs.dp->attached_connector->panel. | |
5304 | fixed_mode->vrefresh); | |
0ddfd203 R |
5305 | |
5306 | /* | |
5307 | * flush also means no more activity hence schedule downclock, if all | |
5308 | * other fbs are quiescent too | |
5309 | */ | |
5310 | if (!dev_priv->drrs.busy_frontbuffer_bits) | |
a93fad0f VK |
5311 | schedule_delayed_work(&dev_priv->drrs.work, |
5312 | msecs_to_jiffies(1000)); | |
5313 | mutex_unlock(&dev_priv->drrs.mutex); | |
5314 | } | |
5315 | ||
b33a2815 VK |
5316 | /** |
5317 | * DOC: Display Refresh Rate Switching (DRRS) | |
5318 | * | |
5319 | * Display Refresh Rate Switching (DRRS) is a power conservation feature | |
5320 | * which enables swtching between low and high refresh rates, | |
5321 | * dynamically, based on the usage scenario. This feature is applicable | |
5322 | * for internal panels. | |
5323 | * | |
5324 | * Indication that the panel supports DRRS is given by the panel EDID, which | |
5325 | * would list multiple refresh rates for one resolution. | |
5326 | * | |
5327 | * DRRS is of 2 types - static and seamless. | |
5328 | * Static DRRS involves changing refresh rate (RR) by doing a full modeset | |
5329 | * (may appear as a blink on screen) and is used in dock-undock scenario. | |
5330 | * Seamless DRRS involves changing RR without any visual effect to the user | |
5331 | * and can be used during normal system usage. This is done by programming | |
5332 | * certain registers. | |
5333 | * | |
5334 | * Support for static/seamless DRRS may be indicated in the VBT based on | |
5335 | * inputs from the panel spec. | |
5336 | * | |
5337 | * DRRS saves power by switching to low RR based on usage scenarios. | |
5338 | * | |
2e7a5701 DV |
5339 | * The implementation is based on frontbuffer tracking implementation. When |
5340 | * there is a disturbance on the screen triggered by user activity or a periodic | |
5341 | * system activity, DRRS is disabled (RR is changed to high RR). When there is | |
5342 | * no movement on screen, after a timeout of 1 second, a switch to low RR is | |
5343 | * made. | |
5344 | * | |
5345 | * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate() | |
5346 | * and intel_edp_drrs_flush() are called. | |
b33a2815 VK |
5347 | * |
5348 | * DRRS can be further extended to support other internal panels and also | |
5349 | * the scenario of video playback wherein RR is set based on the rate | |
5350 | * requested by userspace. | |
5351 | */ | |
5352 | ||
5353 | /** | |
5354 | * intel_dp_drrs_init - Init basic DRRS work and mutex. | |
5355 | * @intel_connector: eDP connector | |
5356 | * @fixed_mode: preferred mode of panel | |
5357 | * | |
5358 | * This function is called only once at driver load to initialize basic | |
5359 | * DRRS stuff. | |
5360 | * | |
5361 | * Returns: | |
5362 | * Downclock mode if panel supports it, else return NULL. | |
5363 | * DRRS support is determined by the presence of downclock mode (apart | |
5364 | * from VBT setting). | |
5365 | */ | |
4f9db5b5 | 5366 | static struct drm_display_mode * |
96178eeb VK |
5367 | intel_dp_drrs_init(struct intel_connector *intel_connector, |
5368 | struct drm_display_mode *fixed_mode) | |
4f9db5b5 PB |
5369 | { |
5370 | struct drm_connector *connector = &intel_connector->base; | |
96178eeb | 5371 | struct drm_device *dev = connector->dev; |
fac5e23e | 5372 | struct drm_i915_private *dev_priv = to_i915(dev); |
4f9db5b5 PB |
5373 | struct drm_display_mode *downclock_mode = NULL; |
5374 | ||
9da7d693 DV |
5375 | INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); |
5376 | mutex_init(&dev_priv->drrs.mutex); | |
5377 | ||
4f9db5b5 PB |
5378 | if (INTEL_INFO(dev)->gen <= 6) { |
5379 | DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); | |
5380 | return NULL; | |
5381 | } | |
5382 | ||
5383 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { | |
4079b8d1 | 5384 | DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); |
4f9db5b5 PB |
5385 | return NULL; |
5386 | } | |
5387 | ||
5388 | downclock_mode = intel_find_panel_downclock | |
5389 | (dev, fixed_mode, connector); | |
5390 | ||
5391 | if (!downclock_mode) { | |
a1d26342 | 5392 | DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n"); |
4f9db5b5 PB |
5393 | return NULL; |
5394 | } | |
5395 | ||
96178eeb | 5396 | dev_priv->drrs.type = dev_priv->vbt.drrs_type; |
4f9db5b5 | 5397 | |
96178eeb | 5398 | dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; |
4079b8d1 | 5399 | DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); |
4f9db5b5 PB |
5400 | return downclock_mode; |
5401 | } | |
5402 | ||
ed92f0b2 | 5403 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
36b5f425 | 5404 | struct intel_connector *intel_connector) |
ed92f0b2 PZ |
5405 | { |
5406 | struct drm_connector *connector = &intel_connector->base; | |
5407 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
63635217 PZ |
5408 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
5409 | struct drm_device *dev = intel_encoder->base.dev; | |
fac5e23e | 5410 | struct drm_i915_private *dev_priv = to_i915(dev); |
ed92f0b2 | 5411 | struct drm_display_mode *fixed_mode = NULL; |
4f9db5b5 | 5412 | struct drm_display_mode *downclock_mode = NULL; |
ed92f0b2 PZ |
5413 | bool has_dpcd; |
5414 | struct drm_display_mode *scan; | |
5415 | struct edid *edid; | |
6517d273 | 5416 | enum pipe pipe = INVALID_PIPE; |
ed92f0b2 PZ |
5417 | |
5418 | if (!is_edp(intel_dp)) | |
5419 | return true; | |
5420 | ||
97a824e1 ID |
5421 | /* |
5422 | * On IBX/CPT we may get here with LVDS already registered. Since the | |
5423 | * driver uses the only internal power sequencer available for both | |
5424 | * eDP and LVDS bail out early in this case to prevent interfering | |
5425 | * with an already powered-on LVDS power sequencer. | |
5426 | */ | |
5427 | if (intel_get_lvds_encoder(dev)) { | |
5428 | WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); | |
5429 | DRM_INFO("LVDS was detected, not registering eDP\n"); | |
5430 | ||
5431 | return false; | |
5432 | } | |
5433 | ||
49e6bc51 | 5434 | pps_lock(intel_dp); |
b4d06ede ID |
5435 | |
5436 | intel_dp_init_panel_power_timestamps(intel_dp); | |
335f752b | 5437 | intel_dp_pps_init(dev, intel_dp); |
49e6bc51 | 5438 | intel_edp_panel_vdd_sanitize(intel_dp); |
b4d06ede | 5439 | |
49e6bc51 | 5440 | pps_unlock(intel_dp); |
63635217 | 5441 | |
ed92f0b2 | 5442 | /* Cache DPCD and EDID for edp. */ |
fe5a66f9 | 5443 | has_dpcd = intel_edp_init_dpcd(intel_dp); |
ed92f0b2 | 5444 | |
fe5a66f9 | 5445 | if (!has_dpcd) { |
ed92f0b2 PZ |
5446 | /* if this fails, presume the device is a ghost */ |
5447 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); | |
b4d06ede | 5448 | goto out_vdd_off; |
ed92f0b2 PZ |
5449 | } |
5450 | ||
060c8778 | 5451 | mutex_lock(&dev->mode_config.mutex); |
0b99836f | 5452 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
ed92f0b2 PZ |
5453 | if (edid) { |
5454 | if (drm_add_edid_modes(connector, edid)) { | |
5455 | drm_mode_connector_update_edid_property(connector, | |
5456 | edid); | |
5457 | drm_edid_to_eld(connector, edid); | |
5458 | } else { | |
5459 | kfree(edid); | |
5460 | edid = ERR_PTR(-EINVAL); | |
5461 | } | |
5462 | } else { | |
5463 | edid = ERR_PTR(-ENOENT); | |
5464 | } | |
5465 | intel_connector->edid = edid; | |
5466 | ||
5467 | /* prefer fixed mode from EDID if available */ | |
5468 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
5469 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { | |
5470 | fixed_mode = drm_mode_duplicate(dev, scan); | |
4f9db5b5 | 5471 | downclock_mode = intel_dp_drrs_init( |
4f9db5b5 | 5472 | intel_connector, fixed_mode); |
ed92f0b2 PZ |
5473 | break; |
5474 | } | |
5475 | } | |
5476 | ||
5477 | /* fallback to VBT if available for eDP */ | |
5478 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { | |
5479 | fixed_mode = drm_mode_duplicate(dev, | |
5480 | dev_priv->vbt.lfp_lvds_vbt_mode); | |
df457245 | 5481 | if (fixed_mode) { |
ed92f0b2 | 5482 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
df457245 VS |
5483 | connector->display_info.width_mm = fixed_mode->width_mm; |
5484 | connector->display_info.height_mm = fixed_mode->height_mm; | |
5485 | } | |
ed92f0b2 | 5486 | } |
060c8778 | 5487 | mutex_unlock(&dev->mode_config.mutex); |
ed92f0b2 | 5488 | |
666a4537 | 5489 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
01527b31 CT |
5490 | intel_dp->edp_notifier.notifier_call = edp_notify_handler; |
5491 | register_reboot_notifier(&intel_dp->edp_notifier); | |
6517d273 VS |
5492 | |
5493 | /* | |
5494 | * Figure out the current pipe for the initial backlight setup. | |
5495 | * If the current pipe isn't valid, try the PPS pipe, and if that | |
5496 | * fails just assume pipe A. | |
5497 | */ | |
5498 | if (IS_CHERRYVIEW(dev)) | |
5499 | pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP); | |
5500 | else | |
5501 | pipe = PORT_TO_PIPE(intel_dp->DP); | |
5502 | ||
5503 | if (pipe != PIPE_A && pipe != PIPE_B) | |
5504 | pipe = intel_dp->pps_pipe; | |
5505 | ||
5506 | if (pipe != PIPE_A && pipe != PIPE_B) | |
5507 | pipe = PIPE_A; | |
5508 | ||
5509 | DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n", | |
5510 | pipe_name(pipe)); | |
01527b31 CT |
5511 | } |
5512 | ||
4f9db5b5 | 5513 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
5507faeb | 5514 | intel_connector->panel.backlight.power = intel_edp_backlight_power; |
6517d273 | 5515 | intel_panel_setup_backlight(connector, pipe); |
ed92f0b2 PZ |
5516 | |
5517 | return true; | |
b4d06ede ID |
5518 | |
5519 | out_vdd_off: | |
5520 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
5521 | /* | |
5522 | * vdd might still be enabled do to the delayed vdd off. | |
5523 | * Make sure vdd is actually turned off here. | |
5524 | */ | |
5525 | pps_lock(intel_dp); | |
5526 | edp_panel_vdd_off_sync(intel_dp); | |
5527 | pps_unlock(intel_dp); | |
5528 | ||
5529 | return false; | |
ed92f0b2 PZ |
5530 | } |
5531 | ||
16c25533 | 5532 | bool |
f0fec3f2 PZ |
5533 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
5534 | struct intel_connector *intel_connector) | |
a4fc5ed6 | 5535 | { |
f0fec3f2 PZ |
5536 | struct drm_connector *connector = &intel_connector->base; |
5537 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
5538 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
5539 | struct drm_device *dev = intel_encoder->base.dev; | |
fac5e23e | 5540 | struct drm_i915_private *dev_priv = to_i915(dev); |
174edf1f | 5541 | enum port port = intel_dig_port->port; |
7a418e34 | 5542 | int type; |
a4fc5ed6 | 5543 | |
ccb1a831 VS |
5544 | if (WARN(intel_dig_port->max_lanes < 1, |
5545 | "Not enough lanes (%d) for DP on port %c\n", | |
5546 | intel_dig_port->max_lanes, port_name(port))) | |
5547 | return false; | |
5548 | ||
a4a5d2f8 VS |
5549 | intel_dp->pps_pipe = INVALID_PIPE; |
5550 | ||
ec5b01dd | 5551 | /* intel_dp vfuncs */ |
b6b5e383 DL |
5552 | if (INTEL_INFO(dev)->gen >= 9) |
5553 | intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; | |
ec5b01dd DL |
5554 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
5555 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; | |
5556 | else if (HAS_PCH_SPLIT(dev)) | |
5557 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; | |
5558 | else | |
6ffb1be7 | 5559 | intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; |
ec5b01dd | 5560 | |
b9ca5fad DL |
5561 | if (INTEL_INFO(dev)->gen >= 9) |
5562 | intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; | |
5563 | else | |
6ffb1be7 | 5564 | intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; |
153b1100 | 5565 | |
ad64217b ACO |
5566 | if (HAS_DDI(dev)) |
5567 | intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain; | |
5568 | ||
0767935e DV |
5569 | /* Preserve the current hw state. */ |
5570 | intel_dp->DP = I915_READ(intel_dp->output_reg); | |
dd06f90e | 5571 | intel_dp->attached_connector = intel_connector; |
3d3dc149 | 5572 | |
3b32a35b | 5573 | if (intel_dp_is_edp(dev, port)) |
b329530c | 5574 | type = DRM_MODE_CONNECTOR_eDP; |
3b32a35b VS |
5575 | else |
5576 | type = DRM_MODE_CONNECTOR_DisplayPort; | |
b329530c | 5577 | |
f7d24902 ID |
5578 | /* |
5579 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but | |
5580 | * for DP the encoder type can be set by the caller to | |
5581 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. | |
5582 | */ | |
5583 | if (type == DRM_MODE_CONNECTOR_eDP) | |
5584 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
5585 | ||
c17ed5b5 | 5586 | /* eDP only on port B and/or C on vlv/chv */ |
666a4537 WB |
5587 | if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
5588 | is_edp(intel_dp) && port != PORT_B && port != PORT_C)) | |
c17ed5b5 VS |
5589 | return false; |
5590 | ||
e7281eab ID |
5591 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
5592 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", | |
5593 | port_name(port)); | |
5594 | ||
b329530c | 5595 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
5596 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
5597 | ||
a4fc5ed6 KP |
5598 | connector->interlace_allowed = true; |
5599 | connector->doublescan_allowed = 0; | |
5600 | ||
7a418e34 CW |
5601 | intel_dp_aux_init(intel_dp, intel_connector); |
5602 | ||
f0fec3f2 | 5603 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
4be73780 | 5604 | edp_panel_vdd_work); |
a4fc5ed6 | 5605 | |
df0e9248 | 5606 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
a4fc5ed6 | 5607 | |
affa9354 | 5608 | if (HAS_DDI(dev)) |
bcbc889b PZ |
5609 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
5610 | else | |
5611 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
5612 | ||
0b99836f | 5613 | /* Set up the hotplug pin. */ |
ab9d7c30 PZ |
5614 | switch (port) { |
5615 | case PORT_A: | |
1d843f9d | 5616 | intel_encoder->hpd_pin = HPD_PORT_A; |
ab9d7c30 PZ |
5617 | break; |
5618 | case PORT_B: | |
1d843f9d | 5619 | intel_encoder->hpd_pin = HPD_PORT_B; |
e87a005d | 5620 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) |
cf1d5883 | 5621 | intel_encoder->hpd_pin = HPD_PORT_A; |
ab9d7c30 PZ |
5622 | break; |
5623 | case PORT_C: | |
1d843f9d | 5624 | intel_encoder->hpd_pin = HPD_PORT_C; |
ab9d7c30 PZ |
5625 | break; |
5626 | case PORT_D: | |
1d843f9d | 5627 | intel_encoder->hpd_pin = HPD_PORT_D; |
ab9d7c30 | 5628 | break; |
26951caf XZ |
5629 | case PORT_E: |
5630 | intel_encoder->hpd_pin = HPD_PORT_E; | |
5631 | break; | |
ab9d7c30 | 5632 | default: |
ad1c0b19 | 5633 | BUG(); |
5eb08b69 ZW |
5634 | } |
5635 | ||
0e32b39c | 5636 | /* init MST on ports that can support it */ |
f8e58ddf | 5637 | if (HAS_DP_MST(dev) && !is_edp(intel_dp) && |
0c9b3715 JN |
5638 | (port == PORT_B || port == PORT_C || port == PORT_D)) |
5639 | intel_dp_mst_encoder_init(intel_dig_port, | |
5640 | intel_connector->base.base.id); | |
0e32b39c | 5641 | |
36b5f425 | 5642 | if (!intel_edp_init_connector(intel_dp, intel_connector)) { |
a121f4e5 VS |
5643 | intel_dp_aux_fini(intel_dp); |
5644 | intel_dp_mst_encoder_cleanup(intel_dig_port); | |
5645 | goto fail; | |
b2f246a8 | 5646 | } |
32f9d658 | 5647 | |
f684960e CW |
5648 | intel_dp_add_properties(intel_dp, connector); |
5649 | ||
a4fc5ed6 KP |
5650 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
5651 | * 0xd. Failure to do so will result in spurious interrupts being | |
5652 | * generated on the port when a cable is not attached. | |
5653 | */ | |
5654 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
5655 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
5656 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
5657 | } | |
16c25533 PZ |
5658 | |
5659 | return true; | |
a121f4e5 VS |
5660 | |
5661 | fail: | |
a121f4e5 VS |
5662 | drm_connector_cleanup(connector); |
5663 | ||
5664 | return false; | |
a4fc5ed6 | 5665 | } |
f0fec3f2 | 5666 | |
457c52d8 CW |
5667 | bool intel_dp_init(struct drm_device *dev, |
5668 | i915_reg_t output_reg, | |
5669 | enum port port) | |
f0fec3f2 | 5670 | { |
fac5e23e | 5671 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0fec3f2 PZ |
5672 | struct intel_digital_port *intel_dig_port; |
5673 | struct intel_encoder *intel_encoder; | |
5674 | struct drm_encoder *encoder; | |
5675 | struct intel_connector *intel_connector; | |
5676 | ||
b14c5679 | 5677 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
f0fec3f2 | 5678 | if (!intel_dig_port) |
457c52d8 | 5679 | return false; |
f0fec3f2 | 5680 | |
08d9bc92 | 5681 | intel_connector = intel_connector_alloc(); |
11aee0f6 SM |
5682 | if (!intel_connector) |
5683 | goto err_connector_alloc; | |
f0fec3f2 PZ |
5684 | |
5685 | intel_encoder = &intel_dig_port->base; | |
5686 | encoder = &intel_encoder->base; | |
5687 | ||
893da0c9 | 5688 | if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
580d8ed5 | 5689 | DRM_MODE_ENCODER_TMDS, "DP %c", port_name(port))) |
893da0c9 | 5690 | goto err_encoder_init; |
f0fec3f2 | 5691 | |
5bfe2ac0 | 5692 | intel_encoder->compute_config = intel_dp_compute_config; |
00c09d70 | 5693 | intel_encoder->disable = intel_disable_dp; |
00c09d70 | 5694 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
045ac3b5 | 5695 | intel_encoder->get_config = intel_dp_get_config; |
07f9cd0b | 5696 | intel_encoder->suspend = intel_dp_encoder_suspend; |
e4a1d846 | 5697 | if (IS_CHERRYVIEW(dev)) { |
9197c88b | 5698 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; |
e4a1d846 CML |
5699 | intel_encoder->pre_enable = chv_pre_enable_dp; |
5700 | intel_encoder->enable = vlv_enable_dp; | |
580d3811 | 5701 | intel_encoder->post_disable = chv_post_disable_dp; |
d6db995f | 5702 | intel_encoder->post_pll_disable = chv_dp_post_pll_disable; |
e4a1d846 | 5703 | } else if (IS_VALLEYVIEW(dev)) { |
ecff4f3b | 5704 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
ab1f90f9 JN |
5705 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
5706 | intel_encoder->enable = vlv_enable_dp; | |
49277c31 | 5707 | intel_encoder->post_disable = vlv_post_disable_dp; |
ab1f90f9 | 5708 | } else { |
ecff4f3b JN |
5709 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
5710 | intel_encoder->enable = g4x_enable_dp; | |
08aff3fe VS |
5711 | if (INTEL_INFO(dev)->gen >= 5) |
5712 | intel_encoder->post_disable = ilk_post_disable_dp; | |
ab1f90f9 | 5713 | } |
f0fec3f2 | 5714 | |
174edf1f | 5715 | intel_dig_port->port = port; |
f0fec3f2 | 5716 | intel_dig_port->dp.output_reg = output_reg; |
ccb1a831 | 5717 | intel_dig_port->max_lanes = 4; |
f0fec3f2 | 5718 | |
cca0502b | 5719 | intel_encoder->type = INTEL_OUTPUT_DP; |
882ec384 VS |
5720 | if (IS_CHERRYVIEW(dev)) { |
5721 | if (port == PORT_D) | |
5722 | intel_encoder->crtc_mask = 1 << 2; | |
5723 | else | |
5724 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
5725 | } else { | |
5726 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
5727 | } | |
bc079e8b | 5728 | intel_encoder->cloneable = 0; |
f0fec3f2 | 5729 | |
13cf5504 | 5730 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
5fcece80 | 5731 | dev_priv->hotplug.irq_port[port] = intel_dig_port; |
13cf5504 | 5732 | |
11aee0f6 SM |
5733 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) |
5734 | goto err_init_connector; | |
5735 | ||
457c52d8 | 5736 | return true; |
11aee0f6 SM |
5737 | |
5738 | err_init_connector: | |
5739 | drm_encoder_cleanup(encoder); | |
893da0c9 | 5740 | err_encoder_init: |
11aee0f6 SM |
5741 | kfree(intel_connector); |
5742 | err_connector_alloc: | |
5743 | kfree(intel_dig_port); | |
457c52d8 | 5744 | return false; |
f0fec3f2 | 5745 | } |
0e32b39c DA |
5746 | |
5747 | void intel_dp_mst_suspend(struct drm_device *dev) | |
5748 | { | |
fac5e23e | 5749 | struct drm_i915_private *dev_priv = to_i915(dev); |
0e32b39c DA |
5750 | int i; |
5751 | ||
5752 | /* disable MST */ | |
5753 | for (i = 0; i < I915_MAX_PORTS; i++) { | |
5fcece80 | 5754 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
5aa56969 VS |
5755 | |
5756 | if (!intel_dig_port || !intel_dig_port->dp.can_mst) | |
0e32b39c DA |
5757 | continue; |
5758 | ||
5aa56969 VS |
5759 | if (intel_dig_port->dp.is_mst) |
5760 | drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); | |
0e32b39c DA |
5761 | } |
5762 | } | |
5763 | ||
5764 | void intel_dp_mst_resume(struct drm_device *dev) | |
5765 | { | |
fac5e23e | 5766 | struct drm_i915_private *dev_priv = to_i915(dev); |
0e32b39c DA |
5767 | int i; |
5768 | ||
5769 | for (i = 0; i < I915_MAX_PORTS; i++) { | |
5fcece80 | 5770 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
5aa56969 | 5771 | int ret; |
0e32b39c | 5772 | |
5aa56969 VS |
5773 | if (!intel_dig_port || !intel_dig_port->dp.can_mst) |
5774 | continue; | |
0e32b39c | 5775 | |
5aa56969 VS |
5776 | ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); |
5777 | if (ret) | |
5778 | intel_dp_check_mst_status(&intel_dig_port->dp); | |
0e32b39c DA |
5779 | } |
5780 | } |