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Merge tag 'v3.14' into drm-intel-next-queued
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
65ce4bf5
CML		 60static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
58f6e632 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
cfcb0fc9
JB		 67/**
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
70 *
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
73 */
74static bool is_edp(struct intel_dp *intel_dp)
75{
da63a9f2
PZ		 76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
77
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 79}
80
68b4d824 81static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 82{
68b4d824
ID		 83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
84
85 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 86}
87
df0e9248
CW		 88static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
89{
fa90ecef 90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 91}
92
ea5b213a 93static void intel_dp_link_down(struct intel_dp *intel_dp);
adddaaf4 94static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 95static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 96
a4fc5ed6 97static int
ea5b213a 98intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 99{
7183dc29 100 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 101 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 102
103 switch (max_link_bw) {
104 case DP_LINK_BW_1_62:
105 case DP_LINK_BW_2_7:
106 break;
d4eead50 107 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
06ea66b6
TP		 108 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
109 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
110 max_link_bw = DP_LINK_BW_5_4;
111 else
112 max_link_bw = DP_LINK_BW_2_7;
d4eead50 113 break;
a4fc5ed6 114 default:
d4eead50
ID		 115 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
116 max_link_bw);
a4fc5ed6
KP		 117 max_link_bw = DP_LINK_BW_1_62;
118 break;
119 }
120 return max_link_bw;
121}
122
cd9dde44
AJ		 123/*
124 * The units on the numbers in the next two are... bizarre. Examples will
125 * make it clearer; this one parallels an example in the eDP spec.
126 *
127 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
128 *
129 * 270000 * 1 * 8 / 10 == 216000
130 *
131 * The actual data capacity of that configuration is 2.16Gbit/s, so the
132 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
133 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
134 * 119000. At 18bpp that's 2142000 kilobits per second.
135 *
136 * Thus the strange-looking division by 10 in intel_dp_link_required, to
137 * get the result in decakilobits instead of kilobits.
138 */
139
a4fc5ed6 140static int
c898261c 141intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 142{
cd9dde44 143 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 144}
145
fe27d53e
DA		 146static int
147intel_dp_max_data_rate(int max_link_clock, int max_lanes)
148{
149 return (max_link_clock * max_lanes * 8) / 10;
150}
151
c19de8eb 152static enum drm_mode_status
a4fc5ed6
KP		 153intel_dp_mode_valid(struct drm_connector *connector,
154 struct drm_display_mode *mode)
155{
df0e9248 156 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 157 struct intel_connector *intel_connector = to_intel_connector(connector);
158 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 159 int target_clock = mode->clock;
160 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 161
dd06f90e
JN		 162 if (is_edp(intel_dp) && fixed_mode) {
163 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 164 return MODE_PANEL;
165
dd06f90e 166 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 167 return MODE_PANEL;
03afc4a2
DV		 168
169 target_clock = fixed_mode->clock;
7de56f43
ZY		 170 }
171
36008365
DV		 172 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
173 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
174
175 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
176 mode_rate = intel_dp_link_required(target_clock, 18);
177
178 if (mode_rate > max_rate)
c4867936 179 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 180
181 if (mode->clock < 10000)
182 return MODE_CLOCK_LOW;
183
0af78a2b
DV		 184 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
185 return MODE_H_ILLEGAL;
186
a4fc5ed6
KP		 187 return MODE_OK;
188}
189
190static uint32_t
191pack_aux(uint8_t *src, int src_bytes)
192{
193 int i;
194 uint32_t v = 0;
195
196 if (src_bytes > 4)
197 src_bytes = 4;
198 for (i = 0; i < src_bytes; i++)
199 v |= ((uint32_t) src[i]) << ((3-i) * 8);
200 return v;
201}
202
203static void
204unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
205{
206 int i;
207 if (dst_bytes > 4)
208 dst_bytes = 4;
209 for (i = 0; i < dst_bytes; i++)
210 dst[i] = src >> ((3-i) * 8);
211}
212
fb0f8fbf
KP		 213/* hrawclock is 1/4 the FSB frequency */
214static int
215intel_hrawclk(struct drm_device *dev)
216{
217 struct drm_i915_private *dev_priv = dev->dev_private;
218 uint32_t clkcfg;
219
9473c8f4
VP		 220 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
221 if (IS_VALLEYVIEW(dev))
222 return 200;
223
fb0f8fbf
KP		 224 clkcfg = I915_READ(CLKCFG);
225 switch (clkcfg & CLKCFG_FSB_MASK) {
226 case CLKCFG_FSB_400:
227 return 100;
228 case CLKCFG_FSB_533:
229 return 133;
230 case CLKCFG_FSB_667:
231 return 166;
232 case CLKCFG_FSB_800:
233 return 200;
234 case CLKCFG_FSB_1067:
235 return 266;
236 case CLKCFG_FSB_1333:
237 return 333;
238 /* these two are just a guess; one of them might be right */
239 case CLKCFG_FSB_1600:
240 case CLKCFG_FSB_1600_ALT:
241 return 400;
242 default:
243 return 133;
244 }
245}
246
bf13e81b
JN		 247static void
248intel_dp_init_panel_power_sequencer(struct drm_device *dev,
249 struct intel_dp *intel_dp,
250 struct edp_power_seq *out);
251static void
252intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
253 struct intel_dp *intel_dp,
254 struct edp_power_seq *out);
255
256static enum pipe
257vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
258{
259 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
260 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
261 struct drm_device *dev = intel_dig_port->base.base.dev;
262 struct drm_i915_private *dev_priv = dev->dev_private;
263 enum port port = intel_dig_port->port;
264 enum pipe pipe;
265
266 /* modeset should have pipe */
267 if (crtc)
268 return to_intel_crtc(crtc)->pipe;
269
270 /* init time, try to find a pipe with this port selected */
271 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
272 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
273 PANEL_PORT_SELECT_MASK;
274 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
275 return pipe;
276 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
277 return pipe;
278 }
279
280 /* shrug */
281 return PIPE_A;
282}
283
284static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
285{
286 struct drm_device *dev = intel_dp_to_dev(intel_dp);
287
288 if (HAS_PCH_SPLIT(dev))
289 return PCH_PP_CONTROL;
290 else
291 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
292}
293
294static u32 _pp_stat_reg(struct intel_dp *intel_dp)
295{
296 struct drm_device *dev = intel_dp_to_dev(intel_dp);
297
298 if (HAS_PCH_SPLIT(dev))
299 return PCH_PP_STATUS;
300 else
301 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
302}
303
4be73780 304static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 305{
30add22d 306 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 307 struct drm_i915_private *dev_priv = dev->dev_private;
308
bf13e81b 309 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 310}
311
4be73780 312static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 313{
30add22d 314 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 315 struct drm_i915_private *dev_priv = dev->dev_private;
316
bf13e81b 317 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 318}
319
9b984dae
KP		 320static void
321intel_dp_check_edp(struct intel_dp *intel_dp)
322{
30add22d 323 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 324 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 325
9b984dae
KP		 326 if (!is_edp(intel_dp))
327 return;
453c5420 328
4be73780 329 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 330 WARN(1, "eDP powered off while attempting aux channel communication.\n");
331 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 332 I915_READ(_pp_stat_reg(intel_dp)),
333 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 334 }
335}
336
9ee32fea
DV		 337static uint32_t
338intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
339{
340 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
341 struct drm_device *dev = intel_dig_port->base.base.dev;
342 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 343 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 344 uint32_t status;
345 bool done;
346
ef04f00d 347#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 348 if (has_aux_irq)
b18ac466 349 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 350 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 351 else
352 done = wait_for_atomic(C, 10) == 0;
353 if (!done)
354 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
355 has_aux_irq);
356#undef C
357
358 return status;
359}
360
ec5b01dd 361static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 362{
174edf1f
PZ		 363 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
364 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 365
ec5b01dd
DL		 366 /*
367 * The clock divider is based off the hrawclk, and would like to run at
368 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 369 */
ec5b01dd
DL		 370 return index ? 0 : intel_hrawclk(dev) / 2;
371}
372
373static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
374{
375 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
376 struct drm_device *dev = intel_dig_port->base.base.dev;
377
378 if (index)
379 return 0;
380
381 if (intel_dig_port->port == PORT_A) {
382 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 383 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 384 else
b84a1cf8 385 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 386 } else {
387 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
388 }
389}
390
391static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
392{
393 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
394 struct drm_device *dev = intel_dig_port->base.base.dev;
395 struct drm_i915_private *dev_priv = dev->dev_private;
396
397 if (intel_dig_port->port == PORT_A) {
398 if (index)
399 return 0;
400 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 401 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
402 /* Workaround for non-ULT HSW */
bc86625a
CW		 403 switch (index) {
404 case 0: return 63;
405 case 1: return 72;
406 default: return 0;
407 }
ec5b01dd 408 } else {
bc86625a 409 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 410 }
b84a1cf8
RV		 411}
412
ec5b01dd
DL		 413static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
414{
415 return index ? 0 : 100;
416}
417
5ed12a19
DL		 418static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
419 bool has_aux_irq,
420 int send_bytes,
421 uint32_t aux_clock_divider)
422{
423 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
424 struct drm_device *dev = intel_dig_port->base.base.dev;
425 uint32_t precharge, timeout;
426
427 if (IS_GEN6(dev))
428 precharge = 3;
429 else
430 precharge = 5;
431
432 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
433 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
434 else
435 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
436
437 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 438 DP_AUX_CH_CTL_DONE |
5ed12a19 439 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 440 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 441 timeout |
788d4433 442 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 443 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
444 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 445 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 446}
447
b84a1cf8
RV		 448static int
449intel_dp_aux_ch(struct intel_dp *intel_dp,
450 uint8_t *send, int send_bytes,
451 uint8_t *recv, int recv_size)
452{
453 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
454 struct drm_device *dev = intel_dig_port->base.base.dev;
455 struct drm_i915_private *dev_priv = dev->dev_private;
456 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
457 uint32_t ch_data = ch_ctl + 4;
bc86625a 458 uint32_t aux_clock_divider;
b84a1cf8
RV		 459 int i, ret, recv_bytes;
460 uint32_t status;
5ed12a19 461 int try, clock = 0;
4e6b788c 462 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 463 bool vdd;
464
465 vdd = _edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 466
467 /* dp aux is extremely sensitive to irq latency, hence request the
468 * lowest possible wakeup latency and so prevent the cpu from going into
469 * deep sleep states.
470 */
471 pm_qos_update_request(&dev_priv->pm_qos, 0);
472
473 intel_dp_check_edp(intel_dp);
5eb08b69 474
c67a470b
PZ		 475 intel_aux_display_runtime_get(dev_priv);
476
11bee43e
JB		 477 /* Try to wait for any previous AUX channel activity */
478 for (try = 0; try < 3; try++) {
ef04f00d 479 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 480 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
481 break;
482 msleep(1);
483 }
484
485 if (try == 3) {
486 WARN(1, "dp_aux_ch not started status 0x%08x\n",
487 I915_READ(ch_ctl));
9ee32fea
DV		 488 ret = -EBUSY;
489 goto out;
4f7f7b7e
CW		 490 }
491
46a5ae9f
PZ		 492 /* Only 5 data registers! */
493 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
494 ret = -E2BIG;
495 goto out;
496 }
497
ec5b01dd 498 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 499 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
500 has_aux_irq,
501 send_bytes,
502 aux_clock_divider);
5ed12a19 503
bc86625a
CW		 504 /* Must try at least 3 times according to DP spec */
505 for (try = 0; try < 5; try++) {
506 /* Load the send data into the aux channel data registers */
507 for (i = 0; i < send_bytes; i += 4)
508 I915_WRITE(ch_data + i,
509 pack_aux(send + i, send_bytes - i));
510
511 /* Send the command and wait for it to complete */
5ed12a19 512 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 513
514 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
515
516 /* Clear done status and any errors */
517 I915_WRITE(ch_ctl,
518 status |
519 DP_AUX_CH_CTL_DONE |
520 DP_AUX_CH_CTL_TIME_OUT_ERROR |
521 DP_AUX_CH_CTL_RECEIVE_ERROR);
522
523 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
524 DP_AUX_CH_CTL_RECEIVE_ERROR))
525 continue;
526 if (status & DP_AUX_CH_CTL_DONE)
527 break;
528 }
4f7f7b7e 529 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 530 break;
531 }
532
a4fc5ed6 533 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 534 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 535 ret = -EBUSY;
536 goto out;
a4fc5ed6
KP		 537 }
538
539 /* Check for timeout or receive error.
540 * Timeouts occur when the sink is not connected
541 */
a5b3da54 542 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 543 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 544 ret = -EIO;
545 goto out;
a5b3da54 546 }
1ae8c0a5
KP		 547
548 /* Timeouts occur when the device isn't connected, so they're
549 * "normal" -- don't fill the kernel log with these */
a5b3da54 550 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 551 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 552 ret = -ETIMEDOUT;
553 goto out;
a4fc5ed6
KP		 554 }
555
556 /* Unload any bytes sent back from the other side */
557 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
558 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 559 if (recv_bytes > recv_size)
560 recv_bytes = recv_size;
0206e353 561
4f7f7b7e
CW		 562 for (i = 0; i < recv_bytes; i += 4)
563 unpack_aux(I915_READ(ch_data + i),
564 recv + i, recv_bytes - i);
a4fc5ed6 565
9ee32fea
DV		 566 ret = recv_bytes;
567out:
568 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 569 intel_aux_display_runtime_put(dev_priv);
9ee32fea 570
884f19e9
JN		 571 if (vdd)
572 edp_panel_vdd_off(intel_dp, false);
573
9ee32fea 574 return ret;
a4fc5ed6
KP		 575}
576
9d1a1031
JN		 577#define HEADER_SIZE 4
578static ssize_t
579intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 580{
9d1a1031
JN		 581 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
582 uint8_t txbuf[20], rxbuf[20];
583 size_t txsize, rxsize;
a4fc5ed6 584 int ret;
a4fc5ed6 585
9d1a1031
JN		 586 txbuf[0] = msg->request << 4;
587 txbuf[1] = msg->address >> 8;
588 txbuf[2] = msg->address & 0xff;
589 txbuf[3] = msg->size - 1;
46a5ae9f 590
9d1a1031
JN		 591 switch (msg->request & ~DP_AUX_I2C_MOT) {
592 case DP_AUX_NATIVE_WRITE:
593 case DP_AUX_I2C_WRITE:
594 txsize = HEADER_SIZE + msg->size;
595 rxsize = 1;
f51a44b9 596
9d1a1031
JN		 597 if (WARN_ON(txsize > 20))
598 return -E2BIG;
a4fc5ed6 599
9d1a1031 600 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 601
9d1a1031
JN		 602 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
603 if (ret > 0) {
604 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 605
9d1a1031
JN		 606 /* Return payload size. */
607 ret = msg->size;
608 }
609 break;
46a5ae9f 610
9d1a1031
JN		 611 case DP_AUX_NATIVE_READ:
612 case DP_AUX_I2C_READ:
613 txsize = HEADER_SIZE;
614 rxsize = msg->size + 1;
a4fc5ed6 615
9d1a1031
JN		 616 if (WARN_ON(rxsize > 20))
617 return -E2BIG;
a4fc5ed6 618
9d1a1031
JN		 619 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
620 if (ret > 0) {
621 msg->reply = rxbuf[0] >> 4;
622 /*
623 * Assume happy day, and copy the data. The caller is
624 * expected to check msg->reply before touching it.
625 *
626 * Return payload size.
627 */
628 ret--;
629 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 630 }
9d1a1031
JN		 631 break;
632
633 default:
634 ret = -EINVAL;
635 break;
a4fc5ed6 636 }
f51a44b9 637
9d1a1031 638 return ret;
a4fc5ed6
KP		 639}
640
9d1a1031
JN		 641static void
642intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
643{
644 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 645 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
646 enum port port = intel_dig_port->port;
0b99836f 647 const char *name = NULL;
ab2c0672
DA		 648 int ret;
649
33ad6626
JN		 650 switch (port) {
651 case PORT_A:
652 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 653 name = "DPDDC-A";
ab2c0672 654 break;
33ad6626
JN		 655 case PORT_B:
656 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 657 name = "DPDDC-B";
ab2c0672 658 break;
33ad6626
JN		 659 case PORT_C:
660 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 661 name = "DPDDC-C";
ab2c0672 662 break;
33ad6626
JN		 663 case PORT_D:
664 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 665 name = "DPDDC-D";
33ad6626
JN		 666 break;
667 default:
668 BUG();
ab2c0672
DA		 669 }
670
33ad6626
JN		 671 if (!HAS_DDI(dev))
672 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 673
0b99836f 674 intel_dp->aux.name = name;
9d1a1031
JN		 675 intel_dp->aux.dev = dev->dev;
676 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 677
0b99836f
JN		 678 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
679 connector->base.kdev->kobj.name);
8316f337 680
0b99836f
JN		 681 ret = drm_dp_aux_register_i2c_bus(&intel_dp->aux);
682 if (ret < 0) {
683 DRM_ERROR("drm_dp_aux_register_i2c_bus() for %s failed (%d)\n",
684 name, ret);
685 return;
ab2c0672 686 }
8a5e6aeb 687
0b99836f
JN		 688 ret = sysfs_create_link(&connector->base.kdev->kobj,
689 &intel_dp->aux.ddc.dev.kobj,
690 intel_dp->aux.ddc.dev.kobj.name);
691 if (ret < 0) {
692 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
693 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
ab2c0672 694 }
a4fc5ed6
KP		 695}
696
80f65de3
ID		 697static void
698intel_dp_connector_unregister(struct intel_connector *intel_connector)
699{
700 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
701
702 sysfs_remove_link(&intel_connector->base.kdev->kobj,
0b99836f 703 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 704 intel_connector_unregister(intel_connector);
705}
706
c6bb3538
DV		 707static void
708intel_dp_set_clock(struct intel_encoder *encoder,
709 struct intel_crtc_config *pipe_config, int link_bw)
710{
711 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 712 const struct dp_link_dpll *divisor = NULL;
713 int i, count = 0;
c6bb3538
DV		 714
715 if (IS_G4X(dev)) {
9dd4ffdf
CML		 716 divisor = gen4_dpll;
717 count = ARRAY_SIZE(gen4_dpll);
c6bb3538
DV		 718 } else if (IS_HASWELL(dev)) {
719 /* Haswell has special-purpose DP DDI clocks. */
720 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 721 divisor = pch_dpll;
722 count = ARRAY_SIZE(pch_dpll);
c6bb3538 723 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 724 divisor = vlv_dpll;
725 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 726 }
9dd4ffdf
CML		 727
728 if (divisor && count) {
729 for (i = 0; i < count; i++) {
730 if (link_bw == divisor[i].link_bw) {
731 pipe_config->dpll = divisor[i].dpll;
732 pipe_config->clock_set = true;
733 break;
734 }
735 }
c6bb3538
DV		 736 }
737}
738
00c09d70 739bool
5bfe2ac0
DV		 740intel_dp_compute_config(struct intel_encoder *encoder,
741 struct intel_crtc_config *pipe_config)
a4fc5ed6 742{
5bfe2ac0 743 struct drm_device *dev = encoder->base.dev;
36008365 744 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 745 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 746 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 747 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 748 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 749 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 750 int lane_count, clock;
397fe157 751 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
06ea66b6
TP		 752 /* Conveniently, the link BW constants become indices with a shift...*/
753 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 754 int bpp, mode_rate;
06ea66b6 755 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 756 int link_avail, link_clock;
a4fc5ed6 757
bc7d38a4 758 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 759 pipe_config->has_pch_encoder = true;
760
03afc4a2 761 pipe_config->has_dp_encoder = true;
a4fc5ed6 762
dd06f90e
JN		 763 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
764 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
765 adjusted_mode);
2dd24552
JB		 766 if (!HAS_PCH_SPLIT(dev))
767 intel_gmch_panel_fitting(intel_crtc, pipe_config,
768 intel_connector->panel.fitting_mode);
769 else
b074cec8
JB		 770 intel_pch_panel_fitting(intel_crtc, pipe_config,
771 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 772 }
773
cb1793ce 774 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 775 return false;
776
083f9560
DV		 777 DRM_DEBUG_KMS("DP link computation with max lane count %i "
778 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 779 max_lane_count, bws[max_clock],
780 adjusted_mode->crtc_clock);
083f9560 781
36008365
DV		 782 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
783 * bpc in between. */
3e7ca985 784 bpp = pipe_config->pipe_bpp;
6da7f10d
JN		 785 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
786 dev_priv->vbt.edp_bpp < bpp) {
7984211e
ID		 787 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
788 dev_priv->vbt.edp_bpp);
6da7f10d 789 bpp = dev_priv->vbt.edp_bpp;
7984211e 790 }
657445fe 791
36008365 792 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 793 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
794 bpp);
36008365 795
38aecea0
DV		 796 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
797 for (clock = 0; clock <= max_clock; clock++) {
36008365
DV		 798 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
799 link_avail = intel_dp_max_data_rate(link_clock,
800 lane_count);
801
802 if (mode_rate <= link_avail) {
803 goto found;
804 }
805 }
806 }
807 }
c4867936 808
36008365 809 return false;
3685a8f3 810
36008365 811found:
55bc60db
VS		 812 if (intel_dp->color_range_auto) {
813 /*
814 * See:
815 * CEA-861-E - 5.1 Default Encoding Parameters
816 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
817 */
18316c8c 818 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 819 intel_dp->color_range = DP_COLOR_RANGE_16_235;
820 else
821 intel_dp->color_range = 0;
822 }
823
3685a8f3 824 if (intel_dp->color_range)
50f3b016 825 pipe_config->limited_color_range = true;
a4fc5ed6 826
36008365
DV		 827 intel_dp->link_bw = bws[clock];
828 intel_dp->lane_count = lane_count;
657445fe 829 pipe_config->pipe_bpp = bpp;
ff9a6750 830 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 831
36008365
DV		 832 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
833 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 834 pipe_config->port_clock, bpp);
36008365
DV		 835 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
836 mode_rate, link_avail);
a4fc5ed6 837
03afc4a2 838 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 839 adjusted_mode->crtc_clock,
840 pipe_config->port_clock,
03afc4a2 841 &pipe_config->dp_m_n);
9d1a455b 842
c6bb3538
DV		 843 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
844
03afc4a2 845 return true;
a4fc5ed6
KP		 846}
847
7c62a164 848static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 849{
7c62a164
DV		 850 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
851 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
852 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 853 struct drm_i915_private *dev_priv = dev->dev_private;
854 u32 dpa_ctl;
855
ff9a6750 856 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 857 dpa_ctl = I915_READ(DP_A);
858 dpa_ctl &= ~DP_PLL_FREQ_MASK;
859
ff9a6750 860 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 861 /* For a long time we've carried around a ILK-DevA w/a for the
862 * 160MHz clock. If we're really unlucky, it's still required.
863 */
864 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 865 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 866 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 867 } else {
868 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 869 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 870 }
1ce17038 871
ea9b6006
DV		 872 I915_WRITE(DP_A, dpa_ctl);
873
874 POSTING_READ(DP_A);
875 udelay(500);
876}
877
b934223d 878static void intel_dp_mode_set(struct intel_encoder *encoder)
a4fc5ed6 879{
b934223d 880 struct drm_device *dev = encoder->base.dev;
417e822d 881 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 882 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 883 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 884 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
885 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 886
417e822d 887 /*
1a2eb460 888 * There are four kinds of DP registers:
417e822d
KP		 889 *
890 * IBX PCH
1a2eb460
KP		 891 * SNB CPU
892 * IVB CPU
417e822d
KP		 893 * CPT PCH
894 *
895 * IBX PCH and CPU are the same for almost everything,
896 * except that the CPU DP PLL is configured in this
897 * register
898 *
899 * CPT PCH is quite different, having many bits moved
900 * to the TRANS_DP_CTL register instead. That
901 * configuration happens (oddly) in ironlake_pch_enable
902 */
9c9e7927 903
417e822d
KP		 904 /* Preserve the BIOS-computed detected bit. This is
905 * supposed to be read-only.
906 */
907 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 908
417e822d 909 /* Handle DP bits in common between all three register formats */
417e822d 910 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 911 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 912
e0dac65e
WF		 913 if (intel_dp->has_audio) {
914 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 915 pipe_name(crtc->pipe));
ea5b213a 916 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 917 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 918 }
247d89f6 919
417e822d 920 /* Split out the IBX/CPU vs CPT settings */
32f9d658 921
bc7d38a4 922 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 923 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
924 intel_dp->DP |= DP_SYNC_HS_HIGH;
925 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
926 intel_dp->DP |= DP_SYNC_VS_HIGH;
927 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
928
6aba5b6c 929 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 930 intel_dp->DP |= DP_ENHANCED_FRAMING;
931
7c62a164 932 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 933 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 934 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 935 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 936
937 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
938 intel_dp->DP |= DP_SYNC_HS_HIGH;
939 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
940 intel_dp->DP |= DP_SYNC_VS_HIGH;
941 intel_dp->DP |= DP_LINK_TRAIN_OFF;
942
6aba5b6c 943 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 944 intel_dp->DP |= DP_ENHANCED_FRAMING;
945
7c62a164 946 if (crtc->pipe == 1)
417e822d 947 intel_dp->DP |= DP_PIPEB_SELECT;
417e822d
KP		 948 } else {
949 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 950 }
ea9b6006 951
bc7d38a4 952 if (port == PORT_A && !IS_VALLEYVIEW(dev))
7c62a164 953 ironlake_set_pll_cpu_edp(intel_dp);
a4fc5ed6
KP		 954}
955
ffd6749d
PZ		 956#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
957#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 958
1a5ef5b7
PZ		 959#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
960#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 961
ffd6749d
PZ		 962#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
963#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 964
4be73780 965static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 966 u32 mask,
967 u32 value)
bd943159 968{
30add22d 969 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 970 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 971 u32 pp_stat_reg, pp_ctrl_reg;
972
bf13e81b
JN		 973 pp_stat_reg = _pp_stat_reg(intel_dp);
974 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 975
99ea7127 976 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 977 mask, value,
978 I915_READ(pp_stat_reg),
979 I915_READ(pp_ctrl_reg));
32ce697c 980
453c5420 981 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 982 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 983 I915_READ(pp_stat_reg),
984 I915_READ(pp_ctrl_reg));
32ce697c 985 }
54c136d4
CW		 986
987 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 988}
32ce697c 989
4be73780 990static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 991{
992 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 993 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 994}
995
4be73780 996static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 997{
998 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 999 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1000}
1001
4be73780 1002static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1003{
1004 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1005
1006 /* When we disable the VDD override bit last we have to do the manual
1007 * wait. */
1008 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1009 intel_dp->panel_power_cycle_delay);
1010
4be73780 1011 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1012}
1013
4be73780 1014static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1015{
1016 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1017 intel_dp->backlight_on_delay);
1018}
1019
4be73780 1020static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1021{
1022 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1023 intel_dp->backlight_off_delay);
1024}
99ea7127 1025
832dd3c1
KP		 1026/* Read the current pp_control value, unlocking the register if it
1027 * is locked
1028 */
1029
453c5420 1030static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1031{
453c5420
JB		 1032 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1033 struct drm_i915_private *dev_priv = dev->dev_private;
1034 u32 control;
832dd3c1 1035
bf13e81b 1036 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1037 control &= ~PANEL_UNLOCK_MASK;
1038 control |= PANEL_UNLOCK_REGS;
1039 return control;
bd943159
KP		 1040}
1041
adddaaf4 1042static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1043{
30add22d 1044 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1045 struct drm_i915_private *dev_priv = dev->dev_private;
1046 u32 pp;
453c5420 1047 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1048 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1049
97af61f5 1050 if (!is_edp(intel_dp))
adddaaf4 1051 return false;
bd943159
KP		 1052
1053 intel_dp->want_panel_vdd = true;
99ea7127 1054
4be73780 1055 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1056 return need_to_disable;
b0665d57 1057
e9cb81a2
PZ		 1058 intel_runtime_pm_get(dev_priv);
1059
b0665d57 1060 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1061
4be73780
DV		 1062 if (!edp_have_panel_power(intel_dp))
1063 wait_panel_power_cycle(intel_dp);
99ea7127 1064
453c5420 1065 pp = ironlake_get_pp_control(intel_dp);
5d613501 1066 pp |= EDP_FORCE_VDD;
ebf33b18 1067
bf13e81b
JN		 1068 pp_stat_reg = _pp_stat_reg(intel_dp);
1069 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1070
1071 I915_WRITE(pp_ctrl_reg, pp);
1072 POSTING_READ(pp_ctrl_reg);
1073 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1074 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1075 /*
1076 * If the panel wasn't on, delay before accessing aux channel
1077 */
4be73780 1078 if (!edp_have_panel_power(intel_dp)) {
bd943159 1079 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1080 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1081 }
adddaaf4
JN		 1082
1083 return need_to_disable;
1084}
1085
b80d6c78 1086void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4
JN		 1087{
1088 if (is_edp(intel_dp)) {
1089 bool vdd = _edp_panel_vdd_on(intel_dp);
1090
1091 WARN(!vdd, "eDP VDD already requested on\n");
1092 }
5d613501
JB		 1093}
1094
4be73780 1095static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1096{
30add22d 1097 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1098 struct drm_i915_private *dev_priv = dev->dev_private;
1099 u32 pp;
453c5420 1100 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1101
a0e99e68
DV		 1102 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1103
4be73780 1104 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
b0665d57
PZ		 1105 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1106
453c5420 1107 pp = ironlake_get_pp_control(intel_dp);
bd943159 1108 pp &= ~EDP_FORCE_VDD;
bd943159 1109
9f08ef59
PZ		 1110 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1111 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1112
1113 I915_WRITE(pp_ctrl_reg, pp);
1114 POSTING_READ(pp_ctrl_reg);
99ea7127 1115
453c5420
JB		 1116 /* Make sure sequencer is idle before allowing subsequent activity */
1117 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1118 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c
PZ		 1119
1120 if ((pp & POWER_TARGET_ON) == 0)
dce56b3c 1121 intel_dp->last_power_cycle = jiffies;
e9cb81a2
PZ		 1122
1123 intel_runtime_pm_put(dev_priv);
bd943159
KP		 1124 }
1125}
5d613501 1126
4be73780 1127static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1128{
1129 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1130 struct intel_dp, panel_vdd_work);
30add22d 1131 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1132
627f7675 1133 mutex_lock(&dev->mode_config.mutex);
4be73780 1134 edp_panel_vdd_off_sync(intel_dp);
627f7675 1135 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1136}
1137
4be73780 1138static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1139{
97af61f5
KP		 1140 if (!is_edp(intel_dp))
1141 return;
5d613501 1142
bd943159 1143 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1144
bd943159
KP		 1145 intel_dp->want_panel_vdd = false;
1146
1147 if (sync) {
4be73780 1148 edp_panel_vdd_off_sync(intel_dp);
bd943159
KP		 1149 } else {
1150 /*
1151 * Queue the timer to fire a long
1152 * time from now (relative to the power down delay)
1153 * to keep the panel power up across a sequence of operations
1154 */
1155 schedule_delayed_work(&intel_dp->panel_vdd_work,
1156 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1157 }
5d613501
JB		 1158}
1159
4be73780 1160void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1161{
30add22d 1162 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1163 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1164 u32 pp;
453c5420 1165 u32 pp_ctrl_reg;
9934c132 1166
97af61f5 1167 if (!is_edp(intel_dp))
bd943159 1168 return;
99ea7127
KP		 1169
1170 DRM_DEBUG_KMS("Turn eDP power on\n");
1171
4be73780 1172 if (edp_have_panel_power(intel_dp)) {
99ea7127 1173 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1174 return;
99ea7127 1175 }
9934c132 1176
4be73780 1177 wait_panel_power_cycle(intel_dp);
37c6c9b0 1178
bf13e81b 1179 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1180 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1181 if (IS_GEN5(dev)) {
1182 /* ILK workaround: disable reset around power sequence */
1183 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1184 I915_WRITE(pp_ctrl_reg, pp);
1185 POSTING_READ(pp_ctrl_reg);
05ce1a49 1186 }
37c6c9b0 1187
1c0ae80a 1188 pp |= POWER_TARGET_ON;
99ea7127
KP		 1189 if (!IS_GEN5(dev))
1190 pp |= PANEL_POWER_RESET;
1191
453c5420
JB		 1192 I915_WRITE(pp_ctrl_reg, pp);
1193 POSTING_READ(pp_ctrl_reg);
9934c132 1194
4be73780 1195 wait_panel_on(intel_dp);
dce56b3c 1196 intel_dp->last_power_on = jiffies;
9934c132 1197
05ce1a49
KP		 1198 if (IS_GEN5(dev)) {
1199 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1200 I915_WRITE(pp_ctrl_reg, pp);
1201 POSTING_READ(pp_ctrl_reg);
05ce1a49 1202 }
9934c132
JB		 1203}
1204
4be73780 1205void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1206{
30add22d 1207 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1208 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1209 u32 pp;
453c5420 1210 u32 pp_ctrl_reg;
9934c132 1211
97af61f5
KP		 1212 if (!is_edp(intel_dp))
1213 return;
37c6c9b0 1214
99ea7127 1215 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1216
4be73780 1217 edp_wait_backlight_off(intel_dp);
dce56b3c 1218
24f3e092
JN		 1219 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1220
453c5420 1221 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1222 /* We need to switch off panel power _and_ force vdd, for otherwise some
1223 * panels get very unhappy and cease to work. */
b3064154
PJ		 1224 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1225 EDP_BLC_ENABLE);
453c5420 1226
bf13e81b 1227 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1228
849e39f5
PZ		 1229 intel_dp->want_panel_vdd = false;
1230
453c5420
JB		 1231 I915_WRITE(pp_ctrl_reg, pp);
1232 POSTING_READ(pp_ctrl_reg);
9934c132 1233
dce56b3c 1234 intel_dp->last_power_cycle = jiffies;
4be73780 1235 wait_panel_off(intel_dp);
849e39f5
PZ		 1236
1237 /* We got a reference when we enabled the VDD. */
1238 intel_runtime_pm_put(dev_priv);
9934c132
JB		 1239}
1240
4be73780 1241void intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1242{
da63a9f2
PZ		 1243 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1244 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1245 struct drm_i915_private *dev_priv = dev->dev_private;
1246 u32 pp;
453c5420 1247 u32 pp_ctrl_reg;
32f9d658 1248
f01eca2e
KP		 1249 if (!is_edp(intel_dp))
1250 return;
1251
28c97730 1252 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1253 /*
1254 * If we enable the backlight right away following a panel power
1255 * on, we may see slight flicker as the panel syncs with the eDP
1256 * link. So delay a bit to make sure the image is solid before
1257 * allowing it to appear.
1258 */
4be73780 1259 wait_backlight_on(intel_dp);
453c5420 1260 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1261 pp |= EDP_BLC_ENABLE;
453c5420 1262
bf13e81b 1263 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1264
1265 I915_WRITE(pp_ctrl_reg, pp);
1266 POSTING_READ(pp_ctrl_reg);
035aa3de 1267
752aa88a 1268 intel_panel_enable_backlight(intel_dp->attached_connector);
32f9d658
ZW		 1269}
1270
4be73780 1271void intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1272{
30add22d 1273 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1274 struct drm_i915_private *dev_priv = dev->dev_private;
1275 u32 pp;
453c5420 1276 u32 pp_ctrl_reg;
32f9d658 1277
f01eca2e
KP		 1278 if (!is_edp(intel_dp))
1279 return;
1280
752aa88a 1281 intel_panel_disable_backlight(intel_dp->attached_connector);
035aa3de 1282
28c97730 1283 DRM_DEBUG_KMS("\n");
453c5420 1284 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1285 pp &= ~EDP_BLC_ENABLE;
453c5420 1286
bf13e81b 1287 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1288
1289 I915_WRITE(pp_ctrl_reg, pp);
1290 POSTING_READ(pp_ctrl_reg);
dce56b3c 1291 intel_dp->last_backlight_off = jiffies;
32f9d658 1292}
a4fc5ed6 1293
2bd2ad64 1294static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1295{
da63a9f2
PZ		 1296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1297 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1298 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1299 struct drm_i915_private *dev_priv = dev->dev_private;
1300 u32 dpa_ctl;
1301
2bd2ad64
DV		 1302 assert_pipe_disabled(dev_priv,
1303 to_intel_crtc(crtc)->pipe);
1304
d240f20f
JB		 1305 DRM_DEBUG_KMS("\n");
1306 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1307 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1308 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1309
1310 /* We don't adjust intel_dp->DP while tearing down the link, to
1311 * facilitate link retraining (e.g. after hotplug). Hence clear all
1312 * enable bits here to ensure that we don't enable too much. */
1313 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1314 intel_dp->DP |= DP_PLL_ENABLE;
1315 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1316 POSTING_READ(DP_A);
1317 udelay(200);
d240f20f
JB		 1318}
1319
2bd2ad64 1320static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1321{
da63a9f2
PZ		 1322 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1323 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1324 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1325 struct drm_i915_private *dev_priv = dev->dev_private;
1326 u32 dpa_ctl;
1327
2bd2ad64
DV		 1328 assert_pipe_disabled(dev_priv,
1329 to_intel_crtc(crtc)->pipe);
1330
d240f20f 1331 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1332 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1333 "dp pll off, should be on\n");
1334 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1335
1336 /* We can't rely on the value tracked for the DP register in
1337 * intel_dp->DP because link_down must not change that (otherwise link
1338 * re-training will fail. */
298b0b39 1339 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1340 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1341 POSTING_READ(DP_A);
d240f20f
JB		 1342 udelay(200);
1343}
1344
c7ad3810 1345/* If the sink supports it, try to set the power state appropriately */
c19b0669 1346void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1347{
1348 int ret, i;
1349
1350 /* Should have a valid DPCD by this point */
1351 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1352 return;
1353
1354 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1355 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1356 DP_SET_POWER_D3);
c7ad3810
JB		 1357 if (ret != 1)
1358 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1359 } else {
1360 /*
1361 * When turning on, we need to retry for 1ms to give the sink
1362 * time to wake up.
1363 */
1364 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1365 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1366 DP_SET_POWER_D0);
c7ad3810
JB		 1367 if (ret == 1)
1368 break;
1369 msleep(1);
1370 }
1371 }
1372}
1373
19d8fe15
DV		 1374static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1375 enum pipe *pipe)
d240f20f 1376{
19d8fe15 1377 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1378 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1379 struct drm_device *dev = encoder->base.dev;
1380 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1381 enum intel_display_power_domain power_domain;
1382 u32 tmp;
1383
1384 power_domain = intel_display_port_power_domain(encoder);
1385 if (!intel_display_power_enabled(dev_priv, power_domain))
1386 return false;
1387
1388 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1389
1390 if (!(tmp & DP_PORT_EN))
1391 return false;
1392
bc7d38a4 1393 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1394 *pipe = PORT_TO_PIPE_CPT(tmp);
bc7d38a4 1395 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1396 *pipe = PORT_TO_PIPE(tmp);
1397 } else {
1398 u32 trans_sel;
1399 u32 trans_dp;
1400 int i;
1401
1402 switch (intel_dp->output_reg) {
1403 case PCH_DP_B:
1404 trans_sel = TRANS_DP_PORT_SEL_B;
1405 break;
1406 case PCH_DP_C:
1407 trans_sel = TRANS_DP_PORT_SEL_C;
1408 break;
1409 case PCH_DP_D:
1410 trans_sel = TRANS_DP_PORT_SEL_D;
1411 break;
1412 default:
1413 return true;
1414 }
1415
1416 for_each_pipe(i) {
1417 trans_dp = I915_READ(TRANS_DP_CTL(i));
1418 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1419 *pipe = i;
1420 return true;
1421 }
1422 }
19d8fe15 1423
4a0833ec
DV		 1424 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1425 intel_dp->output_reg);
1426 }
d240f20f 1427
19d8fe15
DV		 1428 return true;
1429}
d240f20f 1430
045ac3b5
JB		 1431static void intel_dp_get_config(struct intel_encoder *encoder,
1432 struct intel_crtc_config *pipe_config)
1433{
1434 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1435 u32 tmp, flags = 0;
63000ef6
XZ		 1436 struct drm_device *dev = encoder->base.dev;
1437 struct drm_i915_private *dev_priv = dev->dev_private;
1438 enum port port = dp_to_dig_port(intel_dp)->port;
1439 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1440 int dotclock;
045ac3b5 1441
63000ef6
XZ		 1442 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1443 tmp = I915_READ(intel_dp->output_reg);
1444 if (tmp & DP_SYNC_HS_HIGH)
1445 flags |= DRM_MODE_FLAG_PHSYNC;
1446 else
1447 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1448
63000ef6
XZ		 1449 if (tmp & DP_SYNC_VS_HIGH)
1450 flags |= DRM_MODE_FLAG_PVSYNC;
1451 else
1452 flags |= DRM_MODE_FLAG_NVSYNC;
1453 } else {
1454 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1455 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1456 flags |= DRM_MODE_FLAG_PHSYNC;
1457 else
1458 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1459
63000ef6
XZ		 1460 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1461 flags |= DRM_MODE_FLAG_PVSYNC;
1462 else
1463 flags |= DRM_MODE_FLAG_NVSYNC;
1464 }
045ac3b5
JB		 1465
1466 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1467
eb14cb74
VS		 1468 pipe_config->has_dp_encoder = true;
1469
1470 intel_dp_get_m_n(crtc, pipe_config);
1471
18442d08 1472 if (port == PORT_A) {
f1f644dc
JB		 1473 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1474 pipe_config->port_clock = 162000;
1475 else
1476 pipe_config->port_clock = 270000;
1477 }
18442d08
VS		 1478
1479 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1480 &pipe_config->dp_m_n);
1481
1482 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1483 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1484
241bfc38 1485 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1486
c6cd2ee2
JN		 1487 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1488 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1489 /*
1490 * This is a big fat ugly hack.
1491 *
1492 * Some machines in UEFI boot mode provide us a VBT that has 18
1493 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1494 * unknown we fail to light up. Yet the same BIOS boots up with
1495 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1496 * max, not what it tells us to use.
1497 *
1498 * Note: This will still be broken if the eDP panel is not lit
1499 * up by the BIOS, and thus we can't get the mode at module
1500 * load.
1501 */
1502 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1503 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1504 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1505 }
045ac3b5
JB		 1506}
1507
a031d709 1508static bool is_edp_psr(struct drm_device *dev)
2293bb5c 1509{
a031d709
RV		 1510 struct drm_i915_private *dev_priv = dev->dev_private;
1511
1512 return dev_priv->psr.sink_support;
2293bb5c
SK		 1513}
1514
2b28bb1b
RV		 1515static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1516{
1517 struct drm_i915_private *dev_priv = dev->dev_private;
1518
18b5992c 1519 if (!HAS_PSR(dev))
2b28bb1b
RV		 1520 return false;
1521
18b5992c 1522 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1523}
1524
1525static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1526 struct edp_vsc_psr *vsc_psr)
1527{
1528 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1529 struct drm_device *dev = dig_port->base.base.dev;
1530 struct drm_i915_private *dev_priv = dev->dev_private;
1531 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1532 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1533 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1534 uint32_t *data = (uint32_t *) vsc_psr;
1535 unsigned int i;
1536
1537 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1538 the video DIP being updated before program video DIP data buffer
1539 registers for DIP being updated. */
1540 I915_WRITE(ctl_reg, 0);
1541 POSTING_READ(ctl_reg);
1542
1543 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1544 if (i < sizeof(struct edp_vsc_psr))
1545 I915_WRITE(data_reg + i, *data++);
1546 else
1547 I915_WRITE(data_reg + i, 0);
1548 }
1549
1550 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1551 POSTING_READ(ctl_reg);
1552}
1553
1554static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1555{
1556 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1557 struct drm_i915_private *dev_priv = dev->dev_private;
1558 struct edp_vsc_psr psr_vsc;
1559
1560 if (intel_dp->psr_setup_done)
1561 return;
1562
1563 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1564 memset(&psr_vsc, 0, sizeof(psr_vsc));
1565 psr_vsc.sdp_header.HB0 = 0;
1566 psr_vsc.sdp_header.HB1 = 0x7;
1567 psr_vsc.sdp_header.HB2 = 0x2;
1568 psr_vsc.sdp_header.HB3 = 0x8;
1569 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1570
1571 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1572 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1573 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1574
1575 intel_dp->psr_setup_done = true;
1576}
1577
1578static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1579{
1580 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1581 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1582 uint32_t aux_clock_divider;
2b28bb1b
RV		 1583 int precharge = 0x3;
1584 int msg_size = 5; /* Header(4) + Message(1) */
1585
ec5b01dd
DL		 1586 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1587
2b28bb1b
RV		 1588 /* Enable PSR in sink */
1589 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
9d1a1031
JN		 1590 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1591 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 1592 else
9d1a1031
JN		 1593 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1594 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 1595
1596 /* Setup AUX registers */
18b5992c
BW		 1597 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1598 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1599 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1600 DP_AUX_CH_CTL_TIME_OUT_400us |
1601 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1602 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1603 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1604}
1605
1606static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1607{
1608 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1609 struct drm_i915_private *dev_priv = dev->dev_private;
1610 uint32_t max_sleep_time = 0x1f;
1611 uint32_t idle_frames = 1;
1612 uint32_t val = 0x0;
ed8546ac 1613 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
2b28bb1b
RV		 1614
1615 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1616 val |= EDP_PSR_LINK_STANDBY;
1617 val |= EDP_PSR_TP2_TP3_TIME_0us;
1618 val |= EDP_PSR_TP1_TIME_0us;
1619 val |= EDP_PSR_SKIP_AUX_EXIT;
1620 } else
1621 val |= EDP_PSR_LINK_DISABLE;
1622
18b5992c 1623 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 1624 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 1625 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1626 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1627 EDP_PSR_ENABLE);
1628}
1629
3f51e471
RV		 1630static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1631{
1632 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1633 struct drm_device *dev = dig_port->base.base.dev;
1634 struct drm_i915_private *dev_priv = dev->dev_private;
1635 struct drm_crtc *crtc = dig_port->base.base.crtc;
1636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1637 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1638 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1639
a031d709
RV		 1640 dev_priv->psr.source_ok = false;
1641
18b5992c 1642 if (!HAS_PSR(dev)) {
3f51e471 1643 DRM_DEBUG_KMS("PSR not supported on this platform\n");
3f51e471
RV		 1644 return false;
1645 }
1646
1647 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1648 (dig_port->port != PORT_A)) {
1649 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1650 return false;
1651 }
1652
d330a953 1653 if (!i915.enable_psr) {
105b7c11 1654 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1655 return false;
1656 }
1657
cd234b0b
CW		 1658 crtc = dig_port->base.base.crtc;
1659 if (crtc == NULL) {
1660 DRM_DEBUG_KMS("crtc not active for PSR\n");
cd234b0b
CW		 1661 return false;
1662 }
1663
1664 intel_crtc = to_intel_crtc(crtc);
20ddf665 1665 if (!intel_crtc_active(crtc)) {
3f51e471 1666 DRM_DEBUG_KMS("crtc not active for PSR\n");
3f51e471
RV		 1667 return false;
1668 }
1669
cd234b0b 1670 obj = to_intel_framebuffer(crtc->fb)->obj;
3f51e471
RV		 1671 if (obj->tiling_mode != I915_TILING_X ||
1672 obj->fence_reg == I915_FENCE_REG_NONE) {
1673 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
3f51e471
RV		 1674 return false;
1675 }
1676
1677 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1678 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
3f51e471
RV		 1679 return false;
1680 }
1681
1682 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1683 S3D_ENABLE) {
1684 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1685 return false;
1686 }
1687
ca73b4f0 1688 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1689 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1690 return false;
1691 }
1692
a031d709 1693 dev_priv->psr.source_ok = true;
3f51e471
RV		 1694 return true;
1695}
1696
3d739d92 1697static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1698{
1699 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1700
3f51e471
RV		 1701 if (!intel_edp_psr_match_conditions(intel_dp) ||
1702 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1703 return;
1704
1705 /* Setup PSR once */
1706 intel_edp_psr_setup(intel_dp);
1707
1708 /* Enable PSR on the panel */
1709 intel_edp_psr_enable_sink(intel_dp);
1710
1711 /* Enable PSR on the host */
1712 intel_edp_psr_enable_source(intel_dp);
1713}
1714
3d739d92
RV		 1715void intel_edp_psr_enable(struct intel_dp *intel_dp)
1716{
1717 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1718
1719 if (intel_edp_psr_match_conditions(intel_dp) &&
1720 !intel_edp_is_psr_enabled(dev))
1721 intel_edp_psr_do_enable(intel_dp);
1722}
1723
2b28bb1b
RV		 1724void intel_edp_psr_disable(struct intel_dp *intel_dp)
1725{
1726 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1727 struct drm_i915_private *dev_priv = dev->dev_private;
1728
1729 if (!intel_edp_is_psr_enabled(dev))
1730 return;
1731
18b5992c
BW		 1732 I915_WRITE(EDP_PSR_CTL(dev),
1733 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2b28bb1b
RV		 1734
1735 /* Wait till PSR is idle */
18b5992c 1736 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2b28bb1b
RV		 1737 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1738 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1739}
1740
3d739d92
RV		 1741void intel_edp_psr_update(struct drm_device *dev)
1742{
1743 struct intel_encoder *encoder;
1744 struct intel_dp *intel_dp = NULL;
1745
1746 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1747 if (encoder->type == INTEL_OUTPUT_EDP) {
1748 intel_dp = enc_to_intel_dp(&encoder->base);
1749
a031d709 1750 if (!is_edp_psr(dev))
3d739d92
RV		 1751 return;
1752
1753 if (!intel_edp_psr_match_conditions(intel_dp))
1754 intel_edp_psr_disable(intel_dp);
1755 else
1756 if (!intel_edp_is_psr_enabled(dev))
1757 intel_edp_psr_do_enable(intel_dp);
1758 }
1759}
1760
e8cb4558 1761static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1762{
e8cb4558 1763 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1764 enum port port = dp_to_dig_port(intel_dp)->port;
1765 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1766
1767 /* Make sure the panel is off before trying to change the mode. But also
1768 * ensure that we have vdd while we switch off the panel. */
24f3e092 1769 intel_edp_panel_vdd_on(intel_dp);
4be73780 1770 intel_edp_backlight_off(intel_dp);
fdbc3b1f 1771 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 1772 intel_edp_panel_off(intel_dp);
3739850b
DV		 1773
1774 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1775 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1776 intel_dp_link_down(intel_dp);
d240f20f
JB		 1777}
1778
2bd2ad64 1779static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1780{
2bd2ad64 1781 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1782 enum port port = dp_to_dig_port(intel_dp)->port;
b2634017 1783 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1784
982a3866 1785 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
3739850b 1786 intel_dp_link_down(intel_dp);
b2634017
JB		 1787 if (!IS_VALLEYVIEW(dev))
1788 ironlake_edp_pll_off(intel_dp);
3739850b 1789 }
2bd2ad64
DV		 1790}
1791
e8cb4558 1792static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1793{
e8cb4558
DV		 1794 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1795 struct drm_device *dev = encoder->base.dev;
1796 struct drm_i915_private *dev_priv = dev->dev_private;
1797 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1798
0c33d8d7
DV		 1799 if (WARN_ON(dp_reg & DP_PORT_EN))
1800 return;
5d613501 1801
24f3e092 1802 intel_edp_panel_vdd_on(intel_dp);
f01eca2e 1803 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1804 intel_dp_start_link_train(intel_dp);
4be73780
DV		 1805 intel_edp_panel_on(intel_dp);
1806 edp_panel_vdd_off(intel_dp, true);
33a34e4e 1807 intel_dp_complete_link_train(intel_dp);
3ab9c637 1808 intel_dp_stop_link_train(intel_dp);
ab1f90f9 1809}
89b667f8 1810
ecff4f3b
JN		 1811static void g4x_enable_dp(struct intel_encoder *encoder)
1812{
828f5c6e
JN		 1813 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1814
ecff4f3b 1815 intel_enable_dp(encoder);
4be73780 1816 intel_edp_backlight_on(intel_dp);
ab1f90f9 1817}
89b667f8 1818
ab1f90f9
JN		 1819static void vlv_enable_dp(struct intel_encoder *encoder)
1820{
828f5c6e
JN		 1821 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1822
4be73780 1823 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 1824}
1825
ecff4f3b 1826static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 1827{
1828 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1829 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1830
1831 if (dport->port == PORT_A)
1832 ironlake_edp_pll_on(intel_dp);
1833}
1834
1835static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1836{
2bd2ad64 1837 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1838 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1839 struct drm_device *dev = encoder->base.dev;
89b667f8 1840 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 1841 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 1842 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 1843 int pipe = intel_crtc->pipe;
bf13e81b 1844 struct edp_power_seq power_seq;
ab1f90f9 1845 u32 val;
a4fc5ed6 1846
ab1f90f9 1847 mutex_lock(&dev_priv->dpio_lock);
89b667f8 1848
ab3c759a 1849 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 1850 val = 0;
1851 if (pipe)
1852 val |= (1<<21);
1853 else
1854 val &= ~(1<<21);
1855 val |= 0x001000c4;
ab3c759a
CML		 1856 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1857 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1858 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 1859
ab1f90f9
JN		 1860 mutex_unlock(&dev_priv->dpio_lock);
1861
2cac613b
ID		 1862 if (is_edp(intel_dp)) {
1863 /* init power sequencer on this pipe and port */
1864 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1865 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1866 &power_seq);
1867 }
bf13e81b 1868
ab1f90f9
JN		 1869 intel_enable_dp(encoder);
1870
e4607fcf 1871 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 1872}
1873
ecff4f3b 1874static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 1875{
1876 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1877 struct drm_device *dev = encoder->base.dev;
1878 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 1879 struct intel_crtc *intel_crtc =
1880 to_intel_crtc(encoder->base.crtc);
e4607fcf 1881 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 1882 int pipe = intel_crtc->pipe;
89b667f8 1883
89b667f8 1884 /* Program Tx lane resets to default */
0980a60f 1885 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 1886 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 1887 DPIO_PCS_TX_LANE2_RESET |
1888 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 1889 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 1890 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1891 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1892 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1893 DPIO_PCS_CLK_SOFT_RESET);
1894
1895 /* Fix up inter-pair skew failure */
ab3c759a
CML		 1896 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1897 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1898 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 1899 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 1900}
1901
1902/*
df0c237d
JB		 1903 * Native read with retry for link status and receiver capability reads for
1904 * cases where the sink may still be asleep.
9d1a1031
JN		 1905 *
1906 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
1907 * supposed to retry 3 times per the spec.
a4fc5ed6 1908 */
9d1a1031
JN		 1909static ssize_t
1910intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
1911 void *buffer, size_t size)
a4fc5ed6 1912{
9d1a1031
JN		 1913 ssize_t ret;
1914 int i;
61da5fab 1915
61da5fab 1916 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1917 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
1918 if (ret == size)
1919 return ret;
61da5fab
JB		 1920 msleep(1);
1921 }
a4fc5ed6 1922
9d1a1031 1923 return ret;
a4fc5ed6
KP		 1924}
1925
1926/*
1927 * Fetch AUX CH registers 0x202 - 0x207 which contain
1928 * link status information
1929 */
1930static bool
93f62dad 1931intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1932{
9d1a1031
JN		 1933 return intel_dp_dpcd_read_wake(&intel_dp->aux,
1934 DP_LANE0_1_STATUS,
1935 link_status,
1936 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 1937}
1938
a4fc5ed6
KP		 1939/*
1940 * These are source-specific values; current Intel hardware supports
1941 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1942 */
a4fc5ed6
KP		 1943
1944static uint8_t
1a2eb460 1945intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1946{
30add22d 1947 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1948 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1949
8f93f4f1 1950 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
e2fa6fba 1951 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 1952 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 1953 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 1954 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 1955 return DP_TRAIN_VOLTAGE_SWING_1200;
1956 else
1957 return DP_TRAIN_VOLTAGE_SWING_800;
1958}
1959
1960static uint8_t
1961intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1962{
30add22d 1963 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1964 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1965
8f93f4f1
PZ		 1966 if (IS_BROADWELL(dev)) {
1967 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1968 case DP_TRAIN_VOLTAGE_SWING_400:
1969 case DP_TRAIN_VOLTAGE_SWING_600:
1970 return DP_TRAIN_PRE_EMPHASIS_6;
1971 case DP_TRAIN_VOLTAGE_SWING_800:
1972 return DP_TRAIN_PRE_EMPHASIS_3_5;
1973 case DP_TRAIN_VOLTAGE_SWING_1200:
1974 default:
1975 return DP_TRAIN_PRE_EMPHASIS_0;
1976 }
1977 } else if (IS_HASWELL(dev)) {
d6c0d722
PZ		 1978 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1979 case DP_TRAIN_VOLTAGE_SWING_400:
1980 return DP_TRAIN_PRE_EMPHASIS_9_5;
1981 case DP_TRAIN_VOLTAGE_SWING_600:
1982 return DP_TRAIN_PRE_EMPHASIS_6;
1983 case DP_TRAIN_VOLTAGE_SWING_800:
1984 return DP_TRAIN_PRE_EMPHASIS_3_5;
1985 case DP_TRAIN_VOLTAGE_SWING_1200:
1986 default:
1987 return DP_TRAIN_PRE_EMPHASIS_0;
1988 }
e2fa6fba
P		 1989 } else if (IS_VALLEYVIEW(dev)) {
1990 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1991 case DP_TRAIN_VOLTAGE_SWING_400:
1992 return DP_TRAIN_PRE_EMPHASIS_9_5;
1993 case DP_TRAIN_VOLTAGE_SWING_600:
1994 return DP_TRAIN_PRE_EMPHASIS_6;
1995 case DP_TRAIN_VOLTAGE_SWING_800:
1996 return DP_TRAIN_PRE_EMPHASIS_3_5;
1997 case DP_TRAIN_VOLTAGE_SWING_1200:
1998 default:
1999 return DP_TRAIN_PRE_EMPHASIS_0;
2000 }
bc7d38a4 2001 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2002 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2003 case DP_TRAIN_VOLTAGE_SWING_400:
2004 return DP_TRAIN_PRE_EMPHASIS_6;
2005 case DP_TRAIN_VOLTAGE_SWING_600:
2006 case DP_TRAIN_VOLTAGE_SWING_800:
2007 return DP_TRAIN_PRE_EMPHASIS_3_5;
2008 default:
2009 return DP_TRAIN_PRE_EMPHASIS_0;
2010 }
2011 } else {
2012 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2013 case DP_TRAIN_VOLTAGE_SWING_400:
2014 return DP_TRAIN_PRE_EMPHASIS_6;
2015 case DP_TRAIN_VOLTAGE_SWING_600:
2016 return DP_TRAIN_PRE_EMPHASIS_6;
2017 case DP_TRAIN_VOLTAGE_SWING_800:
2018 return DP_TRAIN_PRE_EMPHASIS_3_5;
2019 case DP_TRAIN_VOLTAGE_SWING_1200:
2020 default:
2021 return DP_TRAIN_PRE_EMPHASIS_0;
2022 }
a4fc5ed6
KP		 2023 }
2024}
2025
e2fa6fba
P		 2026static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2027{
2028 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2029 struct drm_i915_private *dev_priv = dev->dev_private;
2030 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2031 struct intel_crtc *intel_crtc =
2032 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2033 unsigned long demph_reg_value, preemph_reg_value,
2034 uniqtranscale_reg_value;
2035 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2036 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2037 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2038
2039 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2040 case DP_TRAIN_PRE_EMPHASIS_0:
2041 preemph_reg_value = 0x0004000;
2042 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2043 case DP_TRAIN_VOLTAGE_SWING_400:
2044 demph_reg_value = 0x2B405555;
2045 uniqtranscale_reg_value = 0x552AB83A;
2046 break;
2047 case DP_TRAIN_VOLTAGE_SWING_600:
2048 demph_reg_value = 0x2B404040;
2049 uniqtranscale_reg_value = 0x5548B83A;
2050 break;
2051 case DP_TRAIN_VOLTAGE_SWING_800:
2052 demph_reg_value = 0x2B245555;
2053 uniqtranscale_reg_value = 0x5560B83A;
2054 break;
2055 case DP_TRAIN_VOLTAGE_SWING_1200:
2056 demph_reg_value = 0x2B405555;
2057 uniqtranscale_reg_value = 0x5598DA3A;
2058 break;
2059 default:
2060 return 0;
2061 }
2062 break;
2063 case DP_TRAIN_PRE_EMPHASIS_3_5:
2064 preemph_reg_value = 0x0002000;
2065 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2066 case DP_TRAIN_VOLTAGE_SWING_400:
2067 demph_reg_value = 0x2B404040;
2068 uniqtranscale_reg_value = 0x5552B83A;
2069 break;
2070 case DP_TRAIN_VOLTAGE_SWING_600:
2071 demph_reg_value = 0x2B404848;
2072 uniqtranscale_reg_value = 0x5580B83A;
2073 break;
2074 case DP_TRAIN_VOLTAGE_SWING_800:
2075 demph_reg_value = 0x2B404040;
2076 uniqtranscale_reg_value = 0x55ADDA3A;
2077 break;
2078 default:
2079 return 0;
2080 }
2081 break;
2082 case DP_TRAIN_PRE_EMPHASIS_6:
2083 preemph_reg_value = 0x0000000;
2084 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2085 case DP_TRAIN_VOLTAGE_SWING_400:
2086 demph_reg_value = 0x2B305555;
2087 uniqtranscale_reg_value = 0x5570B83A;
2088 break;
2089 case DP_TRAIN_VOLTAGE_SWING_600:
2090 demph_reg_value = 0x2B2B4040;
2091 uniqtranscale_reg_value = 0x55ADDA3A;
2092 break;
2093 default:
2094 return 0;
2095 }
2096 break;
2097 case DP_TRAIN_PRE_EMPHASIS_9_5:
2098 preemph_reg_value = 0x0006000;
2099 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2100 case DP_TRAIN_VOLTAGE_SWING_400:
2101 demph_reg_value = 0x1B405555;
2102 uniqtranscale_reg_value = 0x55ADDA3A;
2103 break;
2104 default:
2105 return 0;
2106 }
2107 break;
2108 default:
2109 return 0;
2110 }
2111
0980a60f 2112 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2113 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2114 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2115 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2116 uniqtranscale_reg_value);
ab3c759a
CML		 2117 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2118 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2119 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2120 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2121 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2122
2123 return 0;
2124}
2125
a4fc5ed6 2126static void
0301b3ac
JN		 2127intel_get_adjust_train(struct intel_dp *intel_dp,
2128 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2129{
2130 uint8_t v = 0;
2131 uint8_t p = 0;
2132 int lane;
1a2eb460
KP		 2133 uint8_t voltage_max;
2134 uint8_t preemph_max;
a4fc5ed6 2135
33a34e4e 2136 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2137 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2138 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2139
2140 if (this_v > v)
2141 v = this_v;
2142 if (this_p > p)
2143 p = this_p;
2144 }
2145
1a2eb460 2146 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2147 if (v >= voltage_max)
2148 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2149
1a2eb460
KP		 2150 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2151 if (p >= preemph_max)
2152 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2153
2154 for (lane = 0; lane < 4; lane++)
33a34e4e 2155 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2156}
2157
2158static uint32_t
f0a3424e 2159intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2160{
3cf2efb1 2161 uint32_t signal_levels = 0;
a4fc5ed6 2162
3cf2efb1 2163 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2164 case DP_TRAIN_VOLTAGE_SWING_400:
2165 default:
2166 signal_levels |= DP_VOLTAGE_0_4;
2167 break;
2168 case DP_TRAIN_VOLTAGE_SWING_600:
2169 signal_levels |= DP_VOLTAGE_0_6;
2170 break;
2171 case DP_TRAIN_VOLTAGE_SWING_800:
2172 signal_levels |= DP_VOLTAGE_0_8;
2173 break;
2174 case DP_TRAIN_VOLTAGE_SWING_1200:
2175 signal_levels |= DP_VOLTAGE_1_2;
2176 break;
2177 }
3cf2efb1 2178 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2179 case DP_TRAIN_PRE_EMPHASIS_0:
2180 default:
2181 signal_levels |= DP_PRE_EMPHASIS_0;
2182 break;
2183 case DP_TRAIN_PRE_EMPHASIS_3_5:
2184 signal_levels |= DP_PRE_EMPHASIS_3_5;
2185 break;
2186 case DP_TRAIN_PRE_EMPHASIS_6:
2187 signal_levels |= DP_PRE_EMPHASIS_6;
2188 break;
2189 case DP_TRAIN_PRE_EMPHASIS_9_5:
2190 signal_levels |= DP_PRE_EMPHASIS_9_5;
2191 break;
2192 }
2193 return signal_levels;
2194}
2195
e3421a18
ZW		 2196/* Gen6's DP voltage swing and pre-emphasis control */
2197static uint32_t
2198intel_gen6_edp_signal_levels(uint8_t train_set)
2199{
3c5a62b5
YL		 2200 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2201 DP_TRAIN_PRE_EMPHASIS_MASK);
2202 switch (signal_levels) {
e3421a18 2203 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2204 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2205 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2206 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2207 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2208 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2209 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2210 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2211 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2212 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2213 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2214 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2215 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2216 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2217 default:
3c5a62b5
YL		 2218 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2219 "0x%x\n", signal_levels);
2220 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2221 }
2222}
2223
1a2eb460
KP		 2224/* Gen7's DP voltage swing and pre-emphasis control */
2225static uint32_t
2226intel_gen7_edp_signal_levels(uint8_t train_set)
2227{
2228 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2229 DP_TRAIN_PRE_EMPHASIS_MASK);
2230 switch (signal_levels) {
2231 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2232 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2233 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2234 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2235 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2236 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2237
2238 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2239 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2240 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2241 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2242
2243 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2244 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2245 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2246 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2247
2248 default:
2249 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2250 "0x%x\n", signal_levels);
2251 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2252 }
2253}
2254
d6c0d722
PZ		 2255/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2256static uint32_t
f0a3424e 2257intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2258{
d6c0d722
PZ		 2259 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2260 DP_TRAIN_PRE_EMPHASIS_MASK);
2261 switch (signal_levels) {
2262 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2263 return DDI_BUF_EMP_400MV_0DB_HSW;
2264 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2265 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2266 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2267 return DDI_BUF_EMP_400MV_6DB_HSW;
2268 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2269 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2270
d6c0d722
PZ		 2271 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2272 return DDI_BUF_EMP_600MV_0DB_HSW;
2273 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2274 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2275 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2276 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2277
d6c0d722
PZ		 2278 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2279 return DDI_BUF_EMP_800MV_0DB_HSW;
2280 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2281 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2282 default:
2283 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2284 "0x%x\n", signal_levels);
2285 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2286 }
a4fc5ed6
KP		 2287}
2288
8f93f4f1
PZ		 2289static uint32_t
2290intel_bdw_signal_levels(uint8_t train_set)
2291{
2292 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2293 DP_TRAIN_PRE_EMPHASIS_MASK);
2294 switch (signal_levels) {
2295 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2296 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2297 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2298 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2299 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2300 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2301
2302 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2303 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2304 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2305 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2306 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2307 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2308
2309 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2310 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2311 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2312 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2313
2314 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2315 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2316
2317 default:
2318 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2319 "0x%x\n", signal_levels);
2320 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2321 }
2322}
2323
f0a3424e
PZ		 2324/* Properly updates "DP" with the correct signal levels. */
2325static void
2326intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2327{
2328 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2329 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2330 struct drm_device *dev = intel_dig_port->base.base.dev;
2331 uint32_t signal_levels, mask;
2332 uint8_t train_set = intel_dp->train_set[0];
2333
8f93f4f1
PZ		 2334 if (IS_BROADWELL(dev)) {
2335 signal_levels = intel_bdw_signal_levels(train_set);
2336 mask = DDI_BUF_EMP_MASK;
2337 } else if (IS_HASWELL(dev)) {
f0a3424e
PZ		 2338 signal_levels = intel_hsw_signal_levels(train_set);
2339 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 2340 } else if (IS_VALLEYVIEW(dev)) {
2341 signal_levels = intel_vlv_signal_levels(intel_dp);
2342 mask = 0;
bc7d38a4 2343 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2344 signal_levels = intel_gen7_edp_signal_levels(train_set);
2345 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2346 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2347 signal_levels = intel_gen6_edp_signal_levels(train_set);
2348 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2349 } else {
2350 signal_levels = intel_gen4_signal_levels(train_set);
2351 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2352 }
2353
2354 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2355
2356 *DP = (*DP & ~mask) | signal_levels;
2357}
2358
a4fc5ed6 2359static bool
ea5b213a 2360intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2361 uint32_t *DP,
58e10eb9 2362 uint8_t dp_train_pat)
a4fc5ed6 2363{
174edf1f
PZ		 2364 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2365 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2366 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2367 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2368 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2369 int ret, len;
a4fc5ed6 2370
22b8bf17 2371 if (HAS_DDI(dev)) {
3ab9c637 2372 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2373
2374 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2375 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2376 else
2377 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2378
2379 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2380 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2381 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2382 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2383
2384 break;
2385 case DP_TRAINING_PATTERN_1:
2386 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2387 break;
2388 case DP_TRAINING_PATTERN_2:
2389 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2390 break;
2391 case DP_TRAINING_PATTERN_3:
2392 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2393 break;
2394 }
174edf1f 2395 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2396
bc7d38a4 2397 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2398 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2399
2400 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2401 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2402 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2403 break;
2404 case DP_TRAINING_PATTERN_1:
70aff66c 2405 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2406 break;
2407 case DP_TRAINING_PATTERN_2:
70aff66c 2408 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2409 break;
2410 case DP_TRAINING_PATTERN_3:
2411 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2412 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2413 break;
2414 }
2415
2416 } else {
70aff66c 2417 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2418
2419 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2420 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2421 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2422 break;
2423 case DP_TRAINING_PATTERN_1:
70aff66c 2424 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2425 break;
2426 case DP_TRAINING_PATTERN_2:
70aff66c 2427 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2428 break;
2429 case DP_TRAINING_PATTERN_3:
2430 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2431 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2432 break;
2433 }
2434 }
2435
70aff66c 2436 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 2437 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2438
2cdfe6c8
JN		 2439 buf[0] = dp_train_pat;
2440 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 2441 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 2442 /* don't write DP_TRAINING_LANEx_SET on disable */
2443 len = 1;
2444 } else {
2445 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2446 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2447 len = intel_dp->lane_count + 1;
47ea7542 2448 }
a4fc5ed6 2449
9d1a1031
JN		 2450 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
2451 buf, len);
2cdfe6c8
JN		 2452
2453 return ret == len;
a4fc5ed6
KP		 2454}
2455
70aff66c
JN		 2456static bool
2457intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2458 uint8_t dp_train_pat)
2459{
953d22e8 2460 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 2461 intel_dp_set_signal_levels(intel_dp, DP);
2462 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2463}
2464
2465static bool
2466intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 2467 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 2468{
2469 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2470 struct drm_device *dev = intel_dig_port->base.base.dev;
2471 struct drm_i915_private *dev_priv = dev->dev_private;
2472 int ret;
2473
2474 intel_get_adjust_train(intel_dp, link_status);
2475 intel_dp_set_signal_levels(intel_dp, DP);
2476
2477 I915_WRITE(intel_dp->output_reg, *DP);
2478 POSTING_READ(intel_dp->output_reg);
2479
9d1a1031
JN		 2480 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
2481 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 2482
2483 return ret == intel_dp->lane_count;
2484}
2485
3ab9c637
ID		 2486static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2487{
2488 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2489 struct drm_device *dev = intel_dig_port->base.base.dev;
2490 struct drm_i915_private *dev_priv = dev->dev_private;
2491 enum port port = intel_dig_port->port;
2492 uint32_t val;
2493
2494 if (!HAS_DDI(dev))
2495 return;
2496
2497 val = I915_READ(DP_TP_CTL(port));
2498 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2499 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2500 I915_WRITE(DP_TP_CTL(port), val);
2501
2502 /*
2503 * On PORT_A we can have only eDP in SST mode. There the only reason
2504 * we need to set idle transmission mode is to work around a HW issue
2505 * where we enable the pipe while not in idle link-training mode.
2506 * In this case there is requirement to wait for a minimum number of
2507 * idle patterns to be sent.
2508 */
2509 if (port == PORT_A)
2510 return;
2511
2512 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2513 1))
2514 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2515}
2516
33a34e4e 2517/* Enable corresponding port and start training pattern 1 */
c19b0669 2518void
33a34e4e 2519intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2520{
da63a9f2 2521 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2522 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2523 int i;
2524 uint8_t voltage;
cdb0e95b 2525 int voltage_tries, loop_tries;
ea5b213a 2526 uint32_t DP = intel_dp->DP;
6aba5b6c 2527 uint8_t link_config[2];
a4fc5ed6 2528
affa9354 2529 if (HAS_DDI(dev))
c19b0669
PZ		 2530 intel_ddi_prepare_link_retrain(encoder);
2531
3cf2efb1 2532 /* Write the link configuration data */
6aba5b6c
JN		 2533 link_config[0] = intel_dp->link_bw;
2534 link_config[1] = intel_dp->lane_count;
2535 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2536 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 2537 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 2538
2539 link_config[0] = 0;
2540 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 2541 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 2542
2543 DP |= DP_PORT_EN;
1a2eb460 2544
70aff66c
JN		 2545 /* clock recovery */
2546 if (!intel_dp_reset_link_train(intel_dp, &DP,
2547 DP_TRAINING_PATTERN_1 |
2548 DP_LINK_SCRAMBLING_DISABLE)) {
2549 DRM_ERROR("failed to enable link training\n");
2550 return;
2551 }
2552
a4fc5ed6 2553 voltage = 0xff;
cdb0e95b
KP		 2554 voltage_tries = 0;
2555 loop_tries = 0;
a4fc5ed6 2556 for (;;) {
70aff66c 2557 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 2558
a7c9655f 2559 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2560 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2561 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2562 break;
93f62dad 2563 }
a4fc5ed6 2564
01916270 2565 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2566 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2567 break;
2568 }
2569
2570 /* Check to see if we've tried the max voltage */
2571 for (i = 0; i < intel_dp->lane_count; i++)
2572 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2573 break;
3b4f819d 2574 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2575 ++loop_tries;
2576 if (loop_tries == 5) {
3def84b3 2577 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 2578 break;
2579 }
70aff66c
JN		 2580 intel_dp_reset_link_train(intel_dp, &DP,
2581 DP_TRAINING_PATTERN_1 |
2582 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 2583 voltage_tries = 0;
2584 continue;
2585 }
a4fc5ed6 2586
3cf2efb1 2587 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2588 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2589 ++voltage_tries;
b06fbda3 2590 if (voltage_tries == 5) {
3def84b3 2591 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 2592 break;
2593 }
2594 } else
2595 voltage_tries = 0;
2596 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2597
70aff66c
JN		 2598 /* Update training set as requested by target */
2599 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2600 DRM_ERROR("failed to update link training\n");
2601 break;
2602 }
a4fc5ed6
KP		 2603 }
2604
33a34e4e
JB		 2605 intel_dp->DP = DP;
2606}
2607
c19b0669 2608void
33a34e4e
JB		 2609intel_dp_complete_link_train(struct intel_dp *intel_dp)
2610{
33a34e4e 2611 bool channel_eq = false;
37f80975 2612 int tries, cr_tries;
33a34e4e 2613 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 2614 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2615
2616 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2617 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2618 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 2619
a4fc5ed6 2620 /* channel equalization */
70aff66c 2621 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2622 training_pattern |
70aff66c
JN		 2623 DP_LINK_SCRAMBLING_DISABLE)) {
2624 DRM_ERROR("failed to start channel equalization\n");
2625 return;
2626 }
2627
a4fc5ed6 2628 tries = 0;
37f80975 2629 cr_tries = 0;
a4fc5ed6
KP		 2630 channel_eq = false;
2631 for (;;) {
70aff66c 2632 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2633
37f80975
JB		 2634 if (cr_tries > 5) {
2635 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 2636 break;
2637 }
2638
a7c9655f 2639 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 2640 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2641 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2642 break;
70aff66c 2643 }
a4fc5ed6 2644
37f80975 2645 /* Make sure clock is still ok */
01916270 2646 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 2647 intel_dp_start_link_train(intel_dp);
70aff66c 2648 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2649 training_pattern |
70aff66c 2650 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2651 cr_tries++;
2652 continue;
2653 }
2654
1ffdff13 2655 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2656 channel_eq = true;
2657 break;
2658 }
a4fc5ed6 2659
37f80975
JB		 2660 /* Try 5 times, then try clock recovery if that fails */
2661 if (tries > 5) {
2662 intel_dp_link_down(intel_dp);
2663 intel_dp_start_link_train(intel_dp);
70aff66c 2664 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2665 training_pattern |
70aff66c 2666 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2667 tries = 0;
2668 cr_tries++;
2669 continue;
2670 }
a4fc5ed6 2671
70aff66c
JN		 2672 /* Update training set as requested by target */
2673 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2674 DRM_ERROR("failed to update link training\n");
2675 break;
2676 }
3cf2efb1 2677 ++tries;
869184a6 2678 }
3cf2efb1 2679
3ab9c637
ID		 2680 intel_dp_set_idle_link_train(intel_dp);
2681
2682 intel_dp->DP = DP;
2683
d6c0d722 2684 if (channel_eq)
07f42258 2685 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2686
3ab9c637
ID		 2687}
2688
2689void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2690{
70aff66c 2691 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 2692 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2693}
2694
2695static void
ea5b213a 2696intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2697{
da63a9f2 2698 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2699 enum port port = intel_dig_port->port;
da63a9f2 2700 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2701 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2702 struct intel_crtc *intel_crtc =
2703 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2704 uint32_t DP = intel_dp->DP;
a4fc5ed6 2705
c19b0669
PZ		 2706 /*
2707 * DDI code has a strict mode set sequence and we should try to respect
2708 * it, otherwise we might hang the machine in many different ways. So we
2709 * really should be disabling the port only on a complete crtc_disable
2710 * sequence. This function is just called under two conditions on DDI
2711 * code:
2712 * - Link train failed while doing crtc_enable, and on this case we
2713 * really should respect the mode set sequence and wait for a
2714 * crtc_disable.
2715 * - Someone turned the monitor off and intel_dp_check_link_status
2716 * called us. We don't need to disable the whole port on this case, so
2717 * when someone turns the monitor on again,
2718 * intel_ddi_prepare_link_retrain will take care of redoing the link
2719 * train.
2720 */
affa9354 2721 if (HAS_DDI(dev))
c19b0669
PZ		 2722 return;
2723
0c33d8d7 2724 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2725 return;
2726
28c97730 2727 DRM_DEBUG_KMS("\n");
32f9d658 2728
bc7d38a4 2729 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 2730 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2731 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2732 } else {
2733 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2734 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2735 }
fe255d00 2736 POSTING_READ(intel_dp->output_reg);
5eb08b69 2737
ab527efc
DV		 2738 /* We don't really know why we're doing this */
2739 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2740
493a7081 2741 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2742 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2743 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2744
5bddd17f
EA		 2745 /* Hardware workaround: leaving our transcoder select
2746 * set to transcoder B while it's off will prevent the
2747 * corresponding HDMI output on transcoder A.
2748 *
2749 * Combine this with another hardware workaround:
2750 * transcoder select bit can only be cleared while the
2751 * port is enabled.
2752 */
2753 DP &= ~DP_PIPEB_SELECT;
2754 I915_WRITE(intel_dp->output_reg, DP);
2755
2756 /* Changes to enable or select take place the vblank
2757 * after being written.
2758 */
ff50afe9
DV		 2759 if (WARN_ON(crtc == NULL)) {
2760 /* We should never try to disable a port without a crtc
2761 * attached. For paranoia keep the code around for a
2762 * bit. */
31acbcc4
CW		 2763 POSTING_READ(intel_dp->output_reg);
2764 msleep(50);
2765 } else
ab527efc 2766 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2767 }
2768
832afda6 2769 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2770 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2771 POSTING_READ(intel_dp->output_reg);
f01eca2e 2772 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2773}
2774
26d61aad
KP		 2775static bool
2776intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2777{
a031d709
RV		 2778 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2779 struct drm_device *dev = dig_port->base.base.dev;
2780 struct drm_i915_private *dev_priv = dev->dev_private;
2781
577c7a50
DL		 2782 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2783
9d1a1031
JN		 2784 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
2785 sizeof(intel_dp->dpcd)) < 0)
edb39244 2786 return false; /* aux transfer failed */
92fd8fd1 2787
577c7a50
DL		 2788 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2789 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2790 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2791
edb39244
AJ		 2792 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2793 return false; /* DPCD not present */
2794
2293bb5c
SK		 2795 /* Check if the panel supports PSR */
2796 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 2797 if (is_edp(intel_dp)) {
9d1a1031
JN		 2798 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
2799 intel_dp->psr_dpcd,
2800 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 2801 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2802 dev_priv->psr.sink_support = true;
50003939 2803 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 2804 }
50003939
JN		 2805 }
2806
06ea66b6
TP		 2807 /* Training Pattern 3 support */
2808 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
2809 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
2810 intel_dp->use_tps3 = true;
2811 DRM_DEBUG_KMS("Displayport TPS3 supported");
2812 } else
2813 intel_dp->use_tps3 = false;
2814
edb39244
AJ		 2815 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2816 DP_DWN_STRM_PORT_PRESENT))
2817 return true; /* native DP sink */
2818
2819 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2820 return true; /* no per-port downstream info */
2821
9d1a1031
JN		 2822 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
2823 intel_dp->downstream_ports,
2824 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 2825 return false; /* downstream port status fetch failed */
2826
2827 return true;
92fd8fd1
KP		 2828}
2829
0d198328
AJ		 2830static void
2831intel_dp_probe_oui(struct intel_dp *intel_dp)
2832{
2833 u8 buf[3];
2834
2835 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2836 return;
2837
24f3e092 2838 intel_edp_panel_vdd_on(intel_dp);
351cfc34 2839
9d1a1031 2840 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 2841 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2842 buf[0], buf[1], buf[2]);
2843
9d1a1031 2844 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 2845 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2846 buf[0], buf[1], buf[2]);
351cfc34 2847
4be73780 2848 edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2849}
2850
d2e216d0
RV		 2851int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
2852{
2853 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2854 struct drm_device *dev = intel_dig_port->base.base.dev;
2855 struct intel_crtc *intel_crtc =
2856 to_intel_crtc(intel_dig_port->base.base.crtc);
2857 u8 buf[1];
2858
9d1a1031 2859 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 2860 return -EAGAIN;
2861
2862 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
2863 return -ENOTTY;
2864
9d1a1031
JN		 2865 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
2866 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 2867 return -EAGAIN;
2868
2869 /* Wait 2 vblanks to be sure we will have the correct CRC value */
2870 intel_wait_for_vblank(dev, intel_crtc->pipe);
2871 intel_wait_for_vblank(dev, intel_crtc->pipe);
2872
9d1a1031 2873 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 2874 return -EAGAIN;
2875
9d1a1031 2876 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 2877 return 0;
2878}
2879
a60f0e38
JB		 2880static bool
2881intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2882{
9d1a1031
JN		 2883 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2884 DP_DEVICE_SERVICE_IRQ_VECTOR,
2885 sink_irq_vector, 1) == 1;
a60f0e38
JB		 2886}
2887
2888static void
2889intel_dp_handle_test_request(struct intel_dp *intel_dp)
2890{
2891 /* NAK by default */
9d1a1031 2892 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2893}
2894
a4fc5ed6
KP		 2895/*
2896 * According to DP spec
2897 * 5.1.2:
2898 * 1. Read DPCD
2899 * 2. Configure link according to Receiver Capabilities
2900 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2901 * 4. Check link status on receipt of hot-plug interrupt
2902 */
2903
00c09d70 2904void
ea5b213a 2905intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2906{
da63a9f2 2907 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2908 u8 sink_irq_vector;
93f62dad 2909 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2910
da63a9f2 2911 if (!intel_encoder->connectors_active)
d2b996ac 2912 return;
59cd09e1 2913
da63a9f2 2914 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2915 return;
2916
92fd8fd1 2917 /* Try to read receiver status if the link appears to be up */
93f62dad 2918 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 2919 return;
2920 }
2921
92fd8fd1 2922 /* Now read the DPCD to see if it's actually running */
26d61aad 2923 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2924 return;
2925 }
2926
a60f0e38
JB		 2927 /* Try to read the source of the interrupt */
2928 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2929 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2930 /* Clear interrupt source */
9d1a1031
JN		 2931 drm_dp_dpcd_writeb(&intel_dp->aux,
2932 DP_DEVICE_SERVICE_IRQ_VECTOR,
2933 sink_irq_vector);
a60f0e38
JB		 2934
2935 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2936 intel_dp_handle_test_request(intel_dp);
2937 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2938 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2939 }
2940
1ffdff13 2941 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2942 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2943 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2944 intel_dp_start_link_train(intel_dp);
2945 intel_dp_complete_link_train(intel_dp);
3ab9c637 2946 intel_dp_stop_link_train(intel_dp);
33a34e4e 2947 }
a4fc5ed6 2948}
a4fc5ed6 2949
caf9ab24 2950/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2951static enum drm_connector_status
26d61aad 2952intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2953{
caf9ab24 2954 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 2955 uint8_t type;
2956
2957 if (!intel_dp_get_dpcd(intel_dp))
2958 return connector_status_disconnected;
2959
2960 /* if there's no downstream port, we're done */
2961 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2962 return connector_status_connected;
caf9ab24
AJ		 2963
2964 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 2965 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2966 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 2967 uint8_t reg;
9d1a1031
JN		 2968
2969 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
2970 &reg, 1) < 0)
caf9ab24 2971 return connector_status_unknown;
9d1a1031 2972
23235177
AJ		 2973 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2974 : connector_status_disconnected;
caf9ab24
AJ		 2975 }
2976
2977 /* If no HPD, poke DDC gently */
0b99836f 2978 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 2979 return connector_status_connected;
caf9ab24
AJ		 2980
2981 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 2982 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
2983 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2984 if (type == DP_DS_PORT_TYPE_VGA ||
2985 type == DP_DS_PORT_TYPE_NON_EDID)
2986 return connector_status_unknown;
2987 } else {
2988 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2989 DP_DWN_STRM_PORT_TYPE_MASK;
2990 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
2991 type == DP_DWN_STRM_PORT_TYPE_OTHER)
2992 return connector_status_unknown;
2993 }
caf9ab24
AJ		 2994
2995 /* Anything else is out of spec, warn and ignore */
2996 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2997 return connector_status_disconnected;
71ba9000
AJ		 2998}
2999
5eb08b69 3000static enum drm_connector_status
a9756bb5 3001ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3002{
30add22d 3003 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3004 struct drm_i915_private *dev_priv = dev->dev_private;
3005 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 3006 enum drm_connector_status status;
3007
fe16d949
CW		 3008 /* Can't disconnect eDP, but you can close the lid... */
3009 if (is_edp(intel_dp)) {
30add22d 3010 status = intel_panel_detect(dev);
fe16d949
CW		 3011 if (status == connector_status_unknown)
3012 status = connector_status_connected;
3013 return status;
3014 }
01cb9ea6 3015
1b469639
DL		 3016 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3017 return connector_status_disconnected;
3018
26d61aad 3019 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3020}
3021
a4fc5ed6 3022static enum drm_connector_status
a9756bb5 3023g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3024{
30add22d 3025 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3026 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3027 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3028 uint32_t bit;
5eb08b69 3029
35aad75f
JB		 3030 /* Can't disconnect eDP, but you can close the lid... */
3031 if (is_edp(intel_dp)) {
3032 enum drm_connector_status status;
3033
3034 status = intel_panel_detect(dev);
3035 if (status == connector_status_unknown)
3036 status = connector_status_connected;
3037 return status;
3038 }
3039
232a6ee9
TP		 3040 if (IS_VALLEYVIEW(dev)) {
3041 switch (intel_dig_port->port) {
3042 case PORT_B:
3043 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3044 break;
3045 case PORT_C:
3046 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3047 break;
3048 case PORT_D:
3049 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3050 break;
3051 default:
3052 return connector_status_unknown;
3053 }
3054 } else {
3055 switch (intel_dig_port->port) {
3056 case PORT_B:
3057 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3058 break;
3059 case PORT_C:
3060 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3061 break;
3062 case PORT_D:
3063 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3064 break;
3065 default:
3066 return connector_status_unknown;
3067 }
a4fc5ed6
KP		 3068 }
3069
10f76a38 3070 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3071 return connector_status_disconnected;
3072
26d61aad 3073 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3074}
3075
8c241fef
KP		 3076static struct edid *
3077intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3078{
9cd300e0 3079 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3080
9cd300e0
JN		 3081 /* use cached edid if we have one */
3082 if (intel_connector->edid) {
9cd300e0
JN		 3083 /* invalid edid */
3084 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3085 return NULL;
3086
55e9edeb 3087 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3088 }
8c241fef 3089
9cd300e0 3090 return drm_get_edid(connector, adapter);
8c241fef
KP		 3091}
3092
3093static int
3094intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3095{
9cd300e0 3096 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3097
9cd300e0
JN		 3098 /* use cached edid if we have one */
3099 if (intel_connector->edid) {
3100 /* invalid edid */
3101 if (IS_ERR(intel_connector->edid))
3102 return 0;
3103
3104 return intel_connector_update_modes(connector,
3105 intel_connector->edid);
d6f24d0f
JB		 3106 }
3107
9cd300e0 3108 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3109}
3110
a9756bb5
ZW		 3111static enum drm_connector_status
3112intel_dp_detect(struct drm_connector *connector, bool force)
3113{
3114 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3115 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3116 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3117 struct drm_device *dev = connector->dev;
c8c8fb33 3118 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 3119 enum drm_connector_status status;
671dedd2 3120 enum intel_display_power_domain power_domain;
a9756bb5
ZW		 3121 struct edid *edid = NULL;
3122
c8c8fb33
PZ		 3123 intel_runtime_pm_get(dev_priv);
3124
671dedd2
ID		 3125 power_domain = intel_display_port_power_domain(intel_encoder);
3126 intel_display_power_get(dev_priv, power_domain);
3127
164c8598
CW		 3128 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3129 connector->base.id, drm_get_connector_name(connector));
3130
a9756bb5
ZW		 3131 intel_dp->has_audio = false;
3132
3133 if (HAS_PCH_SPLIT(dev))
3134 status = ironlake_dp_detect(intel_dp);
3135 else
3136 status = g4x_dp_detect(intel_dp);
1b9be9d0 3137
a9756bb5 3138 if (status != connector_status_connected)
c8c8fb33 3139 goto out;
a9756bb5 3140
0d198328
AJ		 3141 intel_dp_probe_oui(intel_dp);
3142
c3e5f67b
DV		 3143 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3144 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3145 } else {
0b99836f 3146 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
f684960e
CW		 3147 if (edid) {
3148 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3149 kfree(edid);
3150 }
a9756bb5
ZW		 3151 }
3152
d63885da
PZ		 3153 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3154 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3155 status = connector_status_connected;
3156
3157out:
671dedd2
ID		 3158 intel_display_power_put(dev_priv, power_domain);
3159
c8c8fb33 3160 intel_runtime_pm_put(dev_priv);
671dedd2 3161
c8c8fb33 3162 return status;
a4fc5ed6
KP		 3163}
3164
3165static int intel_dp_get_modes(struct drm_connector *connector)
3166{
df0e9248 3167 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3168 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3169 struct intel_encoder *intel_encoder = &intel_dig_port->base;
dd06f90e 3170 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3171 struct drm_device *dev = connector->dev;
671dedd2
ID		 3172 struct drm_i915_private *dev_priv = dev->dev_private;
3173 enum intel_display_power_domain power_domain;
32f9d658 3174 int ret;
a4fc5ed6
KP		 3175
3176 /* We should parse the EDID data and find out if it has an audio sink
3177 */
3178
671dedd2
ID		 3179 power_domain = intel_display_port_power_domain(intel_encoder);
3180 intel_display_power_get(dev_priv, power_domain);
3181
0b99836f 3182 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
671dedd2 3183 intel_display_power_put(dev_priv, power_domain);
f8779fda 3184 if (ret)
32f9d658
ZW		 3185 return ret;
3186
f8779fda 3187 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3188 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3189 struct drm_display_mode *mode;
dd06f90e
JN		 3190 mode = drm_mode_duplicate(dev,
3191 intel_connector->panel.fixed_mode);
f8779fda 3192 if (mode) {
32f9d658
ZW		 3193 drm_mode_probed_add(connector, mode);
3194 return 1;
3195 }
3196 }
3197 return 0;
a4fc5ed6
KP		 3198}
3199
1aad7ac0
CW		 3200static bool
3201intel_dp_detect_audio(struct drm_connector *connector)
3202{
3203 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3204 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3205 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3206 struct drm_device *dev = connector->dev;
3207 struct drm_i915_private *dev_priv = dev->dev_private;
3208 enum intel_display_power_domain power_domain;
1aad7ac0
CW		 3209 struct edid *edid;
3210 bool has_audio = false;
3211
671dedd2
ID		 3212 power_domain = intel_display_port_power_domain(intel_encoder);
3213 intel_display_power_get(dev_priv, power_domain);
3214
0b99836f 3215 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
1aad7ac0
CW		 3216 if (edid) {
3217 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3218 kfree(edid);
3219 }
3220
671dedd2
ID		 3221 intel_display_power_put(dev_priv, power_domain);
3222
1aad7ac0
CW		 3223 return has_audio;
3224}
3225
f684960e
CW		 3226static int
3227intel_dp_set_property(struct drm_connector *connector,
3228 struct drm_property *property,
3229 uint64_t val)
3230{
e953fd7b 3231 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3232 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3233 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3234 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3235 int ret;
3236
662595df 3237 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3238 if (ret)
3239 return ret;
3240
3f43c48d 3241 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3242 int i = val;
3243 bool has_audio;
3244
3245 if (i == intel_dp->force_audio)
f684960e
CW		 3246 return 0;
3247
1aad7ac0 3248 intel_dp->force_audio = i;
f684960e 3249
c3e5f67b 3250 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3251 has_audio = intel_dp_detect_audio(connector);
3252 else
c3e5f67b 3253 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3254
3255 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3256 return 0;
3257
1aad7ac0 3258 intel_dp->has_audio = has_audio;
f684960e
CW		 3259 goto done;
3260 }
3261
e953fd7b 3262 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3263 bool old_auto = intel_dp->color_range_auto;
3264 uint32_t old_range = intel_dp->color_range;
3265
55bc60db
VS		 3266 switch (val) {
3267 case INTEL_BROADCAST_RGB_AUTO:
3268 intel_dp->color_range_auto = true;
3269 break;
3270 case INTEL_BROADCAST_RGB_FULL:
3271 intel_dp->color_range_auto = false;
3272 intel_dp->color_range = 0;
3273 break;
3274 case INTEL_BROADCAST_RGB_LIMITED:
3275 intel_dp->color_range_auto = false;
3276 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3277 break;
3278 default:
3279 return -EINVAL;
3280 }
ae4edb80
DV		 3281
3282 if (old_auto == intel_dp->color_range_auto &&
3283 old_range == intel_dp->color_range)
3284 return 0;
3285
e953fd7b
CW		 3286 goto done;
3287 }
3288
53b41837
YN		 3289 if (is_edp(intel_dp) &&
3290 property == connector->dev->mode_config.scaling_mode_property) {
3291 if (val == DRM_MODE_SCALE_NONE) {
3292 DRM_DEBUG_KMS("no scaling not supported\n");
3293 return -EINVAL;
3294 }
3295
3296 if (intel_connector->panel.fitting_mode == val) {
3297 /* the eDP scaling property is not changed */
3298 return 0;
3299 }
3300 intel_connector->panel.fitting_mode = val;
3301
3302 goto done;
3303 }
3304
f684960e
CW		 3305 return -EINVAL;
3306
3307done:
c0c36b94
CW		 3308 if (intel_encoder->base.crtc)
3309 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3310
3311 return 0;
3312}
3313
a4fc5ed6 3314static void
73845adf 3315intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3316{
1d508706 3317 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3318
9cd300e0
JN		 3319 if (!IS_ERR_OR_NULL(intel_connector->edid))
3320 kfree(intel_connector->edid);
3321
acd8db10
PZ		 3322 /* Can't call is_edp() since the encoder may have been destroyed
3323 * already. */
3324 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3325 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3326
a4fc5ed6 3327 drm_connector_cleanup(connector);
55f78c43 3328 kfree(connector);
a4fc5ed6
KP		 3329}
3330
00c09d70 3331void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3332{
da63a9f2
PZ		 3333 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3334 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3335 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927 3336
0b99836f 3337 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
24d05927 3338 drm_encoder_cleanup(encoder);
bd943159
KP		 3339 if (is_edp(intel_dp)) {
3340 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 3341 mutex_lock(&dev->mode_config.mutex);
4be73780 3342 edp_panel_vdd_off_sync(intel_dp);
bd173813 3343 mutex_unlock(&dev->mode_config.mutex);
bd943159 3344 }
da63a9f2 3345 kfree(intel_dig_port);
24d05927
DV		 3346}
3347
a4fc5ed6 3348static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3349 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3350 .detect = intel_dp_detect,
3351 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3352 .set_property = intel_dp_set_property,
73845adf 3353 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3354};
3355
3356static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3357 .get_modes = intel_dp_get_modes,
3358 .mode_valid = intel_dp_mode_valid,
df0e9248 3359 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3360};
3361
a4fc5ed6 3362static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3363 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3364};
3365
995b6762 3366static void
21d40d37 3367intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3368{
fa90ecef 3369 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3370
885a5014 3371 intel_dp_check_link_status(intel_dp);
c8110e52 3372}
6207937d 3373
e3421a18
ZW		 3374/* Return which DP Port should be selected for Transcoder DP control */
3375int
0206e353 3376intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3377{
3378 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3379 struct intel_encoder *intel_encoder;
3380 struct intel_dp *intel_dp;
e3421a18 3381
fa90ecef
PZ		 3382 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3383 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3384
fa90ecef
PZ		 3385 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3386 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3387 return intel_dp->output_reg;
e3421a18 3388 }
ea5b213a 3389
e3421a18
ZW		 3390 return -1;
3391}
3392
36e83a18 3393/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 3394bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 3395{
3396 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 3397 union child_device_config *p_child;
36e83a18 3398 int i;
5d8a7752
VS		 3399 static const short port_mapping[] = {
3400 [PORT_B] = PORT_IDPB,
3401 [PORT_C] = PORT_IDPC,
3402 [PORT_D] = PORT_IDPD,
3403 };
36e83a18 3404
3b32a35b
VS		 3405 if (port == PORT_A)
3406 return true;
3407
41aa3448 3408 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3409 return false;
3410
41aa3448
RV		 3411 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3412 p_child = dev_priv->vbt.child_dev + i;
36e83a18 3413
5d8a7752 3414 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 3415 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3416 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 3417 return true;
3418 }
3419 return false;
3420}
3421
f684960e
CW		 3422static void
3423intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3424{
53b41837
YN		 3425 struct intel_connector *intel_connector = to_intel_connector(connector);
3426
3f43c48d 3427 intel_attach_force_audio_property(connector);
e953fd7b 3428 intel_attach_broadcast_rgb_property(connector);
55bc60db 3429 intel_dp->color_range_auto = true;
53b41837
YN		 3430
3431 if (is_edp(intel_dp)) {
3432 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3433 drm_object_attach_property(
3434 &connector->base,
53b41837 3435 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3436 DRM_MODE_SCALE_ASPECT);
3437 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3438 }
f684960e
CW		 3439}
3440
dada1a9f
ID		 3441static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3442{
3443 intel_dp->last_power_cycle = jiffies;
3444 intel_dp->last_power_on = jiffies;
3445 intel_dp->last_backlight_off = jiffies;
3446}
3447
67a54566
DV		 3448static void
3449intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3450 struct intel_dp *intel_dp,
3451 struct edp_power_seq *out)
67a54566
DV		 3452{
3453 struct drm_i915_private *dev_priv = dev->dev_private;
3454 struct edp_power_seq cur, vbt, spec, final;
3455 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 3456 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 3457
3458 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 3459 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 3460 pp_on_reg = PCH_PP_ON_DELAYS;
3461 pp_off_reg = PCH_PP_OFF_DELAYS;
3462 pp_div_reg = PCH_PP_DIVISOR;
3463 } else {
bf13e81b
JN		 3464 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3465
3466 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3467 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3468 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3469 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 3470 }
67a54566
DV		 3471
3472 /* Workaround: Need to write PP_CONTROL with the unlock key as
3473 * the very first thing. */
453c5420 3474 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 3475 I915_WRITE(pp_ctrl_reg, pp);
67a54566 3476
453c5420
JB		 3477 pp_on = I915_READ(pp_on_reg);
3478 pp_off = I915_READ(pp_off_reg);
3479 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3480
3481 /* Pull timing values out of registers */
3482 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3483 PANEL_POWER_UP_DELAY_SHIFT;
3484
3485 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3486 PANEL_LIGHT_ON_DELAY_SHIFT;
3487
3488 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3489 PANEL_LIGHT_OFF_DELAY_SHIFT;
3490
3491 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3492 PANEL_POWER_DOWN_DELAY_SHIFT;
3493
3494 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3495 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3496
3497 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3498 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3499
41aa3448 3500 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3501
3502 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3503 * our hw here, which are all in 100usec. */
3504 spec.t1_t3 = 210 * 10;
3505 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3506 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3507 spec.t10 = 500 * 10;
3508 /* This one is special and actually in units of 100ms, but zero
3509 * based in the hw (so we need to add 100 ms). But the sw vbt
3510 * table multiplies it with 1000 to make it in units of 100usec,
3511 * too. */
3512 spec.t11_t12 = (510 + 100) * 10;
3513
3514 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3515 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3516
3517 /* Use the max of the register settings and vbt. If both are
3518 * unset, fall back to the spec limits. */
3519#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3520 spec.field : \
3521 max(cur.field, vbt.field))
3522 assign_final(t1_t3);
3523 assign_final(t8);
3524 assign_final(t9);
3525 assign_final(t10);
3526 assign_final(t11_t12);
3527#undef assign_final
3528
3529#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3530 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3531 intel_dp->backlight_on_delay = get_delay(t8);
3532 intel_dp->backlight_off_delay = get_delay(t9);
3533 intel_dp->panel_power_down_delay = get_delay(t10);
3534 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3535#undef get_delay
3536
f30d26e4
JN		 3537 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3538 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3539 intel_dp->panel_power_cycle_delay);
3540
3541 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3542 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3543
3544 if (out)
3545 *out = final;
3546}
3547
3548static void
3549intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3550 struct intel_dp *intel_dp,
3551 struct edp_power_seq *seq)
3552{
3553 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3554 u32 pp_on, pp_off, pp_div, port_sel = 0;
3555 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3556 int pp_on_reg, pp_off_reg, pp_div_reg;
3557
3558 if (HAS_PCH_SPLIT(dev)) {
3559 pp_on_reg = PCH_PP_ON_DELAYS;
3560 pp_off_reg = PCH_PP_OFF_DELAYS;
3561 pp_div_reg = PCH_PP_DIVISOR;
3562 } else {
bf13e81b
JN		 3563 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3564
3565 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3566 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3567 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 3568 }
3569
b2f19d1a
PZ		 3570 /*
3571 * And finally store the new values in the power sequencer. The
3572 * backlight delays are set to 1 because we do manual waits on them. For
3573 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3574 * we'll end up waiting for the backlight off delay twice: once when we
3575 * do the manual sleep, and once when we disable the panel and wait for
3576 * the PP_STATUS bit to become zero.
3577 */
f30d26e4 3578 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 3579 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3580 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 3581 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 3582 /* Compute the divisor for the pp clock, simply match the Bspec
3583 * formula. */
453c5420 3584 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 3585 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 3586 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3587
3588 /* Haswell doesn't have any port selection bits for the panel
3589 * power sequencer any more. */
bc7d38a4 3590 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 3591 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3592 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3593 else
3594 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 3595 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3596 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 3597 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 3598 else
a24c144c 3599 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 3600 }
3601
453c5420
JB		 3602 pp_on |= port_sel;
3603
3604 I915_WRITE(pp_on_reg, pp_on);
3605 I915_WRITE(pp_off_reg, pp_off);
3606 I915_WRITE(pp_div_reg, pp_div);
67a54566 3607
67a54566 3608 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 3609 I915_READ(pp_on_reg),
3610 I915_READ(pp_off_reg),
3611 I915_READ(pp_div_reg));
f684960e
CW		 3612}
3613
ed92f0b2 3614static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 3615 struct intel_connector *intel_connector,
3616 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 3617{
3618 struct drm_connector *connector = &intel_connector->base;
3619 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3620 struct drm_device *dev = intel_dig_port->base.base.dev;
3621 struct drm_i915_private *dev_priv = dev->dev_private;
3622 struct drm_display_mode *fixed_mode = NULL;
ed92f0b2
PZ		 3623 bool has_dpcd;
3624 struct drm_display_mode *scan;
3625 struct edid *edid;
3626
3627 if (!is_edp(intel_dp))
3628 return true;
3629
ed92f0b2 3630 /* Cache DPCD and EDID for edp. */
24f3e092 3631 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 3632 has_dpcd = intel_dp_get_dpcd(intel_dp);
4be73780 3633 edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 3634
3635 if (has_dpcd) {
3636 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3637 dev_priv->no_aux_handshake =
3638 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3639 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3640 } else {
3641 /* if this fails, presume the device is a ghost */
3642 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 3643 return false;
3644 }
3645
3646 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 3647 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 3648
4da98541 3649 mutex_lock(&dev->mode_config.mutex);
0b99836f 3650 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 3651 if (edid) {
3652 if (drm_add_edid_modes(connector, edid)) {
3653 drm_mode_connector_update_edid_property(connector,
3654 edid);
3655 drm_edid_to_eld(connector, edid);
3656 } else {
3657 kfree(edid);
3658 edid = ERR_PTR(-EINVAL);
3659 }
3660 } else {
3661 edid = ERR_PTR(-ENOENT);
3662 }
3663 intel_connector->edid = edid;
3664
3665 /* prefer fixed mode from EDID if available */
3666 list_for_each_entry(scan, &connector->probed_modes, head) {
3667 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3668 fixed_mode = drm_mode_duplicate(dev, scan);
3669 break;
3670 }
3671 }
3672
3673 /* fallback to VBT if available for eDP */
3674 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3675 fixed_mode = drm_mode_duplicate(dev,
3676 dev_priv->vbt.lfp_lvds_vbt_mode);
3677 if (fixed_mode)
3678 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3679 }
4da98541 3680 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 3681
4b6ed685 3682 intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
ed92f0b2
PZ		 3683 intel_panel_setup_backlight(connector);
3684
3685 return true;
3686}
3687
16c25533 3688bool
f0fec3f2
PZ		 3689intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3690 struct intel_connector *intel_connector)
a4fc5ed6 3691{
f0fec3f2
PZ		 3692 struct drm_connector *connector = &intel_connector->base;
3693 struct intel_dp *intel_dp = &intel_dig_port->dp;
3694 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3695 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 3696 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3697 enum port port = intel_dig_port->port;
0095e6dc 3698 struct edp_power_seq power_seq = { 0 };
0b99836f 3699 int type;
a4fc5ed6 3700
ec5b01dd
DL		 3701 /* intel_dp vfuncs */
3702 if (IS_VALLEYVIEW(dev))
3703 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
3704 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3705 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
3706 else if (HAS_PCH_SPLIT(dev))
3707 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
3708 else
3709 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
3710
153b1100
DL		 3711 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
3712
0767935e
DV		 3713 /* Preserve the current hw state. */
3714 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 3715 intel_dp->attached_connector = intel_connector;
3d3dc149 3716
3b32a35b 3717 if (intel_dp_is_edp(dev, port))
b329530c 3718 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 3719 else
3720 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 3721
f7d24902
ID		 3722 /*
3723 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3724 * for DP the encoder type can be set by the caller to
3725 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3726 */
3727 if (type == DRM_MODE_CONNECTOR_eDP)
3728 intel_encoder->type = INTEL_OUTPUT_EDP;
3729
e7281eab
ID		 3730 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3731 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3732 port_name(port));
3733
b329530c 3734 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3735 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3736
a4fc5ed6
KP		 3737 connector->interlace_allowed = true;
3738 connector->doublescan_allowed = 0;
3739
f0fec3f2 3740 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 3741 edp_panel_vdd_work);
a4fc5ed6 3742
df0e9248 3743 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3744 drm_sysfs_connector_add(connector);
3745
affa9354 3746 if (HAS_DDI(dev))
bcbc889b
PZ		 3747 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3748 else
3749 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 3750 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 3751
0b99836f 3752 /* Set up the hotplug pin. */
ab9d7c30
PZ		 3753 switch (port) {
3754 case PORT_A:
1d843f9d 3755 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3756 break;
3757 case PORT_B:
1d843f9d 3758 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3759 break;
3760 case PORT_C:
1d843f9d 3761 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3762 break;
3763 case PORT_D:
1d843f9d 3764 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3765 break;
3766 default:
ad1c0b19 3767 BUG();
5eb08b69
ZW		 3768 }
3769
dada1a9f
ID		 3770 if (is_edp(intel_dp)) {
3771 intel_dp_init_panel_power_timestamps(intel_dp);
0095e6dc 3772 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
dada1a9f 3773 }
0095e6dc 3774
9d1a1031 3775 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 3776
2b28bb1b
RV		 3777 intel_dp->psr_setup_done = false;
3778
0095e6dc 3779 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
0b99836f 3780 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
15b1d171
PZ		 3781 if (is_edp(intel_dp)) {
3782 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3783 mutex_lock(&dev->mode_config.mutex);
4be73780 3784 edp_panel_vdd_off_sync(intel_dp);
15b1d171
PZ		 3785 mutex_unlock(&dev->mode_config.mutex);
3786 }
b2f246a8
PZ		 3787 drm_sysfs_connector_remove(connector);
3788 drm_connector_cleanup(connector);
16c25533 3789 return false;
b2f246a8 3790 }
32f9d658 3791
f684960e
CW		 3792 intel_dp_add_properties(intel_dp, connector);
3793
a4fc5ed6
KP		 3794 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3795 * 0xd. Failure to do so will result in spurious interrupts being
3796 * generated on the port when a cable is not attached.
3797 */
3798 if (IS_G4X(dev) && !IS_GM45(dev)) {
3799 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3800 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3801 }
16c25533
PZ		 3802
3803 return true;
a4fc5ed6 3804}
f0fec3f2
PZ		 3805
3806void
3807intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3808{
3809 struct intel_digital_port *intel_dig_port;
3810 struct intel_encoder *intel_encoder;
3811 struct drm_encoder *encoder;
3812 struct intel_connector *intel_connector;
3813
b14c5679 3814 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 3815 if (!intel_dig_port)
3816 return;
3817
b14c5679 3818 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 3819 if (!intel_connector) {
3820 kfree(intel_dig_port);
3821 return;
3822 }
3823
3824 intel_encoder = &intel_dig_port->base;
3825 encoder = &intel_encoder->base;
3826
3827 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3828 DRM_MODE_ENCODER_TMDS);
3829
5bfe2ac0 3830 intel_encoder->compute_config = intel_dp_compute_config;
b934223d 3831 intel_encoder->mode_set = intel_dp_mode_set;
00c09d70
PZ		 3832 intel_encoder->disable = intel_disable_dp;
3833 intel_encoder->post_disable = intel_post_disable_dp;
3834 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 3835 intel_encoder->get_config = intel_dp_get_config;
ab1f90f9 3836 if (IS_VALLEYVIEW(dev)) {
ecff4f3b 3837 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 3838 intel_encoder->pre_enable = vlv_pre_enable_dp;
3839 intel_encoder->enable = vlv_enable_dp;
3840 } else {
ecff4f3b
JN		 3841 intel_encoder->pre_enable = g4x_pre_enable_dp;
3842 intel_encoder->enable = g4x_enable_dp;
ab1f90f9 3843 }
f0fec3f2 3844
174edf1f 3845 intel_dig_port->port = port;
f0fec3f2
PZ		 3846 intel_dig_port->dp.output_reg = output_reg;
3847
00c09d70 3848 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2 3849 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 3850 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 3851 intel_encoder->hot_plug = intel_dp_hot_plug;
3852
15b1d171
PZ		 3853 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3854 drm_encoder_cleanup(encoder);
3855 kfree(intel_dig_port);
b2f246a8 3856 kfree(intel_connector);
15b1d171 3857 }
f0fec3f2 3858}
Linux kernel - Deliverables
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