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drm/i915: Don't let update_psr function actually enable PSR.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
65ce4bf5
CML		 60static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
58f6e632 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
ef9348c8
CML		 67/*
68 * CHV supports eDP 1.4 that have more link rates.
69 * Below only provides the fixed rate but exclude variable rate.
70 */
71static const struct dp_link_dpll chv_dpll[] = {
72 /*
73 * CHV requires to program fractional division for m2.
74 * m2 is stored in fixed point format using formula below
75 * (m2_int << 22) | m2_fraction
76 */
77 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
78 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
79 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
80 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
81 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
83};
84
cfcb0fc9
JB		 85/**
86 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
87 * @intel_dp: DP struct
88 *
89 * If a CPU or PCH DP output is attached to an eDP panel, this function
90 * will return true, and false otherwise.
91 */
92static bool is_edp(struct intel_dp *intel_dp)
93{
da63a9f2
PZ		 94 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
95
96 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 97}
98
68b4d824 99static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 100{
68b4d824
ID		 101 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
102
103 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 104}
105
df0e9248
CW		 106static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
107{
fa90ecef 108 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 109}
110
ea5b213a 111static void intel_dp_link_down(struct intel_dp *intel_dp);
adddaaf4 112static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 113static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 114
a4fc5ed6 115static int
ea5b213a 116intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 117{
7183dc29 118 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 119 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 120
121 switch (max_link_bw) {
122 case DP_LINK_BW_1_62:
123 case DP_LINK_BW_2_7:
124 break;
d4eead50 125 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 126 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
127 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 128 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
129 max_link_bw = DP_LINK_BW_5_4;
130 else
131 max_link_bw = DP_LINK_BW_2_7;
d4eead50 132 break;
a4fc5ed6 133 default:
d4eead50
ID		 134 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
135 max_link_bw);
a4fc5ed6
KP		 136 max_link_bw = DP_LINK_BW_1_62;
137 break;
138 }
139 return max_link_bw;
140}
141
eeb6324d
PZ		 142static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
143{
144 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
145 struct drm_device *dev = intel_dig_port->base.base.dev;
146 u8 source_max, sink_max;
147
148 source_max = 4;
149 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
150 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
151 source_max = 2;
152
153 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
154
155 return min(source_max, sink_max);
156}
157
cd9dde44
AJ		 158/*
159 * The units on the numbers in the next two are... bizarre. Examples will
160 * make it clearer; this one parallels an example in the eDP spec.
161 *
162 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
163 *
164 * 270000 * 1 * 8 / 10 == 216000
165 *
166 * The actual data capacity of that configuration is 2.16Gbit/s, so the
167 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
168 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
169 * 119000. At 18bpp that's 2142000 kilobits per second.
170 *
171 * Thus the strange-looking division by 10 in intel_dp_link_required, to
172 * get the result in decakilobits instead of kilobits.
173 */
174
a4fc5ed6 175static int
c898261c 176intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 177{
cd9dde44 178 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 179}
180
fe27d53e
DA		 181static int
182intel_dp_max_data_rate(int max_link_clock, int max_lanes)
183{
184 return (max_link_clock * max_lanes * 8) / 10;
185}
186
c19de8eb 187static enum drm_mode_status
a4fc5ed6
KP		 188intel_dp_mode_valid(struct drm_connector *connector,
189 struct drm_display_mode *mode)
190{
df0e9248 191 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 192 struct intel_connector *intel_connector = to_intel_connector(connector);
193 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 194 int target_clock = mode->clock;
195 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 196
dd06f90e
JN		 197 if (is_edp(intel_dp) && fixed_mode) {
198 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 199 return MODE_PANEL;
200
dd06f90e 201 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 202 return MODE_PANEL;
03afc4a2
DV		 203
204 target_clock = fixed_mode->clock;
7de56f43
ZY		 205 }
206
36008365 207 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 208 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 209
210 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
211 mode_rate = intel_dp_link_required(target_clock, 18);
212
213 if (mode_rate > max_rate)
c4867936 214 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 215
216 if (mode->clock < 10000)
217 return MODE_CLOCK_LOW;
218
0af78a2b
DV		 219 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
220 return MODE_H_ILLEGAL;
221
a4fc5ed6
KP		 222 return MODE_OK;
223}
224
225static uint32_t
226pack_aux(uint8_t *src, int src_bytes)
227{
228 int i;
229 uint32_t v = 0;
230
231 if (src_bytes > 4)
232 src_bytes = 4;
233 for (i = 0; i < src_bytes; i++)
234 v |= ((uint32_t) src[i]) << ((3-i) * 8);
235 return v;
236}
237
238static void
239unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
240{
241 int i;
242 if (dst_bytes > 4)
243 dst_bytes = 4;
244 for (i = 0; i < dst_bytes; i++)
245 dst[i] = src >> ((3-i) * 8);
246}
247
fb0f8fbf
KP		 248/* hrawclock is 1/4 the FSB frequency */
249static int
250intel_hrawclk(struct drm_device *dev)
251{
252 struct drm_i915_private *dev_priv = dev->dev_private;
253 uint32_t clkcfg;
254
9473c8f4
VP		 255 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
256 if (IS_VALLEYVIEW(dev))
257 return 200;
258
fb0f8fbf
KP		 259 clkcfg = I915_READ(CLKCFG);
260 switch (clkcfg & CLKCFG_FSB_MASK) {
261 case CLKCFG_FSB_400:
262 return 100;
263 case CLKCFG_FSB_533:
264 return 133;
265 case CLKCFG_FSB_667:
266 return 166;
267 case CLKCFG_FSB_800:
268 return 200;
269 case CLKCFG_FSB_1067:
270 return 266;
271 case CLKCFG_FSB_1333:
272 return 333;
273 /* these two are just a guess; one of them might be right */
274 case CLKCFG_FSB_1600:
275 case CLKCFG_FSB_1600_ALT:
276 return 400;
277 default:
278 return 133;
279 }
280}
281
bf13e81b
JN		 282static void
283intel_dp_init_panel_power_sequencer(struct drm_device *dev,
284 struct intel_dp *intel_dp,
285 struct edp_power_seq *out);
286static void
287intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
288 struct intel_dp *intel_dp,
289 struct edp_power_seq *out);
290
291static enum pipe
292vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
293{
294 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
295 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
296 struct drm_device *dev = intel_dig_port->base.base.dev;
297 struct drm_i915_private *dev_priv = dev->dev_private;
298 enum port port = intel_dig_port->port;
299 enum pipe pipe;
300
301 /* modeset should have pipe */
302 if (crtc)
303 return to_intel_crtc(crtc)->pipe;
304
305 /* init time, try to find a pipe with this port selected */
306 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
307 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
308 PANEL_PORT_SELECT_MASK;
309 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
310 return pipe;
311 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
312 return pipe;
313 }
314
315 /* shrug */
316 return PIPE_A;
317}
318
319static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
320{
321 struct drm_device *dev = intel_dp_to_dev(intel_dp);
322
323 if (HAS_PCH_SPLIT(dev))
324 return PCH_PP_CONTROL;
325 else
326 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
327}
328
329static u32 _pp_stat_reg(struct intel_dp *intel_dp)
330{
331 struct drm_device *dev = intel_dp_to_dev(intel_dp);
332
333 if (HAS_PCH_SPLIT(dev))
334 return PCH_PP_STATUS;
335 else
336 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
337}
338
4be73780 339static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 340{
30add22d 341 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 342 struct drm_i915_private *dev_priv = dev->dev_private;
343
bf13e81b 344 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 345}
346
4be73780 347static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 348{
30add22d 349 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 350 struct drm_i915_private *dev_priv = dev->dev_private;
bb4932c4
ID		 351 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
352 struct intel_encoder *intel_encoder = &intel_dig_port->base;
353 enum intel_display_power_domain power_domain;
ebf33b18 354
bb4932c4
ID		 355 power_domain = intel_display_port_power_domain(intel_encoder);
356 return intel_display_power_enabled(dev_priv, power_domain) &&
efbc20ab 357 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 358}
359
9b984dae
KP		 360static void
361intel_dp_check_edp(struct intel_dp *intel_dp)
362{
30add22d 363 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 364 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 365
9b984dae
KP		 366 if (!is_edp(intel_dp))
367 return;
453c5420 368
4be73780 369 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 370 WARN(1, "eDP powered off while attempting aux channel communication.\n");
371 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 372 I915_READ(_pp_stat_reg(intel_dp)),
373 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 374 }
375}
376
9ee32fea
DV		 377static uint32_t
378intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
379{
380 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
381 struct drm_device *dev = intel_dig_port->base.base.dev;
382 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 383 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 384 uint32_t status;
385 bool done;
386
ef04f00d 387#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 388 if (has_aux_irq)
b18ac466 389 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 390 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 391 else
392 done = wait_for_atomic(C, 10) == 0;
393 if (!done)
394 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
395 has_aux_irq);
396#undef C
397
398 return status;
399}
400
ec5b01dd 401static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 402{
174edf1f
PZ		 403 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
404 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 405
ec5b01dd
DL		 406 /*
407 * The clock divider is based off the hrawclk, and would like to run at
408 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 409 */
ec5b01dd
DL		 410 return index ? 0 : intel_hrawclk(dev) / 2;
411}
412
413static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
414{
415 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
416 struct drm_device *dev = intel_dig_port->base.base.dev;
417
418 if (index)
419 return 0;
420
421 if (intel_dig_port->port == PORT_A) {
422 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 423 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 424 else
b84a1cf8 425 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 426 } else {
427 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
428 }
429}
430
431static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
432{
433 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
434 struct drm_device *dev = intel_dig_port->base.base.dev;
435 struct drm_i915_private *dev_priv = dev->dev_private;
436
437 if (intel_dig_port->port == PORT_A) {
438 if (index)
439 return 0;
440 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 441 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
442 /* Workaround for non-ULT HSW */
bc86625a
CW		 443 switch (index) {
444 case 0: return 63;
445 case 1: return 72;
446 default: return 0;
447 }
ec5b01dd 448 } else {
bc86625a 449 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 450 }
b84a1cf8
RV		 451}
452
ec5b01dd
DL		 453static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
454{
455 return index ? 0 : 100;
456}
457
5ed12a19
DL		 458static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
459 bool has_aux_irq,
460 int send_bytes,
461 uint32_t aux_clock_divider)
462{
463 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
464 struct drm_device *dev = intel_dig_port->base.base.dev;
465 uint32_t precharge, timeout;
466
467 if (IS_GEN6(dev))
468 precharge = 3;
469 else
470 precharge = 5;
471
472 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
473 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
474 else
475 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
476
477 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 478 DP_AUX_CH_CTL_DONE |
5ed12a19 479 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 480 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 481 timeout |
788d4433 482 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 483 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
484 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 485 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 486}
487
b84a1cf8
RV		 488static int
489intel_dp_aux_ch(struct intel_dp *intel_dp,
490 uint8_t *send, int send_bytes,
491 uint8_t *recv, int recv_size)
492{
493 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
494 struct drm_device *dev = intel_dig_port->base.base.dev;
495 struct drm_i915_private *dev_priv = dev->dev_private;
496 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
497 uint32_t ch_data = ch_ctl + 4;
bc86625a 498 uint32_t aux_clock_divider;
b84a1cf8
RV		 499 int i, ret, recv_bytes;
500 uint32_t status;
5ed12a19 501 int try, clock = 0;
4e6b788c 502 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 503 bool vdd;
504
505 vdd = _edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 506
507 /* dp aux is extremely sensitive to irq latency, hence request the
508 * lowest possible wakeup latency and so prevent the cpu from going into
509 * deep sleep states.
510 */
511 pm_qos_update_request(&dev_priv->pm_qos, 0);
512
513 intel_dp_check_edp(intel_dp);
5eb08b69 514
c67a470b
PZ		 515 intel_aux_display_runtime_get(dev_priv);
516
11bee43e
JB		 517 /* Try to wait for any previous AUX channel activity */
518 for (try = 0; try < 3; try++) {
ef04f00d 519 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 520 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
521 break;
522 msleep(1);
523 }
524
525 if (try == 3) {
526 WARN(1, "dp_aux_ch not started status 0x%08x\n",
527 I915_READ(ch_ctl));
9ee32fea
DV		 528 ret = -EBUSY;
529 goto out;
4f7f7b7e
CW		 530 }
531
46a5ae9f
PZ		 532 /* Only 5 data registers! */
533 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
534 ret = -E2BIG;
535 goto out;
536 }
537
ec5b01dd 538 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 539 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
540 has_aux_irq,
541 send_bytes,
542 aux_clock_divider);
5ed12a19 543
bc86625a
CW		 544 /* Must try at least 3 times according to DP spec */
545 for (try = 0; try < 5; try++) {
546 /* Load the send data into the aux channel data registers */
547 for (i = 0; i < send_bytes; i += 4)
548 I915_WRITE(ch_data + i,
549 pack_aux(send + i, send_bytes - i));
550
551 /* Send the command and wait for it to complete */
5ed12a19 552 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 553
554 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
555
556 /* Clear done status and any errors */
557 I915_WRITE(ch_ctl,
558 status |
559 DP_AUX_CH_CTL_DONE |
560 DP_AUX_CH_CTL_TIME_OUT_ERROR |
561 DP_AUX_CH_CTL_RECEIVE_ERROR);
562
563 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
564 DP_AUX_CH_CTL_RECEIVE_ERROR))
565 continue;
566 if (status & DP_AUX_CH_CTL_DONE)
567 break;
568 }
4f7f7b7e 569 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 570 break;
571 }
572
a4fc5ed6 573 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 574 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 575 ret = -EBUSY;
576 goto out;
a4fc5ed6
KP		 577 }
578
579 /* Check for timeout or receive error.
580 * Timeouts occur when the sink is not connected
581 */
a5b3da54 582 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 583 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 584 ret = -EIO;
585 goto out;
a5b3da54 586 }
1ae8c0a5
KP		 587
588 /* Timeouts occur when the device isn't connected, so they're
589 * "normal" -- don't fill the kernel log with these */
a5b3da54 590 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 591 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 592 ret = -ETIMEDOUT;
593 goto out;
a4fc5ed6
KP		 594 }
595
596 /* Unload any bytes sent back from the other side */
597 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
598 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 599 if (recv_bytes > recv_size)
600 recv_bytes = recv_size;
0206e353 601
4f7f7b7e
CW		 602 for (i = 0; i < recv_bytes; i += 4)
603 unpack_aux(I915_READ(ch_data + i),
604 recv + i, recv_bytes - i);
a4fc5ed6 605
9ee32fea
DV		 606 ret = recv_bytes;
607out:
608 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 609 intel_aux_display_runtime_put(dev_priv);
9ee32fea 610
884f19e9
JN		 611 if (vdd)
612 edp_panel_vdd_off(intel_dp, false);
613
9ee32fea 614 return ret;
a4fc5ed6
KP		 615}
616
a6c8aff0
JN		 617#define BARE_ADDRESS_SIZE 3
618#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 619static ssize_t
620intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 621{
9d1a1031
JN		 622 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
623 uint8_t txbuf[20], rxbuf[20];
624 size_t txsize, rxsize;
a4fc5ed6 625 int ret;
a4fc5ed6 626
9d1a1031
JN		 627 txbuf[0] = msg->request << 4;
628 txbuf[1] = msg->address >> 8;
629 txbuf[2] = msg->address & 0xff;
630 txbuf[3] = msg->size - 1;
46a5ae9f 631
9d1a1031
JN		 632 switch (msg->request & ~DP_AUX_I2C_MOT) {
633 case DP_AUX_NATIVE_WRITE:
634 case DP_AUX_I2C_WRITE:
a6c8aff0 635 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 636 rxsize = 1;
f51a44b9 637
9d1a1031
JN		 638 if (WARN_ON(txsize > 20))
639 return -E2BIG;
a4fc5ed6 640
9d1a1031 641 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 642
9d1a1031
JN		 643 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
644 if (ret > 0) {
645 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 646
9d1a1031
JN		 647 /* Return payload size. */
648 ret = msg->size;
649 }
650 break;
46a5ae9f 651
9d1a1031
JN		 652 case DP_AUX_NATIVE_READ:
653 case DP_AUX_I2C_READ:
a6c8aff0 654 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 655 rxsize = msg->size + 1;
a4fc5ed6 656
9d1a1031
JN		 657 if (WARN_ON(rxsize > 20))
658 return -E2BIG;
a4fc5ed6 659
9d1a1031
JN		 660 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
661 if (ret > 0) {
662 msg->reply = rxbuf[0] >> 4;
663 /*
664 * Assume happy day, and copy the data. The caller is
665 * expected to check msg->reply before touching it.
666 *
667 * Return payload size.
668 */
669 ret--;
670 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 671 }
9d1a1031
JN		 672 break;
673
674 default:
675 ret = -EINVAL;
676 break;
a4fc5ed6 677 }
f51a44b9 678
9d1a1031 679 return ret;
a4fc5ed6
KP		 680}
681
9d1a1031
JN		 682static void
683intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
684{
685 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 686 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
687 enum port port = intel_dig_port->port;
0b99836f 688 const char *name = NULL;
ab2c0672
DA		 689 int ret;
690
33ad6626
JN		 691 switch (port) {
692 case PORT_A:
693 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 694 name = "DPDDC-A";
ab2c0672 695 break;
33ad6626
JN		 696 case PORT_B:
697 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 698 name = "DPDDC-B";
ab2c0672 699 break;
33ad6626
JN		 700 case PORT_C:
701 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 702 name = "DPDDC-C";
ab2c0672 703 break;
33ad6626
JN		 704 case PORT_D:
705 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 706 name = "DPDDC-D";
33ad6626
JN		 707 break;
708 default:
709 BUG();
ab2c0672
DA		 710 }
711
33ad6626
JN		 712 if (!HAS_DDI(dev))
713 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 714
0b99836f 715 intel_dp->aux.name = name;
9d1a1031
JN		 716 intel_dp->aux.dev = dev->dev;
717 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 718
0b99836f
JN		 719 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
720 connector->base.kdev->kobj.name);
8316f337 721
4f71d0cb 722 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 723 if (ret < 0) {
4f71d0cb 724 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 725 name, ret);
726 return;
ab2c0672 727 }
8a5e6aeb 728
0b99836f
JN		 729 ret = sysfs_create_link(&connector->base.kdev->kobj,
730 &intel_dp->aux.ddc.dev.kobj,
731 intel_dp->aux.ddc.dev.kobj.name);
732 if (ret < 0) {
733 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 734 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 735 }
a4fc5ed6
KP		 736}
737
80f65de3
ID		 738static void
739intel_dp_connector_unregister(struct intel_connector *intel_connector)
740{
741 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
742
743 sysfs_remove_link(&intel_connector->base.kdev->kobj,
0b99836f 744 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 745 intel_connector_unregister(intel_connector);
746}
747
c6bb3538
DV		 748static void
749intel_dp_set_clock(struct intel_encoder *encoder,
750 struct intel_crtc_config *pipe_config, int link_bw)
751{
752 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 753 const struct dp_link_dpll *divisor = NULL;
754 int i, count = 0;
c6bb3538
DV		 755
756 if (IS_G4X(dev)) {
9dd4ffdf
CML		 757 divisor = gen4_dpll;
758 count = ARRAY_SIZE(gen4_dpll);
c6bb3538
DV		 759 } else if (IS_HASWELL(dev)) {
760 /* Haswell has special-purpose DP DDI clocks. */
761 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 762 divisor = pch_dpll;
763 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 764 } else if (IS_CHERRYVIEW(dev)) {
765 divisor = chv_dpll;
766 count = ARRAY_SIZE(chv_dpll);
c6bb3538 767 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 768 divisor = vlv_dpll;
769 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 770 }
9dd4ffdf
CML		 771
772 if (divisor && count) {
773 for (i = 0; i < count; i++) {
774 if (link_bw == divisor[i].link_bw) {
775 pipe_config->dpll = divisor[i].dpll;
776 pipe_config->clock_set = true;
777 break;
778 }
779 }
c6bb3538
DV		 780 }
781}
782
439d7ac0
PB		 783static void
784intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
785{
786 struct drm_device *dev = crtc->base.dev;
787 struct drm_i915_private *dev_priv = dev->dev_private;
788 enum transcoder transcoder = crtc->config.cpu_transcoder;
789
790 I915_WRITE(PIPE_DATA_M2(transcoder),
791 TU_SIZE(m_n->tu) | m_n->gmch_m);
792 I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
793 I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
794 I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
795}
796
00c09d70 797bool
5bfe2ac0
DV		 798intel_dp_compute_config(struct intel_encoder *encoder,
799 struct intel_crtc_config *pipe_config)
a4fc5ed6 800{
5bfe2ac0 801 struct drm_device *dev = encoder->base.dev;
36008365 802 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 803 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 804 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 805 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 806 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 807 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 808 int lane_count, clock;
56071a20 809 int min_lane_count = 1;
eeb6324d 810 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 811 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 812 int min_clock = 0;
06ea66b6 813 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 814 int bpp, mode_rate;
06ea66b6 815 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 816 int link_avail, link_clock;
a4fc5ed6 817
bc7d38a4 818 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 819 pipe_config->has_pch_encoder = true;
820
03afc4a2 821 pipe_config->has_dp_encoder = true;
9ed109a7 822 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 823
dd06f90e
JN		 824 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
825 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
826 adjusted_mode);
2dd24552
JB		 827 if (!HAS_PCH_SPLIT(dev))
828 intel_gmch_panel_fitting(intel_crtc, pipe_config,
829 intel_connector->panel.fitting_mode);
830 else
b074cec8
JB		 831 intel_pch_panel_fitting(intel_crtc, pipe_config,
832 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 833 }
834
cb1793ce 835 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 836 return false;
837
083f9560
DV		 838 DRM_DEBUG_KMS("DP link computation with max lane count %i "
839 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 840 max_lane_count, bws[max_clock],
841 adjusted_mode->crtc_clock);
083f9560 842
36008365
DV		 843 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
844 * bpc in between. */
3e7ca985 845 bpp = pipe_config->pipe_bpp;
56071a20
JN		 846 if (is_edp(intel_dp)) {
847 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
848 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
849 dev_priv->vbt.edp_bpp);
850 bpp = dev_priv->vbt.edp_bpp;
851 }
852
f4cdbc21
JN		 853 if (IS_BROADWELL(dev)) {
854 /* Yes, it's an ugly hack. */
855 min_lane_count = max_lane_count;
856 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
857 min_lane_count);
858 } else if (dev_priv->vbt.edp_lanes) {
56071a20
JN		 859 min_lane_count = min(dev_priv->vbt.edp_lanes,
860 max_lane_count);
861 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
862 min_lane_count);
863 }
864
865 if (dev_priv->vbt.edp_rate) {
866 min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
867 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
868 bws[min_clock]);
869 }
7984211e 870 }
657445fe 871
36008365 872 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 873 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
874 bpp);
36008365 875
56071a20
JN		 876 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
877 for (clock = min_clock; clock <= max_clock; clock++) {
36008365
DV		 878 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
879 link_avail = intel_dp_max_data_rate(link_clock,
880 lane_count);
881
882 if (mode_rate <= link_avail) {
883 goto found;
884 }
885 }
886 }
887 }
c4867936 888
36008365 889 return false;
3685a8f3 890
36008365 891found:
55bc60db
VS		 892 if (intel_dp->color_range_auto) {
893 /*
894 * See:
895 * CEA-861-E - 5.1 Default Encoding Parameters
896 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
897 */
18316c8c 898 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 899 intel_dp->color_range = DP_COLOR_RANGE_16_235;
900 else
901 intel_dp->color_range = 0;
902 }
903
3685a8f3 904 if (intel_dp->color_range)
50f3b016 905 pipe_config->limited_color_range = true;
a4fc5ed6 906
36008365
DV		 907 intel_dp->link_bw = bws[clock];
908 intel_dp->lane_count = lane_count;
657445fe 909 pipe_config->pipe_bpp = bpp;
ff9a6750 910 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 911
36008365
DV		 912 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
913 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 914 pipe_config->port_clock, bpp);
36008365
DV		 915 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
916 mode_rate, link_avail);
a4fc5ed6 917
03afc4a2 918 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 919 adjusted_mode->crtc_clock,
920 pipe_config->port_clock,
03afc4a2 921 &pipe_config->dp_m_n);
9d1a455b 922
439d7ac0
PB		 923 if (intel_connector->panel.downclock_mode != NULL &&
924 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
925 intel_link_compute_m_n(bpp, lane_count,
926 intel_connector->panel.downclock_mode->clock,
927 pipe_config->port_clock,
928 &pipe_config->dp_m2_n2);
929 }
930
c6bb3538
DV		 931 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
932
03afc4a2 933 return true;
a4fc5ed6
KP		 934}
935
7c62a164 936static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 937{
7c62a164
DV		 938 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
939 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
940 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 941 struct drm_i915_private *dev_priv = dev->dev_private;
942 u32 dpa_ctl;
943
ff9a6750 944 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 945 dpa_ctl = I915_READ(DP_A);
946 dpa_ctl &= ~DP_PLL_FREQ_MASK;
947
ff9a6750 948 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 949 /* For a long time we've carried around a ILK-DevA w/a for the
950 * 160MHz clock. If we're really unlucky, it's still required.
951 */
952 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 953 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 954 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 955 } else {
956 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 957 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 958 }
1ce17038 959
ea9b6006
DV		 960 I915_WRITE(DP_A, dpa_ctl);
961
962 POSTING_READ(DP_A);
963 udelay(500);
964}
965
8ac33ed3 966static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 967{
b934223d 968 struct drm_device *dev = encoder->base.dev;
417e822d 969 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 970 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 971 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 972 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
973 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 974
417e822d 975 /*
1a2eb460 976 * There are four kinds of DP registers:
417e822d
KP		 977 *
978 * IBX PCH
1a2eb460
KP		 979 * SNB CPU
980 * IVB CPU
417e822d
KP		 981 * CPT PCH
982 *
983 * IBX PCH and CPU are the same for almost everything,
984 * except that the CPU DP PLL is configured in this
985 * register
986 *
987 * CPT PCH is quite different, having many bits moved
988 * to the TRANS_DP_CTL register instead. That
989 * configuration happens (oddly) in ironlake_pch_enable
990 */
9c9e7927 991
417e822d
KP		 992 /* Preserve the BIOS-computed detected bit. This is
993 * supposed to be read-only.
994 */
995 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 996
417e822d 997 /* Handle DP bits in common between all three register formats */
417e822d 998 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 999 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1000
9ed109a7 1001 if (crtc->config.has_audio) {
e0dac65e 1002 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1003 pipe_name(crtc->pipe));
ea5b213a 1004 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1005 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1006 }
247d89f6 1007
417e822d 1008 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1009
bc7d38a4 1010 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1011 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1012 intel_dp->DP |= DP_SYNC_HS_HIGH;
1013 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1014 intel_dp->DP |= DP_SYNC_VS_HIGH;
1015 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1016
6aba5b6c 1017 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1018 intel_dp->DP |= DP_ENHANCED_FRAMING;
1019
7c62a164 1020 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1021 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1022 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1023 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1024
1025 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1026 intel_dp->DP |= DP_SYNC_HS_HIGH;
1027 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1028 intel_dp->DP |= DP_SYNC_VS_HIGH;
1029 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1030
6aba5b6c 1031 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1032 intel_dp->DP |= DP_ENHANCED_FRAMING;
1033
44f37d1f
CML		 1034 if (!IS_CHERRYVIEW(dev)) {
1035 if (crtc->pipe == 1)
1036 intel_dp->DP |= DP_PIPEB_SELECT;
1037 } else {
1038 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1039 }
417e822d
KP		 1040 } else {
1041 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1042 }
a4fc5ed6
KP		 1043}
1044
ffd6749d
PZ		 1045#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1046#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1047
1a5ef5b7
PZ		 1048#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1049#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1050
ffd6749d
PZ		 1051#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1052#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1053
4be73780 1054static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1055 u32 mask,
1056 u32 value)
bd943159 1057{
30add22d 1058 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1059 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1060 u32 pp_stat_reg, pp_ctrl_reg;
1061
bf13e81b
JN		 1062 pp_stat_reg = _pp_stat_reg(intel_dp);
1063 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1064
99ea7127 1065 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1066 mask, value,
1067 I915_READ(pp_stat_reg),
1068 I915_READ(pp_ctrl_reg));
32ce697c 1069
453c5420 1070 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1071 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1072 I915_READ(pp_stat_reg),
1073 I915_READ(pp_ctrl_reg));
32ce697c 1074 }
54c136d4
CW		 1075
1076 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1077}
32ce697c 1078
4be73780 1079static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1080{
1081 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1082 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1083}
1084
4be73780 1085static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1086{
1087 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1088 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1089}
1090
4be73780 1091static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1092{
1093 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1094
1095 /* When we disable the VDD override bit last we have to do the manual
1096 * wait. */
1097 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1098 intel_dp->panel_power_cycle_delay);
1099
4be73780 1100 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1101}
1102
4be73780 1103static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1104{
1105 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1106 intel_dp->backlight_on_delay);
1107}
1108
4be73780 1109static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1110{
1111 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1112 intel_dp->backlight_off_delay);
1113}
99ea7127 1114
832dd3c1
KP		 1115/* Read the current pp_control value, unlocking the register if it
1116 * is locked
1117 */
1118
453c5420 1119static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1120{
453c5420
JB		 1121 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1122 struct drm_i915_private *dev_priv = dev->dev_private;
1123 u32 control;
832dd3c1 1124
bf13e81b 1125 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1126 control &= ~PANEL_UNLOCK_MASK;
1127 control |= PANEL_UNLOCK_REGS;
1128 return control;
bd943159
KP		 1129}
1130
adddaaf4 1131static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1132{
30add22d 1133 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1134 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1135 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1136 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1137 enum intel_display_power_domain power_domain;
5d613501 1138 u32 pp;
453c5420 1139 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1140 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1141
97af61f5 1142 if (!is_edp(intel_dp))
adddaaf4 1143 return false;
bd943159
KP		 1144
1145 intel_dp->want_panel_vdd = true;
99ea7127 1146
4be73780 1147 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1148 return need_to_disable;
b0665d57 1149
4e6e1a54
ID		 1150 power_domain = intel_display_port_power_domain(intel_encoder);
1151 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1152
b0665d57 1153 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1154
4be73780
DV		 1155 if (!edp_have_panel_power(intel_dp))
1156 wait_panel_power_cycle(intel_dp);
99ea7127 1157
453c5420 1158 pp = ironlake_get_pp_control(intel_dp);
5d613501 1159 pp |= EDP_FORCE_VDD;
ebf33b18 1160
bf13e81b
JN		 1161 pp_stat_reg = _pp_stat_reg(intel_dp);
1162 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1163
1164 I915_WRITE(pp_ctrl_reg, pp);
1165 POSTING_READ(pp_ctrl_reg);
1166 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1167 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1168 /*
1169 * If the panel wasn't on, delay before accessing aux channel
1170 */
4be73780 1171 if (!edp_have_panel_power(intel_dp)) {
bd943159 1172 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1173 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1174 }
adddaaf4
JN		 1175
1176 return need_to_disable;
1177}
1178
b80d6c78 1179void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4
JN		 1180{
1181 if (is_edp(intel_dp)) {
1182 bool vdd = _edp_panel_vdd_on(intel_dp);
1183
1184 WARN(!vdd, "eDP VDD already requested on\n");
1185 }
5d613501
JB		 1186}
1187
4be73780 1188static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1189{
30add22d 1190 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1191 struct drm_i915_private *dev_priv = dev->dev_private;
1192 u32 pp;
453c5420 1193 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1194
51fd371b 1195 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
a0e99e68 1196
4be73780 1197 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
4e6e1a54
ID		 1198 struct intel_digital_port *intel_dig_port =
1199 dp_to_dig_port(intel_dp);
1200 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1201 enum intel_display_power_domain power_domain;
1202
b0665d57
PZ		 1203 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1204
453c5420 1205 pp = ironlake_get_pp_control(intel_dp);
bd943159 1206 pp &= ~EDP_FORCE_VDD;
bd943159 1207
9f08ef59
PZ		 1208 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1209 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1210
1211 I915_WRITE(pp_ctrl_reg, pp);
1212 POSTING_READ(pp_ctrl_reg);
99ea7127 1213
453c5420
JB		 1214 /* Make sure sequencer is idle before allowing subsequent activity */
1215 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1216 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c
PZ		 1217
1218 if ((pp & POWER_TARGET_ON) == 0)
dce56b3c 1219 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1220
4e6e1a54
ID		 1221 power_domain = intel_display_port_power_domain(intel_encoder);
1222 intel_display_power_put(dev_priv, power_domain);
bd943159
KP		 1223 }
1224}
5d613501 1225
4be73780 1226static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1227{
1228 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1229 struct intel_dp, panel_vdd_work);
30add22d 1230 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1231
51fd371b 1232 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 1233 edp_panel_vdd_off_sync(intel_dp);
51fd371b 1234 drm_modeset_unlock(&dev->mode_config.connection_mutex);
bd943159
KP		 1235}
1236
4be73780 1237static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1238{
97af61f5
KP		 1239 if (!is_edp(intel_dp))
1240 return;
5d613501 1241
bd943159 1242 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1243
bd943159
KP		 1244 intel_dp->want_panel_vdd = false;
1245
1246 if (sync) {
4be73780 1247 edp_panel_vdd_off_sync(intel_dp);
bd943159
KP		 1248 } else {
1249 /*
1250 * Queue the timer to fire a long
1251 * time from now (relative to the power down delay)
1252 * to keep the panel power up across a sequence of operations
1253 */
1254 schedule_delayed_work(&intel_dp->panel_vdd_work,
1255 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1256 }
5d613501
JB		 1257}
1258
4be73780 1259void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1260{
30add22d 1261 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1262 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1263 u32 pp;
453c5420 1264 u32 pp_ctrl_reg;
9934c132 1265
97af61f5 1266 if (!is_edp(intel_dp))
bd943159 1267 return;
99ea7127
KP		 1268
1269 DRM_DEBUG_KMS("Turn eDP power on\n");
1270
4be73780 1271 if (edp_have_panel_power(intel_dp)) {
99ea7127 1272 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1273 return;
99ea7127 1274 }
9934c132 1275
4be73780 1276 wait_panel_power_cycle(intel_dp);
37c6c9b0 1277
bf13e81b 1278 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1279 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1280 if (IS_GEN5(dev)) {
1281 /* ILK workaround: disable reset around power sequence */
1282 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1283 I915_WRITE(pp_ctrl_reg, pp);
1284 POSTING_READ(pp_ctrl_reg);
05ce1a49 1285 }
37c6c9b0 1286
1c0ae80a 1287 pp |= POWER_TARGET_ON;
99ea7127
KP		 1288 if (!IS_GEN5(dev))
1289 pp |= PANEL_POWER_RESET;
1290
453c5420
JB		 1291 I915_WRITE(pp_ctrl_reg, pp);
1292 POSTING_READ(pp_ctrl_reg);
9934c132 1293
4be73780 1294 wait_panel_on(intel_dp);
dce56b3c 1295 intel_dp->last_power_on = jiffies;
9934c132 1296
05ce1a49
KP		 1297 if (IS_GEN5(dev)) {
1298 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1299 I915_WRITE(pp_ctrl_reg, pp);
1300 POSTING_READ(pp_ctrl_reg);
05ce1a49 1301 }
9934c132
JB		 1302}
1303
4be73780 1304void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1305{
4e6e1a54
ID		 1306 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1307 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1308 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1309 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1310 enum intel_display_power_domain power_domain;
99ea7127 1311 u32 pp;
453c5420 1312 u32 pp_ctrl_reg;
9934c132 1313
97af61f5
KP		 1314 if (!is_edp(intel_dp))
1315 return;
37c6c9b0 1316
99ea7127 1317 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1318
4be73780 1319 edp_wait_backlight_off(intel_dp);
dce56b3c 1320
24f3e092
JN		 1321 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1322
453c5420 1323 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1324 /* We need to switch off panel power _and_ force vdd, for otherwise some
1325 * panels get very unhappy and cease to work. */
b3064154
PJ		 1326 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1327 EDP_BLC_ENABLE);
453c5420 1328
bf13e81b 1329 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1330
849e39f5
PZ		 1331 intel_dp->want_panel_vdd = false;
1332
453c5420
JB		 1333 I915_WRITE(pp_ctrl_reg, pp);
1334 POSTING_READ(pp_ctrl_reg);
9934c132 1335
dce56b3c 1336 intel_dp->last_power_cycle = jiffies;
4be73780 1337 wait_panel_off(intel_dp);
849e39f5
PZ		 1338
1339 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1340 power_domain = intel_display_port_power_domain(intel_encoder);
1341 intel_display_power_put(dev_priv, power_domain);
9934c132
JB		 1342}
1343
4be73780 1344void intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1345{
da63a9f2
PZ		 1346 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1347 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1348 struct drm_i915_private *dev_priv = dev->dev_private;
1349 u32 pp;
453c5420 1350 u32 pp_ctrl_reg;
32f9d658 1351
f01eca2e
KP		 1352 if (!is_edp(intel_dp))
1353 return;
1354
28c97730 1355 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1356 /*
1357 * If we enable the backlight right away following a panel power
1358 * on, we may see slight flicker as the panel syncs with the eDP
1359 * link. So delay a bit to make sure the image is solid before
1360 * allowing it to appear.
1361 */
4be73780 1362 wait_backlight_on(intel_dp);
453c5420 1363 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1364 pp |= EDP_BLC_ENABLE;
453c5420 1365
bf13e81b 1366 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1367
1368 I915_WRITE(pp_ctrl_reg, pp);
1369 POSTING_READ(pp_ctrl_reg);
035aa3de 1370
752aa88a 1371 intel_panel_enable_backlight(intel_dp->attached_connector);
32f9d658
ZW		 1372}
1373
4be73780 1374void intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1375{
30add22d 1376 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1377 struct drm_i915_private *dev_priv = dev->dev_private;
1378 u32 pp;
453c5420 1379 u32 pp_ctrl_reg;
32f9d658 1380
f01eca2e
KP		 1381 if (!is_edp(intel_dp))
1382 return;
1383
752aa88a 1384 intel_panel_disable_backlight(intel_dp->attached_connector);
035aa3de 1385
28c97730 1386 DRM_DEBUG_KMS("\n");
453c5420 1387 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1388 pp &= ~EDP_BLC_ENABLE;
453c5420 1389
bf13e81b 1390 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1391
1392 I915_WRITE(pp_ctrl_reg, pp);
1393 POSTING_READ(pp_ctrl_reg);
dce56b3c 1394 intel_dp->last_backlight_off = jiffies;
32f9d658 1395}
a4fc5ed6 1396
2bd2ad64 1397static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1398{
da63a9f2
PZ		 1399 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1400 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1401 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1402 struct drm_i915_private *dev_priv = dev->dev_private;
1403 u32 dpa_ctl;
1404
2bd2ad64
DV		 1405 assert_pipe_disabled(dev_priv,
1406 to_intel_crtc(crtc)->pipe);
1407
d240f20f
JB		 1408 DRM_DEBUG_KMS("\n");
1409 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1410 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1411 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1412
1413 /* We don't adjust intel_dp->DP while tearing down the link, to
1414 * facilitate link retraining (e.g. after hotplug). Hence clear all
1415 * enable bits here to ensure that we don't enable too much. */
1416 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1417 intel_dp->DP |= DP_PLL_ENABLE;
1418 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1419 POSTING_READ(DP_A);
1420 udelay(200);
d240f20f
JB		 1421}
1422
2bd2ad64 1423static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1424{
da63a9f2
PZ		 1425 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1426 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1427 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1428 struct drm_i915_private *dev_priv = dev->dev_private;
1429 u32 dpa_ctl;
1430
2bd2ad64
DV		 1431 assert_pipe_disabled(dev_priv,
1432 to_intel_crtc(crtc)->pipe);
1433
d240f20f 1434 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1435 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1436 "dp pll off, should be on\n");
1437 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1438
1439 /* We can't rely on the value tracked for the DP register in
1440 * intel_dp->DP because link_down must not change that (otherwise link
1441 * re-training will fail. */
298b0b39 1442 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1443 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1444 POSTING_READ(DP_A);
d240f20f
JB		 1445 udelay(200);
1446}
1447
c7ad3810 1448/* If the sink supports it, try to set the power state appropriately */
c19b0669 1449void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1450{
1451 int ret, i;
1452
1453 /* Should have a valid DPCD by this point */
1454 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1455 return;
1456
1457 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1458 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1459 DP_SET_POWER_D3);
c7ad3810
JB		 1460 if (ret != 1)
1461 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1462 } else {
1463 /*
1464 * When turning on, we need to retry for 1ms to give the sink
1465 * time to wake up.
1466 */
1467 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1468 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1469 DP_SET_POWER_D0);
c7ad3810
JB		 1470 if (ret == 1)
1471 break;
1472 msleep(1);
1473 }
1474 }
1475}
1476
19d8fe15
DV		 1477static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1478 enum pipe *pipe)
d240f20f 1479{
19d8fe15 1480 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1481 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1482 struct drm_device *dev = encoder->base.dev;
1483 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1484 enum intel_display_power_domain power_domain;
1485 u32 tmp;
1486
1487 power_domain = intel_display_port_power_domain(encoder);
1488 if (!intel_display_power_enabled(dev_priv, power_domain))
1489 return false;
1490
1491 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1492
1493 if (!(tmp & DP_PORT_EN))
1494 return false;
1495
bc7d38a4 1496 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1497 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1498 } else if (IS_CHERRYVIEW(dev)) {
1499 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1500 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1501 *pipe = PORT_TO_PIPE(tmp);
1502 } else {
1503 u32 trans_sel;
1504 u32 trans_dp;
1505 int i;
1506
1507 switch (intel_dp->output_reg) {
1508 case PCH_DP_B:
1509 trans_sel = TRANS_DP_PORT_SEL_B;
1510 break;
1511 case PCH_DP_C:
1512 trans_sel = TRANS_DP_PORT_SEL_C;
1513 break;
1514 case PCH_DP_D:
1515 trans_sel = TRANS_DP_PORT_SEL_D;
1516 break;
1517 default:
1518 return true;
1519 }
1520
1521 for_each_pipe(i) {
1522 trans_dp = I915_READ(TRANS_DP_CTL(i));
1523 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1524 *pipe = i;
1525 return true;
1526 }
1527 }
19d8fe15 1528
4a0833ec
DV		 1529 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1530 intel_dp->output_reg);
1531 }
d240f20f 1532
19d8fe15
DV		 1533 return true;
1534}
d240f20f 1535
045ac3b5
JB		 1536static void intel_dp_get_config(struct intel_encoder *encoder,
1537 struct intel_crtc_config *pipe_config)
1538{
1539 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1540 u32 tmp, flags = 0;
63000ef6
XZ		 1541 struct drm_device *dev = encoder->base.dev;
1542 struct drm_i915_private *dev_priv = dev->dev_private;
1543 enum port port = dp_to_dig_port(intel_dp)->port;
1544 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1545 int dotclock;
045ac3b5 1546
9ed109a7
DV		 1547 tmp = I915_READ(intel_dp->output_reg);
1548 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1549 pipe_config->has_audio = true;
1550
63000ef6 1551 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1552 if (tmp & DP_SYNC_HS_HIGH)
1553 flags |= DRM_MODE_FLAG_PHSYNC;
1554 else
1555 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1556
63000ef6
XZ		 1557 if (tmp & DP_SYNC_VS_HIGH)
1558 flags |= DRM_MODE_FLAG_PVSYNC;
1559 else
1560 flags |= DRM_MODE_FLAG_NVSYNC;
1561 } else {
1562 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1563 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1564 flags |= DRM_MODE_FLAG_PHSYNC;
1565 else
1566 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1567
63000ef6
XZ		 1568 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1569 flags |= DRM_MODE_FLAG_PVSYNC;
1570 else
1571 flags |= DRM_MODE_FLAG_NVSYNC;
1572 }
045ac3b5
JB		 1573
1574 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1575
eb14cb74
VS		 1576 pipe_config->has_dp_encoder = true;
1577
1578 intel_dp_get_m_n(crtc, pipe_config);
1579
18442d08 1580 if (port == PORT_A) {
f1f644dc
JB		 1581 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1582 pipe_config->port_clock = 162000;
1583 else
1584 pipe_config->port_clock = 270000;
1585 }
18442d08
VS		 1586
1587 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1588 &pipe_config->dp_m_n);
1589
1590 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1591 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1592
241bfc38 1593 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1594
c6cd2ee2
JN		 1595 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1596 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1597 /*
1598 * This is a big fat ugly hack.
1599 *
1600 * Some machines in UEFI boot mode provide us a VBT that has 18
1601 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1602 * unknown we fail to light up. Yet the same BIOS boots up with
1603 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1604 * max, not what it tells us to use.
1605 *
1606 * Note: This will still be broken if the eDP panel is not lit
1607 * up by the BIOS, and thus we can't get the mode at module
1608 * load.
1609 */
1610 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1611 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1612 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1613 }
045ac3b5
JB		 1614}
1615
a031d709 1616static bool is_edp_psr(struct drm_device *dev)
2293bb5c 1617{
a031d709
RV		 1618 struct drm_i915_private *dev_priv = dev->dev_private;
1619
1620 return dev_priv->psr.sink_support;
2293bb5c
SK		 1621}
1622
2b28bb1b
RV		 1623static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1624{
1625 struct drm_i915_private *dev_priv = dev->dev_private;
1626
18b5992c 1627 if (!HAS_PSR(dev))
2b28bb1b
RV		 1628 return false;
1629
18b5992c 1630 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1631}
1632
1633static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1634 struct edp_vsc_psr *vsc_psr)
1635{
1636 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1637 struct drm_device *dev = dig_port->base.base.dev;
1638 struct drm_i915_private *dev_priv = dev->dev_private;
1639 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1640 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1641 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1642 uint32_t *data = (uint32_t *) vsc_psr;
1643 unsigned int i;
1644
1645 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1646 the video DIP being updated before program video DIP data buffer
1647 registers for DIP being updated. */
1648 I915_WRITE(ctl_reg, 0);
1649 POSTING_READ(ctl_reg);
1650
1651 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1652 if (i < sizeof(struct edp_vsc_psr))
1653 I915_WRITE(data_reg + i, *data++);
1654 else
1655 I915_WRITE(data_reg + i, 0);
1656 }
1657
1658 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1659 POSTING_READ(ctl_reg);
1660}
1661
1662static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1663{
1664 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1665 struct drm_i915_private *dev_priv = dev->dev_private;
1666 struct edp_vsc_psr psr_vsc;
1667
6118efe5 1668 if (dev_priv->psr.setup_done)
2b28bb1b
RV		 1669 return;
1670
1671 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1672 memset(&psr_vsc, 0, sizeof(psr_vsc));
1673 psr_vsc.sdp_header.HB0 = 0;
1674 psr_vsc.sdp_header.HB1 = 0x7;
1675 psr_vsc.sdp_header.HB2 = 0x2;
1676 psr_vsc.sdp_header.HB3 = 0x8;
1677 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1678
1679 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1680 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1681 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b 1682
6118efe5 1683 dev_priv->psr.setup_done = true;
2b28bb1b
RV		 1684}
1685
1686static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1687{
1688 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1689 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1690 uint32_t aux_clock_divider;
2b28bb1b
RV		 1691 int precharge = 0x3;
1692 int msg_size = 5; /* Header(4) + Message(1) */
1693
ec5b01dd
DL		 1694 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1695
2b28bb1b
RV		 1696 /* Enable PSR in sink */
1697 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
9d1a1031
JN		 1698 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1699 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 1700 else
9d1a1031
JN		 1701 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1702 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 1703
1704 /* Setup AUX registers */
18b5992c
BW		 1705 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1706 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1707 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1708 DP_AUX_CH_CTL_TIME_OUT_400us |
1709 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1710 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1711 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1712}
1713
1714static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1715{
1716 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1717 struct drm_i915_private *dev_priv = dev->dev_private;
1718 uint32_t max_sleep_time = 0x1f;
1719 uint32_t idle_frames = 1;
1720 uint32_t val = 0x0;
ed8546ac 1721 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
2b28bb1b
RV		 1722
1723 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1724 val |= EDP_PSR_LINK_STANDBY;
1725 val |= EDP_PSR_TP2_TP3_TIME_0us;
1726 val |= EDP_PSR_TP1_TIME_0us;
1727 val |= EDP_PSR_SKIP_AUX_EXIT;
1728 } else
1729 val |= EDP_PSR_LINK_DISABLE;
1730
18b5992c 1731 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 1732 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 1733 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1734 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1735 EDP_PSR_ENABLE);
1736}
1737
3f51e471
RV		 1738static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1739{
1740 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1741 struct drm_device *dev = dig_port->base.base.dev;
1742 struct drm_i915_private *dev_priv = dev->dev_private;
1743 struct drm_crtc *crtc = dig_port->base.base.crtc;
1744 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
f4510a27 1745 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->primary->fb)->obj;
3f51e471
RV		 1746 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1747
a031d709
RV		 1748 dev_priv->psr.source_ok = false;
1749
3f51e471
RV		 1750 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1751 (dig_port->port != PORT_A)) {
1752 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1753 return false;
1754 }
1755
d330a953 1756 if (!i915.enable_psr) {
105b7c11 1757 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1758 return false;
1759 }
1760
cd234b0b
CW		 1761 crtc = dig_port->base.base.crtc;
1762 if (crtc == NULL) {
1763 DRM_DEBUG_KMS("crtc not active for PSR\n");
cd234b0b
CW		 1764 return false;
1765 }
1766
1767 intel_crtc = to_intel_crtc(crtc);
20ddf665 1768 if (!intel_crtc_active(crtc)) {
3f51e471 1769 DRM_DEBUG_KMS("crtc not active for PSR\n");
3f51e471
RV		 1770 return false;
1771 }
1772
f4510a27 1773 obj = to_intel_framebuffer(crtc->primary->fb)->obj;
3f51e471
RV		 1774 if (obj->tiling_mode != I915_TILING_X ||
1775 obj->fence_reg == I915_FENCE_REG_NONE) {
1776 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
3f51e471
RV		 1777 return false;
1778 }
1779
1780 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1781 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
3f51e471
RV		 1782 return false;
1783 }
1784
1785 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1786 S3D_ENABLE) {
1787 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1788 return false;
1789 }
1790
ca73b4f0 1791 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1792 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1793 return false;
1794 }
1795
a031d709 1796 dev_priv->psr.source_ok = true;
3f51e471
RV		 1797 return true;
1798}
1799
3d739d92 1800static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1801{
1802 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1803
3f51e471
RV		 1804 if (!intel_edp_psr_match_conditions(intel_dp) ||
1805 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1806 return;
1807
2b28bb1b
RV		 1808 /* Enable PSR on the panel */
1809 intel_edp_psr_enable_sink(intel_dp);
1810
1811 /* Enable PSR on the host */
1812 intel_edp_psr_enable_source(intel_dp);
1813}
1814
3d739d92
RV		 1815void intel_edp_psr_enable(struct intel_dp *intel_dp)
1816{
1817 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1818
4704c573
RV		 1819 if (!HAS_PSR(dev)) {
1820 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1821 return;
1822 }
1823
16487254
RV		 1824 /* Setup PSR once */
1825 intel_edp_psr_setup(intel_dp);
1826
3d739d92
RV		 1827 if (intel_edp_psr_match_conditions(intel_dp) &&
1828 !intel_edp_is_psr_enabled(dev))
1829 intel_edp_psr_do_enable(intel_dp);
1830}
1831
2b28bb1b
RV		 1832void intel_edp_psr_disable(struct intel_dp *intel_dp)
1833{
1834 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1835 struct drm_i915_private *dev_priv = dev->dev_private;
1836
1837 if (!intel_edp_is_psr_enabled(dev))
1838 return;
1839
18b5992c
BW		 1840 I915_WRITE(EDP_PSR_CTL(dev),
1841 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2b28bb1b
RV		 1842
1843 /* Wait till PSR is idle */
18b5992c 1844 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2b28bb1b
RV		 1845 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1846 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1847}
1848
3d739d92
RV		 1849void intel_edp_psr_update(struct drm_device *dev)
1850{
16487254 1851 struct drm_i915_private *dev_priv = dev->dev_private;
3d739d92
RV		 1852 struct intel_encoder *encoder;
1853 struct intel_dp *intel_dp = NULL;
1854
4704c573
RV		 1855 if (!HAS_PSR(dev))
1856 return;
1857
16487254
RV		 1858 if (!dev_priv->psr.setup_done)
1859 return;
1860
3d739d92
RV		 1861 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1862 if (encoder->type == INTEL_OUTPUT_EDP) {
1863 intel_dp = enc_to_intel_dp(&encoder->base);
1864
a031d709 1865 if (!is_edp_psr(dev))
3d739d92
RV		 1866 return;
1867
1868 if (!intel_edp_psr_match_conditions(intel_dp))
1869 intel_edp_psr_disable(intel_dp);
1870 else
1871 if (!intel_edp_is_psr_enabled(dev))
1872 intel_edp_psr_do_enable(intel_dp);
1873 }
1874}
1875
e8cb4558 1876static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1877{
e8cb4558 1878 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1879 enum port port = dp_to_dig_port(intel_dp)->port;
1880 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1881
1882 /* Make sure the panel is off before trying to change the mode. But also
1883 * ensure that we have vdd while we switch off the panel. */
24f3e092 1884 intel_edp_panel_vdd_on(intel_dp);
4be73780 1885 intel_edp_backlight_off(intel_dp);
fdbc3b1f 1886 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 1887 intel_edp_panel_off(intel_dp);
3739850b
DV		 1888
1889 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1890 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1891 intel_dp_link_down(intel_dp);
d240f20f
JB		 1892}
1893
49277c31 1894static void g4x_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1895{
2bd2ad64 1896 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1897 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 1898
49277c31
VS		 1899 if (port != PORT_A)
1900 return;
1901
1902 intel_dp_link_down(intel_dp);
1903 ironlake_edp_pll_off(intel_dp);
1904}
1905
1906static void vlv_post_disable_dp(struct intel_encoder *encoder)
1907{
1908 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1909
1910 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 1911}
1912
580d3811
VS		 1913static void chv_post_disable_dp(struct intel_encoder *encoder)
1914{
1915 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1916 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1917 struct drm_device *dev = encoder->base.dev;
1918 struct drm_i915_private *dev_priv = dev->dev_private;
1919 struct intel_crtc *intel_crtc =
1920 to_intel_crtc(encoder->base.crtc);
1921 enum dpio_channel ch = vlv_dport_to_channel(dport);
1922 enum pipe pipe = intel_crtc->pipe;
1923 u32 val;
1924
1925 intel_dp_link_down(intel_dp);
1926
1927 mutex_lock(&dev_priv->dpio_lock);
1928
1929 /* Propagate soft reset to data lane reset */
97fd4d5c 1930 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 1931 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 1932 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 1933
97fd4d5c
VS		 1934 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1935 val |= CHV_PCS_REQ_SOFTRESET_EN;
1936 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1937
1938 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1939 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1940 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1941
1942 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 1943 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 1944 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 1945
1946 mutex_unlock(&dev_priv->dpio_lock);
1947}
1948
e8cb4558 1949static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1950{
e8cb4558
DV		 1951 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1952 struct drm_device *dev = encoder->base.dev;
1953 struct drm_i915_private *dev_priv = dev->dev_private;
1954 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1955
0c33d8d7
DV		 1956 if (WARN_ON(dp_reg & DP_PORT_EN))
1957 return;
5d613501 1958
24f3e092 1959 intel_edp_panel_vdd_on(intel_dp);
f01eca2e 1960 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1961 intel_dp_start_link_train(intel_dp);
4be73780
DV		 1962 intel_edp_panel_on(intel_dp);
1963 edp_panel_vdd_off(intel_dp, true);
33a34e4e 1964 intel_dp_complete_link_train(intel_dp);
3ab9c637 1965 intel_dp_stop_link_train(intel_dp);
ab1f90f9 1966}
89b667f8 1967
ecff4f3b
JN		 1968static void g4x_enable_dp(struct intel_encoder *encoder)
1969{
828f5c6e
JN		 1970 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1971
ecff4f3b 1972 intel_enable_dp(encoder);
4be73780 1973 intel_edp_backlight_on(intel_dp);
ab1f90f9 1974}
89b667f8 1975
ab1f90f9
JN		 1976static void vlv_enable_dp(struct intel_encoder *encoder)
1977{
828f5c6e
JN		 1978 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1979
4be73780 1980 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 1981}
1982
ecff4f3b 1983static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 1984{
1985 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1986 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1987
8ac33ed3
DV		 1988 intel_dp_prepare(encoder);
1989
d41f1efb
DV		 1990 /* Only ilk+ has port A */
1991 if (dport->port == PORT_A) {
1992 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 1993 ironlake_edp_pll_on(intel_dp);
d41f1efb 1994 }
ab1f90f9
JN		 1995}
1996
1997static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1998{
2bd2ad64 1999 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2000 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2001 struct drm_device *dev = encoder->base.dev;
89b667f8 2002 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2003 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2004 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 2005 int pipe = intel_crtc->pipe;
bf13e81b 2006 struct edp_power_seq power_seq;
ab1f90f9 2007 u32 val;
a4fc5ed6 2008
ab1f90f9 2009 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2010
ab3c759a 2011 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2012 val = 0;
2013 if (pipe)
2014 val |= (1<<21);
2015 else
2016 val &= ~(1<<21);
2017 val |= 0x001000c4;
ab3c759a
CML		 2018 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2019 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2020 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2021
ab1f90f9
JN		 2022 mutex_unlock(&dev_priv->dpio_lock);
2023
2cac613b
ID		 2024 if (is_edp(intel_dp)) {
2025 /* init power sequencer on this pipe and port */
2026 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2027 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2028 &power_seq);
2029 }
bf13e81b 2030
ab1f90f9
JN		 2031 intel_enable_dp(encoder);
2032
e4607fcf 2033 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 2034}
2035
ecff4f3b 2036static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2037{
2038 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2039 struct drm_device *dev = encoder->base.dev;
2040 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2041 struct intel_crtc *intel_crtc =
2042 to_intel_crtc(encoder->base.crtc);
e4607fcf 2043 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2044 int pipe = intel_crtc->pipe;
89b667f8 2045
8ac33ed3
DV		 2046 intel_dp_prepare(encoder);
2047
89b667f8 2048 /* Program Tx lane resets to default */
0980a60f 2049 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2050 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2051 DPIO_PCS_TX_LANE2_RESET |
2052 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2053 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2054 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2055 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2056 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2057 DPIO_PCS_CLK_SOFT_RESET);
2058
2059 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2060 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2061 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2062 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2063 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2064}
2065
e4a1d846
CML		 2066static void chv_pre_enable_dp(struct intel_encoder *encoder)
2067{
2068 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2069 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2070 struct drm_device *dev = encoder->base.dev;
2071 struct drm_i915_private *dev_priv = dev->dev_private;
2072 struct edp_power_seq power_seq;
2073 struct intel_crtc *intel_crtc =
2074 to_intel_crtc(encoder->base.crtc);
2075 enum dpio_channel ch = vlv_dport_to_channel(dport);
2076 int pipe = intel_crtc->pipe;
2077 int data, i;
949c1d43 2078 u32 val;
e4a1d846 2079
e4a1d846 2080 mutex_lock(&dev_priv->dpio_lock);
949c1d43
VS		 2081
2082 /* Deassert soft data lane reset*/
97fd4d5c 2083 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2084 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2085 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2086
2087 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2088 val |= CHV_PCS_REQ_SOFTRESET_EN;
2089 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2090
2091 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2092 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2093 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2094
97fd4d5c 2095 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2096 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2097 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2098
2099 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2100 for (i = 0; i < 4; i++) {
2101 /* Set the latency optimal bit */
2102 data = (i == 1) ? 0x0 : 0x6;
2103 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2104 data << DPIO_FRC_LATENCY_SHFIT);
2105
2106 /* Set the upar bit */
2107 data = (i == 1) ? 0x0 : 0x1;
2108 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2109 data << DPIO_UPAR_SHIFT);
2110 }
2111
2112 /* Data lane stagger programming */
2113 /* FIXME: Fix up value only after power analysis */
2114
2115 mutex_unlock(&dev_priv->dpio_lock);
2116
2117 if (is_edp(intel_dp)) {
2118 /* init power sequencer on this pipe and port */
2119 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2120 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2121 &power_seq);
2122 }
2123
2124 intel_enable_dp(encoder);
2125
2126 vlv_wait_port_ready(dev_priv, dport);
2127}
2128
9197c88b
VS		 2129static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2130{
2131 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2132 struct drm_device *dev = encoder->base.dev;
2133 struct drm_i915_private *dev_priv = dev->dev_private;
2134 struct intel_crtc *intel_crtc =
2135 to_intel_crtc(encoder->base.crtc);
2136 enum dpio_channel ch = vlv_dport_to_channel(dport);
2137 enum pipe pipe = intel_crtc->pipe;
2138 u32 val;
2139
2140 mutex_lock(&dev_priv->dpio_lock);
2141
b9e5ac3c
VS		 2142 /* program left/right clock distribution */
2143 if (pipe != PIPE_B) {
2144 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2145 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2146 if (ch == DPIO_CH0)
2147 val |= CHV_BUFLEFTENA1_FORCE;
2148 if (ch == DPIO_CH1)
2149 val |= CHV_BUFRIGHTENA1_FORCE;
2150 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2151 } else {
2152 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2153 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2154 if (ch == DPIO_CH0)
2155 val |= CHV_BUFLEFTENA2_FORCE;
2156 if (ch == DPIO_CH1)
2157 val |= CHV_BUFRIGHTENA2_FORCE;
2158 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2159 }
2160
9197c88b
VS		 2161 /* program clock channel usage */
2162 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2163 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2164 if (pipe != PIPE_B)
2165 val &= ~CHV_PCS_USEDCLKCHANNEL;
2166 else
2167 val |= CHV_PCS_USEDCLKCHANNEL;
2168 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2169
2170 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2171 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2172 if (pipe != PIPE_B)
2173 val &= ~CHV_PCS_USEDCLKCHANNEL;
2174 else
2175 val |= CHV_PCS_USEDCLKCHANNEL;
2176 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2177
2178 /*
2179 * This a a bit weird since generally CL
2180 * matches the pipe, but here we need to
2181 * pick the CL based on the port.
2182 */
2183 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2184 if (pipe != PIPE_B)
2185 val &= ~CHV_CMN_USEDCLKCHANNEL;
2186 else
2187 val |= CHV_CMN_USEDCLKCHANNEL;
2188 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2189
2190 mutex_unlock(&dev_priv->dpio_lock);
2191}
2192
a4fc5ed6 2193/*
df0c237d
JB		 2194 * Native read with retry for link status and receiver capability reads for
2195 * cases where the sink may still be asleep.
9d1a1031
JN		 2196 *
2197 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2198 * supposed to retry 3 times per the spec.
a4fc5ed6 2199 */
9d1a1031
JN		 2200static ssize_t
2201intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2202 void *buffer, size_t size)
a4fc5ed6 2203{
9d1a1031
JN		 2204 ssize_t ret;
2205 int i;
61da5fab 2206
61da5fab 2207 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2208 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2209 if (ret == size)
2210 return ret;
61da5fab
JB		 2211 msleep(1);
2212 }
a4fc5ed6 2213
9d1a1031 2214 return ret;
a4fc5ed6
KP		 2215}
2216
2217/*
2218 * Fetch AUX CH registers 0x202 - 0x207 which contain
2219 * link status information
2220 */
2221static bool
93f62dad 2222intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2223{
9d1a1031
JN		 2224 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2225 DP_LANE0_1_STATUS,
2226 link_status,
2227 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2228}
2229
a4fc5ed6
KP		 2230/*
2231 * These are source-specific values; current Intel hardware supports
2232 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
2233 */
a4fc5ed6
KP		 2234
2235static uint8_t
1a2eb460 2236intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2237{
30add22d 2238 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2239 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2240
8f93f4f1 2241 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
e2fa6fba 2242 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 2243 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 2244 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 2245 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 2246 return DP_TRAIN_VOLTAGE_SWING_1200;
2247 else
2248 return DP_TRAIN_VOLTAGE_SWING_800;
2249}
2250
2251static uint8_t
2252intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2253{
30add22d 2254 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2255 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2256
8f93f4f1
PZ		 2257 if (IS_BROADWELL(dev)) {
2258 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2259 case DP_TRAIN_VOLTAGE_SWING_400:
2260 case DP_TRAIN_VOLTAGE_SWING_600:
2261 return DP_TRAIN_PRE_EMPHASIS_6;
2262 case DP_TRAIN_VOLTAGE_SWING_800:
2263 return DP_TRAIN_PRE_EMPHASIS_3_5;
2264 case DP_TRAIN_VOLTAGE_SWING_1200:
2265 default:
2266 return DP_TRAIN_PRE_EMPHASIS_0;
2267 }
2268 } else if (IS_HASWELL(dev)) {
d6c0d722
PZ		 2269 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2270 case DP_TRAIN_VOLTAGE_SWING_400:
2271 return DP_TRAIN_PRE_EMPHASIS_9_5;
2272 case DP_TRAIN_VOLTAGE_SWING_600:
2273 return DP_TRAIN_PRE_EMPHASIS_6;
2274 case DP_TRAIN_VOLTAGE_SWING_800:
2275 return DP_TRAIN_PRE_EMPHASIS_3_5;
2276 case DP_TRAIN_VOLTAGE_SWING_1200:
2277 default:
2278 return DP_TRAIN_PRE_EMPHASIS_0;
2279 }
e2fa6fba
P		 2280 } else if (IS_VALLEYVIEW(dev)) {
2281 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2282 case DP_TRAIN_VOLTAGE_SWING_400:
2283 return DP_TRAIN_PRE_EMPHASIS_9_5;
2284 case DP_TRAIN_VOLTAGE_SWING_600:
2285 return DP_TRAIN_PRE_EMPHASIS_6;
2286 case DP_TRAIN_VOLTAGE_SWING_800:
2287 return DP_TRAIN_PRE_EMPHASIS_3_5;
2288 case DP_TRAIN_VOLTAGE_SWING_1200:
2289 default:
2290 return DP_TRAIN_PRE_EMPHASIS_0;
2291 }
bc7d38a4 2292 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2293 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2294 case DP_TRAIN_VOLTAGE_SWING_400:
2295 return DP_TRAIN_PRE_EMPHASIS_6;
2296 case DP_TRAIN_VOLTAGE_SWING_600:
2297 case DP_TRAIN_VOLTAGE_SWING_800:
2298 return DP_TRAIN_PRE_EMPHASIS_3_5;
2299 default:
2300 return DP_TRAIN_PRE_EMPHASIS_0;
2301 }
2302 } else {
2303 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2304 case DP_TRAIN_VOLTAGE_SWING_400:
2305 return DP_TRAIN_PRE_EMPHASIS_6;
2306 case DP_TRAIN_VOLTAGE_SWING_600:
2307 return DP_TRAIN_PRE_EMPHASIS_6;
2308 case DP_TRAIN_VOLTAGE_SWING_800:
2309 return DP_TRAIN_PRE_EMPHASIS_3_5;
2310 case DP_TRAIN_VOLTAGE_SWING_1200:
2311 default:
2312 return DP_TRAIN_PRE_EMPHASIS_0;
2313 }
a4fc5ed6
KP		 2314 }
2315}
2316
e2fa6fba
P		 2317static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2318{
2319 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2320 struct drm_i915_private *dev_priv = dev->dev_private;
2321 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2322 struct intel_crtc *intel_crtc =
2323 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2324 unsigned long demph_reg_value, preemph_reg_value,
2325 uniqtranscale_reg_value;
2326 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2327 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2328 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2329
2330 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2331 case DP_TRAIN_PRE_EMPHASIS_0:
2332 preemph_reg_value = 0x0004000;
2333 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2334 case DP_TRAIN_VOLTAGE_SWING_400:
2335 demph_reg_value = 0x2B405555;
2336 uniqtranscale_reg_value = 0x552AB83A;
2337 break;
2338 case DP_TRAIN_VOLTAGE_SWING_600:
2339 demph_reg_value = 0x2B404040;
2340 uniqtranscale_reg_value = 0x5548B83A;
2341 break;
2342 case DP_TRAIN_VOLTAGE_SWING_800:
2343 demph_reg_value = 0x2B245555;
2344 uniqtranscale_reg_value = 0x5560B83A;
2345 break;
2346 case DP_TRAIN_VOLTAGE_SWING_1200:
2347 demph_reg_value = 0x2B405555;
2348 uniqtranscale_reg_value = 0x5598DA3A;
2349 break;
2350 default:
2351 return 0;
2352 }
2353 break;
2354 case DP_TRAIN_PRE_EMPHASIS_3_5:
2355 preemph_reg_value = 0x0002000;
2356 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2357 case DP_TRAIN_VOLTAGE_SWING_400:
2358 demph_reg_value = 0x2B404040;
2359 uniqtranscale_reg_value = 0x5552B83A;
2360 break;
2361 case DP_TRAIN_VOLTAGE_SWING_600:
2362 demph_reg_value = 0x2B404848;
2363 uniqtranscale_reg_value = 0x5580B83A;
2364 break;
2365 case DP_TRAIN_VOLTAGE_SWING_800:
2366 demph_reg_value = 0x2B404040;
2367 uniqtranscale_reg_value = 0x55ADDA3A;
2368 break;
2369 default:
2370 return 0;
2371 }
2372 break;
2373 case DP_TRAIN_PRE_EMPHASIS_6:
2374 preemph_reg_value = 0x0000000;
2375 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2376 case DP_TRAIN_VOLTAGE_SWING_400:
2377 demph_reg_value = 0x2B305555;
2378 uniqtranscale_reg_value = 0x5570B83A;
2379 break;
2380 case DP_TRAIN_VOLTAGE_SWING_600:
2381 demph_reg_value = 0x2B2B4040;
2382 uniqtranscale_reg_value = 0x55ADDA3A;
2383 break;
2384 default:
2385 return 0;
2386 }
2387 break;
2388 case DP_TRAIN_PRE_EMPHASIS_9_5:
2389 preemph_reg_value = 0x0006000;
2390 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2391 case DP_TRAIN_VOLTAGE_SWING_400:
2392 demph_reg_value = 0x1B405555;
2393 uniqtranscale_reg_value = 0x55ADDA3A;
2394 break;
2395 default:
2396 return 0;
2397 }
2398 break;
2399 default:
2400 return 0;
2401 }
2402
0980a60f 2403 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2404 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2405 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2406 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2407 uniqtranscale_reg_value);
ab3c759a
CML		 2408 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2409 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2410 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2411 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2412 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2413
2414 return 0;
2415}
2416
e4a1d846
CML		 2417static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2418{
2419 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2420 struct drm_i915_private *dev_priv = dev->dev_private;
2421 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2422 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 2423 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 2424 uint8_t train_set = intel_dp->train_set[0];
2425 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 2426 enum pipe pipe = intel_crtc->pipe;
2427 int i;
e4a1d846
CML		 2428
2429 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2430 case DP_TRAIN_PRE_EMPHASIS_0:
2431 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2432 case DP_TRAIN_VOLTAGE_SWING_400:
2433 deemph_reg_value = 128;
2434 margin_reg_value = 52;
2435 break;
2436 case DP_TRAIN_VOLTAGE_SWING_600:
2437 deemph_reg_value = 128;
2438 margin_reg_value = 77;
2439 break;
2440 case DP_TRAIN_VOLTAGE_SWING_800:
2441 deemph_reg_value = 128;
2442 margin_reg_value = 102;
2443 break;
2444 case DP_TRAIN_VOLTAGE_SWING_1200:
2445 deemph_reg_value = 128;
2446 margin_reg_value = 154;
2447 /* FIXME extra to set for 1200 */
2448 break;
2449 default:
2450 return 0;
2451 }
2452 break;
2453 case DP_TRAIN_PRE_EMPHASIS_3_5:
2454 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2455 case DP_TRAIN_VOLTAGE_SWING_400:
2456 deemph_reg_value = 85;
2457 margin_reg_value = 78;
2458 break;
2459 case DP_TRAIN_VOLTAGE_SWING_600:
2460 deemph_reg_value = 85;
2461 margin_reg_value = 116;
2462 break;
2463 case DP_TRAIN_VOLTAGE_SWING_800:
2464 deemph_reg_value = 85;
2465 margin_reg_value = 154;
2466 break;
2467 default:
2468 return 0;
2469 }
2470 break;
2471 case DP_TRAIN_PRE_EMPHASIS_6:
2472 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2473 case DP_TRAIN_VOLTAGE_SWING_400:
2474 deemph_reg_value = 64;
2475 margin_reg_value = 104;
2476 break;
2477 case DP_TRAIN_VOLTAGE_SWING_600:
2478 deemph_reg_value = 64;
2479 margin_reg_value = 154;
2480 break;
2481 default:
2482 return 0;
2483 }
2484 break;
2485 case DP_TRAIN_PRE_EMPHASIS_9_5:
2486 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2487 case DP_TRAIN_VOLTAGE_SWING_400:
2488 deemph_reg_value = 43;
2489 margin_reg_value = 154;
2490 break;
2491 default:
2492 return 0;
2493 }
2494 break;
2495 default:
2496 return 0;
2497 }
2498
2499 mutex_lock(&dev_priv->dpio_lock);
2500
2501 /* Clear calc init */
1966e59e
VS		 2502 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2503 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2504 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2505
2506 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2507 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2508 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2509
2510 /* Program swing deemph */
f72df8db
VS		 2511 for (i = 0; i < 4; i++) {
2512 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2513 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2514 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2515 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2516 }
e4a1d846
CML		 2517
2518 /* Program swing margin */
f72df8db
VS		 2519 for (i = 0; i < 4; i++) {
2520 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2521 val &= ~DPIO_SWING_MARGIN_MASK;
2522 val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT;
2523 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2524 }
e4a1d846
CML		 2525
2526 /* Disable unique transition scale */
f72df8db
VS		 2527 for (i = 0; i < 4; i++) {
2528 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2529 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2530 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2531 }
e4a1d846
CML		 2532
2533 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2534 == DP_TRAIN_PRE_EMPHASIS_0) &&
2535 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2536 == DP_TRAIN_VOLTAGE_SWING_1200)) {
2537
2538 /*
2539 * The document said it needs to set bit 27 for ch0 and bit 26
2540 * for ch1. Might be a typo in the doc.
2541 * For now, for this unique transition scale selection, set bit
2542 * 27 for ch0 and ch1.
2543 */
f72df8db
VS		 2544 for (i = 0; i < 4; i++) {
2545 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2546 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2547 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2548 }
e4a1d846 2549
f72df8db
VS		 2550 for (i = 0; i < 4; i++) {
2551 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2552 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2553 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2554 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2555 }
e4a1d846
CML		 2556 }
2557
2558 /* Start swing calculation */
1966e59e
VS		 2559 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2560 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2561 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2562
2563 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2564 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2565 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2566
2567 /* LRC Bypass */
2568 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2569 val |= DPIO_LRC_BYPASS;
2570 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2571
2572 mutex_unlock(&dev_priv->dpio_lock);
2573
2574 return 0;
2575}
2576
a4fc5ed6 2577static void
0301b3ac
JN		 2578intel_get_adjust_train(struct intel_dp *intel_dp,
2579 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2580{
2581 uint8_t v = 0;
2582 uint8_t p = 0;
2583 int lane;
1a2eb460
KP		 2584 uint8_t voltage_max;
2585 uint8_t preemph_max;
a4fc5ed6 2586
33a34e4e 2587 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2588 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2589 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2590
2591 if (this_v > v)
2592 v = this_v;
2593 if (this_p > p)
2594 p = this_p;
2595 }
2596
1a2eb460 2597 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2598 if (v >= voltage_max)
2599 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2600
1a2eb460
KP		 2601 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2602 if (p >= preemph_max)
2603 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2604
2605 for (lane = 0; lane < 4; lane++)
33a34e4e 2606 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2607}
2608
2609static uint32_t
f0a3424e 2610intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2611{
3cf2efb1 2612 uint32_t signal_levels = 0;
a4fc5ed6 2613
3cf2efb1 2614 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2615 case DP_TRAIN_VOLTAGE_SWING_400:
2616 default:
2617 signal_levels |= DP_VOLTAGE_0_4;
2618 break;
2619 case DP_TRAIN_VOLTAGE_SWING_600:
2620 signal_levels |= DP_VOLTAGE_0_6;
2621 break;
2622 case DP_TRAIN_VOLTAGE_SWING_800:
2623 signal_levels |= DP_VOLTAGE_0_8;
2624 break;
2625 case DP_TRAIN_VOLTAGE_SWING_1200:
2626 signal_levels |= DP_VOLTAGE_1_2;
2627 break;
2628 }
3cf2efb1 2629 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2630 case DP_TRAIN_PRE_EMPHASIS_0:
2631 default:
2632 signal_levels |= DP_PRE_EMPHASIS_0;
2633 break;
2634 case DP_TRAIN_PRE_EMPHASIS_3_5:
2635 signal_levels |= DP_PRE_EMPHASIS_3_5;
2636 break;
2637 case DP_TRAIN_PRE_EMPHASIS_6:
2638 signal_levels |= DP_PRE_EMPHASIS_6;
2639 break;
2640 case DP_TRAIN_PRE_EMPHASIS_9_5:
2641 signal_levels |= DP_PRE_EMPHASIS_9_5;
2642 break;
2643 }
2644 return signal_levels;
2645}
2646
e3421a18
ZW		 2647/* Gen6's DP voltage swing and pre-emphasis control */
2648static uint32_t
2649intel_gen6_edp_signal_levels(uint8_t train_set)
2650{
3c5a62b5
YL		 2651 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2652 DP_TRAIN_PRE_EMPHASIS_MASK);
2653 switch (signal_levels) {
e3421a18 2654 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2655 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2656 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2657 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2658 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2659 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2660 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2661 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2662 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2663 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2664 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2665 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2666 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2667 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2668 default:
3c5a62b5
YL		 2669 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2670 "0x%x\n", signal_levels);
2671 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2672 }
2673}
2674
1a2eb460
KP		 2675/* Gen7's DP voltage swing and pre-emphasis control */
2676static uint32_t
2677intel_gen7_edp_signal_levels(uint8_t train_set)
2678{
2679 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2680 DP_TRAIN_PRE_EMPHASIS_MASK);
2681 switch (signal_levels) {
2682 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2683 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2684 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2685 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2686 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2687 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2688
2689 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2690 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2691 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2692 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2693
2694 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2695 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2696 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2697 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2698
2699 default:
2700 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2701 "0x%x\n", signal_levels);
2702 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2703 }
2704}
2705
d6c0d722
PZ		 2706/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2707static uint32_t
f0a3424e 2708intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2709{
d6c0d722
PZ		 2710 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2711 DP_TRAIN_PRE_EMPHASIS_MASK);
2712 switch (signal_levels) {
2713 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2714 return DDI_BUF_EMP_400MV_0DB_HSW;
2715 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2716 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2717 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2718 return DDI_BUF_EMP_400MV_6DB_HSW;
2719 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2720 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2721
d6c0d722
PZ		 2722 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2723 return DDI_BUF_EMP_600MV_0DB_HSW;
2724 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2725 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2726 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2727 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2728
d6c0d722
PZ		 2729 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2730 return DDI_BUF_EMP_800MV_0DB_HSW;
2731 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2732 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2733 default:
2734 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2735 "0x%x\n", signal_levels);
2736 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2737 }
a4fc5ed6
KP		 2738}
2739
8f93f4f1
PZ		 2740static uint32_t
2741intel_bdw_signal_levels(uint8_t train_set)
2742{
2743 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2744 DP_TRAIN_PRE_EMPHASIS_MASK);
2745 switch (signal_levels) {
2746 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2747 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2748 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2749 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2750 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2751 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2752
2753 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2754 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2755 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2756 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2757 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2758 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2759
2760 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2761 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2762 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2763 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2764
2765 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2766 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2767
2768 default:
2769 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2770 "0x%x\n", signal_levels);
2771 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2772 }
2773}
2774
f0a3424e
PZ		 2775/* Properly updates "DP" with the correct signal levels. */
2776static void
2777intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2778{
2779 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2780 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2781 struct drm_device *dev = intel_dig_port->base.base.dev;
2782 uint32_t signal_levels, mask;
2783 uint8_t train_set = intel_dp->train_set[0];
2784
8f93f4f1
PZ		 2785 if (IS_BROADWELL(dev)) {
2786 signal_levels = intel_bdw_signal_levels(train_set);
2787 mask = DDI_BUF_EMP_MASK;
2788 } else if (IS_HASWELL(dev)) {
f0a3424e
PZ		 2789 signal_levels = intel_hsw_signal_levels(train_set);
2790 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 2791 } else if (IS_CHERRYVIEW(dev)) {
2792 signal_levels = intel_chv_signal_levels(intel_dp);
2793 mask = 0;
e2fa6fba
P		 2794 } else if (IS_VALLEYVIEW(dev)) {
2795 signal_levels = intel_vlv_signal_levels(intel_dp);
2796 mask = 0;
bc7d38a4 2797 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2798 signal_levels = intel_gen7_edp_signal_levels(train_set);
2799 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2800 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2801 signal_levels = intel_gen6_edp_signal_levels(train_set);
2802 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2803 } else {
2804 signal_levels = intel_gen4_signal_levels(train_set);
2805 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2806 }
2807
2808 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2809
2810 *DP = (*DP & ~mask) | signal_levels;
2811}
2812
a4fc5ed6 2813static bool
ea5b213a 2814intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2815 uint32_t *DP,
58e10eb9 2816 uint8_t dp_train_pat)
a4fc5ed6 2817{
174edf1f
PZ		 2818 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2819 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2820 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2821 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2822 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2823 int ret, len;
a4fc5ed6 2824
22b8bf17 2825 if (HAS_DDI(dev)) {
3ab9c637 2826 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2827
2828 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2829 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2830 else
2831 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2832
2833 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2834 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2835 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2836 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2837
2838 break;
2839 case DP_TRAINING_PATTERN_1:
2840 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2841 break;
2842 case DP_TRAINING_PATTERN_2:
2843 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2844 break;
2845 case DP_TRAINING_PATTERN_3:
2846 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2847 break;
2848 }
174edf1f 2849 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2850
bc7d38a4 2851 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2852 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2853
2854 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2855 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2856 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2857 break;
2858 case DP_TRAINING_PATTERN_1:
70aff66c 2859 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2860 break;
2861 case DP_TRAINING_PATTERN_2:
70aff66c 2862 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2863 break;
2864 case DP_TRAINING_PATTERN_3:
2865 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2866 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2867 break;
2868 }
2869
2870 } else {
70aff66c 2871 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2872
2873 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2874 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2875 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2876 break;
2877 case DP_TRAINING_PATTERN_1:
70aff66c 2878 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2879 break;
2880 case DP_TRAINING_PATTERN_2:
70aff66c 2881 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2882 break;
2883 case DP_TRAINING_PATTERN_3:
2884 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2885 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2886 break;
2887 }
2888 }
2889
70aff66c 2890 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 2891 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2892
2cdfe6c8
JN		 2893 buf[0] = dp_train_pat;
2894 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 2895 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 2896 /* don't write DP_TRAINING_LANEx_SET on disable */
2897 len = 1;
2898 } else {
2899 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2900 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2901 len = intel_dp->lane_count + 1;
47ea7542 2902 }
a4fc5ed6 2903
9d1a1031
JN		 2904 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
2905 buf, len);
2cdfe6c8
JN		 2906
2907 return ret == len;
a4fc5ed6
KP		 2908}
2909
70aff66c
JN		 2910static bool
2911intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2912 uint8_t dp_train_pat)
2913{
953d22e8 2914 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 2915 intel_dp_set_signal_levels(intel_dp, DP);
2916 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2917}
2918
2919static bool
2920intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 2921 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 2922{
2923 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2924 struct drm_device *dev = intel_dig_port->base.base.dev;
2925 struct drm_i915_private *dev_priv = dev->dev_private;
2926 int ret;
2927
2928 intel_get_adjust_train(intel_dp, link_status);
2929 intel_dp_set_signal_levels(intel_dp, DP);
2930
2931 I915_WRITE(intel_dp->output_reg, *DP);
2932 POSTING_READ(intel_dp->output_reg);
2933
9d1a1031
JN		 2934 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
2935 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 2936
2937 return ret == intel_dp->lane_count;
2938}
2939
3ab9c637
ID		 2940static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2941{
2942 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2943 struct drm_device *dev = intel_dig_port->base.base.dev;
2944 struct drm_i915_private *dev_priv = dev->dev_private;
2945 enum port port = intel_dig_port->port;
2946 uint32_t val;
2947
2948 if (!HAS_DDI(dev))
2949 return;
2950
2951 val = I915_READ(DP_TP_CTL(port));
2952 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2953 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2954 I915_WRITE(DP_TP_CTL(port), val);
2955
2956 /*
2957 * On PORT_A we can have only eDP in SST mode. There the only reason
2958 * we need to set idle transmission mode is to work around a HW issue
2959 * where we enable the pipe while not in idle link-training mode.
2960 * In this case there is requirement to wait for a minimum number of
2961 * idle patterns to be sent.
2962 */
2963 if (port == PORT_A)
2964 return;
2965
2966 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2967 1))
2968 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2969}
2970
33a34e4e 2971/* Enable corresponding port and start training pattern 1 */
c19b0669 2972void
33a34e4e 2973intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2974{
da63a9f2 2975 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2976 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2977 int i;
2978 uint8_t voltage;
cdb0e95b 2979 int voltage_tries, loop_tries;
ea5b213a 2980 uint32_t DP = intel_dp->DP;
6aba5b6c 2981 uint8_t link_config[2];
a4fc5ed6 2982
affa9354 2983 if (HAS_DDI(dev))
c19b0669
PZ		 2984 intel_ddi_prepare_link_retrain(encoder);
2985
3cf2efb1 2986 /* Write the link configuration data */
6aba5b6c
JN		 2987 link_config[0] = intel_dp->link_bw;
2988 link_config[1] = intel_dp->lane_count;
2989 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2990 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 2991 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 2992
2993 link_config[0] = 0;
2994 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 2995 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 2996
2997 DP |= DP_PORT_EN;
1a2eb460 2998
70aff66c
JN		 2999 /* clock recovery */
3000 if (!intel_dp_reset_link_train(intel_dp, &DP,
3001 DP_TRAINING_PATTERN_1 |
3002 DP_LINK_SCRAMBLING_DISABLE)) {
3003 DRM_ERROR("failed to enable link training\n");
3004 return;
3005 }
3006
a4fc5ed6 3007 voltage = 0xff;
cdb0e95b
KP		 3008 voltage_tries = 0;
3009 loop_tries = 0;
a4fc5ed6 3010 for (;;) {
70aff66c 3011 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3012
a7c9655f 3013 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3014 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3015 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3016 break;
93f62dad 3017 }
a4fc5ed6 3018
01916270 3019 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3020 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3021 break;
3022 }
3023
3024 /* Check to see if we've tried the max voltage */
3025 for (i = 0; i < intel_dp->lane_count; i++)
3026 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3027 break;
3b4f819d 3028 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3029 ++loop_tries;
3030 if (loop_tries == 5) {
3def84b3 3031 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3032 break;
3033 }
70aff66c
JN		 3034 intel_dp_reset_link_train(intel_dp, &DP,
3035 DP_TRAINING_PATTERN_1 |
3036 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3037 voltage_tries = 0;
3038 continue;
3039 }
a4fc5ed6 3040
3cf2efb1 3041 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3042 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3043 ++voltage_tries;
b06fbda3 3044 if (voltage_tries == 5) {
3def84b3 3045 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3046 break;
3047 }
3048 } else
3049 voltage_tries = 0;
3050 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3051
70aff66c
JN		 3052 /* Update training set as requested by target */
3053 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3054 DRM_ERROR("failed to update link training\n");
3055 break;
3056 }
a4fc5ed6
KP		 3057 }
3058
33a34e4e
JB		 3059 intel_dp->DP = DP;
3060}
3061
c19b0669 3062void
33a34e4e
JB		 3063intel_dp_complete_link_train(struct intel_dp *intel_dp)
3064{
33a34e4e 3065 bool channel_eq = false;
37f80975 3066 int tries, cr_tries;
33a34e4e 3067 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3068 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3069
3070 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3071 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3072 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3073
a4fc5ed6 3074 /* channel equalization */
70aff66c 3075 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3076 training_pattern |
70aff66c
JN		 3077 DP_LINK_SCRAMBLING_DISABLE)) {
3078 DRM_ERROR("failed to start channel equalization\n");
3079 return;
3080 }
3081
a4fc5ed6 3082 tries = 0;
37f80975 3083 cr_tries = 0;
a4fc5ed6
KP		 3084 channel_eq = false;
3085 for (;;) {
70aff66c 3086 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3087
37f80975
JB		 3088 if (cr_tries > 5) {
3089 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3090 break;
3091 }
3092
a7c9655f 3093 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3094 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3095 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3096 break;
70aff66c 3097 }
a4fc5ed6 3098
37f80975 3099 /* Make sure clock is still ok */
01916270 3100 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3101 intel_dp_start_link_train(intel_dp);
70aff66c 3102 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3103 training_pattern |
70aff66c 3104 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3105 cr_tries++;
3106 continue;
3107 }
3108
1ffdff13 3109 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3110 channel_eq = true;
3111 break;
3112 }
a4fc5ed6 3113
37f80975
JB		 3114 /* Try 5 times, then try clock recovery if that fails */
3115 if (tries > 5) {
3116 intel_dp_link_down(intel_dp);
3117 intel_dp_start_link_train(intel_dp);
70aff66c 3118 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3119 training_pattern |
70aff66c 3120 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3121 tries = 0;
3122 cr_tries++;
3123 continue;
3124 }
a4fc5ed6 3125
70aff66c
JN		 3126 /* Update training set as requested by target */
3127 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3128 DRM_ERROR("failed to update link training\n");
3129 break;
3130 }
3cf2efb1 3131 ++tries;
869184a6 3132 }
3cf2efb1 3133
3ab9c637
ID		 3134 intel_dp_set_idle_link_train(intel_dp);
3135
3136 intel_dp->DP = DP;
3137
d6c0d722 3138 if (channel_eq)
07f42258 3139 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3140
3ab9c637
ID		 3141}
3142
3143void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3144{
70aff66c 3145 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3146 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3147}
3148
3149static void
ea5b213a 3150intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3151{
da63a9f2 3152 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3153 enum port port = intel_dig_port->port;
da63a9f2 3154 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3155 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3156 struct intel_crtc *intel_crtc =
3157 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3158 uint32_t DP = intel_dp->DP;
a4fc5ed6 3159
bc76e320 3160 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3161 return;
3162
0c33d8d7 3163 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3164 return;
3165
28c97730 3166 DRM_DEBUG_KMS("\n");
32f9d658 3167
bc7d38a4 3168 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3169 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3170 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 3171 } else {
3172 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3173 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3174 }
fe255d00 3175 POSTING_READ(intel_dp->output_reg);
5eb08b69 3176
493a7081 3177 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3178 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3179 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3180
5bddd17f
EA		 3181 /* Hardware workaround: leaving our transcoder select
3182 * set to transcoder B while it's off will prevent the
3183 * corresponding HDMI output on transcoder A.
3184 *
3185 * Combine this with another hardware workaround:
3186 * transcoder select bit can only be cleared while the
3187 * port is enabled.
3188 */
3189 DP &= ~DP_PIPEB_SELECT;
3190 I915_WRITE(intel_dp->output_reg, DP);
3191
3192 /* Changes to enable or select take place the vblank
3193 * after being written.
3194 */
ff50afe9
DV		 3195 if (WARN_ON(crtc == NULL)) {
3196 /* We should never try to disable a port without a crtc
3197 * attached. For paranoia keep the code around for a
3198 * bit. */
31acbcc4
CW		 3199 POSTING_READ(intel_dp->output_reg);
3200 msleep(50);
3201 } else
ab527efc 3202 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3203 }
3204
832afda6 3205 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3206 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3207 POSTING_READ(intel_dp->output_reg);
f01eca2e 3208 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3209}
3210
26d61aad
KP		 3211static bool
3212intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3213{
a031d709
RV		 3214 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3215 struct drm_device *dev = dig_port->base.base.dev;
3216 struct drm_i915_private *dev_priv = dev->dev_private;
3217
577c7a50
DL		 3218 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
3219
9d1a1031
JN		 3220 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3221 sizeof(intel_dp->dpcd)) < 0)
edb39244 3222 return false; /* aux transfer failed */
92fd8fd1 3223
577c7a50
DL		 3224 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
3225 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
3226 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
3227
edb39244
AJ		 3228 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3229 return false; /* DPCD not present */
3230
2293bb5c
SK		 3231 /* Check if the panel supports PSR */
3232 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3233 if (is_edp(intel_dp)) {
9d1a1031
JN		 3234 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3235 intel_dp->psr_dpcd,
3236 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3237 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3238 dev_priv->psr.sink_support = true;
50003939 3239 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3240 }
50003939
JN		 3241 }
3242
06ea66b6
TP		 3243 /* Training Pattern 3 support */
3244 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3245 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3246 intel_dp->use_tps3 = true;
3247 DRM_DEBUG_KMS("Displayport TPS3 supported");
3248 } else
3249 intel_dp->use_tps3 = false;
3250
edb39244
AJ		 3251 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3252 DP_DWN_STRM_PORT_PRESENT))
3253 return true; /* native DP sink */
3254
3255 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3256 return true; /* no per-port downstream info */
3257
9d1a1031
JN		 3258 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3259 intel_dp->downstream_ports,
3260 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3261 return false; /* downstream port status fetch failed */
3262
3263 return true;
92fd8fd1
KP		 3264}
3265
0d198328
AJ		 3266static void
3267intel_dp_probe_oui(struct intel_dp *intel_dp)
3268{
3269 u8 buf[3];
3270
3271 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3272 return;
3273
24f3e092 3274 intel_edp_panel_vdd_on(intel_dp);
351cfc34 3275
9d1a1031 3276 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3277 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3278 buf[0], buf[1], buf[2]);
3279
9d1a1031 3280 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3281 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3282 buf[0], buf[1], buf[2]);
351cfc34 3283
4be73780 3284 edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 3285}
3286
d2e216d0
RV		 3287int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3288{
3289 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3290 struct drm_device *dev = intel_dig_port->base.base.dev;
3291 struct intel_crtc *intel_crtc =
3292 to_intel_crtc(intel_dig_port->base.base.crtc);
3293 u8 buf[1];
3294
9d1a1031 3295 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 3296 return -EAGAIN;
3297
3298 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3299 return -ENOTTY;
3300
9d1a1031
JN		 3301 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3302 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 3303 return -EAGAIN;
3304
3305 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3306 intel_wait_for_vblank(dev, intel_crtc->pipe);
3307 intel_wait_for_vblank(dev, intel_crtc->pipe);
3308
9d1a1031 3309 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 3310 return -EAGAIN;
3311
9d1a1031 3312 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 3313 return 0;
3314}
3315
a60f0e38
JB		 3316static bool
3317intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3318{
9d1a1031
JN		 3319 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3320 DP_DEVICE_SERVICE_IRQ_VECTOR,
3321 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3322}
3323
3324static void
3325intel_dp_handle_test_request(struct intel_dp *intel_dp)
3326{
3327 /* NAK by default */
9d1a1031 3328 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3329}
3330
a4fc5ed6
KP		 3331/*
3332 * According to DP spec
3333 * 5.1.2:
3334 * 1. Read DPCD
3335 * 2. Configure link according to Receiver Capabilities
3336 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3337 * 4. Check link status on receipt of hot-plug interrupt
3338 */
3339
00c09d70 3340void
ea5b213a 3341intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3342{
da63a9f2 3343 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3344 u8 sink_irq_vector;
93f62dad 3345 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3346
6e9f798d 3347 /* FIXME: This access isn't protected by any locks. */
da63a9f2 3348 if (!intel_encoder->connectors_active)
d2b996ac 3349 return;
59cd09e1 3350
da63a9f2 3351 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3352 return;
3353
92fd8fd1 3354 /* Try to read receiver status if the link appears to be up */
93f62dad 3355 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3356 return;
3357 }
3358
92fd8fd1 3359 /* Now read the DPCD to see if it's actually running */
26d61aad 3360 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3361 return;
3362 }
3363
a60f0e38
JB		 3364 /* Try to read the source of the interrupt */
3365 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3366 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3367 /* Clear interrupt source */
9d1a1031
JN		 3368 drm_dp_dpcd_writeb(&intel_dp->aux,
3369 DP_DEVICE_SERVICE_IRQ_VECTOR,
3370 sink_irq_vector);
a60f0e38
JB		 3371
3372 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3373 intel_dp_handle_test_request(intel_dp);
3374 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3375 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3376 }
3377
1ffdff13 3378 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3379 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 3380 intel_encoder->base.name);
33a34e4e
JB		 3381 intel_dp_start_link_train(intel_dp);
3382 intel_dp_complete_link_train(intel_dp);
3ab9c637 3383 intel_dp_stop_link_train(intel_dp);
33a34e4e 3384 }
a4fc5ed6 3385}
a4fc5ed6 3386
caf9ab24 3387/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3388static enum drm_connector_status
26d61aad 3389intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3390{
caf9ab24 3391 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3392 uint8_t type;
3393
3394 if (!intel_dp_get_dpcd(intel_dp))
3395 return connector_status_disconnected;
3396
3397 /* if there's no downstream port, we're done */
3398 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3399 return connector_status_connected;
caf9ab24
AJ		 3400
3401 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3402 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3403 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3404 uint8_t reg;
9d1a1031
JN		 3405
3406 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3407 &reg, 1) < 0)
caf9ab24 3408 return connector_status_unknown;
9d1a1031 3409
23235177
AJ		 3410 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3411 : connector_status_disconnected;
caf9ab24
AJ		 3412 }
3413
3414 /* If no HPD, poke DDC gently */
0b99836f 3415 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3416 return connector_status_connected;
caf9ab24
AJ		 3417
3418 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3419 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3420 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3421 if (type == DP_DS_PORT_TYPE_VGA ||
3422 type == DP_DS_PORT_TYPE_NON_EDID)
3423 return connector_status_unknown;
3424 } else {
3425 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3426 DP_DWN_STRM_PORT_TYPE_MASK;
3427 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3428 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3429 return connector_status_unknown;
3430 }
caf9ab24
AJ		 3431
3432 /* Anything else is out of spec, warn and ignore */
3433 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3434 return connector_status_disconnected;
71ba9000
AJ		 3435}
3436
5eb08b69 3437static enum drm_connector_status
a9756bb5 3438ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3439{
30add22d 3440 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3441 struct drm_i915_private *dev_priv = dev->dev_private;
3442 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 3443 enum drm_connector_status status;
3444
fe16d949
CW		 3445 /* Can't disconnect eDP, but you can close the lid... */
3446 if (is_edp(intel_dp)) {
30add22d 3447 status = intel_panel_detect(dev);
fe16d949
CW		 3448 if (status == connector_status_unknown)
3449 status = connector_status_connected;
3450 return status;
3451 }
01cb9ea6 3452
1b469639
DL		 3453 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3454 return connector_status_disconnected;
3455
26d61aad 3456 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3457}
3458
a4fc5ed6 3459static enum drm_connector_status
a9756bb5 3460g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3461{
30add22d 3462 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3463 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3464 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3465 uint32_t bit;
5eb08b69 3466
35aad75f
JB		 3467 /* Can't disconnect eDP, but you can close the lid... */
3468 if (is_edp(intel_dp)) {
3469 enum drm_connector_status status;
3470
3471 status = intel_panel_detect(dev);
3472 if (status == connector_status_unknown)
3473 status = connector_status_connected;
3474 return status;
3475 }
3476
232a6ee9
TP		 3477 if (IS_VALLEYVIEW(dev)) {
3478 switch (intel_dig_port->port) {
3479 case PORT_B:
3480 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3481 break;
3482 case PORT_C:
3483 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3484 break;
3485 case PORT_D:
3486 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3487 break;
3488 default:
3489 return connector_status_unknown;
3490 }
3491 } else {
3492 switch (intel_dig_port->port) {
3493 case PORT_B:
3494 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3495 break;
3496 case PORT_C:
3497 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3498 break;
3499 case PORT_D:
3500 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3501 break;
3502 default:
3503 return connector_status_unknown;
3504 }
a4fc5ed6
KP		 3505 }
3506
10f76a38 3507 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3508 return connector_status_disconnected;
3509
26d61aad 3510 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3511}
3512
8c241fef
KP		 3513static struct edid *
3514intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3515{
9cd300e0 3516 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3517
9cd300e0
JN		 3518 /* use cached edid if we have one */
3519 if (intel_connector->edid) {
9cd300e0
JN		 3520 /* invalid edid */
3521 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3522 return NULL;
3523
55e9edeb 3524 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3525 }
8c241fef 3526
9cd300e0 3527 return drm_get_edid(connector, adapter);
8c241fef
KP		 3528}
3529
3530static int
3531intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3532{
9cd300e0 3533 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3534
9cd300e0
JN		 3535 /* use cached edid if we have one */
3536 if (intel_connector->edid) {
3537 /* invalid edid */
3538 if (IS_ERR(intel_connector->edid))
3539 return 0;
3540
3541 return intel_connector_update_modes(connector,
3542 intel_connector->edid);
d6f24d0f
JB		 3543 }
3544
9cd300e0 3545 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3546}
3547
a9756bb5
ZW		 3548static enum drm_connector_status
3549intel_dp_detect(struct drm_connector *connector, bool force)
3550{
3551 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3552 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3553 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3554 struct drm_device *dev = connector->dev;
c8c8fb33 3555 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 3556 enum drm_connector_status status;
671dedd2 3557 enum intel_display_power_domain power_domain;
a9756bb5
ZW		 3558 struct edid *edid = NULL;
3559
c8c8fb33
PZ		 3560 intel_runtime_pm_get(dev_priv);
3561
671dedd2
ID		 3562 power_domain = intel_display_port_power_domain(intel_encoder);
3563 intel_display_power_get(dev_priv, power_domain);
3564
164c8598 3565 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 3566 connector->base.id, connector->name);
164c8598 3567
a9756bb5
ZW		 3568 intel_dp->has_audio = false;
3569
3570 if (HAS_PCH_SPLIT(dev))
3571 status = ironlake_dp_detect(intel_dp);
3572 else
3573 status = g4x_dp_detect(intel_dp);
1b9be9d0 3574
a9756bb5 3575 if (status != connector_status_connected)
c8c8fb33 3576 goto out;
a9756bb5 3577
0d198328
AJ		 3578 intel_dp_probe_oui(intel_dp);
3579
c3e5f67b
DV		 3580 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3581 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3582 } else {
0b99836f 3583 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
f684960e
CW		 3584 if (edid) {
3585 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3586 kfree(edid);
3587 }
a9756bb5
ZW		 3588 }
3589
d63885da
PZ		 3590 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3591 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3592 status = connector_status_connected;
3593
3594out:
671dedd2
ID		 3595 intel_display_power_put(dev_priv, power_domain);
3596
c8c8fb33 3597 intel_runtime_pm_put(dev_priv);
671dedd2 3598
c8c8fb33 3599 return status;
a4fc5ed6
KP		 3600}
3601
3602static int intel_dp_get_modes(struct drm_connector *connector)
3603{
df0e9248 3604 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3605 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3606 struct intel_encoder *intel_encoder = &intel_dig_port->base;
dd06f90e 3607 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3608 struct drm_device *dev = connector->dev;
671dedd2
ID		 3609 struct drm_i915_private *dev_priv = dev->dev_private;
3610 enum intel_display_power_domain power_domain;
32f9d658 3611 int ret;
a4fc5ed6
KP		 3612
3613 /* We should parse the EDID data and find out if it has an audio sink
3614 */
3615
671dedd2
ID		 3616 power_domain = intel_display_port_power_domain(intel_encoder);
3617 intel_display_power_get(dev_priv, power_domain);
3618
0b99836f 3619 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
671dedd2 3620 intel_display_power_put(dev_priv, power_domain);
f8779fda 3621 if (ret)
32f9d658
ZW		 3622 return ret;
3623
f8779fda 3624 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3625 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3626 struct drm_display_mode *mode;
dd06f90e
JN		 3627 mode = drm_mode_duplicate(dev,
3628 intel_connector->panel.fixed_mode);
f8779fda 3629 if (mode) {
32f9d658
ZW		 3630 drm_mode_probed_add(connector, mode);
3631 return 1;
3632 }
3633 }
3634 return 0;
a4fc5ed6
KP		 3635}
3636
1aad7ac0
CW		 3637static bool
3638intel_dp_detect_audio(struct drm_connector *connector)
3639{
3640 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3641 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3642 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3643 struct drm_device *dev = connector->dev;
3644 struct drm_i915_private *dev_priv = dev->dev_private;
3645 enum intel_display_power_domain power_domain;
1aad7ac0
CW		 3646 struct edid *edid;
3647 bool has_audio = false;
3648
671dedd2
ID		 3649 power_domain = intel_display_port_power_domain(intel_encoder);
3650 intel_display_power_get(dev_priv, power_domain);
3651
0b99836f 3652 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
1aad7ac0
CW		 3653 if (edid) {
3654 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3655 kfree(edid);
3656 }
3657
671dedd2
ID		 3658 intel_display_power_put(dev_priv, power_domain);
3659
1aad7ac0
CW		 3660 return has_audio;
3661}
3662
f684960e
CW		 3663static int
3664intel_dp_set_property(struct drm_connector *connector,
3665 struct drm_property *property,
3666 uint64_t val)
3667{
e953fd7b 3668 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3669 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3670 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3671 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3672 int ret;
3673
662595df 3674 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3675 if (ret)
3676 return ret;
3677
3f43c48d 3678 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3679 int i = val;
3680 bool has_audio;
3681
3682 if (i == intel_dp->force_audio)
f684960e
CW		 3683 return 0;
3684
1aad7ac0 3685 intel_dp->force_audio = i;
f684960e 3686
c3e5f67b 3687 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3688 has_audio = intel_dp_detect_audio(connector);
3689 else
c3e5f67b 3690 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3691
3692 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3693 return 0;
3694
1aad7ac0 3695 intel_dp->has_audio = has_audio;
f684960e
CW		 3696 goto done;
3697 }
3698
e953fd7b 3699 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3700 bool old_auto = intel_dp->color_range_auto;
3701 uint32_t old_range = intel_dp->color_range;
3702
55bc60db
VS		 3703 switch (val) {
3704 case INTEL_BROADCAST_RGB_AUTO:
3705 intel_dp->color_range_auto = true;
3706 break;
3707 case INTEL_BROADCAST_RGB_FULL:
3708 intel_dp->color_range_auto = false;
3709 intel_dp->color_range = 0;
3710 break;
3711 case INTEL_BROADCAST_RGB_LIMITED:
3712 intel_dp->color_range_auto = false;
3713 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3714 break;
3715 default:
3716 return -EINVAL;
3717 }
ae4edb80
DV		 3718
3719 if (old_auto == intel_dp->color_range_auto &&
3720 old_range == intel_dp->color_range)
3721 return 0;
3722
e953fd7b
CW		 3723 goto done;
3724 }
3725
53b41837
YN		 3726 if (is_edp(intel_dp) &&
3727 property == connector->dev->mode_config.scaling_mode_property) {
3728 if (val == DRM_MODE_SCALE_NONE) {
3729 DRM_DEBUG_KMS("no scaling not supported\n");
3730 return -EINVAL;
3731 }
3732
3733 if (intel_connector->panel.fitting_mode == val) {
3734 /* the eDP scaling property is not changed */
3735 return 0;
3736 }
3737 intel_connector->panel.fitting_mode = val;
3738
3739 goto done;
3740 }
3741
f684960e
CW		 3742 return -EINVAL;
3743
3744done:
c0c36b94
CW		 3745 if (intel_encoder->base.crtc)
3746 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3747
3748 return 0;
3749}
3750
a4fc5ed6 3751static void
73845adf 3752intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3753{
1d508706 3754 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3755
9cd300e0
JN		 3756 if (!IS_ERR_OR_NULL(intel_connector->edid))
3757 kfree(intel_connector->edid);
3758
acd8db10
PZ		 3759 /* Can't call is_edp() since the encoder may have been destroyed
3760 * already. */
3761 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3762 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3763
a4fc5ed6 3764 drm_connector_cleanup(connector);
55f78c43 3765 kfree(connector);
a4fc5ed6
KP		 3766}
3767
00c09d70 3768void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3769{
da63a9f2
PZ		 3770 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3771 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3772 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927 3773
4f71d0cb 3774 drm_dp_aux_unregister(&intel_dp->aux);
24d05927 3775 drm_encoder_cleanup(encoder);
bd943159
KP		 3776 if (is_edp(intel_dp)) {
3777 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
51fd371b 3778 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 3779 edp_panel_vdd_off_sync(intel_dp);
51fd371b 3780 drm_modeset_unlock(&dev->mode_config.connection_mutex);
bd943159 3781 }
da63a9f2 3782 kfree(intel_dig_port);
24d05927
DV		 3783}
3784
a4fc5ed6 3785static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3786 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3787 .detect = intel_dp_detect,
3788 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3789 .set_property = intel_dp_set_property,
73845adf 3790 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3791};
3792
3793static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3794 .get_modes = intel_dp_get_modes,
3795 .mode_valid = intel_dp_mode_valid,
df0e9248 3796 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3797};
3798
a4fc5ed6 3799static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3800 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3801};
3802
995b6762 3803static void
21d40d37 3804intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3805{
fa90ecef 3806 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3807
885a5014 3808 intel_dp_check_link_status(intel_dp);
c8110e52 3809}
6207937d 3810
e3421a18
ZW		 3811/* Return which DP Port should be selected for Transcoder DP control */
3812int
0206e353 3813intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3814{
3815 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3816 struct intel_encoder *intel_encoder;
3817 struct intel_dp *intel_dp;
e3421a18 3818
fa90ecef
PZ		 3819 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3820 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3821
fa90ecef
PZ		 3822 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3823 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3824 return intel_dp->output_reg;
e3421a18 3825 }
ea5b213a 3826
e3421a18
ZW		 3827 return -1;
3828}
3829
36e83a18 3830/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 3831bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 3832{
3833 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 3834 union child_device_config *p_child;
36e83a18 3835 int i;
5d8a7752
VS		 3836 static const short port_mapping[] = {
3837 [PORT_B] = PORT_IDPB,
3838 [PORT_C] = PORT_IDPC,
3839 [PORT_D] = PORT_IDPD,
3840 };
36e83a18 3841
3b32a35b
VS		 3842 if (port == PORT_A)
3843 return true;
3844
41aa3448 3845 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3846 return false;
3847
41aa3448
RV		 3848 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3849 p_child = dev_priv->vbt.child_dev + i;
36e83a18 3850
5d8a7752 3851 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 3852 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3853 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 3854 return true;
3855 }
3856 return false;
3857}
3858
f684960e
CW		 3859static void
3860intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3861{
53b41837
YN		 3862 struct intel_connector *intel_connector = to_intel_connector(connector);
3863
3f43c48d 3864 intel_attach_force_audio_property(connector);
e953fd7b 3865 intel_attach_broadcast_rgb_property(connector);
55bc60db 3866 intel_dp->color_range_auto = true;
53b41837
YN		 3867
3868 if (is_edp(intel_dp)) {
3869 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3870 drm_object_attach_property(
3871 &connector->base,
53b41837 3872 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3873 DRM_MODE_SCALE_ASPECT);
3874 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3875 }
f684960e
CW		 3876}
3877
dada1a9f
ID		 3878static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3879{
3880 intel_dp->last_power_cycle = jiffies;
3881 intel_dp->last_power_on = jiffies;
3882 intel_dp->last_backlight_off = jiffies;
3883}
3884
67a54566
DV		 3885static void
3886intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3887 struct intel_dp *intel_dp,
3888 struct edp_power_seq *out)
67a54566
DV		 3889{
3890 struct drm_i915_private *dev_priv = dev->dev_private;
3891 struct edp_power_seq cur, vbt, spec, final;
3892 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 3893 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 3894
3895 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 3896 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 3897 pp_on_reg = PCH_PP_ON_DELAYS;
3898 pp_off_reg = PCH_PP_OFF_DELAYS;
3899 pp_div_reg = PCH_PP_DIVISOR;
3900 } else {
bf13e81b
JN		 3901 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3902
3903 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3904 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3905 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3906 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 3907 }
67a54566
DV		 3908
3909 /* Workaround: Need to write PP_CONTROL with the unlock key as
3910 * the very first thing. */
453c5420 3911 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 3912 I915_WRITE(pp_ctrl_reg, pp);
67a54566 3913
453c5420
JB		 3914 pp_on = I915_READ(pp_on_reg);
3915 pp_off = I915_READ(pp_off_reg);
3916 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3917
3918 /* Pull timing values out of registers */
3919 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3920 PANEL_POWER_UP_DELAY_SHIFT;
3921
3922 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3923 PANEL_LIGHT_ON_DELAY_SHIFT;
3924
3925 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3926 PANEL_LIGHT_OFF_DELAY_SHIFT;
3927
3928 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3929 PANEL_POWER_DOWN_DELAY_SHIFT;
3930
3931 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3932 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3933
3934 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3935 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3936
41aa3448 3937 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3938
3939 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3940 * our hw here, which are all in 100usec. */
3941 spec.t1_t3 = 210 * 10;
3942 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3943 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3944 spec.t10 = 500 * 10;
3945 /* This one is special and actually in units of 100ms, but zero
3946 * based in the hw (so we need to add 100 ms). But the sw vbt
3947 * table multiplies it with 1000 to make it in units of 100usec,
3948 * too. */
3949 spec.t11_t12 = (510 + 100) * 10;
3950
3951 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3952 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3953
3954 /* Use the max of the register settings and vbt. If both are
3955 * unset, fall back to the spec limits. */
3956#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3957 spec.field : \
3958 max(cur.field, vbt.field))
3959 assign_final(t1_t3);
3960 assign_final(t8);
3961 assign_final(t9);
3962 assign_final(t10);
3963 assign_final(t11_t12);
3964#undef assign_final
3965
3966#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3967 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3968 intel_dp->backlight_on_delay = get_delay(t8);
3969 intel_dp->backlight_off_delay = get_delay(t9);
3970 intel_dp->panel_power_down_delay = get_delay(t10);
3971 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3972#undef get_delay
3973
f30d26e4
JN		 3974 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3975 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3976 intel_dp->panel_power_cycle_delay);
3977
3978 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3979 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3980
3981 if (out)
3982 *out = final;
3983}
3984
3985static void
3986intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3987 struct intel_dp *intel_dp,
3988 struct edp_power_seq *seq)
3989{
3990 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3991 u32 pp_on, pp_off, pp_div, port_sel = 0;
3992 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3993 int pp_on_reg, pp_off_reg, pp_div_reg;
3994
3995 if (HAS_PCH_SPLIT(dev)) {
3996 pp_on_reg = PCH_PP_ON_DELAYS;
3997 pp_off_reg = PCH_PP_OFF_DELAYS;
3998 pp_div_reg = PCH_PP_DIVISOR;
3999 } else {
bf13e81b
JN		 4000 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4001
4002 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4003 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4004 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4005 }
4006
b2f19d1a
PZ		 4007 /*
4008 * And finally store the new values in the power sequencer. The
4009 * backlight delays are set to 1 because we do manual waits on them. For
4010 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4011 * we'll end up waiting for the backlight off delay twice: once when we
4012 * do the manual sleep, and once when we disable the panel and wait for
4013 * the PP_STATUS bit to become zero.
4014 */
f30d26e4 4015 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4016 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4017 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4018 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4019 /* Compute the divisor for the pp clock, simply match the Bspec
4020 * formula. */
453c5420 4021 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4022 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4023 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4024
4025 /* Haswell doesn't have any port selection bits for the panel
4026 * power sequencer any more. */
bc7d38a4 4027 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 4028 if (dp_to_dig_port(intel_dp)->port == PORT_B)
4029 port_sel = PANEL_PORT_SELECT_DPB_VLV;
4030 else
4031 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 4032 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4033 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 4034 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4035 else
a24c144c 4036 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4037 }
4038
453c5420
JB		 4039 pp_on |= port_sel;
4040
4041 I915_WRITE(pp_on_reg, pp_on);
4042 I915_WRITE(pp_off_reg, pp_off);
4043 I915_WRITE(pp_div_reg, pp_div);
67a54566 4044
67a54566 4045 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4046 I915_READ(pp_on_reg),
4047 I915_READ(pp_off_reg),
4048 I915_READ(pp_div_reg));
f684960e
CW		 4049}
4050
439d7ac0
PB		 4051void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4052{
4053 struct drm_i915_private *dev_priv = dev->dev_private;
4054 struct intel_encoder *encoder;
4055 struct intel_dp *intel_dp = NULL;
4056 struct intel_crtc_config *config = NULL;
4057 struct intel_crtc *intel_crtc = NULL;
4058 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4059 u32 reg, val;
4060 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4061
4062 if (refresh_rate <= 0) {
4063 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4064 return;
4065 }
4066
4067 if (intel_connector == NULL) {
4068 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4069 return;
4070 }
4071
4072 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4073 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4074 return;
4075 }
4076
4077 encoder = intel_attached_encoder(&intel_connector->base);
4078 intel_dp = enc_to_intel_dp(&encoder->base);
4079 intel_crtc = encoder->new_crtc;
4080
4081 if (!intel_crtc) {
4082 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4083 return;
4084 }
4085
4086 config = &intel_crtc->config;
4087
4088 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4089 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4090 return;
4091 }
4092
4093 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4094 index = DRRS_LOW_RR;
4095
4096 if (index == intel_dp->drrs_state.refresh_rate_type) {
4097 DRM_DEBUG_KMS(
4098 "DRRS requested for previously set RR...ignoring\n");
4099 return;
4100 }
4101
4102 if (!intel_crtc->active) {
4103 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4104 return;
4105 }
4106
4107 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4108 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4109 val = I915_READ(reg);
4110 if (index > DRRS_HIGH_RR) {
4111 val |= PIPECONF_EDP_RR_MODE_SWITCH;
4112 intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
4113 } else {
4114 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4115 }
4116 I915_WRITE(reg, val);
4117 }
4118
4119 /*
4120 * mutex taken to ensure that there is no race between differnt
4121 * drrs calls trying to update refresh rate. This scenario may occur
4122 * in future when idleness detection based DRRS in kernel and
4123 * possible calls from user space to set differnt RR are made.
4124 */
4125
4126 mutex_lock(&intel_dp->drrs_state.mutex);
4127
4128 intel_dp->drrs_state.refresh_rate_type = index;
4129
4130 mutex_unlock(&intel_dp->drrs_state.mutex);
4131
4132 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4133}
4134
4f9db5b5
PB		 4135static struct drm_display_mode *
4136intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4137 struct intel_connector *intel_connector,
4138 struct drm_display_mode *fixed_mode)
4139{
4140 struct drm_connector *connector = &intel_connector->base;
4141 struct intel_dp *intel_dp = &intel_dig_port->dp;
4142 struct drm_device *dev = intel_dig_port->base.base.dev;
4143 struct drm_i915_private *dev_priv = dev->dev_private;
4144 struct drm_display_mode *downclock_mode = NULL;
4145
4146 if (INTEL_INFO(dev)->gen <= 6) {
4147 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4148 return NULL;
4149 }
4150
4151 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4152 DRM_INFO("VBT doesn't support DRRS\n");
4153 return NULL;
4154 }
4155
4156 downclock_mode = intel_find_panel_downclock
4157 (dev, fixed_mode, connector);
4158
4159 if (!downclock_mode) {
4160 DRM_INFO("DRRS not supported\n");
4161 return NULL;
4162 }
4163
439d7ac0
PB		 4164 dev_priv->drrs.connector = intel_connector;
4165
4166 mutex_init(&intel_dp->drrs_state.mutex);
4167
4f9db5b5
PB		 4168 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4169
4170 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4171 DRM_INFO("seamless DRRS supported for eDP panel.\n");
4172 return downclock_mode;
4173}
4174
ed92f0b2 4175static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 4176 struct intel_connector *intel_connector,
4177 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 4178{
4179 struct drm_connector *connector = &intel_connector->base;
4180 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 4181 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4182 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 4183 struct drm_i915_private *dev_priv = dev->dev_private;
4184 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 4185 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 4186 bool has_dpcd;
4187 struct drm_display_mode *scan;
4188 struct edid *edid;
4189
4f9db5b5
PB		 4190 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4191
ed92f0b2
PZ		 4192 if (!is_edp(intel_dp))
4193 return true;
4194
63635217
PZ		 4195 /* The VDD bit needs a power domain reference, so if the bit is already
4196 * enabled when we boot, grab this reference. */
4197 if (edp_have_panel_vdd(intel_dp)) {
4198 enum intel_display_power_domain power_domain;
4199 power_domain = intel_display_port_power_domain(intel_encoder);
4200 intel_display_power_get(dev_priv, power_domain);
4201 }
4202
ed92f0b2 4203 /* Cache DPCD and EDID for edp. */
24f3e092 4204 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 4205 has_dpcd = intel_dp_get_dpcd(intel_dp);
4be73780 4206 edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 4207
4208 if (has_dpcd) {
4209 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4210 dev_priv->no_aux_handshake =
4211 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4212 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4213 } else {
4214 /* if this fails, presume the device is a ghost */
4215 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 4216 return false;
4217 }
4218
4219 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 4220 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 4221
060c8778 4222 mutex_lock(&dev->mode_config.mutex);
0b99836f 4223 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 4224 if (edid) {
4225 if (drm_add_edid_modes(connector, edid)) {
4226 drm_mode_connector_update_edid_property(connector,
4227 edid);
4228 drm_edid_to_eld(connector, edid);
4229 } else {
4230 kfree(edid);
4231 edid = ERR_PTR(-EINVAL);
4232 }
4233 } else {
4234 edid = ERR_PTR(-ENOENT);
4235 }
4236 intel_connector->edid = edid;
4237
4238 /* prefer fixed mode from EDID if available */
4239 list_for_each_entry(scan, &connector->probed_modes, head) {
4240 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4241 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 4242 downclock_mode = intel_dp_drrs_init(
4243 intel_dig_port,
4244 intel_connector, fixed_mode);
ed92f0b2
PZ		 4245 break;
4246 }
4247 }
4248
4249 /* fallback to VBT if available for eDP */
4250 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4251 fixed_mode = drm_mode_duplicate(dev,
4252 dev_priv->vbt.lfp_lvds_vbt_mode);
4253 if (fixed_mode)
4254 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4255 }
060c8778 4256 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 4257
4f9db5b5 4258 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
ed92f0b2
PZ		 4259 intel_panel_setup_backlight(connector);
4260
4261 return true;
4262}
4263
16c25533 4264bool
f0fec3f2
PZ		 4265intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4266 struct intel_connector *intel_connector)
a4fc5ed6 4267{
f0fec3f2
PZ		 4268 struct drm_connector *connector = &intel_connector->base;
4269 struct intel_dp *intel_dp = &intel_dig_port->dp;
4270 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4271 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 4272 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 4273 enum port port = intel_dig_port->port;
0095e6dc 4274 struct edp_power_seq power_seq = { 0 };
0b99836f 4275 int type;
a4fc5ed6 4276
ec5b01dd
DL		 4277 /* intel_dp vfuncs */
4278 if (IS_VALLEYVIEW(dev))
4279 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4280 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4281 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4282 else if (HAS_PCH_SPLIT(dev))
4283 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4284 else
4285 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4286
153b1100
DL		 4287 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4288
0767935e
DV		 4289 /* Preserve the current hw state. */
4290 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 4291 intel_dp->attached_connector = intel_connector;
3d3dc149 4292
3b32a35b 4293 if (intel_dp_is_edp(dev, port))
b329530c 4294 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 4295 else
4296 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 4297
f7d24902
ID		 4298 /*
4299 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4300 * for DP the encoder type can be set by the caller to
4301 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4302 */
4303 if (type == DRM_MODE_CONNECTOR_eDP)
4304 intel_encoder->type = INTEL_OUTPUT_EDP;
4305
e7281eab
ID		 4306 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4307 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4308 port_name(port));
4309
b329530c 4310 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 4311 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4312
a4fc5ed6
KP		 4313 connector->interlace_allowed = true;
4314 connector->doublescan_allowed = 0;
4315
f0fec3f2 4316 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 4317 edp_panel_vdd_work);
a4fc5ed6 4318
df0e9248 4319 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 4320 drm_sysfs_connector_add(connector);
4321
affa9354 4322 if (HAS_DDI(dev))
bcbc889b
PZ		 4323 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4324 else
4325 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 4326 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 4327
0b99836f 4328 /* Set up the hotplug pin. */
ab9d7c30
PZ		 4329 switch (port) {
4330 case PORT_A:
1d843f9d 4331 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 4332 break;
4333 case PORT_B:
1d843f9d 4334 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 4335 break;
4336 case PORT_C:
1d843f9d 4337 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 4338 break;
4339 case PORT_D:
1d843f9d 4340 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 4341 break;
4342 default:
ad1c0b19 4343 BUG();
5eb08b69
ZW		 4344 }
4345
dada1a9f
ID		 4346 if (is_edp(intel_dp)) {
4347 intel_dp_init_panel_power_timestamps(intel_dp);
0095e6dc 4348 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
dada1a9f 4349 }
0095e6dc 4350
9d1a1031 4351 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 4352
0095e6dc 4353 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4f71d0cb 4354 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 4355 if (is_edp(intel_dp)) {
4356 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
51fd371b 4357 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 4358 edp_panel_vdd_off_sync(intel_dp);
51fd371b 4359 drm_modeset_unlock(&dev->mode_config.connection_mutex);
15b1d171 4360 }
b2f246a8
PZ		 4361 drm_sysfs_connector_remove(connector);
4362 drm_connector_cleanup(connector);
16c25533 4363 return false;
b2f246a8 4364 }
32f9d658 4365
f684960e
CW		 4366 intel_dp_add_properties(intel_dp, connector);
4367
a4fc5ed6
KP		 4368 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4369 * 0xd. Failure to do so will result in spurious interrupts being
4370 * generated on the port when a cable is not attached.
4371 */
4372 if (IS_G4X(dev) && !IS_GM45(dev)) {
4373 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4374 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4375 }
16c25533
PZ		 4376
4377 return true;
a4fc5ed6 4378}
f0fec3f2
PZ		 4379
4380void
4381intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4382{
4383 struct intel_digital_port *intel_dig_port;
4384 struct intel_encoder *intel_encoder;
4385 struct drm_encoder *encoder;
4386 struct intel_connector *intel_connector;
4387
b14c5679 4388 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 4389 if (!intel_dig_port)
4390 return;
4391
b14c5679 4392 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 4393 if (!intel_connector) {
4394 kfree(intel_dig_port);
4395 return;
4396 }
4397
4398 intel_encoder = &intel_dig_port->base;
4399 encoder = &intel_encoder->base;
4400
4401 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4402 DRM_MODE_ENCODER_TMDS);
4403
5bfe2ac0 4404 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 4405 intel_encoder->disable = intel_disable_dp;
00c09d70 4406 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 4407 intel_encoder->get_config = intel_dp_get_config;
e4a1d846 4408 if (IS_CHERRYVIEW(dev)) {
9197c88b 4409 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 4410 intel_encoder->pre_enable = chv_pre_enable_dp;
4411 intel_encoder->enable = vlv_enable_dp;
580d3811 4412 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 4413 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 4414 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 4415 intel_encoder->pre_enable = vlv_pre_enable_dp;
4416 intel_encoder->enable = vlv_enable_dp;
49277c31 4417 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 4418 } else {
ecff4f3b
JN		 4419 intel_encoder->pre_enable = g4x_pre_enable_dp;
4420 intel_encoder->enable = g4x_enable_dp;
49277c31 4421 intel_encoder->post_disable = g4x_post_disable_dp;
ab1f90f9 4422 }
f0fec3f2 4423
174edf1f 4424 intel_dig_port->port = port;
f0fec3f2
PZ		 4425 intel_dig_port->dp.output_reg = output_reg;
4426
00c09d70 4427 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 4428 if (IS_CHERRYVIEW(dev)) {
4429 if (port == PORT_D)
4430 intel_encoder->crtc_mask = 1 << 2;
4431 else
4432 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
4433 } else {
4434 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4435 }
bc079e8b 4436 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 4437 intel_encoder->hot_plug = intel_dp_hot_plug;
4438
15b1d171
PZ		 4439 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4440 drm_encoder_cleanup(encoder);
4441 kfree(intel_dig_port);
b2f246a8 4442 kfree(intel_connector);
15b1d171 4443 }
f0fec3f2 4444}
Linux kernel - Deliverables
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