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drm: Remove duplicate drm_mode_cea_vic()
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
cfcb0fc9
JB		 41/**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48static bool is_edp(struct intel_dp *intel_dp)
49{
da63a9f2
PZ		 50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 53}
54
55/**
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
58 *
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
62 */
63static bool is_pch_edp(struct intel_dp *intel_dp)
64{
65 return intel_dp->is_pch_edp;
66}
67
1c95822a
AJ		 68/**
69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
70 * @intel_dp: DP struct
71 *
72 * Returns true if the given DP struct corresponds to a CPU eDP port.
73 */
74static bool is_cpu_edp(struct intel_dp *intel_dp)
75{
76 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
77}
78
30add22d 79static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
ea5b213a 80{
da63a9f2
PZ		 81 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
82
83 return intel_dig_port->base.base.dev;
ea5b213a 84}
a4fc5ed6 85
df0e9248
CW		 86static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
87{
fa90ecef 88 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 89}
90
814948ad
JB		 91/**
92 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
93 * @encoder: DRM encoder
94 *
95 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
96 * by intel_display.c.
97 */
98bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
99{
100 struct intel_dp *intel_dp;
101
102 if (!encoder)
103 return false;
104
105 intel_dp = enc_to_intel_dp(encoder);
106
107 return is_pch_edp(intel_dp);
108}
109
ea5b213a 110static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 111
32f9d658 112void
0206e353 113intel_edp_link_config(struct intel_encoder *intel_encoder,
ea5b213a 114 int *lane_num, int *link_bw)
32f9d658 115{
fa90ecef 116 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
32f9d658 117
ea5b213a 118 *lane_num = intel_dp->lane_count;
3b5c662e 119 *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
32f9d658
ZW		 120}
121
94bf2ced
DV		 122int
123intel_edp_target_clock(struct intel_encoder *intel_encoder,
124 struct drm_display_mode *mode)
125{
fa90ecef 126 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
dd06f90e 127 struct intel_connector *intel_connector = intel_dp->attached_connector;
94bf2ced 128
dd06f90e
JN		 129 if (intel_connector->panel.fixed_mode)
130 return intel_connector->panel.fixed_mode->clock;
94bf2ced
DV		 131 else
132 return mode->clock;
133}
134
a4fc5ed6 135static int
ea5b213a 136intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 137{
7183dc29 138 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 139
140 switch (max_link_bw) {
141 case DP_LINK_BW_1_62:
142 case DP_LINK_BW_2_7:
143 break;
144 default:
145 max_link_bw = DP_LINK_BW_1_62;
146 break;
147 }
148 return max_link_bw;
149}
150
cd9dde44
AJ		 151/*
152 * The units on the numbers in the next two are... bizarre. Examples will
153 * make it clearer; this one parallels an example in the eDP spec.
154 *
155 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
156 *
157 * 270000 * 1 * 8 / 10 == 216000
158 *
159 * The actual data capacity of that configuration is 2.16Gbit/s, so the
160 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
161 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
162 * 119000. At 18bpp that's 2142000 kilobits per second.
163 *
164 * Thus the strange-looking division by 10 in intel_dp_link_required, to
165 * get the result in decakilobits instead of kilobits.
166 */
167
a4fc5ed6 168static int
c898261c 169intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 170{
cd9dde44 171 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 172}
173
fe27d53e
DA		 174static int
175intel_dp_max_data_rate(int max_link_clock, int max_lanes)
176{
177 return (max_link_clock * max_lanes * 8) / 10;
178}
179
c4867936
DV		 180static bool
181intel_dp_adjust_dithering(struct intel_dp *intel_dp,
182 struct drm_display_mode *mode,
cb1793ce 183 bool adjust_mode)
c4867936 184{
9fa5f652
PZ		 185 int max_link_clock =
186 drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
397fe157 187 int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
c4867936
DV		 188 int max_rate, mode_rate;
189
190 mode_rate = intel_dp_link_required(mode->clock, 24);
191 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
192
193 if (mode_rate > max_rate) {
194 mode_rate = intel_dp_link_required(mode->clock, 18);
195 if (mode_rate > max_rate)
196 return false;
197
cb1793ce
DV		 198 if (adjust_mode)
199 mode->private_flags
c4867936
DV		 200 |= INTEL_MODE_DP_FORCE_6BPC;
201
202 return true;
203 }
204
205 return true;
206}
207
a4fc5ed6
KP		 208static int
209intel_dp_mode_valid(struct drm_connector *connector,
210 struct drm_display_mode *mode)
211{
df0e9248 212 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 213 struct intel_connector *intel_connector = to_intel_connector(connector);
214 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
a4fc5ed6 215
dd06f90e
JN		 216 if (is_edp(intel_dp) && fixed_mode) {
217 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 218 return MODE_PANEL;
219
dd06f90e 220 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43
ZY		 221 return MODE_PANEL;
222 }
223
cb1793ce 224 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
c4867936 225 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 226
227 if (mode->clock < 10000)
228 return MODE_CLOCK_LOW;
229
0af78a2b
DV		 230 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
231 return MODE_H_ILLEGAL;
232
a4fc5ed6
KP		 233 return MODE_OK;
234}
235
236static uint32_t
237pack_aux(uint8_t *src, int src_bytes)
238{
239 int i;
240 uint32_t v = 0;
241
242 if (src_bytes > 4)
243 src_bytes = 4;
244 for (i = 0; i < src_bytes; i++)
245 v |= ((uint32_t) src[i]) << ((3-i) * 8);
246 return v;
247}
248
249static void
250unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
251{
252 int i;
253 if (dst_bytes > 4)
254 dst_bytes = 4;
255 for (i = 0; i < dst_bytes; i++)
256 dst[i] = src >> ((3-i) * 8);
257}
258
fb0f8fbf
KP		 259/* hrawclock is 1/4 the FSB frequency */
260static int
261intel_hrawclk(struct drm_device *dev)
262{
263 struct drm_i915_private *dev_priv = dev->dev_private;
264 uint32_t clkcfg;
265
9473c8f4
VP		 266 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
267 if (IS_VALLEYVIEW(dev))
268 return 200;
269
fb0f8fbf
KP		 270 clkcfg = I915_READ(CLKCFG);
271 switch (clkcfg & CLKCFG_FSB_MASK) {
272 case CLKCFG_FSB_400:
273 return 100;
274 case CLKCFG_FSB_533:
275 return 133;
276 case CLKCFG_FSB_667:
277 return 166;
278 case CLKCFG_FSB_800:
279 return 200;
280 case CLKCFG_FSB_1067:
281 return 266;
282 case CLKCFG_FSB_1333:
283 return 333;
284 /* these two are just a guess; one of them might be right */
285 case CLKCFG_FSB_1600:
286 case CLKCFG_FSB_1600_ALT:
287 return 400;
288 default:
289 return 133;
290 }
291}
292
ebf33b18
KP		 293static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
294{
30add22d 295 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 296 struct drm_i915_private *dev_priv = dev->dev_private;
297
298 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
299}
300
301static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
302{
30add22d 303 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 304 struct drm_i915_private *dev_priv = dev->dev_private;
305
306 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
307}
308
9b984dae
KP		 309static void
310intel_dp_check_edp(struct intel_dp *intel_dp)
311{
30add22d 312 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 313 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 314
9b984dae
KP		 315 if (!is_edp(intel_dp))
316 return;
ebf33b18 317 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 318 WARN(1, "eDP powered off while attempting aux channel communication.\n");
319 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
ebf33b18 320 I915_READ(PCH_PP_STATUS),
9b984dae
KP		 321 I915_READ(PCH_PP_CONTROL));
322 }
323}
324
9ee32fea
DV		 325static uint32_t
326intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
327{
328 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
329 struct drm_device *dev = intel_dig_port->base.base.dev;
330 struct drm_i915_private *dev_priv = dev->dev_private;
331 uint32_t ch_ctl = intel_dp->output_reg + 0x10;
332 uint32_t status;
333 bool done;
334
335 if (IS_HASWELL(dev)) {
336 switch (intel_dig_port->port) {
337 case PORT_A:
338 ch_ctl = DPA_AUX_CH_CTL;
339 break;
340 case PORT_B:
341 ch_ctl = PCH_DPB_AUX_CH_CTL;
342 break;
343 case PORT_C:
344 ch_ctl = PCH_DPC_AUX_CH_CTL;
345 break;
346 case PORT_D:
347 ch_ctl = PCH_DPD_AUX_CH_CTL;
348 break;
349 default:
350 BUG();
351 }
352 }
353
ef04f00d 354#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea
DV		 355 if (has_aux_irq)
356 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 10);
357 else
358 done = wait_for_atomic(C, 10) == 0;
359 if (!done)
360 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
361 has_aux_irq);
362#undef C
363
364 return status;
365}
366
a4fc5ed6 367static int
ea5b213a 368intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 369 uint8_t *send, int send_bytes,
370 uint8_t *recv, int recv_size)
371{
ea5b213a 372 uint32_t output_reg = intel_dp->output_reg;
174edf1f
PZ		 373 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
374 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6
KP		 375 struct drm_i915_private *dev_priv = dev->dev_private;
376 uint32_t ch_ctl = output_reg + 0x10;
377 uint32_t ch_data = ch_ctl + 4;
9ee32fea 378 int i, ret, recv_bytes;
a4fc5ed6 379 uint32_t status;
fb0f8fbf 380 uint32_t aux_clock_divider;
6b4e0a93 381 int try, precharge;
9ee32fea
DV		 382 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
383
384 /* dp aux is extremely sensitive to irq latency, hence request the
385 * lowest possible wakeup latency and so prevent the cpu from going into
386 * deep sleep states.
387 */
388 pm_qos_update_request(&dev_priv->pm_qos, 0);
a4fc5ed6 389
750eb99e 390 if (IS_HASWELL(dev)) {
174edf1f 391 switch (intel_dig_port->port) {
750eb99e
PZ		 392 case PORT_A:
393 ch_ctl = DPA_AUX_CH_CTL;
394 ch_data = DPA_AUX_CH_DATA1;
395 break;
396 case PORT_B:
397 ch_ctl = PCH_DPB_AUX_CH_CTL;
398 ch_data = PCH_DPB_AUX_CH_DATA1;
399 break;
400 case PORT_C:
401 ch_ctl = PCH_DPC_AUX_CH_CTL;
402 ch_data = PCH_DPC_AUX_CH_DATA1;
403 break;
404 case PORT_D:
405 ch_ctl = PCH_DPD_AUX_CH_CTL;
406 ch_data = PCH_DPD_AUX_CH_DATA1;
407 break;
408 default:
409 BUG();
410 }
411 }
412
9b984dae 413 intel_dp_check_edp(intel_dp);
a4fc5ed6 414 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 415 * and would like to run at 2MHz. So, take the
416 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 417 *
418 * Note that PCH attached eDP panels should use a 125MHz input
419 * clock divider.
a4fc5ed6 420 */
1c95822a 421 if (is_cpu_edp(intel_dp)) {
affa9354 422 if (HAS_DDI(dev))
b8fc2f6a
PZ		 423 aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
424 else if (IS_VALLEYVIEW(dev))
9473c8f4
VP		 425 aux_clock_divider = 100;
426 else if (IS_GEN6(dev) || IS_GEN7(dev))
1a2eb460 427 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 428 else
429 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
430 } else if (HAS_PCH_SPLIT(dev))
6b3ec1c9 431 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
5eb08b69
ZW		 432 else
433 aux_clock_divider = intel_hrawclk(dev) / 2;
434
6b4e0a93
DV		 435 if (IS_GEN6(dev))
436 precharge = 3;
437 else
438 precharge = 5;
439
11bee43e
JB		 440 /* Try to wait for any previous AUX channel activity */
441 for (try = 0; try < 3; try++) {
ef04f00d 442 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 443 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
444 break;
445 msleep(1);
446 }
447
448 if (try == 3) {
449 WARN(1, "dp_aux_ch not started status 0x%08x\n",
450 I915_READ(ch_ctl));
9ee32fea
DV		 451 ret = -EBUSY;
452 goto out;
4f7f7b7e
CW		 453 }
454
fb0f8fbf
KP		 455 /* Must try at least 3 times according to DP spec */
456 for (try = 0; try < 5; try++) {
457 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 458 for (i = 0; i < send_bytes; i += 4)
459 I915_WRITE(ch_data + i,
460 pack_aux(send + i, send_bytes - i));
0206e353 461
fb0f8fbf 462 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 463 I915_WRITE(ch_ctl,
464 DP_AUX_CH_CTL_SEND_BUSY |
9ee32fea 465 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
4f7f7b7e
CW		 466 DP_AUX_CH_CTL_TIME_OUT_400us |
467 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
468 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
469 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
470 DP_AUX_CH_CTL_DONE |
471 DP_AUX_CH_CTL_TIME_OUT_ERROR |
472 DP_AUX_CH_CTL_RECEIVE_ERROR);
9ee32fea
DV		 473
474 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
0206e353 475
fb0f8fbf 476 /* Clear done status and any errors */
4f7f7b7e
CW		 477 I915_WRITE(ch_ctl,
478 status |
479 DP_AUX_CH_CTL_DONE |
480 DP_AUX_CH_CTL_TIME_OUT_ERROR |
481 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 482
483 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
484 DP_AUX_CH_CTL_RECEIVE_ERROR))
485 continue;
4f7f7b7e 486 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 487 break;
488 }
489
a4fc5ed6 490 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 491 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 492 ret = -EBUSY;
493 goto out;
a4fc5ed6
KP		 494 }
495
496 /* Check for timeout or receive error.
497 * Timeouts occur when the sink is not connected
498 */
a5b3da54 499 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 500 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 501 ret = -EIO;
502 goto out;
a5b3da54 503 }
1ae8c0a5
KP		 504
505 /* Timeouts occur when the device isn't connected, so they're
506 * "normal" -- don't fill the kernel log with these */
a5b3da54 507 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 508 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 509 ret = -ETIMEDOUT;
510 goto out;
a4fc5ed6
KP		 511 }
512
513 /* Unload any bytes sent back from the other side */
514 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
515 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 516 if (recv_bytes > recv_size)
517 recv_bytes = recv_size;
0206e353 518
4f7f7b7e
CW		 519 for (i = 0; i < recv_bytes; i += 4)
520 unpack_aux(I915_READ(ch_data + i),
521 recv + i, recv_bytes - i);
a4fc5ed6 522
9ee32fea
DV		 523 ret = recv_bytes;
524out:
525 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
526
527 return ret;
a4fc5ed6
KP		 528}
529
530/* Write data to the aux channel in native mode */
531static int
ea5b213a 532intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 533 uint16_t address, uint8_t *send, int send_bytes)
534{
535 int ret;
536 uint8_t msg[20];
537 int msg_bytes;
538 uint8_t ack;
539
9b984dae 540 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 541 if (send_bytes > 16)
542 return -1;
543 msg[0] = AUX_NATIVE_WRITE << 4;
544 msg[1] = address >> 8;
eebc863e 545 msg[2] = address & 0xff;
a4fc5ed6
KP		 546 msg[3] = send_bytes - 1;
547 memcpy(&msg[4], send, send_bytes);
548 msg_bytes = send_bytes + 4;
549 for (;;) {
ea5b213a 550 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 551 if (ret < 0)
552 return ret;
553 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
554 break;
555 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
556 udelay(100);
557 else
a5b3da54 558 return -EIO;
a4fc5ed6
KP		 559 }
560 return send_bytes;
561}
562
563/* Write a single byte to the aux channel in native mode */
564static int
ea5b213a 565intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 566 uint16_t address, uint8_t byte)
567{
ea5b213a 568 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 569}
570
571/* read bytes from a native aux channel */
572static int
ea5b213a 573intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 574 uint16_t address, uint8_t *recv, int recv_bytes)
575{
576 uint8_t msg[4];
577 int msg_bytes;
578 uint8_t reply[20];
579 int reply_bytes;
580 uint8_t ack;
581 int ret;
582
9b984dae 583 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 584 msg[0] = AUX_NATIVE_READ << 4;
585 msg[1] = address >> 8;
586 msg[2] = address & 0xff;
587 msg[3] = recv_bytes - 1;
588
589 msg_bytes = 4;
590 reply_bytes = recv_bytes + 1;
591
592 for (;;) {
ea5b213a 593 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 594 reply, reply_bytes);
a5b3da54
KP		 595 if (ret == 0)
596 return -EPROTO;
597 if (ret < 0)
a4fc5ed6
KP		 598 return ret;
599 ack = reply[0];
600 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
601 memcpy(recv, reply + 1, ret - 1);
602 return ret - 1;
603 }
604 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
605 udelay(100);
606 else
a5b3da54 607 return -EIO;
a4fc5ed6
KP		 608 }
609}
610
611static int
ab2c0672
DA		 612intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
613 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 614{
ab2c0672 615 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 616 struct intel_dp *intel_dp = container_of(adapter,
617 struct intel_dp,
618 adapter);
ab2c0672
DA		 619 uint16_t address = algo_data->address;
620 uint8_t msg[5];
621 uint8_t reply[2];
8316f337 622 unsigned retry;
ab2c0672
DA		 623 int msg_bytes;
624 int reply_bytes;
625 int ret;
626
9b984dae 627 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 628 /* Set up the command byte */
629 if (mode & MODE_I2C_READ)
630 msg[0] = AUX_I2C_READ << 4;
631 else
632 msg[0] = AUX_I2C_WRITE << 4;
633
634 if (!(mode & MODE_I2C_STOP))
635 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 636
ab2c0672
DA		 637 msg[1] = address >> 8;
638 msg[2] = address;
639
640 switch (mode) {
641 case MODE_I2C_WRITE:
642 msg[3] = 0;
643 msg[4] = write_byte;
644 msg_bytes = 5;
645 reply_bytes = 1;
646 break;
647 case MODE_I2C_READ:
648 msg[3] = 0;
649 msg_bytes = 4;
650 reply_bytes = 2;
651 break;
652 default:
653 msg_bytes = 3;
654 reply_bytes = 1;
655 break;
656 }
657
8316f337
DF		 658 for (retry = 0; retry < 5; retry++) {
659 ret = intel_dp_aux_ch(intel_dp,
660 msg, msg_bytes,
661 reply, reply_bytes);
ab2c0672 662 if (ret < 0) {
3ff99164 663 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 664 return ret;
665 }
8316f337
DF		 666
667 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
668 case AUX_NATIVE_REPLY_ACK:
669 /* I2C-over-AUX Reply field is only valid
670 * when paired with AUX ACK.
671 */
672 break;
673 case AUX_NATIVE_REPLY_NACK:
674 DRM_DEBUG_KMS("aux_ch native nack\n");
675 return -EREMOTEIO;
676 case AUX_NATIVE_REPLY_DEFER:
677 udelay(100);
678 continue;
679 default:
680 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
681 reply[0]);
682 return -EREMOTEIO;
683 }
684
ab2c0672
DA		 685 switch (reply[0] & AUX_I2C_REPLY_MASK) {
686 case AUX_I2C_REPLY_ACK:
687 if (mode == MODE_I2C_READ) {
688 *read_byte = reply[1];
689 }
690 return reply_bytes - 1;
691 case AUX_I2C_REPLY_NACK:
8316f337 692 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 693 return -EREMOTEIO;
694 case AUX_I2C_REPLY_DEFER:
8316f337 695 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 696 udelay(100);
697 break;
698 default:
8316f337 699 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 700 return -EREMOTEIO;
701 }
702 }
8316f337
DF		 703
704 DRM_ERROR("too many retries, giving up\n");
705 return -EREMOTEIO;
a4fc5ed6
KP		 706}
707
708static int
ea5b213a 709intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 710 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 711{
0b5c541b
KP		 712 int ret;
713
d54e9d28 714 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 715 intel_dp->algo.running = false;
716 intel_dp->algo.address = 0;
717 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
718
0206e353 719 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 720 intel_dp->adapter.owner = THIS_MODULE;
721 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 722 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 723 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
724 intel_dp->adapter.algo_data = &intel_dp->algo;
725 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
726
0b5c541b
KP		 727 ironlake_edp_panel_vdd_on(intel_dp);
728 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 729 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 730 return ret;
a4fc5ed6
KP		 731}
732
00c09d70 733bool
e811f5ae
LP		 734intel_dp_mode_fixup(struct drm_encoder *encoder,
735 const struct drm_display_mode *mode,
a4fc5ed6
KP		 736 struct drm_display_mode *adjusted_mode)
737{
0d3a1bee 738 struct drm_device *dev = encoder->dev;
ea5b213a 739 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
dd06f90e 740 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 741 int lane_count, clock;
397fe157 742 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 743 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 744 int bpp, mode_rate;
a4fc5ed6
KP		 745 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
746
dd06f90e
JN		 747 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
748 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
749 adjusted_mode);
53b41837
YN		 750 intel_pch_panel_fitting(dev,
751 intel_connector->panel.fitting_mode,
1d8e1c75 752 mode, adjusted_mode);
0d3a1bee
ZY		 753 }
754
cb1793ce 755 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 756 return false;
757
083f9560
DV		 758 DRM_DEBUG_KMS("DP link computation with max lane count %i "
759 "max bw %02x pixel clock %iKHz\n",
71244653 760 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 761
cb1793ce 762 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
c4867936
DV		 763 return false;
764
765 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
3685a8f3 766
55bc60db
VS		 767 if (intel_dp->color_range_auto) {
768 /*
769 * See:
770 * CEA-861-E - 5.1 Default Encoding Parameters
771 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
772 */
18316c8c 773 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 774 intel_dp->color_range = DP_COLOR_RANGE_16_235;
775 else
776 intel_dp->color_range = 0;
777 }
778
3685a8f3
VS		 779 if (intel_dp->color_range)
780 adjusted_mode->private_flags |= INTEL_MODE_LIMITED_COLOR_RANGE;
781
71244653 782 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
c4867936 783
2514bc51
JB		 784 for (clock = 0; clock <= max_clock; clock++) {
785 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
9fa5f652
PZ		 786 int link_bw_clock =
787 drm_dp_bw_code_to_link_rate(bws[clock]);
788 int link_avail = intel_dp_max_data_rate(link_bw_clock,
789 lane_count);
a4fc5ed6 790
083f9560 791 if (mode_rate <= link_avail) {
ea5b213a
CW		 792 intel_dp->link_bw = bws[clock];
793 intel_dp->lane_count = lane_count;
9fa5f652 794 adjusted_mode->clock = link_bw_clock;
083f9560
DV		 795 DRM_DEBUG_KMS("DP link bw %02x lane "
796 "count %d clock %d bpp %d\n",
ea5b213a 797 intel_dp->link_bw, intel_dp->lane_count,
083f9560
DV		 798 adjusted_mode->clock, bpp);
799 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
800 mode_rate, link_avail);
a4fc5ed6
KP		 801 return true;
802 }
803 }
804 }
fe27d53e 805
a4fc5ed6
KP		 806 return false;
807}
808
a4fc5ed6
KP		 809void
810intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
811 struct drm_display_mode *adjusted_mode)
812{
813 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 814 struct intel_encoder *intel_encoder;
815 struct intel_dp *intel_dp;
a4fc5ed6
KP		 816 struct drm_i915_private *dev_priv = dev->dev_private;
817 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
858fa035 818 int lane_count = 4;
e69d0bc1 819 struct intel_link_m_n m_n;
9db4a9c7 820 int pipe = intel_crtc->pipe;
afe2fcf5 821 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
a4fc5ed6
KP		 822
823 /*
21d40d37 824 * Find the lane count in the intel_encoder private
a4fc5ed6 825 */
fa90ecef
PZ		 826 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
827 intel_dp = enc_to_intel_dp(&intel_encoder->base);
a4fc5ed6 828
fa90ecef
PZ		 829 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
830 intel_encoder->type == INTEL_OUTPUT_EDP)
9a10f401 831 {
ea5b213a 832 lane_count = intel_dp->lane_count;
51190667 833 break;
a4fc5ed6
KP		 834 }
835 }
836
837 /*
838 * Compute the GMCH and Link ratios. The '3' here is
839 * the number of bytes_per_pixel post-LUT, which we always
840 * set up for 8-bits of R/G/B, or 3 bytes total.
841 */
e69d0bc1
DV		 842 intel_link_compute_m_n(intel_crtc->bpp, lane_count,
843 mode->clock, adjusted_mode->clock, &m_n);
a4fc5ed6 844
1eb8dfec 845 if (IS_HASWELL(dev)) {
afe2fcf5
PZ		 846 I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
847 TU_SIZE(m_n.tu) | m_n.gmch_m);
848 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
849 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
850 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
1eb8dfec 851 } else if (HAS_PCH_SPLIT(dev)) {
7346bfa0 852 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
9db4a9c7
JB		 853 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
854 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
855 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
74a4dd2e
VP		 856 } else if (IS_VALLEYVIEW(dev)) {
857 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
858 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
859 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
860 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
a4fc5ed6 861 } else {
9db4a9c7 862 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
7346bfa0 863 TU_SIZE(m_n.tu) | m_n.gmch_m);
9db4a9c7
JB		 864 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
865 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
866 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
a4fc5ed6
KP		 867 }
868}
869
247d89f6
PZ		 870void intel_dp_init_link_config(struct intel_dp *intel_dp)
871{
872 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
873 intel_dp->link_configuration[0] = intel_dp->link_bw;
874 intel_dp->link_configuration[1] = intel_dp->lane_count;
875 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
876 /*
877 * Check for DPCD version > 1.1 and enhanced framing support
878 */
879 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
880 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
881 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
882 }
883}
884
ea9b6006
DV		 885static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
886{
887 struct drm_device *dev = crtc->dev;
888 struct drm_i915_private *dev_priv = dev->dev_private;
889 u32 dpa_ctl;
890
891 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
892 dpa_ctl = I915_READ(DP_A);
893 dpa_ctl &= ~DP_PLL_FREQ_MASK;
894
895 if (clock < 200000) {
1ce17038
DV		 896 /* For a long time we've carried around a ILK-DevA w/a for the
897 * 160MHz clock. If we're really unlucky, it's still required.
898 */
899 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 900 dpa_ctl |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 901 } else {
902 dpa_ctl |= DP_PLL_FREQ_270MHZ;
903 }
1ce17038 904
ea9b6006
DV		 905 I915_WRITE(DP_A, dpa_ctl);
906
907 POSTING_READ(DP_A);
908 udelay(500);
909}
910
a4fc5ed6
KP		 911static void
912intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
913 struct drm_display_mode *adjusted_mode)
914{
e3421a18 915 struct drm_device *dev = encoder->dev;
417e822d 916 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 917 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
fa90ecef 918 struct drm_crtc *crtc = encoder->crtc;
a4fc5ed6
KP		 919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
920
417e822d 921 /*
1a2eb460 922 * There are four kinds of DP registers:
417e822d
KP		 923 *
924 * IBX PCH
1a2eb460
KP		 925 * SNB CPU
926 * IVB CPU
417e822d
KP		 927 * CPT PCH
928 *
929 * IBX PCH and CPU are the same for almost everything,
930 * except that the CPU DP PLL is configured in this
931 * register
932 *
933 * CPT PCH is quite different, having many bits moved
934 * to the TRANS_DP_CTL register instead. That
935 * configuration happens (oddly) in ironlake_pch_enable
936 */
9c9e7927 937
417e822d
KP		 938 /* Preserve the BIOS-computed detected bit. This is
939 * supposed to be read-only.
940 */
941 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 942
417e822d 943 /* Handle DP bits in common between all three register formats */
417e822d 944 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 945
ea5b213a 946 switch (intel_dp->lane_count) {
a4fc5ed6 947 case 1:
ea5b213a 948 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 949 break;
950 case 2:
ea5b213a 951 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 952 break;
953 case 4:
ea5b213a 954 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 955 break;
956 }
e0dac65e
WF		 957 if (intel_dp->has_audio) {
958 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
959 pipe_name(intel_crtc->pipe));
ea5b213a 960 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 961 intel_write_eld(encoder, adjusted_mode);
962 }
247d89f6
PZ		 963
964 intel_dp_init_link_config(intel_dp);
a4fc5ed6 965
417e822d 966 /* Split out the IBX/CPU vs CPT settings */
32f9d658 967
19c03924 968 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 969 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
970 intel_dp->DP |= DP_SYNC_HS_HIGH;
971 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
972 intel_dp->DP |= DP_SYNC_VS_HIGH;
973 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
974
975 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
976 intel_dp->DP |= DP_ENHANCED_FRAMING;
977
978 intel_dp->DP |= intel_crtc->pipe << 29;
979
980 /* don't miss out required setting for eDP */
1a2eb460
KP		 981 if (adjusted_mode->clock < 200000)
982 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
983 else
984 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
985 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
3685a8f3
VS		 986 if (!HAS_PCH_SPLIT(dev))
987 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 988
989 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
990 intel_dp->DP |= DP_SYNC_HS_HIGH;
991 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
992 intel_dp->DP |= DP_SYNC_VS_HIGH;
993 intel_dp->DP |= DP_LINK_TRAIN_OFF;
994
995 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
996 intel_dp->DP |= DP_ENHANCED_FRAMING;
997
998 if (intel_crtc->pipe == 1)
999 intel_dp->DP |= DP_PIPEB_SELECT;
1000
1001 if (is_cpu_edp(intel_dp)) {
1002 /* don't miss out required setting for eDP */
417e822d
KP		 1003 if (adjusted_mode->clock < 200000)
1004 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
1005 else
1006 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
1007 }
1008 } else {
1009 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1010 }
ea9b6006
DV		 1011
1012 if (is_cpu_edp(intel_dp))
1013 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
a4fc5ed6
KP		 1014}
1015
99ea7127
KP		 1016#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1017#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1018
1019#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1020#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1021
1022#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1023#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1024
1025static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
1026 u32 mask,
1027 u32 value)
bd943159 1028{
30add22d 1029 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1030 struct drm_i915_private *dev_priv = dev->dev_private;
32ce697c 1031
99ea7127
KP		 1032 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1033 mask, value,
1034 I915_READ(PCH_PP_STATUS),
1035 I915_READ(PCH_PP_CONTROL));
32ce697c 1036
99ea7127
KP		 1037 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
1038 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1039 I915_READ(PCH_PP_STATUS),
1040 I915_READ(PCH_PP_CONTROL));
32ce697c 1041 }
99ea7127 1042}
32ce697c 1043
99ea7127
KP		 1044static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1045{
1046 DRM_DEBUG_KMS("Wait for panel power on\n");
1047 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1048}
1049
99ea7127
KP		 1050static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1051{
1052 DRM_DEBUG_KMS("Wait for panel power off time\n");
1053 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1054}
1055
1056static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1057{
1058 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1059 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1060}
1061
1062
832dd3c1
KP		 1063/* Read the current pp_control value, unlocking the register if it
1064 * is locked
1065 */
1066
1067static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1068{
1069 u32 control = I915_READ(PCH_PP_CONTROL);
1070
1071 control &= ~PANEL_UNLOCK_MASK;
1072 control |= PANEL_UNLOCK_REGS;
1073 return control;
bd943159
KP		 1074}
1075
82a4d9c0 1076void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1077{
30add22d 1078 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1079 struct drm_i915_private *dev_priv = dev->dev_private;
1080 u32 pp;
1081
97af61f5
KP		 1082 if (!is_edp(intel_dp))
1083 return;
f01eca2e 1084 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 1085
bd943159
KP		 1086 WARN(intel_dp->want_panel_vdd,
1087 "eDP VDD already requested on\n");
1088
1089 intel_dp->want_panel_vdd = true;
99ea7127 1090
bd943159
KP		 1091 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1092 DRM_DEBUG_KMS("eDP VDD already on\n");
1093 return;
1094 }
1095
99ea7127
KP		 1096 if (!ironlake_edp_have_panel_power(intel_dp))
1097 ironlake_wait_panel_power_cycle(intel_dp);
1098
832dd3c1 1099 pp = ironlake_get_pp_control(dev_priv);
5d613501
JB		 1100 pp |= EDP_FORCE_VDD;
1101 I915_WRITE(PCH_PP_CONTROL, pp);
1102 POSTING_READ(PCH_PP_CONTROL);
f01eca2e
KP		 1103 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1104 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
ebf33b18
KP		 1105
1106 /*
1107 * If the panel wasn't on, delay before accessing aux channel
1108 */
1109 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1110 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1111 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1112 }
5d613501
JB		 1113}
1114
bd943159 1115static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1116{
30add22d 1117 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1118 struct drm_i915_private *dev_priv = dev->dev_private;
1119 u32 pp;
1120
a0e99e68
DV		 1121 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1122
bd943159 1123 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
832dd3c1 1124 pp = ironlake_get_pp_control(dev_priv);
bd943159
KP		 1125 pp &= ~EDP_FORCE_VDD;
1126 I915_WRITE(PCH_PP_CONTROL, pp);
1127 POSTING_READ(PCH_PP_CONTROL);
1128
1129 /* Make sure sequencer is idle before allowing subsequent activity */
1130 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1131 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
99ea7127
KP		 1132
1133 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1134 }
1135}
5d613501 1136
bd943159
KP		 1137static void ironlake_panel_vdd_work(struct work_struct *__work)
1138{
1139 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1140 struct intel_dp, panel_vdd_work);
30add22d 1141 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1142
627f7675 1143 mutex_lock(&dev->mode_config.mutex);
bd943159 1144 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1145 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1146}
1147
82a4d9c0 1148void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1149{
97af61f5
KP		 1150 if (!is_edp(intel_dp))
1151 return;
5d613501 1152
bd943159
KP		 1153 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1154 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1155
bd943159
KP		 1156 intel_dp->want_panel_vdd = false;
1157
1158 if (sync) {
1159 ironlake_panel_vdd_off_sync(intel_dp);
1160 } else {
1161 /*
1162 * Queue the timer to fire a long
1163 * time from now (relative to the power down delay)
1164 * to keep the panel power up across a sequence of operations
1165 */
1166 schedule_delayed_work(&intel_dp->panel_vdd_work,
1167 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1168 }
5d613501
JB		 1169}
1170
82a4d9c0 1171void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1172{
30add22d 1173 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1174 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1175 u32 pp;
9934c132 1176
97af61f5 1177 if (!is_edp(intel_dp))
bd943159 1178 return;
99ea7127
KP		 1179
1180 DRM_DEBUG_KMS("Turn eDP power on\n");
1181
1182 if (ironlake_edp_have_panel_power(intel_dp)) {
1183 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1184 return;
99ea7127 1185 }
9934c132 1186
99ea7127 1187 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1188
99ea7127 1189 pp = ironlake_get_pp_control(dev_priv);
05ce1a49
KP		 1190 if (IS_GEN5(dev)) {
1191 /* ILK workaround: disable reset around power sequence */
1192 pp &= ~PANEL_POWER_RESET;
1193 I915_WRITE(PCH_PP_CONTROL, pp);
1194 POSTING_READ(PCH_PP_CONTROL);
1195 }
37c6c9b0 1196
1c0ae80a 1197 pp |= POWER_TARGET_ON;
99ea7127
KP		 1198 if (!IS_GEN5(dev))
1199 pp |= PANEL_POWER_RESET;
1200
9934c132 1201 I915_WRITE(PCH_PP_CONTROL, pp);
01cb9ea6 1202 POSTING_READ(PCH_PP_CONTROL);
9934c132 1203
99ea7127 1204 ironlake_wait_panel_on(intel_dp);
9934c132 1205
05ce1a49
KP		 1206 if (IS_GEN5(dev)) {
1207 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1208 I915_WRITE(PCH_PP_CONTROL, pp);
1209 POSTING_READ(PCH_PP_CONTROL);
1210 }
9934c132
JB		 1211}
1212
82a4d9c0 1213void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1214{
30add22d 1215 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1216 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1217 u32 pp;
9934c132 1218
97af61f5
KP		 1219 if (!is_edp(intel_dp))
1220 return;
37c6c9b0 1221
99ea7127 1222 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1223
6cb49835 1224 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1225
99ea7127 1226 pp = ironlake_get_pp_control(dev_priv);
35a38556
DV		 1227 /* We need to switch off panel power _and_ force vdd, for otherwise some
1228 * panels get very unhappy and cease to work. */
1229 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
99ea7127
KP		 1230 I915_WRITE(PCH_PP_CONTROL, pp);
1231 POSTING_READ(PCH_PP_CONTROL);
9934c132 1232
35a38556
DV		 1233 intel_dp->want_panel_vdd = false;
1234
99ea7127 1235 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1236}
1237
d6c50ff8 1238void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1239{
da63a9f2
PZ		 1240 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1241 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658 1242 struct drm_i915_private *dev_priv = dev->dev_private;
da63a9f2 1243 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
32f9d658
ZW		 1244 u32 pp;
1245
f01eca2e
KP		 1246 if (!is_edp(intel_dp))
1247 return;
1248
28c97730 1249 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1250 /*
1251 * If we enable the backlight right away following a panel power
1252 * on, we may see slight flicker as the panel syncs with the eDP
1253 * link. So delay a bit to make sure the image is solid before
1254 * allowing it to appear.
1255 */
f01eca2e 1256 msleep(intel_dp->backlight_on_delay);
832dd3c1 1257 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1258 pp |= EDP_BLC_ENABLE;
1259 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e 1260 POSTING_READ(PCH_PP_CONTROL);
035aa3de
DV		 1261
1262 intel_panel_enable_backlight(dev, pipe);
32f9d658
ZW		 1263}
1264
d6c50ff8 1265void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1266{
30add22d 1267 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1268 struct drm_i915_private *dev_priv = dev->dev_private;
1269 u32 pp;
1270
f01eca2e
KP		 1271 if (!is_edp(intel_dp))
1272 return;
1273
035aa3de
DV		 1274 intel_panel_disable_backlight(dev);
1275
28c97730 1276 DRM_DEBUG_KMS("\n");
832dd3c1 1277 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1278 pp &= ~EDP_BLC_ENABLE;
1279 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e
KP		 1280 POSTING_READ(PCH_PP_CONTROL);
1281 msleep(intel_dp->backlight_off_delay);
32f9d658 1282}
a4fc5ed6 1283
2bd2ad64 1284static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1285{
da63a9f2
PZ		 1286 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1287 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1288 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1289 struct drm_i915_private *dev_priv = dev->dev_private;
1290 u32 dpa_ctl;
1291
2bd2ad64
DV		 1292 assert_pipe_disabled(dev_priv,
1293 to_intel_crtc(crtc)->pipe);
1294
d240f20f
JB		 1295 DRM_DEBUG_KMS("\n");
1296 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1297 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1298 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1299
1300 /* We don't adjust intel_dp->DP while tearing down the link, to
1301 * facilitate link retraining (e.g. after hotplug). Hence clear all
1302 * enable bits here to ensure that we don't enable too much. */
1303 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1304 intel_dp->DP |= DP_PLL_ENABLE;
1305 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1306 POSTING_READ(DP_A);
1307 udelay(200);
d240f20f
JB		 1308}
1309
2bd2ad64 1310static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1311{
da63a9f2
PZ		 1312 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1313 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1314 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1315 struct drm_i915_private *dev_priv = dev->dev_private;
1316 u32 dpa_ctl;
1317
2bd2ad64
DV		 1318 assert_pipe_disabled(dev_priv,
1319 to_intel_crtc(crtc)->pipe);
1320
d240f20f 1321 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1322 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1323 "dp pll off, should be on\n");
1324 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1325
1326 /* We can't rely on the value tracked for the DP register in
1327 * intel_dp->DP because link_down must not change that (otherwise link
1328 * re-training will fail. */
298b0b39 1329 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1330 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1331 POSTING_READ(DP_A);
d240f20f
JB		 1332 udelay(200);
1333}
1334
c7ad3810 1335/* If the sink supports it, try to set the power state appropriately */
c19b0669 1336void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1337{
1338 int ret, i;
1339
1340 /* Should have a valid DPCD by this point */
1341 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1342 return;
1343
1344 if (mode != DRM_MODE_DPMS_ON) {
1345 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1346 DP_SET_POWER_D3);
1347 if (ret != 1)
1348 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1349 } else {
1350 /*
1351 * When turning on, we need to retry for 1ms to give the sink
1352 * time to wake up.
1353 */
1354 for (i = 0; i < 3; i++) {
1355 ret = intel_dp_aux_native_write_1(intel_dp,
1356 DP_SET_POWER,
1357 DP_SET_POWER_D0);
1358 if (ret == 1)
1359 break;
1360 msleep(1);
1361 }
1362 }
1363}
1364
19d8fe15
DV		 1365static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1366 enum pipe *pipe)
d240f20f 1367{
19d8fe15
DV		 1368 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1369 struct drm_device *dev = encoder->base.dev;
1370 struct drm_i915_private *dev_priv = dev->dev_private;
1371 u32 tmp = I915_READ(intel_dp->output_reg);
1372
1373 if (!(tmp & DP_PORT_EN))
1374 return false;
1375
1376 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1377 *pipe = PORT_TO_PIPE_CPT(tmp);
1378 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1379 *pipe = PORT_TO_PIPE(tmp);
1380 } else {
1381 u32 trans_sel;
1382 u32 trans_dp;
1383 int i;
1384
1385 switch (intel_dp->output_reg) {
1386 case PCH_DP_B:
1387 trans_sel = TRANS_DP_PORT_SEL_B;
1388 break;
1389 case PCH_DP_C:
1390 trans_sel = TRANS_DP_PORT_SEL_C;
1391 break;
1392 case PCH_DP_D:
1393 trans_sel = TRANS_DP_PORT_SEL_D;
1394 break;
1395 default:
1396 return true;
1397 }
1398
1399 for_each_pipe(i) {
1400 trans_dp = I915_READ(TRANS_DP_CTL(i));
1401 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1402 *pipe = i;
1403 return true;
1404 }
1405 }
19d8fe15 1406
4a0833ec
DV		 1407 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1408 intel_dp->output_reg);
1409 }
d240f20f 1410
19d8fe15
DV		 1411 return true;
1412}
d240f20f 1413
e8cb4558 1414static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1415{
e8cb4558 1416 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
6cb49835
DV		 1417
1418 /* Make sure the panel is off before trying to change the mode. But also
1419 * ensure that we have vdd while we switch off the panel. */
1420 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1421 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1422 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1423 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1424
1425 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1426 if (!is_cpu_edp(intel_dp))
1427 intel_dp_link_down(intel_dp);
d240f20f
JB		 1428}
1429
2bd2ad64 1430static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1431{
2bd2ad64
DV		 1432 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1433
3739850b
DV		 1434 if (is_cpu_edp(intel_dp)) {
1435 intel_dp_link_down(intel_dp);
2bd2ad64 1436 ironlake_edp_pll_off(intel_dp);
3739850b 1437 }
2bd2ad64
DV		 1438}
1439
e8cb4558 1440static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1441{
e8cb4558
DV		 1442 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1443 struct drm_device *dev = encoder->base.dev;
1444 struct drm_i915_private *dev_priv = dev->dev_private;
1445 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1446
0c33d8d7
DV		 1447 if (WARN_ON(dp_reg & DP_PORT_EN))
1448 return;
5d613501 1449
97af61f5 1450 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1451 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1452 intel_dp_start_link_train(intel_dp);
97af61f5 1453 ironlake_edp_panel_on(intel_dp);
bd943159 1454 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1455 intel_dp_complete_link_train(intel_dp);
f01eca2e 1456 ironlake_edp_backlight_on(intel_dp);
d240f20f
JB		 1457}
1458
2bd2ad64 1459static void intel_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1460{
2bd2ad64 1461 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
a4fc5ed6 1462
2bd2ad64
DV		 1463 if (is_cpu_edp(intel_dp))
1464 ironlake_edp_pll_on(intel_dp);
a4fc5ed6
KP		 1465}
1466
1467/*
df0c237d
JB		 1468 * Native read with retry for link status and receiver capability reads for
1469 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1470 */
1471static bool
df0c237d
JB		 1472intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1473 uint8_t *recv, int recv_bytes)
a4fc5ed6 1474{
61da5fab
JB		 1475 int ret, i;
1476
df0c237d
JB		 1477 /*
1478 * Sinks are *supposed* to come up within 1ms from an off state,
1479 * but we're also supposed to retry 3 times per the spec.
1480 */
61da5fab 1481 for (i = 0; i < 3; i++) {
df0c237d
JB		 1482 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1483 recv_bytes);
1484 if (ret == recv_bytes)
61da5fab
JB		 1485 return true;
1486 msleep(1);
1487 }
a4fc5ed6 1488
61da5fab 1489 return false;
a4fc5ed6
KP		 1490}
1491
1492/*
1493 * Fetch AUX CH registers 0x202 - 0x207 which contain
1494 * link status information
1495 */
1496static bool
93f62dad 1497intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1498{
df0c237d
JB		 1499 return intel_dp_aux_native_read_retry(intel_dp,
1500 DP_LANE0_1_STATUS,
93f62dad 1501 link_status,
df0c237d 1502 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1503}
1504
a4fc5ed6
KP		 1505#if 0
1506static char *voltage_names[] = {
1507 "0.4V", "0.6V", "0.8V", "1.2V"
1508};
1509static char *pre_emph_names[] = {
1510 "0dB", "3.5dB", "6dB", "9.5dB"
1511};
1512static char *link_train_names[] = {
1513 "pattern 1", "pattern 2", "idle", "off"
1514};
1515#endif
1516
1517/*
1518 * These are source-specific values; current Intel hardware supports
1519 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1520 */
a4fc5ed6
KP		 1521
1522static uint8_t
1a2eb460 1523intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1524{
30add22d 1525 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1a2eb460
KP		 1526
1527 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1528 return DP_TRAIN_VOLTAGE_SWING_800;
1529 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1530 return DP_TRAIN_VOLTAGE_SWING_1200;
1531 else
1532 return DP_TRAIN_VOLTAGE_SWING_800;
1533}
1534
1535static uint8_t
1536intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1537{
30add22d 1538 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1a2eb460 1539
d6c0d722
PZ		 1540 if (IS_HASWELL(dev)) {
1541 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1542 case DP_TRAIN_VOLTAGE_SWING_400:
1543 return DP_TRAIN_PRE_EMPHASIS_9_5;
1544 case DP_TRAIN_VOLTAGE_SWING_600:
1545 return DP_TRAIN_PRE_EMPHASIS_6;
1546 case DP_TRAIN_VOLTAGE_SWING_800:
1547 return DP_TRAIN_PRE_EMPHASIS_3_5;
1548 case DP_TRAIN_VOLTAGE_SWING_1200:
1549 default:
1550 return DP_TRAIN_PRE_EMPHASIS_0;
1551 }
1552 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1553 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1554 case DP_TRAIN_VOLTAGE_SWING_400:
1555 return DP_TRAIN_PRE_EMPHASIS_6;
1556 case DP_TRAIN_VOLTAGE_SWING_600:
1557 case DP_TRAIN_VOLTAGE_SWING_800:
1558 return DP_TRAIN_PRE_EMPHASIS_3_5;
1559 default:
1560 return DP_TRAIN_PRE_EMPHASIS_0;
1561 }
1562 } else {
1563 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1564 case DP_TRAIN_VOLTAGE_SWING_400:
1565 return DP_TRAIN_PRE_EMPHASIS_6;
1566 case DP_TRAIN_VOLTAGE_SWING_600:
1567 return DP_TRAIN_PRE_EMPHASIS_6;
1568 case DP_TRAIN_VOLTAGE_SWING_800:
1569 return DP_TRAIN_PRE_EMPHASIS_3_5;
1570 case DP_TRAIN_VOLTAGE_SWING_1200:
1571 default:
1572 return DP_TRAIN_PRE_EMPHASIS_0;
1573 }
a4fc5ed6
KP		 1574 }
1575}
1576
1577static void
93f62dad 1578intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1579{
1580 uint8_t v = 0;
1581 uint8_t p = 0;
1582 int lane;
1a2eb460
KP		 1583 uint8_t voltage_max;
1584 uint8_t preemph_max;
a4fc5ed6 1585
33a34e4e 1586 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 1587 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1588 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 1589
1590 if (this_v > v)
1591 v = this_v;
1592 if (this_p > p)
1593 p = this_p;
1594 }
1595
1a2eb460 1596 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1597 if (v >= voltage_max)
1598 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1599
1a2eb460
KP		 1600 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1601 if (p >= preemph_max)
1602 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1603
1604 for (lane = 0; lane < 4; lane++)
33a34e4e 1605 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1606}
1607
1608static uint32_t
f0a3424e 1609intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 1610{
3cf2efb1 1611 uint32_t signal_levels = 0;
a4fc5ed6 1612
3cf2efb1 1613 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1614 case DP_TRAIN_VOLTAGE_SWING_400:
1615 default:
1616 signal_levels |= DP_VOLTAGE_0_4;
1617 break;
1618 case DP_TRAIN_VOLTAGE_SWING_600:
1619 signal_levels |= DP_VOLTAGE_0_6;
1620 break;
1621 case DP_TRAIN_VOLTAGE_SWING_800:
1622 signal_levels |= DP_VOLTAGE_0_8;
1623 break;
1624 case DP_TRAIN_VOLTAGE_SWING_1200:
1625 signal_levels |= DP_VOLTAGE_1_2;
1626 break;
1627 }
3cf2efb1 1628 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1629 case DP_TRAIN_PRE_EMPHASIS_0:
1630 default:
1631 signal_levels |= DP_PRE_EMPHASIS_0;
1632 break;
1633 case DP_TRAIN_PRE_EMPHASIS_3_5:
1634 signal_levels |= DP_PRE_EMPHASIS_3_5;
1635 break;
1636 case DP_TRAIN_PRE_EMPHASIS_6:
1637 signal_levels |= DP_PRE_EMPHASIS_6;
1638 break;
1639 case DP_TRAIN_PRE_EMPHASIS_9_5:
1640 signal_levels |= DP_PRE_EMPHASIS_9_5;
1641 break;
1642 }
1643 return signal_levels;
1644}
1645
e3421a18
ZW		 1646/* Gen6's DP voltage swing and pre-emphasis control */
1647static uint32_t
1648intel_gen6_edp_signal_levels(uint8_t train_set)
1649{
3c5a62b5
YL		 1650 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1651 DP_TRAIN_PRE_EMPHASIS_MASK);
1652 switch (signal_levels) {
e3421a18 1653 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1654 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1655 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1656 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1657 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1658 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1659 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1660 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1661 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1662 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1663 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1664 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1665 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1666 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1667 default:
3c5a62b5
YL		 1668 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1669 "0x%x\n", signal_levels);
1670 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1671 }
1672}
1673
1a2eb460
KP		 1674/* Gen7's DP voltage swing and pre-emphasis control */
1675static uint32_t
1676intel_gen7_edp_signal_levels(uint8_t train_set)
1677{
1678 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1679 DP_TRAIN_PRE_EMPHASIS_MASK);
1680 switch (signal_levels) {
1681 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1682 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1683 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1684 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1685 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1686 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1687
1688 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1689 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1690 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1691 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1692
1693 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1694 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1695 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1696 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1697
1698 default:
1699 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1700 "0x%x\n", signal_levels);
1701 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1702 }
1703}
1704
d6c0d722
PZ		 1705/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1706static uint32_t
f0a3424e 1707intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 1708{
d6c0d722
PZ		 1709 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1710 DP_TRAIN_PRE_EMPHASIS_MASK);
1711 switch (signal_levels) {
1712 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1713 return DDI_BUF_EMP_400MV_0DB_HSW;
1714 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1715 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1716 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1717 return DDI_BUF_EMP_400MV_6DB_HSW;
1718 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1719 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 1720
d6c0d722
PZ		 1721 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1722 return DDI_BUF_EMP_600MV_0DB_HSW;
1723 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1724 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1725 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1726 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 1727
d6c0d722
PZ		 1728 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1729 return DDI_BUF_EMP_800MV_0DB_HSW;
1730 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1731 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1732 default:
1733 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1734 "0x%x\n", signal_levels);
1735 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 1736 }
a4fc5ed6
KP		 1737}
1738
f0a3424e
PZ		 1739/* Properly updates "DP" with the correct signal levels. */
1740static void
1741intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1742{
1743 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1744 struct drm_device *dev = intel_dig_port->base.base.dev;
1745 uint32_t signal_levels, mask;
1746 uint8_t train_set = intel_dp->train_set[0];
1747
1748 if (IS_HASWELL(dev)) {
1749 signal_levels = intel_hsw_signal_levels(train_set);
1750 mask = DDI_BUF_EMP_MASK;
1751 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1752 signal_levels = intel_gen7_edp_signal_levels(train_set);
1753 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1754 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1755 signal_levels = intel_gen6_edp_signal_levels(train_set);
1756 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1757 } else {
1758 signal_levels = intel_gen4_signal_levels(train_set);
1759 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1760 }
1761
1762 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1763
1764 *DP = (*DP & ~mask) | signal_levels;
1765}
1766
a4fc5ed6 1767static bool
ea5b213a 1768intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1769 uint32_t dp_reg_value,
58e10eb9 1770 uint8_t dp_train_pat)
a4fc5ed6 1771{
174edf1f
PZ		 1772 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1773 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 1774 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 1775 enum port port = intel_dig_port->port;
a4fc5ed6 1776 int ret;
d6c0d722 1777 uint32_t temp;
a4fc5ed6 1778
d6c0d722 1779 if (IS_HASWELL(dev)) {
174edf1f 1780 temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 1781
1782 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1783 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1784 else
1785 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1786
1787 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1788 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1789 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722 1790
10aa17c8
PZ		 1791 if (port != PORT_A) {
1792 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1793 I915_WRITE(DP_TP_CTL(port), temp);
1794
1795 if (wait_for((I915_READ(DP_TP_STATUS(port)) &
1796 DP_TP_STATUS_IDLE_DONE), 1))
1797 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1798
1799 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1800 }
d6c0d722 1801
d6c0d722
PZ		 1802 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1803
1804 break;
1805 case DP_TRAINING_PATTERN_1:
1806 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1807 break;
1808 case DP_TRAINING_PATTERN_2:
1809 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1810 break;
1811 case DP_TRAINING_PATTERN_3:
1812 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1813 break;
1814 }
174edf1f 1815 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722
PZ		 1816
1817 } else if (HAS_PCH_CPT(dev) &&
1818 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
47ea7542
PZ		 1819 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1820
1821 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1822 case DP_TRAINING_PATTERN_DISABLE:
1823 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1824 break;
1825 case DP_TRAINING_PATTERN_1:
1826 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1827 break;
1828 case DP_TRAINING_PATTERN_2:
1829 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1830 break;
1831 case DP_TRAINING_PATTERN_3:
1832 DRM_ERROR("DP training pattern 3 not supported\n");
1833 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1834 break;
1835 }
1836
1837 } else {
1838 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1839
1840 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1841 case DP_TRAINING_PATTERN_DISABLE:
1842 dp_reg_value |= DP_LINK_TRAIN_OFF;
1843 break;
1844 case DP_TRAINING_PATTERN_1:
1845 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1846 break;
1847 case DP_TRAINING_PATTERN_2:
1848 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1849 break;
1850 case DP_TRAINING_PATTERN_3:
1851 DRM_ERROR("DP training pattern 3 not supported\n");
1852 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1853 break;
1854 }
1855 }
1856
ea5b213a
CW		 1857 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1858 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1859
ea5b213a 1860 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1861 DP_TRAINING_PATTERN_SET,
1862 dp_train_pat);
1863
47ea7542
PZ		 1864 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1865 DP_TRAINING_PATTERN_DISABLE) {
1866 ret = intel_dp_aux_native_write(intel_dp,
1867 DP_TRAINING_LANE0_SET,
1868 intel_dp->train_set,
1869 intel_dp->lane_count);
1870 if (ret != intel_dp->lane_count)
1871 return false;
1872 }
a4fc5ed6
KP		 1873
1874 return true;
1875}
1876
33a34e4e 1877/* Enable corresponding port and start training pattern 1 */
c19b0669 1878void
33a34e4e 1879intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1880{
da63a9f2 1881 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 1882 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 1883 int i;
1884 uint8_t voltage;
1885 bool clock_recovery = false;
cdb0e95b 1886 int voltage_tries, loop_tries;
ea5b213a 1887 uint32_t DP = intel_dp->DP;
a4fc5ed6 1888
affa9354 1889 if (HAS_DDI(dev))
c19b0669
PZ		 1890 intel_ddi_prepare_link_retrain(encoder);
1891
3cf2efb1
CW		 1892 /* Write the link configuration data */
1893 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1894 intel_dp->link_configuration,
1895 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1896
1897 DP |= DP_PORT_EN;
1a2eb460 1898
33a34e4e 1899 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 1900 voltage = 0xff;
cdb0e95b
KP		 1901 voltage_tries = 0;
1902 loop_tries = 0;
a4fc5ed6
KP		 1903 clock_recovery = false;
1904 for (;;) {
33a34e4e 1905 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 1906 uint8_t link_status[DP_LINK_STATUS_SIZE];
f0a3424e
PZ		 1907
1908 intel_dp_set_signal_levels(intel_dp, &DP);
a4fc5ed6 1909
a7c9655f 1910 /* Set training pattern 1 */
47ea7542 1911 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1912 DP_TRAINING_PATTERN_1 |
1913 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 1914 break;
a4fc5ed6 1915
a7c9655f 1916 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 1917 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1918 DRM_ERROR("failed to get link status\n");
a4fc5ed6 1919 break;
93f62dad 1920 }
a4fc5ed6 1921
01916270 1922 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 1923 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 1924 clock_recovery = true;
1925 break;
1926 }
1927
1928 /* Check to see if we've tried the max voltage */
1929 for (i = 0; i < intel_dp->lane_count; i++)
1930 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 1931 break;
0d710688 1932 if (i == intel_dp->lane_count && voltage_tries == 5) {
b06fbda3
DV		 1933 ++loop_tries;
1934 if (loop_tries == 5) {
cdb0e95b
KP		 1935 DRM_DEBUG_KMS("too many full retries, give up\n");
1936 break;
1937 }
1938 memset(intel_dp->train_set, 0, 4);
1939 voltage_tries = 0;
1940 continue;
1941 }
a4fc5ed6 1942
3cf2efb1 1943 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 1944 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 1945 ++voltage_tries;
b06fbda3
DV		 1946 if (voltage_tries == 5) {
1947 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1948 break;
1949 }
1950 } else
1951 voltage_tries = 0;
1952 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 1953
3cf2efb1 1954 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1955 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 1956 }
1957
33a34e4e
JB		 1958 intel_dp->DP = DP;
1959}
1960
c19b0669 1961void
33a34e4e
JB		 1962intel_dp_complete_link_train(struct intel_dp *intel_dp)
1963{
33a34e4e 1964 bool channel_eq = false;
37f80975 1965 int tries, cr_tries;
33a34e4e
JB		 1966 uint32_t DP = intel_dp->DP;
1967
a4fc5ed6
KP		 1968 /* channel equalization */
1969 tries = 0;
37f80975 1970 cr_tries = 0;
a4fc5ed6
KP		 1971 channel_eq = false;
1972 for (;;) {
93f62dad 1973 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1974
37f80975
JB		 1975 if (cr_tries > 5) {
1976 DRM_ERROR("failed to train DP, aborting\n");
1977 intel_dp_link_down(intel_dp);
1978 break;
1979 }
1980
f0a3424e 1981 intel_dp_set_signal_levels(intel_dp, &DP);
e3421a18 1982
a4fc5ed6 1983 /* channel eq pattern */
47ea7542 1984 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1985 DP_TRAINING_PATTERN_2 |
1986 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 1987 break;
1988
a7c9655f 1989 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
93f62dad 1990 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 1991 break;
a4fc5ed6 1992
37f80975 1993 /* Make sure clock is still ok */
01916270 1994 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 1995 intel_dp_start_link_train(intel_dp);
1996 cr_tries++;
1997 continue;
1998 }
1999
1ffdff13 2000 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2001 channel_eq = true;
2002 break;
2003 }
a4fc5ed6 2004
37f80975
JB		 2005 /* Try 5 times, then try clock recovery if that fails */
2006 if (tries > 5) {
2007 intel_dp_link_down(intel_dp);
2008 intel_dp_start_link_train(intel_dp);
2009 tries = 0;
2010 cr_tries++;
2011 continue;
2012 }
a4fc5ed6 2013
3cf2efb1 2014 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2015 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 2016 ++tries;
869184a6 2017 }
3cf2efb1 2018
d6c0d722
PZ		 2019 if (channel_eq)
2020 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
2021
47ea7542 2022 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2023}
2024
2025static void
ea5b213a 2026intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2027{
da63a9f2
PZ		 2028 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2029 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2030 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2031 struct intel_crtc *intel_crtc =
2032 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2033 uint32_t DP = intel_dp->DP;
a4fc5ed6 2034
c19b0669
PZ		 2035 /*
2036 * DDI code has a strict mode set sequence and we should try to respect
2037 * it, otherwise we might hang the machine in many different ways. So we
2038 * really should be disabling the port only on a complete crtc_disable
2039 * sequence. This function is just called under two conditions on DDI
2040 * code:
2041 * - Link train failed while doing crtc_enable, and on this case we
2042 * really should respect the mode set sequence and wait for a
2043 * crtc_disable.
2044 * - Someone turned the monitor off and intel_dp_check_link_status
2045 * called us. We don't need to disable the whole port on this case, so
2046 * when someone turns the monitor on again,
2047 * intel_ddi_prepare_link_retrain will take care of redoing the link
2048 * train.
2049 */
affa9354 2050 if (HAS_DDI(dev))
c19b0669
PZ		 2051 return;
2052
0c33d8d7 2053 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2054 return;
2055
28c97730 2056 DRM_DEBUG_KMS("\n");
32f9d658 2057
1a2eb460 2058 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 2059 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2060 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2061 } else {
2062 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2063 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2064 }
fe255d00 2065 POSTING_READ(intel_dp->output_reg);
5eb08b69 2066
ab527efc
DV		 2067 /* We don't really know why we're doing this */
2068 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2069
493a7081 2070 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2071 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2072 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2073
5bddd17f
EA		 2074 /* Hardware workaround: leaving our transcoder select
2075 * set to transcoder B while it's off will prevent the
2076 * corresponding HDMI output on transcoder A.
2077 *
2078 * Combine this with another hardware workaround:
2079 * transcoder select bit can only be cleared while the
2080 * port is enabled.
2081 */
2082 DP &= ~DP_PIPEB_SELECT;
2083 I915_WRITE(intel_dp->output_reg, DP);
2084
2085 /* Changes to enable or select take place the vblank
2086 * after being written.
2087 */
ff50afe9
DV		 2088 if (WARN_ON(crtc == NULL)) {
2089 /* We should never try to disable a port without a crtc
2090 * attached. For paranoia keep the code around for a
2091 * bit. */
31acbcc4
CW		 2092 POSTING_READ(intel_dp->output_reg);
2093 msleep(50);
2094 } else
ab527efc 2095 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2096 }
2097
832afda6 2098 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2099 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2100 POSTING_READ(intel_dp->output_reg);
f01eca2e 2101 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2102}
2103
26d61aad
KP		 2104static bool
2105intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2106{
577c7a50
DL		 2107 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2108
92fd8fd1 2109 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2110 sizeof(intel_dp->dpcd)) == 0)
2111 return false; /* aux transfer failed */
92fd8fd1 2112
577c7a50
DL		 2113 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2114 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2115 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2116
edb39244
AJ		 2117 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2118 return false; /* DPCD not present */
2119
2120 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2121 DP_DWN_STRM_PORT_PRESENT))
2122 return true; /* native DP sink */
2123
2124 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2125 return true; /* no per-port downstream info */
2126
2127 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2128 intel_dp->downstream_ports,
2129 DP_MAX_DOWNSTREAM_PORTS) == 0)
2130 return false; /* downstream port status fetch failed */
2131
2132 return true;
92fd8fd1
KP		 2133}
2134
0d198328
AJ		 2135static void
2136intel_dp_probe_oui(struct intel_dp *intel_dp)
2137{
2138 u8 buf[3];
2139
2140 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2141 return;
2142
351cfc34
DV		 2143 ironlake_edp_panel_vdd_on(intel_dp);
2144
0d198328
AJ		 2145 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2146 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2147 buf[0], buf[1], buf[2]);
2148
2149 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2150 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2151 buf[0], buf[1], buf[2]);
351cfc34
DV		 2152
2153 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2154}
2155
a60f0e38
JB		 2156static bool
2157intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2158{
2159 int ret;
2160
2161 ret = intel_dp_aux_native_read_retry(intel_dp,
2162 DP_DEVICE_SERVICE_IRQ_VECTOR,
2163 sink_irq_vector, 1);
2164 if (!ret)
2165 return false;
2166
2167 return true;
2168}
2169
2170static void
2171intel_dp_handle_test_request(struct intel_dp *intel_dp)
2172{
2173 /* NAK by default */
9324cf7f 2174 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2175}
2176
a4fc5ed6
KP		 2177/*
2178 * According to DP spec
2179 * 5.1.2:
2180 * 1. Read DPCD
2181 * 2. Configure link according to Receiver Capabilities
2182 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2183 * 4. Check link status on receipt of hot-plug interrupt
2184 */
2185
00c09d70 2186void
ea5b213a 2187intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2188{
da63a9f2 2189 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2190 u8 sink_irq_vector;
93f62dad 2191 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2192
da63a9f2 2193 if (!intel_encoder->connectors_active)
d2b996ac 2194 return;
59cd09e1 2195
da63a9f2 2196 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2197 return;
2198
92fd8fd1 2199 /* Try to read receiver status if the link appears to be up */
93f62dad 2200 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2201 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2202 return;
2203 }
2204
92fd8fd1 2205 /* Now read the DPCD to see if it's actually running */
26d61aad 2206 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2207 intel_dp_link_down(intel_dp);
2208 return;
2209 }
2210
a60f0e38
JB		 2211 /* Try to read the source of the interrupt */
2212 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2213 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2214 /* Clear interrupt source */
2215 intel_dp_aux_native_write_1(intel_dp,
2216 DP_DEVICE_SERVICE_IRQ_VECTOR,
2217 sink_irq_vector);
2218
2219 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2220 intel_dp_handle_test_request(intel_dp);
2221 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2222 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2223 }
2224
1ffdff13 2225 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2226 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2227 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2228 intel_dp_start_link_train(intel_dp);
2229 intel_dp_complete_link_train(intel_dp);
2230 }
a4fc5ed6 2231}
a4fc5ed6 2232
caf9ab24 2233/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2234static enum drm_connector_status
26d61aad 2235intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2236{
caf9ab24
AJ		 2237 uint8_t *dpcd = intel_dp->dpcd;
2238 bool hpd;
2239 uint8_t type;
2240
2241 if (!intel_dp_get_dpcd(intel_dp))
2242 return connector_status_disconnected;
2243
2244 /* if there's no downstream port, we're done */
2245 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2246 return connector_status_connected;
caf9ab24
AJ		 2247
2248 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2249 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2250 if (hpd) {
23235177 2251 uint8_t reg;
caf9ab24 2252 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 2253 &reg, 1))
caf9ab24 2254 return connector_status_unknown;
23235177
AJ		 2255 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2256 : connector_status_disconnected;
caf9ab24
AJ		 2257 }
2258
2259 /* If no HPD, poke DDC gently */
2260 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2261 return connector_status_connected;
caf9ab24
AJ		 2262
2263 /* Well we tried, say unknown for unreliable port types */
2264 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2265 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2266 return connector_status_unknown;
2267
2268 /* Anything else is out of spec, warn and ignore */
2269 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2270 return connector_status_disconnected;
71ba9000
AJ		 2271}
2272
5eb08b69 2273static enum drm_connector_status
a9756bb5 2274ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2275{
30add22d 2276 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 2277 struct drm_i915_private *dev_priv = dev->dev_private;
2278 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 2279 enum drm_connector_status status;
2280
fe16d949
CW		 2281 /* Can't disconnect eDP, but you can close the lid... */
2282 if (is_edp(intel_dp)) {
30add22d 2283 status = intel_panel_detect(dev);
fe16d949
CW		 2284 if (status == connector_status_unknown)
2285 status = connector_status_connected;
2286 return status;
2287 }
01cb9ea6 2288
1b469639
DL		 2289 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2290 return connector_status_disconnected;
2291
26d61aad 2292 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2293}
2294
a4fc5ed6 2295static enum drm_connector_status
a9756bb5 2296g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2297{
30add22d 2298 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 2299 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 2300 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 2301 uint32_t bit;
5eb08b69 2302
34f2be46
VS		 2303 switch (intel_dig_port->port) {
2304 case PORT_B:
26739f12 2305 bit = PORTB_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2306 break;
34f2be46 2307 case PORT_C:
26739f12 2308 bit = PORTC_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2309 break;
34f2be46 2310 case PORT_D:
26739f12 2311 bit = PORTD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2312 break;
2313 default:
2314 return connector_status_unknown;
2315 }
2316
10f76a38 2317 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2318 return connector_status_disconnected;
2319
26d61aad 2320 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2321}
2322
8c241fef
KP		 2323static struct edid *
2324intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2325{
9cd300e0 2326 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 2327
9cd300e0
JN		 2328 /* use cached edid if we have one */
2329 if (intel_connector->edid) {
2330 struct edid *edid;
2331 int size;
2332
2333 /* invalid edid */
2334 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 2335 return NULL;
2336
9cd300e0 2337 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
d6f24d0f
JB		 2338 edid = kmalloc(size, GFP_KERNEL);
2339 if (!edid)
2340 return NULL;
2341
9cd300e0 2342 memcpy(edid, intel_connector->edid, size);
d6f24d0f
JB		 2343 return edid;
2344 }
8c241fef 2345
9cd300e0 2346 return drm_get_edid(connector, adapter);
8c241fef
KP		 2347}
2348
2349static int
2350intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2351{
9cd300e0 2352 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 2353
9cd300e0
JN		 2354 /* use cached edid if we have one */
2355 if (intel_connector->edid) {
2356 /* invalid edid */
2357 if (IS_ERR(intel_connector->edid))
2358 return 0;
2359
2360 return intel_connector_update_modes(connector,
2361 intel_connector->edid);
d6f24d0f
JB		 2362 }
2363
9cd300e0 2364 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2365}
2366
a9756bb5
ZW		 2367static enum drm_connector_status
2368intel_dp_detect(struct drm_connector *connector, bool force)
2369{
2370 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 2371 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2372 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 2373 struct drm_device *dev = connector->dev;
a9756bb5
ZW		 2374 enum drm_connector_status status;
2375 struct edid *edid = NULL;
2376
2377 intel_dp->has_audio = false;
2378
2379 if (HAS_PCH_SPLIT(dev))
2380 status = ironlake_dp_detect(intel_dp);
2381 else
2382 status = g4x_dp_detect(intel_dp);
1b9be9d0 2383
a9756bb5
ZW		 2384 if (status != connector_status_connected)
2385 return status;
2386
0d198328
AJ		 2387 intel_dp_probe_oui(intel_dp);
2388
c3e5f67b
DV		 2389 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2390 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2391 } else {
8c241fef 2392 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2393 if (edid) {
2394 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2395 kfree(edid);
2396 }
a9756bb5
ZW		 2397 }
2398
d63885da
PZ		 2399 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2400 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
a9756bb5 2401 return connector_status_connected;
a4fc5ed6
KP		 2402}
2403
2404static int intel_dp_get_modes(struct drm_connector *connector)
2405{
df0e9248 2406 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 2407 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 2408 struct drm_device *dev = connector->dev;
32f9d658 2409 int ret;
a4fc5ed6
KP		 2410
2411 /* We should parse the EDID data and find out if it has an audio sink
2412 */
2413
8c241fef 2414 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 2415 if (ret)
32f9d658
ZW		 2416 return ret;
2417
f8779fda 2418 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 2419 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 2420 struct drm_display_mode *mode;
dd06f90e
JN		 2421 mode = drm_mode_duplicate(dev,
2422 intel_connector->panel.fixed_mode);
f8779fda 2423 if (mode) {
32f9d658
ZW		 2424 drm_mode_probed_add(connector, mode);
2425 return 1;
2426 }
2427 }
2428 return 0;
a4fc5ed6
KP		 2429}
2430
1aad7ac0
CW		 2431static bool
2432intel_dp_detect_audio(struct drm_connector *connector)
2433{
2434 struct intel_dp *intel_dp = intel_attached_dp(connector);
2435 struct edid *edid;
2436 bool has_audio = false;
2437
8c241fef 2438 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2439 if (edid) {
2440 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2441 kfree(edid);
2442 }
2443
2444 return has_audio;
2445}
2446
f684960e
CW		 2447static int
2448intel_dp_set_property(struct drm_connector *connector,
2449 struct drm_property *property,
2450 uint64_t val)
2451{
e953fd7b 2452 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 2453 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 2454 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2455 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 2456 int ret;
2457
662595df 2458 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 2459 if (ret)
2460 return ret;
2461
3f43c48d 2462 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2463 int i = val;
2464 bool has_audio;
2465
2466 if (i == intel_dp->force_audio)
f684960e
CW		 2467 return 0;
2468
1aad7ac0 2469 intel_dp->force_audio = i;
f684960e 2470
c3e5f67b 2471 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2472 has_audio = intel_dp_detect_audio(connector);
2473 else
c3e5f67b 2474 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2475
2476 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2477 return 0;
2478
1aad7ac0 2479 intel_dp->has_audio = has_audio;
f684960e
CW		 2480 goto done;
2481 }
2482
e953fd7b 2483 if (property == dev_priv->broadcast_rgb_property) {
55bc60db
VS		 2484 switch (val) {
2485 case INTEL_BROADCAST_RGB_AUTO:
2486 intel_dp->color_range_auto = true;
2487 break;
2488 case INTEL_BROADCAST_RGB_FULL:
2489 intel_dp->color_range_auto = false;
2490 intel_dp->color_range = 0;
2491 break;
2492 case INTEL_BROADCAST_RGB_LIMITED:
2493 intel_dp->color_range_auto = false;
2494 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2495 break;
2496 default:
2497 return -EINVAL;
2498 }
e953fd7b
CW		 2499 goto done;
2500 }
2501
53b41837
YN		 2502 if (is_edp(intel_dp) &&
2503 property == connector->dev->mode_config.scaling_mode_property) {
2504 if (val == DRM_MODE_SCALE_NONE) {
2505 DRM_DEBUG_KMS("no scaling not supported\n");
2506 return -EINVAL;
2507 }
2508
2509 if (intel_connector->panel.fitting_mode == val) {
2510 /* the eDP scaling property is not changed */
2511 return 0;
2512 }
2513 intel_connector->panel.fitting_mode = val;
2514
2515 goto done;
2516 }
2517
f684960e
CW		 2518 return -EINVAL;
2519
2520done:
c0c36b94
CW		 2521 if (intel_encoder->base.crtc)
2522 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 2523
2524 return 0;
2525}
2526
a4fc5ed6 2527static void
0206e353 2528intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2529{
aaa6fd2a 2530 struct drm_device *dev = connector->dev;
be3cd5e3 2531 struct intel_dp *intel_dp = intel_attached_dp(connector);
1d508706 2532 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 2533
9cd300e0
JN		 2534 if (!IS_ERR_OR_NULL(intel_connector->edid))
2535 kfree(intel_connector->edid);
2536
1d508706 2537 if (is_edp(intel_dp)) {
aaa6fd2a 2538 intel_panel_destroy_backlight(dev);
1d508706
JN		 2539 intel_panel_fini(&intel_connector->panel);
2540 }
aaa6fd2a 2541
a4fc5ed6
KP		 2542 drm_sysfs_connector_remove(connector);
2543 drm_connector_cleanup(connector);
55f78c43 2544 kfree(connector);
a4fc5ed6
KP		 2545}
2546
00c09d70 2547void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 2548{
da63a9f2
PZ		 2549 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2550 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927
DV		 2551
2552 i2c_del_adapter(&intel_dp->adapter);
2553 drm_encoder_cleanup(encoder);
bd943159
KP		 2554 if (is_edp(intel_dp)) {
2555 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2556 ironlake_panel_vdd_off_sync(intel_dp);
2557 }
da63a9f2 2558 kfree(intel_dig_port);
24d05927
DV		 2559}
2560
a4fc5ed6 2561static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 2562 .mode_fixup = intel_dp_mode_fixup,
a4fc5ed6 2563 .mode_set = intel_dp_mode_set,
a4fc5ed6
KP		 2564};
2565
2566static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 2567 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 2568 .detect = intel_dp_detect,
2569 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2570 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2571 .destroy = intel_dp_destroy,
2572};
2573
2574static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2575 .get_modes = intel_dp_get_modes,
2576 .mode_valid = intel_dp_mode_valid,
df0e9248 2577 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2578};
2579
a4fc5ed6 2580static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2581 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2582};
2583
995b6762 2584static void
21d40d37 2585intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2586{
fa90ecef 2587 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 2588
885a5014 2589 intel_dp_check_link_status(intel_dp);
c8110e52 2590}
6207937d 2591
e3421a18
ZW		 2592/* Return which DP Port should be selected for Transcoder DP control */
2593int
0206e353 2594intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2595{
2596 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 2597 struct intel_encoder *intel_encoder;
2598 struct intel_dp *intel_dp;
e3421a18 2599
fa90ecef
PZ		 2600 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2601 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 2602
fa90ecef
PZ		 2603 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2604 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 2605 return intel_dp->output_reg;
e3421a18 2606 }
ea5b213a 2607
e3421a18
ZW		 2608 return -1;
2609}
2610
36e83a18 2611/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2612bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2613{
2614 struct drm_i915_private *dev_priv = dev->dev_private;
2615 struct child_device_config *p_child;
2616 int i;
2617
2618 if (!dev_priv->child_dev_num)
2619 return false;
2620
2621 for (i = 0; i < dev_priv->child_dev_num; i++) {
2622 p_child = dev_priv->child_dev + i;
2623
2624 if (p_child->dvo_port == PORT_IDPD &&
2625 p_child->device_type == DEVICE_TYPE_eDP)
2626 return true;
2627 }
2628 return false;
2629}
2630
f684960e
CW		 2631static void
2632intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2633{
53b41837
YN		 2634 struct intel_connector *intel_connector = to_intel_connector(connector);
2635
3f43c48d 2636 intel_attach_force_audio_property(connector);
e953fd7b 2637 intel_attach_broadcast_rgb_property(connector);
55bc60db 2638 intel_dp->color_range_auto = true;
53b41837
YN		 2639
2640 if (is_edp(intel_dp)) {
2641 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 2642 drm_object_attach_property(
2643 &connector->base,
53b41837 2644 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 2645 DRM_MODE_SCALE_ASPECT);
2646 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 2647 }
f684960e
CW		 2648}
2649
67a54566
DV		 2650static void
2651intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 2652 struct intel_dp *intel_dp,
2653 struct edp_power_seq *out)
67a54566
DV		 2654{
2655 struct drm_i915_private *dev_priv = dev->dev_private;
2656 struct edp_power_seq cur, vbt, spec, final;
2657 u32 pp_on, pp_off, pp_div, pp;
2658
2659 /* Workaround: Need to write PP_CONTROL with the unlock key as
2660 * the very first thing. */
2661 pp = ironlake_get_pp_control(dev_priv);
2662 I915_WRITE(PCH_PP_CONTROL, pp);
2663
2664 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2665 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2666 pp_div = I915_READ(PCH_PP_DIVISOR);
2667
2668 /* Pull timing values out of registers */
2669 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2670 PANEL_POWER_UP_DELAY_SHIFT;
2671
2672 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2673 PANEL_LIGHT_ON_DELAY_SHIFT;
2674
2675 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2676 PANEL_LIGHT_OFF_DELAY_SHIFT;
2677
2678 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2679 PANEL_POWER_DOWN_DELAY_SHIFT;
2680
2681 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2682 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2683
2684 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2685 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2686
2687 vbt = dev_priv->edp.pps;
2688
2689 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2690 * our hw here, which are all in 100usec. */
2691 spec.t1_t3 = 210 * 10;
2692 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2693 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2694 spec.t10 = 500 * 10;
2695 /* This one is special and actually in units of 100ms, but zero
2696 * based in the hw (so we need to add 100 ms). But the sw vbt
2697 * table multiplies it with 1000 to make it in units of 100usec,
2698 * too. */
2699 spec.t11_t12 = (510 + 100) * 10;
2700
2701 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2702 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2703
2704 /* Use the max of the register settings and vbt. If both are
2705 * unset, fall back to the spec limits. */
2706#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2707 spec.field : \
2708 max(cur.field, vbt.field))
2709 assign_final(t1_t3);
2710 assign_final(t8);
2711 assign_final(t9);
2712 assign_final(t10);
2713 assign_final(t11_t12);
2714#undef assign_final
2715
2716#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2717 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2718 intel_dp->backlight_on_delay = get_delay(t8);
2719 intel_dp->backlight_off_delay = get_delay(t9);
2720 intel_dp->panel_power_down_delay = get_delay(t10);
2721 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2722#undef get_delay
2723
f30d26e4
JN		 2724 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2725 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2726 intel_dp->panel_power_cycle_delay);
2727
2728 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2729 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2730
2731 if (out)
2732 *out = final;
2733}
2734
2735static void
2736intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2737 struct intel_dp *intel_dp,
2738 struct edp_power_seq *seq)
2739{
2740 struct drm_i915_private *dev_priv = dev->dev_private;
2741 u32 pp_on, pp_off, pp_div;
2742
67a54566 2743 /* And finally store the new values in the power sequencer. */
f30d26e4
JN		 2744 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2745 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2746 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2747 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 2748 /* Compute the divisor for the pp clock, simply match the Bspec
2749 * formula. */
2750 pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
2751 << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 2752 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 2753 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2754
2755 /* Haswell doesn't have any port selection bits for the panel
2756 * power sequencer any more. */
2757 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2758 if (is_cpu_edp(intel_dp))
2759 pp_on |= PANEL_POWER_PORT_DP_A;
2760 else
2761 pp_on |= PANEL_POWER_PORT_DP_D;
2762 }
2763
2764 I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
2765 I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
2766 I915_WRITE(PCH_PP_DIVISOR, pp_div);
2767
67a54566
DV		 2768 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2769 I915_READ(PCH_PP_ON_DELAYS),
2770 I915_READ(PCH_PP_OFF_DELAYS),
2771 I915_READ(PCH_PP_DIVISOR));
f684960e
CW		 2772}
2773
a4fc5ed6 2774void
f0fec3f2
PZ		 2775intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2776 struct intel_connector *intel_connector)
a4fc5ed6 2777{
f0fec3f2
PZ		 2778 struct drm_connector *connector = &intel_connector->base;
2779 struct intel_dp *intel_dp = &intel_dig_port->dp;
2780 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2781 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 2782 struct drm_i915_private *dev_priv = dev->dev_private;
f8779fda 2783 struct drm_display_mode *fixed_mode = NULL;
f30d26e4 2784 struct edp_power_seq power_seq = { 0 };
174edf1f 2785 enum port port = intel_dig_port->port;
5eb08b69 2786 const char *name = NULL;
b329530c 2787 int type;
a4fc5ed6 2788
0767935e
DV		 2789 /* Preserve the current hw state. */
2790 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 2791 intel_dp->attached_connector = intel_connector;
3d3dc149 2792
f0fec3f2 2793 if (HAS_PCH_SPLIT(dev) && port == PORT_D)
b329530c 2794 if (intel_dpd_is_edp(dev))
ea5b213a 2795 intel_dp->is_pch_edp = true;
b329530c 2796
19c03924
GB		 2797 /*
2798 * FIXME : We need to initialize built-in panels before external panels.
2799 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2800 */
f0fec3f2 2801 if (IS_VALLEYVIEW(dev) && port == PORT_C) {
19c03924
GB		 2802 type = DRM_MODE_CONNECTOR_eDP;
2803 intel_encoder->type = INTEL_OUTPUT_EDP;
f0fec3f2 2804 } else if (port == PORT_A || is_pch_edp(intel_dp)) {
b329530c
AJ		 2805 type = DRM_MODE_CONNECTOR_eDP;
2806 intel_encoder->type = INTEL_OUTPUT_EDP;
2807 } else {
00c09d70
PZ		 2808 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
2809 * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
2810 * rewrite it.
2811 */
b329530c 2812 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c
AJ		 2813 }
2814
b329530c 2815 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 2816 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2817
eb1f8e4f 2818 connector->polled = DRM_CONNECTOR_POLL_HPD;
a4fc5ed6
KP		 2819 connector->interlace_allowed = true;
2820 connector->doublescan_allowed = 0;
2821
f0fec3f2
PZ		 2822 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2823 ironlake_panel_vdd_work);
a4fc5ed6 2824
df0e9248 2825 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 2826 drm_sysfs_connector_add(connector);
2827
affa9354 2828 if (HAS_DDI(dev))
bcbc889b
PZ		 2829 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2830 else
2831 intel_connector->get_hw_state = intel_connector_get_hw_state;
2832
e8cb4558 2833
a4fc5ed6 2834 /* Set up the DDC bus. */
ab9d7c30
PZ		 2835 switch (port) {
2836 case PORT_A:
2837 name = "DPDDC-A";
2838 break;
2839 case PORT_B:
26739f12 2840 dev_priv->hotplug_supported_mask |= PORTB_HOTPLUG_INT_STATUS;
ab9d7c30
PZ		 2841 name = "DPDDC-B";
2842 break;
2843 case PORT_C:
26739f12 2844 dev_priv->hotplug_supported_mask |= PORTC_HOTPLUG_INT_STATUS;
ab9d7c30
PZ		 2845 name = "DPDDC-C";
2846 break;
2847 case PORT_D:
26739f12 2848 dev_priv->hotplug_supported_mask |= PORTD_HOTPLUG_INT_STATUS;
ab9d7c30
PZ		 2849 name = "DPDDC-D";
2850 break;
2851 default:
2852 WARN(1, "Invalid port %c\n", port_name(port));
2853 break;
5eb08b69
ZW		 2854 }
2855
67a54566 2856 if (is_edp(intel_dp))
f30d26e4 2857 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
c1f05264
DA		 2858
2859 intel_dp_i2c_init(intel_dp, intel_connector, name);
2860
67a54566 2861 /* Cache DPCD and EDID for edp. */
c1f05264
DA		 2862 if (is_edp(intel_dp)) {
2863 bool ret;
f8779fda 2864 struct drm_display_mode *scan;
c1f05264 2865 struct edid *edid;
5d613501
JB		 2866
2867 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 2868 ret = intel_dp_get_dpcd(intel_dp);
bd943159 2869 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 2870
59f3e272 2871 if (ret) {
7183dc29
JB		 2872 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2873 dev_priv->no_aux_handshake =
2874 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 2875 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2876 } else {
3d3dc149 2877 /* if this fails, presume the device is a ghost */
48898b03 2878 DRM_INFO("failed to retrieve link info, disabling eDP\n");
fa90ecef
PZ		 2879 intel_dp_encoder_destroy(&intel_encoder->base);
2880 intel_dp_destroy(connector);
3d3dc149 2881 return;
89667383 2882 }
89667383 2883
f30d26e4
JN		 2884 /* We now know it's not a ghost, init power sequence regs. */
2885 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2886 &power_seq);
2887
d6f24d0f
JB		 2888 ironlake_edp_panel_vdd_on(intel_dp);
2889 edid = drm_get_edid(connector, &intel_dp->adapter);
2890 if (edid) {
9cd300e0
JN		 2891 if (drm_add_edid_modes(connector, edid)) {
2892 drm_mode_connector_update_edid_property(connector, edid);
2893 drm_edid_to_eld(connector, edid);
2894 } else {
2895 kfree(edid);
2896 edid = ERR_PTR(-EINVAL);
2897 }
2898 } else {
2899 edid = ERR_PTR(-ENOENT);
d6f24d0f 2900 }
9cd300e0 2901 intel_connector->edid = edid;
f8779fda
JN		 2902
2903 /* prefer fixed mode from EDID if available */
2904 list_for_each_entry(scan, &connector->probed_modes, head) {
2905 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2906 fixed_mode = drm_mode_duplicate(dev, scan);
2907 break;
2908 }
d6f24d0f 2909 }
f8779fda
JN		 2910
2911 /* fallback to VBT if available for eDP */
2912 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2913 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2914 if (fixed_mode)
2915 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2916 }
f8779fda 2917
d6f24d0f
JB		 2918 ironlake_edp_panel_vdd_off(intel_dp, false);
2919 }
552fb0b7 2920
4d926461 2921 if (is_edp(intel_dp)) {
dd06f90e 2922 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 2923 intel_panel_setup_backlight(connector);
32f9d658
ZW		 2924 }
2925
f684960e
CW		 2926 intel_dp_add_properties(intel_dp, connector);
2927
a4fc5ed6
KP		 2928 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2929 * 0xd. Failure to do so will result in spurious interrupts being
2930 * generated on the port when a cable is not attached.
2931 */
2932 if (IS_G4X(dev) && !IS_GM45(dev)) {
2933 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2934 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2935 }
2936}
f0fec3f2
PZ		 2937
2938void
2939intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2940{
2941 struct intel_digital_port *intel_dig_port;
2942 struct intel_encoder *intel_encoder;
2943 struct drm_encoder *encoder;
2944 struct intel_connector *intel_connector;
2945
2946 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
2947 if (!intel_dig_port)
2948 return;
2949
2950 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2951 if (!intel_connector) {
2952 kfree(intel_dig_port);
2953 return;
2954 }
2955
2956 intel_encoder = &intel_dig_port->base;
2957 encoder = &intel_encoder->base;
2958
2959 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2960 DRM_MODE_ENCODER_TMDS);
00c09d70 2961 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
f0fec3f2 2962
00c09d70
PZ		 2963 intel_encoder->enable = intel_enable_dp;
2964 intel_encoder->pre_enable = intel_pre_enable_dp;
2965 intel_encoder->disable = intel_disable_dp;
2966 intel_encoder->post_disable = intel_post_disable_dp;
2967 intel_encoder->get_hw_state = intel_dp_get_hw_state;
f0fec3f2 2968
174edf1f 2969 intel_dig_port->port = port;
f0fec3f2
PZ		 2970 intel_dig_port->dp.output_reg = output_reg;
2971
00c09d70 2972 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 2973 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2974 intel_encoder->cloneable = false;
2975 intel_encoder->hot_plug = intel_dp_hot_plug;
2976
2977 intel_dp_init_connector(intel_dig_port, intel_connector);
2978}
Linux kernel - Deliverables
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