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drm/i915: add DP support to intel_ddi_mode_set
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
a4fc5ed6
KP		 31#include "drmP.h"
32#include "drm.h"
33#include "drm_crtc.h"
34#include "drm_crtc_helper.h"
d6f24d0f 35#include "drm_edid.h"
a4fc5ed6
KP		 36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
a4fc5ed6 39
b091cd92 40#define DP_RECEIVER_CAP_SIZE 0xf
a4fc5ed6
KP		 41#define DP_LINK_STATUS_SIZE 6
42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
cfcb0fc9
JB		 44/**
45 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
46 * @intel_dp: DP struct
47 *
48 * If a CPU or PCH DP output is attached to an eDP panel, this function
49 * will return true, and false otherwise.
50 */
51static bool is_edp(struct intel_dp *intel_dp)
52{
53 return intel_dp->base.type == INTEL_OUTPUT_EDP;
54}
55
56/**
57 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
58 * @intel_dp: DP struct
59 *
60 * Returns true if the given DP struct corresponds to a PCH DP port attached
61 * to an eDP panel, false otherwise. Helpful for determining whether we
62 * may need FDI resources for a given DP output or not.
63 */
64static bool is_pch_edp(struct intel_dp *intel_dp)
65{
66 return intel_dp->is_pch_edp;
67}
68
1c95822a
AJ		 69/**
70 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
71 * @intel_dp: DP struct
72 *
73 * Returns true if the given DP struct corresponds to a CPU eDP port.
74 */
75static bool is_cpu_edp(struct intel_dp *intel_dp)
76{
77 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
78}
79
df0e9248
CW		 80static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
81{
82 return container_of(intel_attached_encoder(connector),
83 struct intel_dp, base);
84}
85
814948ad
JB		 86/**
87 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
88 * @encoder: DRM encoder
89 *
90 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
91 * by intel_display.c.
92 */
93bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
94{
95 struct intel_dp *intel_dp;
96
97 if (!encoder)
98 return false;
99
100 intel_dp = enc_to_intel_dp(encoder);
101
102 return is_pch_edp(intel_dp);
103}
104
33a34e4e
JB		 105static void intel_dp_start_link_train(struct intel_dp *intel_dp);
106static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
ea5b213a 107static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 108
32f9d658 109void
0206e353 110intel_edp_link_config(struct intel_encoder *intel_encoder,
ea5b213a 111 int *lane_num, int *link_bw)
32f9d658 112{
ea5b213a 113 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
32f9d658 114
ea5b213a
CW		 115 *lane_num = intel_dp->lane_count;
116 if (intel_dp->link_bw == DP_LINK_BW_1_62)
32f9d658 117 *link_bw = 162000;
ea5b213a 118 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
32f9d658
ZW		 119 *link_bw = 270000;
120}
121
94bf2ced
DV		 122int
123intel_edp_target_clock(struct intel_encoder *intel_encoder,
124 struct drm_display_mode *mode)
125{
126 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
127
128 if (intel_dp->panel_fixed_mode)
129 return intel_dp->panel_fixed_mode->clock;
130 else
131 return mode->clock;
132}
133
a4fc5ed6 134static int
ea5b213a 135intel_dp_max_lane_count(struct intel_dp *intel_dp)
a4fc5ed6 136{
9a10f401
KP		 137 int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
138 switch (max_lane_count) {
139 case 1: case 2: case 4:
140 break;
141 default:
142 max_lane_count = 4;
a4fc5ed6
KP		 143 }
144 return max_lane_count;
145}
146
147static int
ea5b213a 148intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 149{
7183dc29 150 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 151
152 switch (max_link_bw) {
153 case DP_LINK_BW_1_62:
154 case DP_LINK_BW_2_7:
155 break;
156 default:
157 max_link_bw = DP_LINK_BW_1_62;
158 break;
159 }
160 return max_link_bw;
161}
162
163static int
164intel_dp_link_clock(uint8_t link_bw)
165{
166 if (link_bw == DP_LINK_BW_2_7)
167 return 270000;
168 else
169 return 162000;
170}
171
cd9dde44
AJ		 172/*
173 * The units on the numbers in the next two are... bizarre. Examples will
174 * make it clearer; this one parallels an example in the eDP spec.
175 *
176 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
177 *
178 * 270000 * 1 * 8 / 10 == 216000
179 *
180 * The actual data capacity of that configuration is 2.16Gbit/s, so the
181 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
182 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
183 * 119000. At 18bpp that's 2142000 kilobits per second.
184 *
185 * Thus the strange-looking division by 10 in intel_dp_link_required, to
186 * get the result in decakilobits instead of kilobits.
187 */
188
a4fc5ed6 189static int
c898261c 190intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 191{
cd9dde44 192 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 193}
194
fe27d53e
DA		 195static int
196intel_dp_max_data_rate(int max_link_clock, int max_lanes)
197{
198 return (max_link_clock * max_lanes * 8) / 10;
199}
200
c4867936
DV		 201static bool
202intel_dp_adjust_dithering(struct intel_dp *intel_dp,
203 struct drm_display_mode *mode,
cb1793ce 204 bool adjust_mode)
c4867936
DV		 205{
206 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
207 int max_lanes = intel_dp_max_lane_count(intel_dp);
208 int max_rate, mode_rate;
209
210 mode_rate = intel_dp_link_required(mode->clock, 24);
211 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
212
213 if (mode_rate > max_rate) {
214 mode_rate = intel_dp_link_required(mode->clock, 18);
215 if (mode_rate > max_rate)
216 return false;
217
cb1793ce
DV		 218 if (adjust_mode)
219 mode->private_flags
c4867936
DV		 220 |= INTEL_MODE_DP_FORCE_6BPC;
221
222 return true;
223 }
224
225 return true;
226}
227
a4fc5ed6
KP		 228static int
229intel_dp_mode_valid(struct drm_connector *connector,
230 struct drm_display_mode *mode)
231{
df0e9248 232 struct intel_dp *intel_dp = intel_attached_dp(connector);
a4fc5ed6 233
d15456de
KP		 234 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
235 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
7de56f43
ZY		 236 return MODE_PANEL;
237
d15456de 238 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
7de56f43
ZY		 239 return MODE_PANEL;
240 }
241
cb1793ce 242 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
c4867936 243 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 244
245 if (mode->clock < 10000)
246 return MODE_CLOCK_LOW;
247
0af78a2b
DV		 248 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
249 return MODE_H_ILLEGAL;
250
a4fc5ed6
KP		 251 return MODE_OK;
252}
253
254static uint32_t
255pack_aux(uint8_t *src, int src_bytes)
256{
257 int i;
258 uint32_t v = 0;
259
260 if (src_bytes > 4)
261 src_bytes = 4;
262 for (i = 0; i < src_bytes; i++)
263 v |= ((uint32_t) src[i]) << ((3-i) * 8);
264 return v;
265}
266
267static void
268unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
269{
270 int i;
271 if (dst_bytes > 4)
272 dst_bytes = 4;
273 for (i = 0; i < dst_bytes; i++)
274 dst[i] = src >> ((3-i) * 8);
275}
276
fb0f8fbf
KP		 277/* hrawclock is 1/4 the FSB frequency */
278static int
279intel_hrawclk(struct drm_device *dev)
280{
281 struct drm_i915_private *dev_priv = dev->dev_private;
282 uint32_t clkcfg;
283
9473c8f4
VP		 284 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
285 if (IS_VALLEYVIEW(dev))
286 return 200;
287
fb0f8fbf
KP		 288 clkcfg = I915_READ(CLKCFG);
289 switch (clkcfg & CLKCFG_FSB_MASK) {
290 case CLKCFG_FSB_400:
291 return 100;
292 case CLKCFG_FSB_533:
293 return 133;
294 case CLKCFG_FSB_667:
295 return 166;
296 case CLKCFG_FSB_800:
297 return 200;
298 case CLKCFG_FSB_1067:
299 return 266;
300 case CLKCFG_FSB_1333:
301 return 333;
302 /* these two are just a guess; one of them might be right */
303 case CLKCFG_FSB_1600:
304 case CLKCFG_FSB_1600_ALT:
305 return 400;
306 default:
307 return 133;
308 }
309}
310
ebf33b18
KP		 311static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
312{
313 struct drm_device *dev = intel_dp->base.base.dev;
314 struct drm_i915_private *dev_priv = dev->dev_private;
315
316 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
317}
318
319static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
320{
321 struct drm_device *dev = intel_dp->base.base.dev;
322 struct drm_i915_private *dev_priv = dev->dev_private;
323
324 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
325}
326
9b984dae
KP		 327static void
328intel_dp_check_edp(struct intel_dp *intel_dp)
329{
330 struct drm_device *dev = intel_dp->base.base.dev;
331 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 332
9b984dae
KP		 333 if (!is_edp(intel_dp))
334 return;
ebf33b18 335 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 336 WARN(1, "eDP powered off while attempting aux channel communication.\n");
337 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
ebf33b18 338 I915_READ(PCH_PP_STATUS),
9b984dae
KP		 339 I915_READ(PCH_PP_CONTROL));
340 }
341}
342
a4fc5ed6 343static int
ea5b213a 344intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 345 uint8_t *send, int send_bytes,
346 uint8_t *recv, int recv_size)
347{
ea5b213a 348 uint32_t output_reg = intel_dp->output_reg;
4ef69c7a 349 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6
KP		 350 struct drm_i915_private *dev_priv = dev->dev_private;
351 uint32_t ch_ctl = output_reg + 0x10;
352 uint32_t ch_data = ch_ctl + 4;
353 int i;
354 int recv_bytes;
a4fc5ed6 355 uint32_t status;
fb0f8fbf 356 uint32_t aux_clock_divider;
6b4e0a93 357 int try, precharge;
a4fc5ed6 358
750eb99e
PZ		 359 if (IS_HASWELL(dev)) {
360 switch (intel_dp->port) {
361 case PORT_A:
362 ch_ctl = DPA_AUX_CH_CTL;
363 ch_data = DPA_AUX_CH_DATA1;
364 break;
365 case PORT_B:
366 ch_ctl = PCH_DPB_AUX_CH_CTL;
367 ch_data = PCH_DPB_AUX_CH_DATA1;
368 break;
369 case PORT_C:
370 ch_ctl = PCH_DPC_AUX_CH_CTL;
371 ch_data = PCH_DPC_AUX_CH_DATA1;
372 break;
373 case PORT_D:
374 ch_ctl = PCH_DPD_AUX_CH_CTL;
375 ch_data = PCH_DPD_AUX_CH_DATA1;
376 break;
377 default:
378 BUG();
379 }
380 }
381
9b984dae 382 intel_dp_check_edp(intel_dp);
a4fc5ed6 383 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 384 * and would like to run at 2MHz. So, take the
385 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 386 *
387 * Note that PCH attached eDP panels should use a 125MHz input
388 * clock divider.
a4fc5ed6 389 */
1c95822a 390 if (is_cpu_edp(intel_dp)) {
9473c8f4
VP		 391 if (IS_VALLEYVIEW(dev))
392 aux_clock_divider = 100;
393 else if (IS_GEN6(dev) || IS_GEN7(dev))
1a2eb460 394 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 395 else
396 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
397 } else if (HAS_PCH_SPLIT(dev))
6919132e 398 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
5eb08b69
ZW		 399 else
400 aux_clock_divider = intel_hrawclk(dev) / 2;
401
6b4e0a93
DV		 402 if (IS_GEN6(dev))
403 precharge = 3;
404 else
405 precharge = 5;
406
11bee43e
JB		 407 /* Try to wait for any previous AUX channel activity */
408 for (try = 0; try < 3; try++) {
409 status = I915_READ(ch_ctl);
410 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
411 break;
412 msleep(1);
413 }
414
415 if (try == 3) {
416 WARN(1, "dp_aux_ch not started status 0x%08x\n",
417 I915_READ(ch_ctl));
4f7f7b7e
CW		 418 return -EBUSY;
419 }
420
fb0f8fbf
KP		 421 /* Must try at least 3 times according to DP spec */
422 for (try = 0; try < 5; try++) {
423 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 424 for (i = 0; i < send_bytes; i += 4)
425 I915_WRITE(ch_data + i,
426 pack_aux(send + i, send_bytes - i));
0206e353 427
fb0f8fbf 428 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 429 I915_WRITE(ch_ctl,
430 DP_AUX_CH_CTL_SEND_BUSY |
431 DP_AUX_CH_CTL_TIME_OUT_400us |
432 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
433 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
434 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
435 DP_AUX_CH_CTL_DONE |
436 DP_AUX_CH_CTL_TIME_OUT_ERROR |
437 DP_AUX_CH_CTL_RECEIVE_ERROR);
fb0f8fbf 438 for (;;) {
fb0f8fbf
KP		 439 status = I915_READ(ch_ctl);
440 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
441 break;
4f7f7b7e 442 udelay(100);
fb0f8fbf 443 }
0206e353 444
fb0f8fbf 445 /* Clear done status and any errors */
4f7f7b7e
CW		 446 I915_WRITE(ch_ctl,
447 status |
448 DP_AUX_CH_CTL_DONE |
449 DP_AUX_CH_CTL_TIME_OUT_ERROR |
450 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 451
452 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
453 DP_AUX_CH_CTL_RECEIVE_ERROR))
454 continue;
4f7f7b7e 455 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 456 break;
457 }
458
a4fc5ed6 459 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 460 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
a5b3da54 461 return -EBUSY;
a4fc5ed6
KP		 462 }
463
464 /* Check for timeout or receive error.
465 * Timeouts occur when the sink is not connected
466 */
a5b3da54 467 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 468 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
a5b3da54
KP		 469 return -EIO;
470 }
1ae8c0a5
KP		 471
472 /* Timeouts occur when the device isn't connected, so they're
473 * "normal" -- don't fill the kernel log with these */
a5b3da54 474 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 475 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
a5b3da54 476 return -ETIMEDOUT;
a4fc5ed6
KP		 477 }
478
479 /* Unload any bytes sent back from the other side */
480 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
481 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 482 if (recv_bytes > recv_size)
483 recv_bytes = recv_size;
0206e353 484
4f7f7b7e
CW		 485 for (i = 0; i < recv_bytes; i += 4)
486 unpack_aux(I915_READ(ch_data + i),
487 recv + i, recv_bytes - i);
a4fc5ed6
KP		 488
489 return recv_bytes;
490}
491
492/* Write data to the aux channel in native mode */
493static int
ea5b213a 494intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 495 uint16_t address, uint8_t *send, int send_bytes)
496{
497 int ret;
498 uint8_t msg[20];
499 int msg_bytes;
500 uint8_t ack;
501
9b984dae 502 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 503 if (send_bytes > 16)
504 return -1;
505 msg[0] = AUX_NATIVE_WRITE << 4;
506 msg[1] = address >> 8;
eebc863e 507 msg[2] = address & 0xff;
a4fc5ed6
KP		 508 msg[3] = send_bytes - 1;
509 memcpy(&msg[4], send, send_bytes);
510 msg_bytes = send_bytes + 4;
511 for (;;) {
ea5b213a 512 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 513 if (ret < 0)
514 return ret;
515 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
516 break;
517 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
518 udelay(100);
519 else
a5b3da54 520 return -EIO;
a4fc5ed6
KP		 521 }
522 return send_bytes;
523}
524
525/* Write a single byte to the aux channel in native mode */
526static int
ea5b213a 527intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 528 uint16_t address, uint8_t byte)
529{
ea5b213a 530 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 531}
532
533/* read bytes from a native aux channel */
534static int
ea5b213a 535intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 536 uint16_t address, uint8_t *recv, int recv_bytes)
537{
538 uint8_t msg[4];
539 int msg_bytes;
540 uint8_t reply[20];
541 int reply_bytes;
542 uint8_t ack;
543 int ret;
544
9b984dae 545 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 546 msg[0] = AUX_NATIVE_READ << 4;
547 msg[1] = address >> 8;
548 msg[2] = address & 0xff;
549 msg[3] = recv_bytes - 1;
550
551 msg_bytes = 4;
552 reply_bytes = recv_bytes + 1;
553
554 for (;;) {
ea5b213a 555 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 556 reply, reply_bytes);
a5b3da54
KP		 557 if (ret == 0)
558 return -EPROTO;
559 if (ret < 0)
a4fc5ed6
KP		 560 return ret;
561 ack = reply[0];
562 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
563 memcpy(recv, reply + 1, ret - 1);
564 return ret - 1;
565 }
566 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
567 udelay(100);
568 else
a5b3da54 569 return -EIO;
a4fc5ed6
KP		 570 }
571}
572
573static int
ab2c0672
DA		 574intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
575 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 576{
ab2c0672 577 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 578 struct intel_dp *intel_dp = container_of(adapter,
579 struct intel_dp,
580 adapter);
ab2c0672
DA		 581 uint16_t address = algo_data->address;
582 uint8_t msg[5];
583 uint8_t reply[2];
8316f337 584 unsigned retry;
ab2c0672
DA		 585 int msg_bytes;
586 int reply_bytes;
587 int ret;
588
9b984dae 589 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 590 /* Set up the command byte */
591 if (mode & MODE_I2C_READ)
592 msg[0] = AUX_I2C_READ << 4;
593 else
594 msg[0] = AUX_I2C_WRITE << 4;
595
596 if (!(mode & MODE_I2C_STOP))
597 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 598
ab2c0672
DA		 599 msg[1] = address >> 8;
600 msg[2] = address;
601
602 switch (mode) {
603 case MODE_I2C_WRITE:
604 msg[3] = 0;
605 msg[4] = write_byte;
606 msg_bytes = 5;
607 reply_bytes = 1;
608 break;
609 case MODE_I2C_READ:
610 msg[3] = 0;
611 msg_bytes = 4;
612 reply_bytes = 2;
613 break;
614 default:
615 msg_bytes = 3;
616 reply_bytes = 1;
617 break;
618 }
619
8316f337
DF		 620 for (retry = 0; retry < 5; retry++) {
621 ret = intel_dp_aux_ch(intel_dp,
622 msg, msg_bytes,
623 reply, reply_bytes);
ab2c0672 624 if (ret < 0) {
3ff99164 625 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 626 return ret;
627 }
8316f337
DF		 628
629 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
630 case AUX_NATIVE_REPLY_ACK:
631 /* I2C-over-AUX Reply field is only valid
632 * when paired with AUX ACK.
633 */
634 break;
635 case AUX_NATIVE_REPLY_NACK:
636 DRM_DEBUG_KMS("aux_ch native nack\n");
637 return -EREMOTEIO;
638 case AUX_NATIVE_REPLY_DEFER:
639 udelay(100);
640 continue;
641 default:
642 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
643 reply[0]);
644 return -EREMOTEIO;
645 }
646
ab2c0672
DA		 647 switch (reply[0] & AUX_I2C_REPLY_MASK) {
648 case AUX_I2C_REPLY_ACK:
649 if (mode == MODE_I2C_READ) {
650 *read_byte = reply[1];
651 }
652 return reply_bytes - 1;
653 case AUX_I2C_REPLY_NACK:
8316f337 654 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 655 return -EREMOTEIO;
656 case AUX_I2C_REPLY_DEFER:
8316f337 657 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 658 udelay(100);
659 break;
660 default:
8316f337 661 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 662 return -EREMOTEIO;
663 }
664 }
8316f337
DF		 665
666 DRM_ERROR("too many retries, giving up\n");
667 return -EREMOTEIO;
a4fc5ed6
KP		 668}
669
0b5c541b 670static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
bd943159 671static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
0b5c541b 672
a4fc5ed6 673static int
ea5b213a 674intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 675 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 676{
0b5c541b
KP		 677 int ret;
678
d54e9d28 679 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 680 intel_dp->algo.running = false;
681 intel_dp->algo.address = 0;
682 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
683
0206e353 684 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 685 intel_dp->adapter.owner = THIS_MODULE;
686 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 687 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 688 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
689 intel_dp->adapter.algo_data = &intel_dp->algo;
690 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
691
0b5c541b
KP		 692 ironlake_edp_panel_vdd_on(intel_dp);
693 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 694 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 695 return ret;
a4fc5ed6
KP		 696}
697
698static bool
e811f5ae
LP		 699intel_dp_mode_fixup(struct drm_encoder *encoder,
700 const struct drm_display_mode *mode,
a4fc5ed6
KP		 701 struct drm_display_mode *adjusted_mode)
702{
0d3a1bee 703 struct drm_device *dev = encoder->dev;
ea5b213a 704 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
a4fc5ed6 705 int lane_count, clock;
ea5b213a
CW		 706 int max_lane_count = intel_dp_max_lane_count(intel_dp);
707 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 708 int bpp, mode_rate;
a4fc5ed6
KP		 709 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
710
d15456de
KP		 711 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
712 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
1d8e1c75
CW		 713 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
714 mode, adjusted_mode);
0d3a1bee
ZY		 715 }
716
cb1793ce 717 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 718 return false;
719
083f9560
DV		 720 DRM_DEBUG_KMS("DP link computation with max lane count %i "
721 "max bw %02x pixel clock %iKHz\n",
71244653 722 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 723
cb1793ce 724 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
c4867936
DV		 725 return false;
726
727 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
71244653 728 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
c4867936 729
2514bc51
JB		 730 for (clock = 0; clock <= max_clock; clock++) {
731 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
fe27d53e 732 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
a4fc5ed6 733
083f9560 734 if (mode_rate <= link_avail) {
ea5b213a
CW		 735 intel_dp->link_bw = bws[clock];
736 intel_dp->lane_count = lane_count;
737 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
083f9560
DV		 738 DRM_DEBUG_KMS("DP link bw %02x lane "
739 "count %d clock %d bpp %d\n",
ea5b213a 740 intel_dp->link_bw, intel_dp->lane_count,
083f9560
DV		 741 adjusted_mode->clock, bpp);
742 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
743 mode_rate, link_avail);
a4fc5ed6
KP		 744 return true;
745 }
746 }
747 }
fe27d53e 748
a4fc5ed6
KP		 749 return false;
750}
751
752struct intel_dp_m_n {
753 uint32_t tu;
754 uint32_t gmch_m;
755 uint32_t gmch_n;
756 uint32_t link_m;
757 uint32_t link_n;
758};
759
760static void
761intel_reduce_ratio(uint32_t *num, uint32_t *den)
762{
763 while (*num > 0xffffff || *den > 0xffffff) {
764 *num >>= 1;
765 *den >>= 1;
766 }
767}
768
769static void
36e83a18 770intel_dp_compute_m_n(int bpp,
a4fc5ed6
KP		 771 int nlanes,
772 int pixel_clock,
773 int link_clock,
774 struct intel_dp_m_n *m_n)
775{
776 m_n->tu = 64;
36e83a18 777 m_n->gmch_m = (pixel_clock * bpp) >> 3;
a4fc5ed6
KP		 778 m_n->gmch_n = link_clock * nlanes;
779 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
780 m_n->link_m = pixel_clock;
781 m_n->link_n = link_clock;
782 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
783}
784
785void
786intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
787 struct drm_display_mode *adjusted_mode)
788{
789 struct drm_device *dev = crtc->dev;
6c2b7c12 790 struct intel_encoder *encoder;
a4fc5ed6
KP		 791 struct drm_i915_private *dev_priv = dev->dev_private;
792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
858fa035 793 int lane_count = 4;
a4fc5ed6 794 struct intel_dp_m_n m_n;
9db4a9c7 795 int pipe = intel_crtc->pipe;
a4fc5ed6
KP		 796
797 /*
21d40d37 798 * Find the lane count in the intel_encoder private
a4fc5ed6 799 */
6c2b7c12
DV		 800 for_each_encoder_on_crtc(dev, crtc, encoder) {
801 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
a4fc5ed6 802
9a10f401
KP		 803 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
804 intel_dp->base.type == INTEL_OUTPUT_EDP)
805 {
ea5b213a 806 lane_count = intel_dp->lane_count;
51190667 807 break;
a4fc5ed6
KP		 808 }
809 }
810
811 /*
812 * Compute the GMCH and Link ratios. The '3' here is
813 * the number of bytes_per_pixel post-LUT, which we always
814 * set up for 8-bits of R/G/B, or 3 bytes total.
815 */
858fa035 816 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
a4fc5ed6
KP		 817 mode->clock, adjusted_mode->clock, &m_n);
818
c619eed4 819 if (HAS_PCH_SPLIT(dev)) {
7346bfa0 820 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
9db4a9c7
JB		 821 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
822 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
823 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
74a4dd2e
VP		 824 } else if (IS_VALLEYVIEW(dev)) {
825 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
826 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
827 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
828 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
a4fc5ed6 829 } else {
9db4a9c7 830 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
7346bfa0 831 TU_SIZE(m_n.tu) | m_n.gmch_m);
9db4a9c7
JB		 832 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
833 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
834 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
a4fc5ed6
KP		 835 }
836}
837
247d89f6
PZ		 838void intel_dp_init_link_config(struct intel_dp *intel_dp)
839{
840 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
841 intel_dp->link_configuration[0] = intel_dp->link_bw;
842 intel_dp->link_configuration[1] = intel_dp->lane_count;
843 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
844 /*
845 * Check for DPCD version > 1.1 and enhanced framing support
846 */
847 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
848 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
849 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
850 }
851}
852
a4fc5ed6
KP		 853static void
854intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
855 struct drm_display_mode *adjusted_mode)
856{
e3421a18 857 struct drm_device *dev = encoder->dev;
417e822d 858 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 859 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4ef69c7a 860 struct drm_crtc *crtc = intel_dp->base.base.crtc;
a4fc5ed6
KP		 861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
862
417e822d 863 /*
1a2eb460 864 * There are four kinds of DP registers:
417e822d
KP		 865 *
866 * IBX PCH
1a2eb460
KP		 867 * SNB CPU
868 * IVB CPU
417e822d
KP		 869 * CPT PCH
870 *
871 * IBX PCH and CPU are the same for almost everything,
872 * except that the CPU DP PLL is configured in this
873 * register
874 *
875 * CPT PCH is quite different, having many bits moved
876 * to the TRANS_DP_CTL register instead. That
877 * configuration happens (oddly) in ironlake_pch_enable
878 */
9c9e7927 879
417e822d
KP		 880 /* Preserve the BIOS-computed detected bit. This is
881 * supposed to be read-only.
882 */
883 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 884
417e822d 885 /* Handle DP bits in common between all three register formats */
417e822d 886 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 887
ea5b213a 888 switch (intel_dp->lane_count) {
a4fc5ed6 889 case 1:
ea5b213a 890 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 891 break;
892 case 2:
ea5b213a 893 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 894 break;
895 case 4:
ea5b213a 896 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 897 break;
898 }
e0dac65e
WF		 899 if (intel_dp->has_audio) {
900 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
901 pipe_name(intel_crtc->pipe));
ea5b213a 902 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 903 intel_write_eld(encoder, adjusted_mode);
904 }
247d89f6
PZ		 905
906 intel_dp_init_link_config(intel_dp);
a4fc5ed6 907
417e822d 908 /* Split out the IBX/CPU vs CPT settings */
32f9d658 909
19c03924 910 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 911 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
912 intel_dp->DP |= DP_SYNC_HS_HIGH;
913 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
914 intel_dp->DP |= DP_SYNC_VS_HIGH;
915 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
916
917 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
918 intel_dp->DP |= DP_ENHANCED_FRAMING;
919
920 intel_dp->DP |= intel_crtc->pipe << 29;
921
922 /* don't miss out required setting for eDP */
1a2eb460
KP		 923 if (adjusted_mode->clock < 200000)
924 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
925 else
926 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
927 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
417e822d
KP		 928 intel_dp->DP |= intel_dp->color_range;
929
930 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
931 intel_dp->DP |= DP_SYNC_HS_HIGH;
932 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
933 intel_dp->DP |= DP_SYNC_VS_HIGH;
934 intel_dp->DP |= DP_LINK_TRAIN_OFF;
935
936 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
937 intel_dp->DP |= DP_ENHANCED_FRAMING;
938
939 if (intel_crtc->pipe == 1)
940 intel_dp->DP |= DP_PIPEB_SELECT;
941
942 if (is_cpu_edp(intel_dp)) {
943 /* don't miss out required setting for eDP */
417e822d
KP		 944 if (adjusted_mode->clock < 200000)
945 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
946 else
947 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
948 }
949 } else {
950 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 951 }
a4fc5ed6
KP		 952}
953
99ea7127
KP		 954#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
955#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
956
957#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
958#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
959
960#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
961#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
962
963static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
964 u32 mask,
965 u32 value)
bd943159 966{
99ea7127
KP		 967 struct drm_device *dev = intel_dp->base.base.dev;
968 struct drm_i915_private *dev_priv = dev->dev_private;
32ce697c 969
99ea7127
KP		 970 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
971 mask, value,
972 I915_READ(PCH_PP_STATUS),
973 I915_READ(PCH_PP_CONTROL));
32ce697c 974
99ea7127
KP		 975 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
976 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
977 I915_READ(PCH_PP_STATUS),
978 I915_READ(PCH_PP_CONTROL));
32ce697c 979 }
99ea7127 980}
32ce697c 981
99ea7127
KP		 982static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
983{
984 DRM_DEBUG_KMS("Wait for panel power on\n");
985 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 986}
987
99ea7127
KP		 988static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
989{
990 DRM_DEBUG_KMS("Wait for panel power off time\n");
991 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
992}
993
994static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
995{
996 DRM_DEBUG_KMS("Wait for panel power cycle\n");
997 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
998}
999
1000
832dd3c1
KP		 1001/* Read the current pp_control value, unlocking the register if it
1002 * is locked
1003 */
1004
1005static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1006{
1007 u32 control = I915_READ(PCH_PP_CONTROL);
1008
1009 control &= ~PANEL_UNLOCK_MASK;
1010 control |= PANEL_UNLOCK_REGS;
1011 return control;
bd943159
KP		 1012}
1013
5d613501
JB		 1014static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1015{
1016 struct drm_device *dev = intel_dp->base.base.dev;
1017 struct drm_i915_private *dev_priv = dev->dev_private;
1018 u32 pp;
1019
97af61f5
KP		 1020 if (!is_edp(intel_dp))
1021 return;
f01eca2e 1022 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 1023
bd943159
KP		 1024 WARN(intel_dp->want_panel_vdd,
1025 "eDP VDD already requested on\n");
1026
1027 intel_dp->want_panel_vdd = true;
99ea7127 1028
bd943159
KP		 1029 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1030 DRM_DEBUG_KMS("eDP VDD already on\n");
1031 return;
1032 }
1033
99ea7127
KP		 1034 if (!ironlake_edp_have_panel_power(intel_dp))
1035 ironlake_wait_panel_power_cycle(intel_dp);
1036
832dd3c1 1037 pp = ironlake_get_pp_control(dev_priv);
5d613501
JB		 1038 pp |= EDP_FORCE_VDD;
1039 I915_WRITE(PCH_PP_CONTROL, pp);
1040 POSTING_READ(PCH_PP_CONTROL);
f01eca2e
KP		 1041 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1042 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
ebf33b18
KP		 1043
1044 /*
1045 * If the panel wasn't on, delay before accessing aux channel
1046 */
1047 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1048 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1049 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1050 }
5d613501
JB		 1051}
1052
bd943159 1053static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501
JB		 1054{
1055 struct drm_device *dev = intel_dp->base.base.dev;
1056 struct drm_i915_private *dev_priv = dev->dev_private;
1057 u32 pp;
1058
bd943159 1059 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
832dd3c1 1060 pp = ironlake_get_pp_control(dev_priv);
bd943159
KP		 1061 pp &= ~EDP_FORCE_VDD;
1062 I915_WRITE(PCH_PP_CONTROL, pp);
1063 POSTING_READ(PCH_PP_CONTROL);
1064
1065 /* Make sure sequencer is idle before allowing subsequent activity */
1066 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1067 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
99ea7127
KP		 1068
1069 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1070 }
1071}
5d613501 1072
bd943159
KP		 1073static void ironlake_panel_vdd_work(struct work_struct *__work)
1074{
1075 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1076 struct intel_dp, panel_vdd_work);
1077 struct drm_device *dev = intel_dp->base.base.dev;
1078
627f7675 1079 mutex_lock(&dev->mode_config.mutex);
bd943159 1080 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1081 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1082}
1083
1084static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1085{
97af61f5
KP		 1086 if (!is_edp(intel_dp))
1087 return;
5d613501 1088
bd943159
KP		 1089 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1090 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1091
bd943159
KP		 1092 intel_dp->want_panel_vdd = false;
1093
1094 if (sync) {
1095 ironlake_panel_vdd_off_sync(intel_dp);
1096 } else {
1097 /*
1098 * Queue the timer to fire a long
1099 * time from now (relative to the power down delay)
1100 * to keep the panel power up across a sequence of operations
1101 */
1102 schedule_delayed_work(&intel_dp->panel_vdd_work,
1103 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1104 }
5d613501
JB		 1105}
1106
86a3073e 1107static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1108{
01cb9ea6 1109 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1110 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1111 u32 pp;
9934c132 1112
97af61f5 1113 if (!is_edp(intel_dp))
bd943159 1114 return;
99ea7127
KP		 1115
1116 DRM_DEBUG_KMS("Turn eDP power on\n");
1117
1118 if (ironlake_edp_have_panel_power(intel_dp)) {
1119 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1120 return;
99ea7127 1121 }
9934c132 1122
99ea7127 1123 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1124
99ea7127 1125 pp = ironlake_get_pp_control(dev_priv);
05ce1a49
KP		 1126 if (IS_GEN5(dev)) {
1127 /* ILK workaround: disable reset around power sequence */
1128 pp &= ~PANEL_POWER_RESET;
1129 I915_WRITE(PCH_PP_CONTROL, pp);
1130 POSTING_READ(PCH_PP_CONTROL);
1131 }
37c6c9b0 1132
1c0ae80a 1133 pp |= POWER_TARGET_ON;
99ea7127
KP		 1134 if (!IS_GEN5(dev))
1135 pp |= PANEL_POWER_RESET;
1136
9934c132 1137 I915_WRITE(PCH_PP_CONTROL, pp);
01cb9ea6 1138 POSTING_READ(PCH_PP_CONTROL);
9934c132 1139
99ea7127 1140 ironlake_wait_panel_on(intel_dp);
9934c132 1141
05ce1a49
KP		 1142 if (IS_GEN5(dev)) {
1143 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1144 I915_WRITE(PCH_PP_CONTROL, pp);
1145 POSTING_READ(PCH_PP_CONTROL);
1146 }
9934c132
JB		 1147}
1148
99ea7127 1149static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1150{
99ea7127 1151 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1152 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1153 u32 pp;
9934c132 1154
97af61f5
KP		 1155 if (!is_edp(intel_dp))
1156 return;
37c6c9b0 1157
99ea7127 1158 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1159
6cb49835 1160 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1161
99ea7127 1162 pp = ironlake_get_pp_control(dev_priv);
35a38556
DV		 1163 /* We need to switch off panel power _and_ force vdd, for otherwise some
1164 * panels get very unhappy and cease to work. */
1165 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
99ea7127
KP		 1166 I915_WRITE(PCH_PP_CONTROL, pp);
1167 POSTING_READ(PCH_PP_CONTROL);
9934c132 1168
35a38556
DV		 1169 intel_dp->want_panel_vdd = false;
1170
99ea7127 1171 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1172}
1173
86a3073e 1174static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1175{
f01eca2e 1176 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1177 struct drm_i915_private *dev_priv = dev->dev_private;
1178 u32 pp;
1179
f01eca2e
KP		 1180 if (!is_edp(intel_dp))
1181 return;
1182
28c97730 1183 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1184 /*
1185 * If we enable the backlight right away following a panel power
1186 * on, we may see slight flicker as the panel syncs with the eDP
1187 * link. So delay a bit to make sure the image is solid before
1188 * allowing it to appear.
1189 */
f01eca2e 1190 msleep(intel_dp->backlight_on_delay);
832dd3c1 1191 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1192 pp |= EDP_BLC_ENABLE;
1193 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e 1194 POSTING_READ(PCH_PP_CONTROL);
32f9d658
ZW		 1195}
1196
86a3073e 1197static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1198{
f01eca2e 1199 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1200 struct drm_i915_private *dev_priv = dev->dev_private;
1201 u32 pp;
1202
f01eca2e
KP		 1203 if (!is_edp(intel_dp))
1204 return;
1205
28c97730 1206 DRM_DEBUG_KMS("\n");
832dd3c1 1207 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1208 pp &= ~EDP_BLC_ENABLE;
1209 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e
KP		 1210 POSTING_READ(PCH_PP_CONTROL);
1211 msleep(intel_dp->backlight_off_delay);
32f9d658 1212}
a4fc5ed6 1213
2bd2ad64 1214static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1215{
2bd2ad64
DV		 1216 struct drm_device *dev = intel_dp->base.base.dev;
1217 struct drm_crtc *crtc = intel_dp->base.base.crtc;
d240f20f
JB		 1218 struct drm_i915_private *dev_priv = dev->dev_private;
1219 u32 dpa_ctl;
1220
2bd2ad64
DV		 1221 assert_pipe_disabled(dev_priv,
1222 to_intel_crtc(crtc)->pipe);
1223
d240f20f
JB		 1224 DRM_DEBUG_KMS("\n");
1225 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1226 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1227 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1228
1229 /* We don't adjust intel_dp->DP while tearing down the link, to
1230 * facilitate link retraining (e.g. after hotplug). Hence clear all
1231 * enable bits here to ensure that we don't enable too much. */
1232 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1233 intel_dp->DP |= DP_PLL_ENABLE;
1234 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1235 POSTING_READ(DP_A);
1236 udelay(200);
d240f20f
JB		 1237}
1238
2bd2ad64 1239static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1240{
2bd2ad64
DV		 1241 struct drm_device *dev = intel_dp->base.base.dev;
1242 struct drm_crtc *crtc = intel_dp->base.base.crtc;
d240f20f
JB		 1243 struct drm_i915_private *dev_priv = dev->dev_private;
1244 u32 dpa_ctl;
1245
2bd2ad64
DV		 1246 assert_pipe_disabled(dev_priv,
1247 to_intel_crtc(crtc)->pipe);
1248
d240f20f 1249 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1250 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1251 "dp pll off, should be on\n");
1252 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1253
1254 /* We can't rely on the value tracked for the DP register in
1255 * intel_dp->DP because link_down must not change that (otherwise link
1256 * re-training will fail. */
298b0b39 1257 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1258 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1259 POSTING_READ(DP_A);
d240f20f
JB		 1260 udelay(200);
1261}
1262
c7ad3810
JB		 1263/* If the sink supports it, try to set the power state appropriately */
1264static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1265{
1266 int ret, i;
1267
1268 /* Should have a valid DPCD by this point */
1269 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1270 return;
1271
1272 if (mode != DRM_MODE_DPMS_ON) {
1273 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1274 DP_SET_POWER_D3);
1275 if (ret != 1)
1276 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1277 } else {
1278 /*
1279 * When turning on, we need to retry for 1ms to give the sink
1280 * time to wake up.
1281 */
1282 for (i = 0; i < 3; i++) {
1283 ret = intel_dp_aux_native_write_1(intel_dp,
1284 DP_SET_POWER,
1285 DP_SET_POWER_D0);
1286 if (ret == 1)
1287 break;
1288 msleep(1);
1289 }
1290 }
1291}
1292
19d8fe15
DV		 1293static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1294 enum pipe *pipe)
d240f20f 1295{
19d8fe15
DV		 1296 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1297 struct drm_device *dev = encoder->base.dev;
1298 struct drm_i915_private *dev_priv = dev->dev_private;
1299 u32 tmp = I915_READ(intel_dp->output_reg);
1300
1301 if (!(tmp & DP_PORT_EN))
1302 return false;
1303
1304 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1305 *pipe = PORT_TO_PIPE_CPT(tmp);
1306 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1307 *pipe = PORT_TO_PIPE(tmp);
1308 } else {
1309 u32 trans_sel;
1310 u32 trans_dp;
1311 int i;
1312
1313 switch (intel_dp->output_reg) {
1314 case PCH_DP_B:
1315 trans_sel = TRANS_DP_PORT_SEL_B;
1316 break;
1317 case PCH_DP_C:
1318 trans_sel = TRANS_DP_PORT_SEL_C;
1319 break;
1320 case PCH_DP_D:
1321 trans_sel = TRANS_DP_PORT_SEL_D;
1322 break;
1323 default:
1324 return true;
1325 }
1326
1327 for_each_pipe(i) {
1328 trans_dp = I915_READ(TRANS_DP_CTL(i));
1329 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1330 *pipe = i;
1331 return true;
1332 }
1333 }
1334 }
1335
1336 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp->output_reg);
d240f20f 1337
19d8fe15
DV		 1338 return true;
1339}
1340
e8cb4558 1341static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1342{
e8cb4558 1343 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
6cb49835
DV		 1344
1345 /* Make sure the panel is off before trying to change the mode. But also
1346 * ensure that we have vdd while we switch off the panel. */
1347 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1348 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1349 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1350 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1351
1352 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1353 if (!is_cpu_edp(intel_dp))
1354 intel_dp_link_down(intel_dp);
d240f20f
JB		 1355}
1356
2bd2ad64
DV		 1357static void intel_post_disable_dp(struct intel_encoder *encoder)
1358{
1359 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1360
3739850b
DV		 1361 if (is_cpu_edp(intel_dp)) {
1362 intel_dp_link_down(intel_dp);
2bd2ad64 1363 ironlake_edp_pll_off(intel_dp);
3739850b 1364 }
2bd2ad64
DV		 1365}
1366
e8cb4558 1367static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1368{
e8cb4558
DV		 1369 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1370 struct drm_device *dev = encoder->base.dev;
1371 struct drm_i915_private *dev_priv = dev->dev_private;
1372 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1373
0c33d8d7
DV		 1374 if (WARN_ON(dp_reg & DP_PORT_EN))
1375 return;
1376
97af61f5 1377 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1378 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
0c33d8d7
DV		 1379 intel_dp_start_link_train(intel_dp);
1380 ironlake_edp_panel_on(intel_dp);
1381 ironlake_edp_panel_vdd_off(intel_dp, true);
1382 intel_dp_complete_link_train(intel_dp);
f01eca2e 1383 ironlake_edp_backlight_on(intel_dp);
d240f20f
JB		 1384}
1385
2bd2ad64 1386static void intel_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1387{
2bd2ad64 1388 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
0a91ca29 1389
2bd2ad64
DV		 1390 if (is_cpu_edp(intel_dp))
1391 ironlake_edp_pll_on(intel_dp);
a4fc5ed6
KP		 1392}
1393
1394/*
df0c237d
JB		 1395 * Native read with retry for link status and receiver capability reads for
1396 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1397 */
1398static bool
df0c237d
JB		 1399intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1400 uint8_t *recv, int recv_bytes)
a4fc5ed6 1401{
61da5fab
JB		 1402 int ret, i;
1403
df0c237d
JB		 1404 /*
1405 * Sinks are *supposed* to come up within 1ms from an off state,
1406 * but we're also supposed to retry 3 times per the spec.
1407 */
61da5fab 1408 for (i = 0; i < 3; i++) {
df0c237d
JB		 1409 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1410 recv_bytes);
1411 if (ret == recv_bytes)
61da5fab
JB		 1412 return true;
1413 msleep(1);
1414 }
a4fc5ed6 1415
61da5fab 1416 return false;
a4fc5ed6
KP		 1417}
1418
1419/*
1420 * Fetch AUX CH registers 0x202 - 0x207 which contain
1421 * link status information
1422 */
1423static bool
93f62dad 1424intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1425{
df0c237d
JB		 1426 return intel_dp_aux_native_read_retry(intel_dp,
1427 DP_LANE0_1_STATUS,
93f62dad 1428 link_status,
df0c237d 1429 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1430}
1431
1432static uint8_t
1433intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1434 int r)
1435{
1436 return link_status[r - DP_LANE0_1_STATUS];
1437}
1438
a4fc5ed6 1439static uint8_t
93f62dad 1440intel_get_adjust_request_voltage(uint8_t adjust_request[2],
a4fc5ed6
KP		 1441 int lane)
1442{
a4fc5ed6
KP		 1443 int s = ((lane & 1) ?
1444 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1445 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
93f62dad 1446 uint8_t l = adjust_request[lane>>1];
a4fc5ed6
KP		 1447
1448 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1449}
1450
1451static uint8_t
93f62dad 1452intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
a4fc5ed6
KP		 1453 int lane)
1454{
a4fc5ed6
KP		 1455 int s = ((lane & 1) ?
1456 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1457 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
93f62dad 1458 uint8_t l = adjust_request[lane>>1];
a4fc5ed6
KP		 1459
1460 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1461}
1462
1463
1464#if 0
1465static char *voltage_names[] = {
1466 "0.4V", "0.6V", "0.8V", "1.2V"
1467};
1468static char *pre_emph_names[] = {
1469 "0dB", "3.5dB", "6dB", "9.5dB"
1470};
1471static char *link_train_names[] = {
1472 "pattern 1", "pattern 2", "idle", "off"
1473};
1474#endif
1475
1476/*
1477 * These are source-specific values; current Intel hardware supports
1478 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1479 */
a4fc5ed6
KP		 1480
1481static uint8_t
1a2eb460 1482intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1483{
1a2eb460
KP		 1484 struct drm_device *dev = intel_dp->base.base.dev;
1485
1486 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1487 return DP_TRAIN_VOLTAGE_SWING_800;
1488 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1489 return DP_TRAIN_VOLTAGE_SWING_1200;
1490 else
1491 return DP_TRAIN_VOLTAGE_SWING_800;
1492}
1493
1494static uint8_t
1495intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1496{
1497 struct drm_device *dev = intel_dp->base.base.dev;
1498
d6c0d722
PZ		 1499 if (IS_HASWELL(dev)) {
1500 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1501 case DP_TRAIN_VOLTAGE_SWING_400:
1502 return DP_TRAIN_PRE_EMPHASIS_9_5;
1503 case DP_TRAIN_VOLTAGE_SWING_600:
1504 return DP_TRAIN_PRE_EMPHASIS_6;
1505 case DP_TRAIN_VOLTAGE_SWING_800:
1506 return DP_TRAIN_PRE_EMPHASIS_3_5;
1507 case DP_TRAIN_VOLTAGE_SWING_1200:
1508 default:
1509 return DP_TRAIN_PRE_EMPHASIS_0;
1510 }
1511 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1512 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1513 case DP_TRAIN_VOLTAGE_SWING_400:
1514 return DP_TRAIN_PRE_EMPHASIS_6;
1515 case DP_TRAIN_VOLTAGE_SWING_600:
1516 case DP_TRAIN_VOLTAGE_SWING_800:
1517 return DP_TRAIN_PRE_EMPHASIS_3_5;
1518 default:
1519 return DP_TRAIN_PRE_EMPHASIS_0;
1520 }
1521 } else {
1522 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1523 case DP_TRAIN_VOLTAGE_SWING_400:
1524 return DP_TRAIN_PRE_EMPHASIS_6;
1525 case DP_TRAIN_VOLTAGE_SWING_600:
1526 return DP_TRAIN_PRE_EMPHASIS_6;
1527 case DP_TRAIN_VOLTAGE_SWING_800:
1528 return DP_TRAIN_PRE_EMPHASIS_3_5;
1529 case DP_TRAIN_VOLTAGE_SWING_1200:
1530 default:
1531 return DP_TRAIN_PRE_EMPHASIS_0;
1532 }
a4fc5ed6
KP		 1533 }
1534}
1535
1536static void
93f62dad 1537intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1538{
1539 uint8_t v = 0;
1540 uint8_t p = 0;
1541 int lane;
93f62dad 1542 uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1a2eb460
KP		 1543 uint8_t voltage_max;
1544 uint8_t preemph_max;
a4fc5ed6 1545
33a34e4e 1546 for (lane = 0; lane < intel_dp->lane_count; lane++) {
93f62dad
KP		 1547 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1548 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
a4fc5ed6
KP		 1549
1550 if (this_v > v)
1551 v = this_v;
1552 if (this_p > p)
1553 p = this_p;
1554 }
1555
1a2eb460 1556 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1557 if (v >= voltage_max)
1558 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1559
1a2eb460
KP		 1560 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1561 if (p >= preemph_max)
1562 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1563
1564 for (lane = 0; lane < 4; lane++)
33a34e4e 1565 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1566}
1567
1568static uint32_t
93f62dad 1569intel_dp_signal_levels(uint8_t train_set)
a4fc5ed6 1570{
3cf2efb1 1571 uint32_t signal_levels = 0;
a4fc5ed6 1572
3cf2efb1 1573 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1574 case DP_TRAIN_VOLTAGE_SWING_400:
1575 default:
1576 signal_levels |= DP_VOLTAGE_0_4;
1577 break;
1578 case DP_TRAIN_VOLTAGE_SWING_600:
1579 signal_levels |= DP_VOLTAGE_0_6;
1580 break;
1581 case DP_TRAIN_VOLTAGE_SWING_800:
1582 signal_levels |= DP_VOLTAGE_0_8;
1583 break;
1584 case DP_TRAIN_VOLTAGE_SWING_1200:
1585 signal_levels |= DP_VOLTAGE_1_2;
1586 break;
1587 }
3cf2efb1 1588 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1589 case DP_TRAIN_PRE_EMPHASIS_0:
1590 default:
1591 signal_levels |= DP_PRE_EMPHASIS_0;
1592 break;
1593 case DP_TRAIN_PRE_EMPHASIS_3_5:
1594 signal_levels |= DP_PRE_EMPHASIS_3_5;
1595 break;
1596 case DP_TRAIN_PRE_EMPHASIS_6:
1597 signal_levels |= DP_PRE_EMPHASIS_6;
1598 break;
1599 case DP_TRAIN_PRE_EMPHASIS_9_5:
1600 signal_levels |= DP_PRE_EMPHASIS_9_5;
1601 break;
1602 }
1603 return signal_levels;
1604}
1605
e3421a18
ZW		 1606/* Gen6's DP voltage swing and pre-emphasis control */
1607static uint32_t
1608intel_gen6_edp_signal_levels(uint8_t train_set)
1609{
3c5a62b5
YL		 1610 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1611 DP_TRAIN_PRE_EMPHASIS_MASK);
1612 switch (signal_levels) {
e3421a18 1613 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1614 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1615 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1616 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1617 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1618 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1619 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1620 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1621 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1622 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1623 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1624 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1625 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1626 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1627 default:
3c5a62b5
YL		 1628 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1629 "0x%x\n", signal_levels);
1630 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1631 }
1632}
1633
1a2eb460
KP		 1634/* Gen7's DP voltage swing and pre-emphasis control */
1635static uint32_t
1636intel_gen7_edp_signal_levels(uint8_t train_set)
1637{
1638 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1639 DP_TRAIN_PRE_EMPHASIS_MASK);
1640 switch (signal_levels) {
1641 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1642 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1643 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1644 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1645 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1646 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1647
1648 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1649 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1650 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1651 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1652
1653 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1654 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1655 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1656 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1657
1658 default:
1659 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1660 "0x%x\n", signal_levels);
1661 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1662 }
1663}
1664
d6c0d722
PZ		 1665/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1666static uint32_t
1667intel_dp_signal_levels_hsw(uint8_t train_set)
1668{
1669 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1670 DP_TRAIN_PRE_EMPHASIS_MASK);
1671 switch (signal_levels) {
1672 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1673 return DDI_BUF_EMP_400MV_0DB_HSW;
1674 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1675 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1676 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1677 return DDI_BUF_EMP_400MV_6DB_HSW;
1678 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1679 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1680
1681 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1682 return DDI_BUF_EMP_600MV_0DB_HSW;
1683 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1684 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1685 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1686 return DDI_BUF_EMP_600MV_6DB_HSW;
1687
1688 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1689 return DDI_BUF_EMP_800MV_0DB_HSW;
1690 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1691 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1692 default:
1693 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1694 "0x%x\n", signal_levels);
1695 return DDI_BUF_EMP_400MV_0DB_HSW;
1696 }
1697}
1698
a4fc5ed6
KP		 1699static uint8_t
1700intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1701 int lane)
1702{
a4fc5ed6 1703 int s = (lane & 1) * 4;
93f62dad 1704 uint8_t l = link_status[lane>>1];
a4fc5ed6
KP		 1705
1706 return (l >> s) & 0xf;
1707}
1708
1709/* Check for clock recovery is done on all channels */
1710static bool
1711intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1712{
1713 int lane;
1714 uint8_t lane_status;
1715
1716 for (lane = 0; lane < lane_count; lane++) {
1717 lane_status = intel_get_lane_status(link_status, lane);
1718 if ((lane_status & DP_LANE_CR_DONE) == 0)
1719 return false;
1720 }
1721 return true;
1722}
1723
1724/* Check to see if channel eq is done on all channels */
1725#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1726 DP_LANE_CHANNEL_EQ_DONE|\
1727 DP_LANE_SYMBOL_LOCKED)
1728static bool
93f62dad 1729intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1730{
1731 uint8_t lane_align;
1732 uint8_t lane_status;
1733 int lane;
1734
93f62dad 1735 lane_align = intel_dp_link_status(link_status,
a4fc5ed6
KP		 1736 DP_LANE_ALIGN_STATUS_UPDATED);
1737 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1738 return false;
33a34e4e 1739 for (lane = 0; lane < intel_dp->lane_count; lane++) {
93f62dad 1740 lane_status = intel_get_lane_status(link_status, lane);
a4fc5ed6
KP		 1741 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1742 return false;
1743 }
1744 return true;
1745}
1746
1747static bool
ea5b213a 1748intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1749 uint32_t dp_reg_value,
58e10eb9 1750 uint8_t dp_train_pat)
a4fc5ed6 1751{
4ef69c7a 1752 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1753 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6 1754 int ret;
d6c0d722 1755 uint32_t temp;
a4fc5ed6 1756
d6c0d722
PZ		 1757 if (IS_HASWELL(dev)) {
1758 temp = I915_READ(DP_TP_CTL(intel_dp->port));
1759
1760 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1761 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1762 else
1763 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1764
1765 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1766 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1767 case DP_TRAINING_PATTERN_DISABLE:
1768 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1769 I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1770
1771 if (wait_for((I915_READ(DP_TP_STATUS(intel_dp->port)) &
1772 DP_TP_STATUS_IDLE_DONE), 1))
1773 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1774
1775 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1776 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1777
1778 break;
1779 case DP_TRAINING_PATTERN_1:
1780 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1781 break;
1782 case DP_TRAINING_PATTERN_2:
1783 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1784 break;
1785 case DP_TRAINING_PATTERN_3:
1786 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1787 break;
1788 }
1789 I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1790
1791 } else if (HAS_PCH_CPT(dev) &&
1792 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
47ea7542
PZ		 1793 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1794
1795 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1796 case DP_TRAINING_PATTERN_DISABLE:
1797 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1798 break;
1799 case DP_TRAINING_PATTERN_1:
1800 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1801 break;
1802 case DP_TRAINING_PATTERN_2:
1803 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1804 break;
1805 case DP_TRAINING_PATTERN_3:
1806 DRM_ERROR("DP training pattern 3 not supported\n");
1807 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1808 break;
1809 }
1810
1811 } else {
1812 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1813
1814 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1815 case DP_TRAINING_PATTERN_DISABLE:
1816 dp_reg_value |= DP_LINK_TRAIN_OFF;
1817 break;
1818 case DP_TRAINING_PATTERN_1:
1819 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1820 break;
1821 case DP_TRAINING_PATTERN_2:
1822 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1823 break;
1824 case DP_TRAINING_PATTERN_3:
1825 DRM_ERROR("DP training pattern 3 not supported\n");
1826 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1827 break;
1828 }
1829 }
1830
ea5b213a
CW		 1831 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1832 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1833
ea5b213a 1834 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1835 DP_TRAINING_PATTERN_SET,
1836 dp_train_pat);
1837
47ea7542
PZ		 1838 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1839 DP_TRAINING_PATTERN_DISABLE) {
1840 ret = intel_dp_aux_native_write(intel_dp,
1841 DP_TRAINING_LANE0_SET,
1842 intel_dp->train_set,
1843 intel_dp->lane_count);
1844 if (ret != intel_dp->lane_count)
1845 return false;
1846 }
a4fc5ed6
KP		 1847
1848 return true;
1849}
1850
33a34e4e 1851/* Enable corresponding port and start training pattern 1 */
a4fc5ed6 1852static void
33a34e4e 1853intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1854{
4ef69c7a 1855 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6
KP		 1856 int i;
1857 uint8_t voltage;
1858 bool clock_recovery = false;
cdb0e95b 1859 int voltage_tries, loop_tries;
ea5b213a 1860 uint32_t DP = intel_dp->DP;
a4fc5ed6 1861
3cf2efb1
CW		 1862 /* Write the link configuration data */
1863 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1864 intel_dp->link_configuration,
1865 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1866
1867 DP |= DP_PORT_EN;
1a2eb460 1868
33a34e4e 1869 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 1870 voltage = 0xff;
cdb0e95b
KP		 1871 voltage_tries = 0;
1872 loop_tries = 0;
a4fc5ed6
KP		 1873 clock_recovery = false;
1874 for (;;) {
33a34e4e 1875 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 1876 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1877 uint32_t signal_levels;
417e822d 1878
d6c0d722
PZ		 1879 if (IS_HASWELL(dev)) {
1880 signal_levels = intel_dp_signal_levels_hsw(
1881 intel_dp->train_set[0]);
1882 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1883 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1884 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1885 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1886 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1887 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1888 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1889 } else {
93f62dad 1890 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1891 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1892 }
d6c0d722
PZ		 1893 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
1894 signal_levels);
a4fc5ed6 1895
47ea7542 1896 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1897 DP_TRAINING_PATTERN_1 |
1898 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 1899 break;
a4fc5ed6
KP		 1900 /* Set training pattern 1 */
1901
3cf2efb1 1902 udelay(100);
93f62dad
KP		 1903 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1904 DRM_ERROR("failed to get link status\n");
a4fc5ed6 1905 break;
93f62dad 1906 }
a4fc5ed6 1907
93f62dad
KP		 1908 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1909 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 1910 clock_recovery = true;
1911 break;
1912 }
1913
1914 /* Check to see if we've tried the max voltage */
1915 for (i = 0; i < intel_dp->lane_count; i++)
1916 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 1917 break;
0d710688 1918 if (i == intel_dp->lane_count && voltage_tries == 5) {
cdb0e95b
KP		 1919 ++loop_tries;
1920 if (loop_tries == 5) {
1921 DRM_DEBUG_KMS("too many full retries, give up\n");
1922 break;
1923 }
1924 memset(intel_dp->train_set, 0, 4);
1925 voltage_tries = 0;
1926 continue;
1927 }
a4fc5ed6 1928
3cf2efb1
CW		 1929 /* Check to see if we've tried the same voltage 5 times */
1930 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
cdb0e95b
KP		 1931 ++voltage_tries;
1932 if (voltage_tries == 5) {
1933 DRM_DEBUG_KMS("too many voltage retries, give up\n");
a4fc5ed6 1934 break;
cdb0e95b 1935 }
3cf2efb1 1936 } else
cdb0e95b 1937 voltage_tries = 0;
3cf2efb1 1938 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 1939
3cf2efb1 1940 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1941 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 1942 }
1943
33a34e4e
JB		 1944 intel_dp->DP = DP;
1945}
1946
1947static void
1948intel_dp_complete_link_train(struct intel_dp *intel_dp)
1949{
4ef69c7a 1950 struct drm_device *dev = intel_dp->base.base.dev;
33a34e4e 1951 bool channel_eq = false;
37f80975 1952 int tries, cr_tries;
33a34e4e
JB		 1953 uint32_t DP = intel_dp->DP;
1954
a4fc5ed6
KP		 1955 /* channel equalization */
1956 tries = 0;
37f80975 1957 cr_tries = 0;
a4fc5ed6
KP		 1958 channel_eq = false;
1959 for (;;) {
33a34e4e 1960 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
e3421a18 1961 uint32_t signal_levels;
93f62dad 1962 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1963
37f80975
JB		 1964 if (cr_tries > 5) {
1965 DRM_ERROR("failed to train DP, aborting\n");
1966 intel_dp_link_down(intel_dp);
1967 break;
1968 }
1969
d6c0d722
PZ		 1970 if (IS_HASWELL(dev)) {
1971 signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]);
1972 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1973 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1974 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1975 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1976 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1977 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1978 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1979 } else {
93f62dad 1980 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1981 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1982 }
1983
a4fc5ed6 1984 /* channel eq pattern */
47ea7542 1985 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1986 DP_TRAINING_PATTERN_2 |
1987 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 1988 break;
1989
3cf2efb1 1990 udelay(400);
93f62dad 1991 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 1992 break;
a4fc5ed6 1993
37f80975 1994 /* Make sure clock is still ok */
93f62dad 1995 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 1996 intel_dp_start_link_train(intel_dp);
1997 cr_tries++;
1998 continue;
1999 }
2000
93f62dad 2001 if (intel_channel_eq_ok(intel_dp, link_status)) {
3cf2efb1
CW		 2002 channel_eq = true;
2003 break;
2004 }
a4fc5ed6 2005
37f80975
JB		 2006 /* Try 5 times, then try clock recovery if that fails */
2007 if (tries > 5) {
2008 intel_dp_link_down(intel_dp);
2009 intel_dp_start_link_train(intel_dp);
2010 tries = 0;
2011 cr_tries++;
2012 continue;
2013 }
a4fc5ed6 2014
3cf2efb1 2015 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2016 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 2017 ++tries;
869184a6 2018 }
3cf2efb1 2019
d6c0d722
PZ		 2020 if (channel_eq)
2021 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
2022
47ea7542 2023 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2024}
2025
2026static void
ea5b213a 2027intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2028{
4ef69c7a 2029 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 2030 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 2031 uint32_t DP = intel_dp->DP;
a4fc5ed6 2032
0c33d8d7 2033 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2034 return;
2035
28c97730 2036 DRM_DEBUG_KMS("\n");
32f9d658 2037
1a2eb460 2038 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 2039 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2040 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2041 } else {
2042 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2043 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2044 }
fe255d00 2045 POSTING_READ(intel_dp->output_reg);
5eb08b69 2046
fe255d00 2047 msleep(17);
5eb08b69 2048
493a7081 2049 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2050 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
31acbcc4
CW		 2051 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2052
5bddd17f
EA		 2053 /* Hardware workaround: leaving our transcoder select
2054 * set to transcoder B while it's off will prevent the
2055 * corresponding HDMI output on transcoder A.
2056 *
2057 * Combine this with another hardware workaround:
2058 * transcoder select bit can only be cleared while the
2059 * port is enabled.
2060 */
2061 DP &= ~DP_PIPEB_SELECT;
2062 I915_WRITE(intel_dp->output_reg, DP);
2063
2064 /* Changes to enable or select take place the vblank
2065 * after being written.
2066 */
31acbcc4
CW		 2067 if (crtc == NULL) {
2068 /* We can arrive here never having been attached
2069 * to a CRTC, for instance, due to inheriting
2070 * random state from the BIOS.
2071 *
2072 * If the pipe is not running, play safe and
2073 * wait for the clocks to stabilise before
2074 * continuing.
2075 */
2076 POSTING_READ(intel_dp->output_reg);
2077 msleep(50);
2078 } else
2079 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
5bddd17f
EA		 2080 }
2081
832afda6 2082 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2083 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2084 POSTING_READ(intel_dp->output_reg);
f01eca2e 2085 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2086}
2087
26d61aad
KP		 2088static bool
2089intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2090{
92fd8fd1 2091 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
b091cd92
AJ		 2092 sizeof(intel_dp->dpcd)) == 0)
2093 return false; /* aux transfer failed */
92fd8fd1 2094
b091cd92
AJ		 2095 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2096 return false; /* DPCD not present */
2097
2098 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2099 DP_DWN_STRM_PORT_PRESENT))
2100 return true; /* native DP sink */
2101
2102 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2103 return true; /* no per-port downstream info */
2104
2105 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2106 intel_dp->downstream_ports,
2107 DP_MAX_DOWNSTREAM_PORTS) == 0)
2108 return false; /* downstream port status fetch failed */
2109
2110 return true;
92fd8fd1
KP		 2111}
2112
0d198328
AJ		 2113static void
2114intel_dp_probe_oui(struct intel_dp *intel_dp)
2115{
2116 u8 buf[3];
2117
2118 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2119 return;
2120
351cfc34
DV		 2121 ironlake_edp_panel_vdd_on(intel_dp);
2122
0d198328
AJ		 2123 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2124 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2125 buf[0], buf[1], buf[2]);
2126
2127 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2128 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2129 buf[0], buf[1], buf[2]);
351cfc34
DV		 2130
2131 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2132}
2133
a60f0e38
JB		 2134static bool
2135intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2136{
2137 int ret;
2138
2139 ret = intel_dp_aux_native_read_retry(intel_dp,
2140 DP_DEVICE_SERVICE_IRQ_VECTOR,
2141 sink_irq_vector, 1);
2142 if (!ret)
2143 return false;
2144
2145 return true;
2146}
2147
2148static void
2149intel_dp_handle_test_request(struct intel_dp *intel_dp)
2150{
2151 /* NAK by default */
2152 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
2153}
2154
a4fc5ed6
KP		 2155/*
2156 * According to DP spec
2157 * 5.1.2:
2158 * 1. Read DPCD
2159 * 2. Configure link according to Receiver Capabilities
2160 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2161 * 4. Check link status on receipt of hot-plug interrupt
2162 */
2163
2164static void
ea5b213a 2165intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2166{
a60f0e38 2167 u8 sink_irq_vector;
93f62dad 2168 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2169
24e804ba 2170 if (!intel_dp->base.connectors_active)
d2b996ac 2171 return;
59cd09e1 2172
24e804ba 2173 if (WARN_ON(!intel_dp->base.base.crtc))
a4fc5ed6
KP		 2174 return;
2175
92fd8fd1 2176 /* Try to read receiver status if the link appears to be up */
93f62dad 2177 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2178 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2179 return;
2180 }
2181
92fd8fd1 2182 /* Now read the DPCD to see if it's actually running */
26d61aad 2183 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2184 intel_dp_link_down(intel_dp);
2185 return;
2186 }
2187
a60f0e38
JB		 2188 /* Try to read the source of the interrupt */
2189 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2190 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2191 /* Clear interrupt source */
2192 intel_dp_aux_native_write_1(intel_dp,
2193 DP_DEVICE_SERVICE_IRQ_VECTOR,
2194 sink_irq_vector);
2195
2196 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2197 intel_dp_handle_test_request(intel_dp);
2198 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2199 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2200 }
2201
93f62dad 2202 if (!intel_channel_eq_ok(intel_dp, link_status)) {
92fd8fd1
KP		 2203 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2204 drm_get_encoder_name(&intel_dp->base.base));
33a34e4e
JB		 2205 intel_dp_start_link_train(intel_dp);
2206 intel_dp_complete_link_train(intel_dp);
2207 }
a4fc5ed6 2208}
a4fc5ed6 2209
07d3dc18 2210/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2211static enum drm_connector_status
26d61aad 2212intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2213{
07d3dc18
AJ		 2214 uint8_t *dpcd = intel_dp->dpcd;
2215 bool hpd;
2216 uint8_t type;
2217
2218 if (!intel_dp_get_dpcd(intel_dp))
2219 return connector_status_disconnected;
2220
2221 /* if there's no downstream port, we're done */
2222 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2223 return connector_status_connected;
2224
2225 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2226 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2227 if (hpd) {
da131a46 2228 uint8_t reg;
07d3dc18 2229 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
da131a46 2230 &reg, 1))
07d3dc18 2231 return connector_status_unknown;
da131a46
AJ		 2232 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2233 : connector_status_disconnected;
07d3dc18
AJ		 2234 }
2235
2236 /* If no HPD, poke DDC gently */
2237 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2238 return connector_status_connected;
07d3dc18
AJ		 2239
2240 /* Well we tried, say unknown for unreliable port types */
2241 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2242 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2243 return connector_status_unknown;
2244
2245 /* Anything else is out of spec, warn and ignore */
2246 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2247 return connector_status_disconnected;
71ba9000
AJ		 2248}
2249
5eb08b69 2250static enum drm_connector_status
a9756bb5 2251ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2252{
5eb08b69
ZW		 2253 enum drm_connector_status status;
2254
fe16d949
CW		 2255 /* Can't disconnect eDP, but you can close the lid... */
2256 if (is_edp(intel_dp)) {
2257 status = intel_panel_detect(intel_dp->base.base.dev);
2258 if (status == connector_status_unknown)
2259 status = connector_status_connected;
2260 return status;
2261 }
01cb9ea6 2262
26d61aad 2263 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2264}
2265
a4fc5ed6 2266static enum drm_connector_status
a9756bb5 2267g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2268{
4ef69c7a 2269 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 2270 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 2271 uint32_t bit;
5eb08b69 2272
ea5b213a 2273 switch (intel_dp->output_reg) {
a4fc5ed6 2274 case DP_B:
10f76a38 2275 bit = DPB_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2276 break;
2277 case DP_C:
10f76a38 2278 bit = DPC_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2279 break;
2280 case DP_D:
10f76a38 2281 bit = DPD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2282 break;
2283 default:
2284 return connector_status_unknown;
2285 }
2286
10f76a38 2287 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2288 return connector_status_disconnected;
2289
26d61aad 2290 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2291}
2292
8c241fef
KP		 2293static struct edid *
2294intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2295{
2296 struct intel_dp *intel_dp = intel_attached_dp(connector);
2297 struct edid *edid;
d6f24d0f
JB		 2298 int size;
2299
2300 if (is_edp(intel_dp)) {
2301 if (!intel_dp->edid)
2302 return NULL;
2303
2304 size = (intel_dp->edid->extensions + 1) * EDID_LENGTH;
2305 edid = kmalloc(size, GFP_KERNEL);
2306 if (!edid)
2307 return NULL;
2308
2309 memcpy(edid, intel_dp->edid, size);
2310 return edid;
2311 }
8c241fef 2312
8c241fef 2313 edid = drm_get_edid(connector, adapter);
8c241fef
KP		 2314 return edid;
2315}
2316
2317static int
2318intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2319{
2320 struct intel_dp *intel_dp = intel_attached_dp(connector);
2321 int ret;
2322
d6f24d0f
JB		 2323 if (is_edp(intel_dp)) {
2324 drm_mode_connector_update_edid_property(connector,
2325 intel_dp->edid);
2326 ret = drm_add_edid_modes(connector, intel_dp->edid);
2327 drm_edid_to_eld(connector,
2328 intel_dp->edid);
d6f24d0f
JB		 2329 return intel_dp->edid_mode_count;
2330 }
2331
8c241fef 2332 ret = intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2333 return ret;
2334}
2335
2336
a9756bb5
ZW		 2337/**
2338 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2339 *
2340 * \return true if DP port is connected.
2341 * \return false if DP port is disconnected.
2342 */
2343static enum drm_connector_status
2344intel_dp_detect(struct drm_connector *connector, bool force)
2345{
2346 struct intel_dp *intel_dp = intel_attached_dp(connector);
2347 struct drm_device *dev = intel_dp->base.base.dev;
2348 enum drm_connector_status status;
2349 struct edid *edid = NULL;
2350
2351 intel_dp->has_audio = false;
2352
2353 if (HAS_PCH_SPLIT(dev))
2354 status = ironlake_dp_detect(intel_dp);
2355 else
2356 status = g4x_dp_detect(intel_dp);
1b9be9d0 2357
ac66ae83
AJ		 2358 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2359 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2360 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2361 intel_dp->dpcd[6], intel_dp->dpcd[7]);
1b9be9d0 2362
a9756bb5
ZW		 2363 if (status != connector_status_connected)
2364 return status;
2365
0d198328
AJ		 2366 intel_dp_probe_oui(intel_dp);
2367
c3e5f67b
DV		 2368 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2369 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2370 } else {
8c241fef 2371 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2372 if (edid) {
2373 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2374 kfree(edid);
2375 }
a9756bb5
ZW		 2376 }
2377
2378 return connector_status_connected;
a4fc5ed6
KP		 2379}
2380
2381static int intel_dp_get_modes(struct drm_connector *connector)
2382{
df0e9248 2383 struct intel_dp *intel_dp = intel_attached_dp(connector);
4ef69c7a 2384 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 2385 struct drm_i915_private *dev_priv = dev->dev_private;
2386 int ret;
a4fc5ed6
KP		 2387
2388 /* We should parse the EDID data and find out if it has an audio sink
2389 */
2390
8c241fef 2391 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
b9efc480 2392 if (ret) {
d15456de 2393 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
b9efc480
ZY		 2394 struct drm_display_mode *newmode;
2395 list_for_each_entry(newmode, &connector->probed_modes,
2396 head) {
d15456de
KP		 2397 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2398 intel_dp->panel_fixed_mode =
b9efc480
ZY		 2399 drm_mode_duplicate(dev, newmode);
2400 break;
2401 }
2402 }
2403 }
32f9d658 2404 return ret;
b9efc480 2405 }
32f9d658
ZW		 2406
2407 /* if eDP has no EDID, try to use fixed panel mode from VBT */
4d926461 2408 if (is_edp(intel_dp)) {
47f0eb22 2409 /* initialize panel mode from VBT if available for eDP */
d15456de
KP		 2410 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2411 intel_dp->panel_fixed_mode =
47f0eb22 2412 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
d15456de
KP		 2413 if (intel_dp->panel_fixed_mode) {
2414 intel_dp->panel_fixed_mode->type |=
47f0eb22
KP		 2415 DRM_MODE_TYPE_PREFERRED;
2416 }
2417 }
d15456de 2418 if (intel_dp->panel_fixed_mode) {
32f9d658 2419 struct drm_display_mode *mode;
d15456de 2420 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
32f9d658
ZW		 2421 drm_mode_probed_add(connector, mode);
2422 return 1;
2423 }
2424 }
2425 return 0;
a4fc5ed6
KP		 2426}
2427
1aad7ac0
CW		 2428static bool
2429intel_dp_detect_audio(struct drm_connector *connector)
2430{
2431 struct intel_dp *intel_dp = intel_attached_dp(connector);
2432 struct edid *edid;
2433 bool has_audio = false;
2434
8c241fef 2435 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2436 if (edid) {
2437 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2438 kfree(edid);
2439 }
2440
2441 return has_audio;
2442}
2443
f684960e
CW		 2444static int
2445intel_dp_set_property(struct drm_connector *connector,
2446 struct drm_property *property,
2447 uint64_t val)
2448{
e953fd7b 2449 struct drm_i915_private *dev_priv = connector->dev->dev_private;
f684960e
CW		 2450 struct intel_dp *intel_dp = intel_attached_dp(connector);
2451 int ret;
2452
2453 ret = drm_connector_property_set_value(connector, property, val);
2454 if (ret)
2455 return ret;
2456
3f43c48d 2457 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2458 int i = val;
2459 bool has_audio;
2460
2461 if (i == intel_dp->force_audio)
f684960e
CW		 2462 return 0;
2463
1aad7ac0 2464 intel_dp->force_audio = i;
f684960e 2465
c3e5f67b 2466 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2467 has_audio = intel_dp_detect_audio(connector);
2468 else
c3e5f67b 2469 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2470
2471 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2472 return 0;
2473
1aad7ac0 2474 intel_dp->has_audio = has_audio;
f684960e
CW		 2475 goto done;
2476 }
2477
e953fd7b
CW		 2478 if (property == dev_priv->broadcast_rgb_property) {
2479 if (val == !!intel_dp->color_range)
2480 return 0;
2481
2482 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2483 goto done;
2484 }
2485
f684960e
CW		 2486 return -EINVAL;
2487
2488done:
2489 if (intel_dp->base.base.crtc) {
2490 struct drm_crtc *crtc = intel_dp->base.base.crtc;
a6778b3c
DV		 2491 intel_set_mode(crtc, &crtc->mode,
2492 crtc->x, crtc->y, crtc->fb);
f684960e
CW		 2493 }
2494
2495 return 0;
2496}
2497
a4fc5ed6 2498static void
0206e353 2499intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2500{
aaa6fd2a
MG		 2501 struct drm_device *dev = connector->dev;
2502
2503 if (intel_dpd_is_edp(dev))
2504 intel_panel_destroy_backlight(dev);
2505
a4fc5ed6
KP		 2506 drm_sysfs_connector_remove(connector);
2507 drm_connector_cleanup(connector);
55f78c43 2508 kfree(connector);
a4fc5ed6
KP		 2509}
2510
24d05927
DV		 2511static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2512{
2513 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2514
2515 i2c_del_adapter(&intel_dp->adapter);
2516 drm_encoder_cleanup(encoder);
bd943159 2517 if (is_edp(intel_dp)) {
d6f24d0f 2518 kfree(intel_dp->edid);
bd943159
KP		 2519 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2520 ironlake_panel_vdd_off_sync(intel_dp);
2521 }
24d05927
DV		 2522 kfree(intel_dp);
2523}
2524
a4fc5ed6 2525static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 2526 .mode_fixup = intel_dp_mode_fixup,
a4fc5ed6 2527 .mode_set = intel_dp_mode_set,
1f703855 2528 .disable = intel_encoder_noop,
a4fc5ed6
KP		 2529};
2530
2531static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 2532 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 2533 .detect = intel_dp_detect,
2534 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2535 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2536 .destroy = intel_dp_destroy,
2537};
2538
2539static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2540 .get_modes = intel_dp_get_modes,
2541 .mode_valid = intel_dp_mode_valid,
df0e9248 2542 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2543};
2544
a4fc5ed6 2545static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2546 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2547};
2548
995b6762 2549static void
21d40d37 2550intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2551{
ea5b213a 2552 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
c8110e52 2553
885a5014 2554 intel_dp_check_link_status(intel_dp);
c8110e52 2555}
6207937d 2556
e3421a18
ZW		 2557/* Return which DP Port should be selected for Transcoder DP control */
2558int
0206e353 2559intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2560{
2561 struct drm_device *dev = crtc->dev;
6c2b7c12 2562 struct intel_encoder *encoder;
e3421a18 2563
6c2b7c12
DV		 2564 for_each_encoder_on_crtc(dev, crtc, encoder) {
2565 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
e3421a18 2566
417e822d
KP		 2567 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2568 intel_dp->base.type == INTEL_OUTPUT_EDP)
ea5b213a 2569 return intel_dp->output_reg;
e3421a18 2570 }
ea5b213a 2571
e3421a18
ZW		 2572 return -1;
2573}
2574
36e83a18 2575/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2576bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2577{
2578 struct drm_i915_private *dev_priv = dev->dev_private;
2579 struct child_device_config *p_child;
2580 int i;
2581
2582 if (!dev_priv->child_dev_num)
2583 return false;
2584
2585 for (i = 0; i < dev_priv->child_dev_num; i++) {
2586 p_child = dev_priv->child_dev + i;
2587
2588 if (p_child->dvo_port == PORT_IDPD &&
2589 p_child->device_type == DEVICE_TYPE_eDP)
2590 return true;
2591 }
2592 return false;
2593}
2594
f684960e
CW		 2595static void
2596intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2597{
3f43c48d 2598 intel_attach_force_audio_property(connector);
e953fd7b 2599 intel_attach_broadcast_rgb_property(connector);
f684960e
CW		 2600}
2601
a4fc5ed6 2602void
ab9d7c30 2603intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
a4fc5ed6
KP		 2604{
2605 struct drm_i915_private *dev_priv = dev->dev_private;
2606 struct drm_connector *connector;
ea5b213a 2607 struct intel_dp *intel_dp;
21d40d37 2608 struct intel_encoder *intel_encoder;
55f78c43 2609 struct intel_connector *intel_connector;
5eb08b69 2610 const char *name = NULL;
b329530c 2611 int type;
a4fc5ed6 2612
ea5b213a
CW		 2613 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2614 if (!intel_dp)
a4fc5ed6
KP		 2615 return;
2616
3d3dc149 2617 intel_dp->output_reg = output_reg;
ab9d7c30 2618 intel_dp->port = port;
0767935e
DV		 2619 /* Preserve the current hw state. */
2620 intel_dp->DP = I915_READ(intel_dp->output_reg);
3d3dc149 2621
55f78c43
ZW		 2622 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2623 if (!intel_connector) {
ea5b213a 2624 kfree(intel_dp);
55f78c43
ZW		 2625 return;
2626 }
ea5b213a 2627 intel_encoder = &intel_dp->base;
55f78c43 2628
ea5b213a 2629 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
b329530c 2630 if (intel_dpd_is_edp(dev))
ea5b213a 2631 intel_dp->is_pch_edp = true;
b329530c 2632
19c03924
GB		 2633 /*
2634 * FIXME : We need to initialize built-in panels before external panels.
2635 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2636 */
2637 if (IS_VALLEYVIEW(dev) && output_reg == DP_C) {
2638 type = DRM_MODE_CONNECTOR_eDP;
2639 intel_encoder->type = INTEL_OUTPUT_EDP;
2640 } else if (output_reg == DP_A || is_pch_edp(intel_dp)) {
b329530c
AJ		 2641 type = DRM_MODE_CONNECTOR_eDP;
2642 intel_encoder->type = INTEL_OUTPUT_EDP;
2643 } else {
2644 type = DRM_MODE_CONNECTOR_DisplayPort;
2645 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2646 }
2647
55f78c43 2648 connector = &intel_connector->base;
b329530c 2649 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 2650 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2651
eb1f8e4f
DA		 2652 connector->polled = DRM_CONNECTOR_POLL_HPD;
2653
66a9278e 2654 intel_encoder->cloneable = false;
f8aed700 2655
66a9278e
DV		 2656 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2657 ironlake_panel_vdd_work);
6251ec0a 2658
27f8227b 2659 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
ee7b9f93 2660
a4fc5ed6
KP		 2661 connector->interlace_allowed = true;
2662 connector->doublescan_allowed = 0;
2663
4ef69c7a 2664 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
a4fc5ed6 2665 DRM_MODE_ENCODER_TMDS);
4ef69c7a 2666 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
a4fc5ed6 2667
df0e9248 2668 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 2669 drm_sysfs_connector_add(connector);
2670
e8cb4558 2671 intel_encoder->enable = intel_enable_dp;
2bd2ad64 2672 intel_encoder->pre_enable = intel_pre_enable_dp;
e8cb4558 2673 intel_encoder->disable = intel_disable_dp;
2bd2ad64 2674 intel_encoder->post_disable = intel_post_disable_dp;
19d8fe15
DV		 2675 intel_encoder->get_hw_state = intel_dp_get_hw_state;
2676 intel_connector->get_hw_state = intel_connector_get_hw_state;
e8cb4558 2677
a4fc5ed6 2678 /* Set up the DDC bus. */
ab9d7c30
PZ		 2679 switch (port) {
2680 case PORT_A:
2681 name = "DPDDC-A";
2682 break;
2683 case PORT_B:
2684 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2685 name = "DPDDC-B";
2686 break;
2687 case PORT_C:
2688 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2689 name = "DPDDC-C";
2690 break;
2691 case PORT_D:
2692 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2693 name = "DPDDC-D";
2694 break;
2695 default:
2696 WARN(1, "Invalid port %c\n", port_name(port));
2697 break;
5eb08b69
ZW		 2698 }
2699
89667383
JB		 2700 /* Cache some DPCD data in the eDP case */
2701 if (is_edp(intel_dp)) {
f01eca2e
KP		 2702 struct edp_power_seq cur, vbt;
2703 u32 pp_on, pp_off, pp_div;
5d613501
JB		 2704
2705 pp_on = I915_READ(PCH_PP_ON_DELAYS);
f01eca2e 2706 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
5d613501 2707 pp_div = I915_READ(PCH_PP_DIVISOR);
89667383 2708
bfa3384a
JB		 2709 if (!pp_on || !pp_off || !pp_div) {
2710 DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2711 intel_dp_encoder_destroy(&intel_dp->base.base);
2712 intel_dp_destroy(&intel_connector->base);
2713 return;
2714 }
2715
f01eca2e
KP		 2716 /* Pull timing values out of registers */
2717 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2718 PANEL_POWER_UP_DELAY_SHIFT;
2719
2720 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2721 PANEL_LIGHT_ON_DELAY_SHIFT;
f2e8b18a 2722
f01eca2e
KP		 2723 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2724 PANEL_LIGHT_OFF_DELAY_SHIFT;
2725
2726 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2727 PANEL_POWER_DOWN_DELAY_SHIFT;
2728
2729 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2730 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2731
2732 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2733 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2734
2735 vbt = dev_priv->edp.pps;
2736
2737 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2738 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2739
2740#define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2741
2742 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2743 intel_dp->backlight_on_delay = get_delay(t8);
2744 intel_dp->backlight_off_delay = get_delay(t9);
2745 intel_dp->panel_power_down_delay = get_delay(t10);
2746 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2747
2748 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2749 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2750 intel_dp->panel_power_cycle_delay);
2751
2752 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2753 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
c1f05264
DA		 2754 }
2755
2756 intel_dp_i2c_init(intel_dp, intel_connector, name);
2757
2758 if (is_edp(intel_dp)) {
2759 bool ret;
2760 struct edid *edid;
5d613501
JB		 2761
2762 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 2763 ret = intel_dp_get_dpcd(intel_dp);
bd943159 2764 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 2765
59f3e272 2766 if (ret) {
7183dc29
JB		 2767 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2768 dev_priv->no_aux_handshake =
2769 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 2770 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2771 } else {
3d3dc149 2772 /* if this fails, presume the device is a ghost */
48898b03 2773 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3d3dc149 2774 intel_dp_encoder_destroy(&intel_dp->base.base);
48898b03 2775 intel_dp_destroy(&intel_connector->base);
3d3dc149 2776 return;
89667383 2777 }
89667383 2778
d6f24d0f
JB		 2779 ironlake_edp_panel_vdd_on(intel_dp);
2780 edid = drm_get_edid(connector, &intel_dp->adapter);
2781 if (edid) {
2782 drm_mode_connector_update_edid_property(connector,
2783 edid);
2784 intel_dp->edid_mode_count =
2785 drm_add_edid_modes(connector, edid);
2786 drm_edid_to_eld(connector, edid);
2787 intel_dp->edid = edid;
2788 }
2789 ironlake_edp_panel_vdd_off(intel_dp, false);
2790 }
552fb0b7 2791
21d40d37 2792 intel_encoder->hot_plug = intel_dp_hot_plug;
a4fc5ed6 2793
4d926461 2794 if (is_edp(intel_dp)) {
aaa6fd2a
MG		 2795 dev_priv->int_edp_connector = connector;
2796 intel_panel_setup_backlight(dev);
32f9d658
ZW		 2797 }
2798
f684960e
CW		 2799 intel_dp_add_properties(intel_dp, connector);
2800
a4fc5ed6
KP		 2801 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2802 * 0xd. Failure to do so will result in spurious interrupts being
2803 * generated on the port when a cable is not attached.
2804 */
2805 if (IS_G4X(dev) && !IS_GM45(dev)) {
2806 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2807 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2808 }
2809}
Linux kernel - Deliverables
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