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Merge branch 'x86-debug-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
a4fc5ed6
KP		 31#include "drmP.h"
32#include "drm.h"
33#include "drm_crtc.h"
34#include "drm_crtc_helper.h"
d6f24d0f 35#include "drm_edid.h"
a4fc5ed6
KP		 36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
ab2c0672 39#include "drm_dp_helper.h"
a4fc5ed6 40
a2006cf5 41#define DP_RECEIVER_CAP_SIZE 0xf
a4fc5ed6
KP		 42#define DP_LINK_STATUS_SIZE 6
43#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
44
45#define DP_LINK_CONFIGURATION_SIZE 9
46
ea5b213a
CW		 47struct intel_dp {
48 struct intel_encoder base;
a4fc5ed6
KP		 49 uint32_t output_reg;
50 uint32_t DP;
51 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
a4fc5ed6 52 bool has_audio;
c3e5f67b 53 enum hdmi_force_audio force_audio;
e953fd7b 54 uint32_t color_range;
d2b996ac 55 int dpms_mode;
a4fc5ed6
KP		 56 uint8_t link_bw;
57 uint8_t lane_count;
a2006cf5 58 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
a4fc5ed6
KP		 59 struct i2c_adapter adapter;
60 struct i2c_algo_dp_aux_data algo;
f0917379 61 bool is_pch_edp;
33a34e4e 62 uint8_t train_set[4];
f01eca2e
KP		 63 int panel_power_up_delay;
64 int panel_power_down_delay;
65 int panel_power_cycle_delay;
66 int backlight_on_delay;
67 int backlight_off_delay;
d15456de 68 struct drm_display_mode *panel_fixed_mode; /* for eDP */
bd943159
KP		 69 struct delayed_work panel_vdd_work;
70 bool want_panel_vdd;
d6f24d0f
JB		 71 struct edid *edid; /* cached EDID for eDP */
72 int edid_mode_count;
a4fc5ed6
KP		 73};
74
cfcb0fc9
JB		 75/**
76 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
77 * @intel_dp: DP struct
78 *
79 * If a CPU or PCH DP output is attached to an eDP panel, this function
80 * will return true, and false otherwise.
81 */
82static bool is_edp(struct intel_dp *intel_dp)
83{
84 return intel_dp->base.type == INTEL_OUTPUT_EDP;
85}
86
87/**
88 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
89 * @intel_dp: DP struct
90 *
91 * Returns true if the given DP struct corresponds to a PCH DP port attached
92 * to an eDP panel, false otherwise. Helpful for determining whether we
93 * may need FDI resources for a given DP output or not.
94 */
95static bool is_pch_edp(struct intel_dp *intel_dp)
96{
97 return intel_dp->is_pch_edp;
98}
99
1c95822a
AJ		 100/**
101 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
102 * @intel_dp: DP struct
103 *
104 * Returns true if the given DP struct corresponds to a CPU eDP port.
105 */
106static bool is_cpu_edp(struct intel_dp *intel_dp)
107{
108 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
109}
110
ea5b213a
CW		 111static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
112{
4ef69c7a 113 return container_of(encoder, struct intel_dp, base.base);
ea5b213a 114}
a4fc5ed6 115
df0e9248
CW		 116static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
117{
118 return container_of(intel_attached_encoder(connector),
119 struct intel_dp, base);
120}
121
814948ad
JB		 122/**
123 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
124 * @encoder: DRM encoder
125 *
126 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
127 * by intel_display.c.
128 */
129bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
130{
131 struct intel_dp *intel_dp;
132
133 if (!encoder)
134 return false;
135
136 intel_dp = enc_to_intel_dp(encoder);
137
138 return is_pch_edp(intel_dp);
139}
140
33a34e4e
JB		 141static void intel_dp_start_link_train(struct intel_dp *intel_dp);
142static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
ea5b213a 143static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 144
32f9d658 145void
0206e353 146intel_edp_link_config(struct intel_encoder *intel_encoder,
ea5b213a 147 int *lane_num, int *link_bw)
32f9d658 148{
ea5b213a 149 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
32f9d658 150
ea5b213a
CW		 151 *lane_num = intel_dp->lane_count;
152 if (intel_dp->link_bw == DP_LINK_BW_1_62)
32f9d658 153 *link_bw = 162000;
ea5b213a 154 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
32f9d658
ZW		 155 *link_bw = 270000;
156}
157
a4fc5ed6 158static int
ea5b213a 159intel_dp_max_lane_count(struct intel_dp *intel_dp)
a4fc5ed6 160{
9a10f401
KP		 161 int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
162 switch (max_lane_count) {
163 case 1: case 2: case 4:
164 break;
165 default:
166 max_lane_count = 4;
a4fc5ed6
KP		 167 }
168 return max_lane_count;
169}
170
171static int
ea5b213a 172intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 173{
7183dc29 174 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 175
176 switch (max_link_bw) {
177 case DP_LINK_BW_1_62:
178 case DP_LINK_BW_2_7:
179 break;
180 default:
181 max_link_bw = DP_LINK_BW_1_62;
182 break;
183 }
184 return max_link_bw;
185}
186
187static int
188intel_dp_link_clock(uint8_t link_bw)
189{
190 if (link_bw == DP_LINK_BW_2_7)
191 return 270000;
192 else
193 return 162000;
194}
195
cd9dde44
AJ		 196/*
197 * The units on the numbers in the next two are... bizarre. Examples will
198 * make it clearer; this one parallels an example in the eDP spec.
199 *
200 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
201 *
202 * 270000 * 1 * 8 / 10 == 216000
203 *
204 * The actual data capacity of that configuration is 2.16Gbit/s, so the
205 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
206 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
207 * 119000. At 18bpp that's 2142000 kilobits per second.
208 *
209 * Thus the strange-looking division by 10 in intel_dp_link_required, to
210 * get the result in decakilobits instead of kilobits.
211 */
212
a4fc5ed6 213static int
c898261c 214intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 215{
cd9dde44 216 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 217}
218
fe27d53e
DA		 219static int
220intel_dp_max_data_rate(int max_link_clock, int max_lanes)
221{
222 return (max_link_clock * max_lanes * 8) / 10;
223}
224
c4867936
DV		 225static bool
226intel_dp_adjust_dithering(struct intel_dp *intel_dp,
227 struct drm_display_mode *mode,
228 struct drm_display_mode *adjusted_mode)
229{
230 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
231 int max_lanes = intel_dp_max_lane_count(intel_dp);
232 int max_rate, mode_rate;
233
234 mode_rate = intel_dp_link_required(mode->clock, 24);
235 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
236
237 if (mode_rate > max_rate) {
238 mode_rate = intel_dp_link_required(mode->clock, 18);
239 if (mode_rate > max_rate)
240 return false;
241
242 if (adjusted_mode)
243 adjusted_mode->private_flags
244 |= INTEL_MODE_DP_FORCE_6BPC;
245
246 return true;
247 }
248
249 return true;
250}
251
a4fc5ed6
KP		 252static int
253intel_dp_mode_valid(struct drm_connector *connector,
254 struct drm_display_mode *mode)
255{
df0e9248 256 struct intel_dp *intel_dp = intel_attached_dp(connector);
a4fc5ed6 257
d15456de
KP		 258 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
259 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
7de56f43
ZY		 260 return MODE_PANEL;
261
d15456de 262 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
7de56f43
ZY		 263 return MODE_PANEL;
264 }
265
c4867936
DV		 266 if (!intel_dp_adjust_dithering(intel_dp, mode, NULL))
267 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 268
269 if (mode->clock < 10000)
270 return MODE_CLOCK_LOW;
271
0af78a2b
DV		 272 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
273 return MODE_H_ILLEGAL;
274
a4fc5ed6
KP		 275 return MODE_OK;
276}
277
278static uint32_t
279pack_aux(uint8_t *src, int src_bytes)
280{
281 int i;
282 uint32_t v = 0;
283
284 if (src_bytes > 4)
285 src_bytes = 4;
286 for (i = 0; i < src_bytes; i++)
287 v |= ((uint32_t) src[i]) << ((3-i) * 8);
288 return v;
289}
290
291static void
292unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
293{
294 int i;
295 if (dst_bytes > 4)
296 dst_bytes = 4;
297 for (i = 0; i < dst_bytes; i++)
298 dst[i] = src >> ((3-i) * 8);
299}
300
fb0f8fbf
KP		 301/* hrawclock is 1/4 the FSB frequency */
302static int
303intel_hrawclk(struct drm_device *dev)
304{
305 struct drm_i915_private *dev_priv = dev->dev_private;
306 uint32_t clkcfg;
307
308 clkcfg = I915_READ(CLKCFG);
309 switch (clkcfg & CLKCFG_FSB_MASK) {
310 case CLKCFG_FSB_400:
311 return 100;
312 case CLKCFG_FSB_533:
313 return 133;
314 case CLKCFG_FSB_667:
315 return 166;
316 case CLKCFG_FSB_800:
317 return 200;
318 case CLKCFG_FSB_1067:
319 return 266;
320 case CLKCFG_FSB_1333:
321 return 333;
322 /* these two are just a guess; one of them might be right */
323 case CLKCFG_FSB_1600:
324 case CLKCFG_FSB_1600_ALT:
325 return 400;
326 default:
327 return 133;
328 }
329}
330
ebf33b18
KP		 331static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
332{
333 struct drm_device *dev = intel_dp->base.base.dev;
334 struct drm_i915_private *dev_priv = dev->dev_private;
335
336 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
337}
338
339static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
340{
341 struct drm_device *dev = intel_dp->base.base.dev;
342 struct drm_i915_private *dev_priv = dev->dev_private;
343
344 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
345}
346
9b984dae
KP		 347static void
348intel_dp_check_edp(struct intel_dp *intel_dp)
349{
350 struct drm_device *dev = intel_dp->base.base.dev;
351 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 352
9b984dae
KP		 353 if (!is_edp(intel_dp))
354 return;
ebf33b18 355 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 356 WARN(1, "eDP powered off while attempting aux channel communication.\n");
357 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
ebf33b18 358 I915_READ(PCH_PP_STATUS),
9b984dae
KP		 359 I915_READ(PCH_PP_CONTROL));
360 }
361}
362
a4fc5ed6 363static int
ea5b213a 364intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 365 uint8_t *send, int send_bytes,
366 uint8_t *recv, int recv_size)
367{
ea5b213a 368 uint32_t output_reg = intel_dp->output_reg;
4ef69c7a 369 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6
KP		 370 struct drm_i915_private *dev_priv = dev->dev_private;
371 uint32_t ch_ctl = output_reg + 0x10;
372 uint32_t ch_data = ch_ctl + 4;
373 int i;
374 int recv_bytes;
a4fc5ed6 375 uint32_t status;
fb0f8fbf 376 uint32_t aux_clock_divider;
6b4e0a93 377 int try, precharge;
a4fc5ed6 378
9b984dae 379 intel_dp_check_edp(intel_dp);
a4fc5ed6 380 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 381 * and would like to run at 2MHz. So, take the
382 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 383 *
384 * Note that PCH attached eDP panels should use a 125MHz input
385 * clock divider.
a4fc5ed6 386 */
1c95822a 387 if (is_cpu_edp(intel_dp)) {
1a2eb460
KP		 388 if (IS_GEN6(dev) || IS_GEN7(dev))
389 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 390 else
391 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
392 } else if (HAS_PCH_SPLIT(dev))
6919132e 393 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
5eb08b69
ZW		 394 else
395 aux_clock_divider = intel_hrawclk(dev) / 2;
396
6b4e0a93
DV		 397 if (IS_GEN6(dev))
398 precharge = 3;
399 else
400 precharge = 5;
401
11bee43e
JB		 402 /* Try to wait for any previous AUX channel activity */
403 for (try = 0; try < 3; try++) {
404 status = I915_READ(ch_ctl);
405 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
406 break;
407 msleep(1);
408 }
409
410 if (try == 3) {
411 WARN(1, "dp_aux_ch not started status 0x%08x\n",
412 I915_READ(ch_ctl));
4f7f7b7e
CW		 413 return -EBUSY;
414 }
415
fb0f8fbf
KP		 416 /* Must try at least 3 times according to DP spec */
417 for (try = 0; try < 5; try++) {
418 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 419 for (i = 0; i < send_bytes; i += 4)
420 I915_WRITE(ch_data + i,
421 pack_aux(send + i, send_bytes - i));
0206e353 422
fb0f8fbf 423 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 424 I915_WRITE(ch_ctl,
425 DP_AUX_CH_CTL_SEND_BUSY |
426 DP_AUX_CH_CTL_TIME_OUT_400us |
427 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
428 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
429 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
430 DP_AUX_CH_CTL_DONE |
431 DP_AUX_CH_CTL_TIME_OUT_ERROR |
432 DP_AUX_CH_CTL_RECEIVE_ERROR);
fb0f8fbf 433 for (;;) {
fb0f8fbf
KP		 434 status = I915_READ(ch_ctl);
435 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
436 break;
4f7f7b7e 437 udelay(100);
fb0f8fbf 438 }
0206e353 439
fb0f8fbf 440 /* Clear done status and any errors */
4f7f7b7e
CW		 441 I915_WRITE(ch_ctl,
442 status |
443 DP_AUX_CH_CTL_DONE |
444 DP_AUX_CH_CTL_TIME_OUT_ERROR |
445 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 446
447 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
448 DP_AUX_CH_CTL_RECEIVE_ERROR))
449 continue;
4f7f7b7e 450 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 451 break;
452 }
453
a4fc5ed6 454 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 455 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
a5b3da54 456 return -EBUSY;
a4fc5ed6
KP		 457 }
458
459 /* Check for timeout or receive error.
460 * Timeouts occur when the sink is not connected
461 */
a5b3da54 462 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 463 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
a5b3da54
KP		 464 return -EIO;
465 }
1ae8c0a5
KP		 466
467 /* Timeouts occur when the device isn't connected, so they're
468 * "normal" -- don't fill the kernel log with these */
a5b3da54 469 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 470 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
a5b3da54 471 return -ETIMEDOUT;
a4fc5ed6
KP		 472 }
473
474 /* Unload any bytes sent back from the other side */
475 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
476 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 477 if (recv_bytes > recv_size)
478 recv_bytes = recv_size;
0206e353 479
4f7f7b7e
CW		 480 for (i = 0; i < recv_bytes; i += 4)
481 unpack_aux(I915_READ(ch_data + i),
482 recv + i, recv_bytes - i);
a4fc5ed6
KP		 483
484 return recv_bytes;
485}
486
487/* Write data to the aux channel in native mode */
488static int
ea5b213a 489intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 490 uint16_t address, uint8_t *send, int send_bytes)
491{
492 int ret;
493 uint8_t msg[20];
494 int msg_bytes;
495 uint8_t ack;
496
9b984dae 497 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 498 if (send_bytes > 16)
499 return -1;
500 msg[0] = AUX_NATIVE_WRITE << 4;
501 msg[1] = address >> 8;
eebc863e 502 msg[2] = address & 0xff;
a4fc5ed6
KP		 503 msg[3] = send_bytes - 1;
504 memcpy(&msg[4], send, send_bytes);
505 msg_bytes = send_bytes + 4;
506 for (;;) {
ea5b213a 507 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 508 if (ret < 0)
509 return ret;
510 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
511 break;
512 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
513 udelay(100);
514 else
a5b3da54 515 return -EIO;
a4fc5ed6
KP		 516 }
517 return send_bytes;
518}
519
520/* Write a single byte to the aux channel in native mode */
521static int
ea5b213a 522intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 523 uint16_t address, uint8_t byte)
524{
ea5b213a 525 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 526}
527
528/* read bytes from a native aux channel */
529static int
ea5b213a 530intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 531 uint16_t address, uint8_t *recv, int recv_bytes)
532{
533 uint8_t msg[4];
534 int msg_bytes;
535 uint8_t reply[20];
536 int reply_bytes;
537 uint8_t ack;
538 int ret;
539
9b984dae 540 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 541 msg[0] = AUX_NATIVE_READ << 4;
542 msg[1] = address >> 8;
543 msg[2] = address & 0xff;
544 msg[3] = recv_bytes - 1;
545
546 msg_bytes = 4;
547 reply_bytes = recv_bytes + 1;
548
549 for (;;) {
ea5b213a 550 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 551 reply, reply_bytes);
a5b3da54
KP		 552 if (ret == 0)
553 return -EPROTO;
554 if (ret < 0)
a4fc5ed6
KP		 555 return ret;
556 ack = reply[0];
557 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
558 memcpy(recv, reply + 1, ret - 1);
559 return ret - 1;
560 }
561 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
562 udelay(100);
563 else
a5b3da54 564 return -EIO;
a4fc5ed6
KP		 565 }
566}
567
568static int
ab2c0672
DA		 569intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
570 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 571{
ab2c0672 572 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 573 struct intel_dp *intel_dp = container_of(adapter,
574 struct intel_dp,
575 adapter);
ab2c0672
DA		 576 uint16_t address = algo_data->address;
577 uint8_t msg[5];
578 uint8_t reply[2];
8316f337 579 unsigned retry;
ab2c0672
DA		 580 int msg_bytes;
581 int reply_bytes;
582 int ret;
583
9b984dae 584 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 585 /* Set up the command byte */
586 if (mode & MODE_I2C_READ)
587 msg[0] = AUX_I2C_READ << 4;
588 else
589 msg[0] = AUX_I2C_WRITE << 4;
590
591 if (!(mode & MODE_I2C_STOP))
592 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 593
ab2c0672
DA		 594 msg[1] = address >> 8;
595 msg[2] = address;
596
597 switch (mode) {
598 case MODE_I2C_WRITE:
599 msg[3] = 0;
600 msg[4] = write_byte;
601 msg_bytes = 5;
602 reply_bytes = 1;
603 break;
604 case MODE_I2C_READ:
605 msg[3] = 0;
606 msg_bytes = 4;
607 reply_bytes = 2;
608 break;
609 default:
610 msg_bytes = 3;
611 reply_bytes = 1;
612 break;
613 }
614
8316f337
DF		 615 for (retry = 0; retry < 5; retry++) {
616 ret = intel_dp_aux_ch(intel_dp,
617 msg, msg_bytes,
618 reply, reply_bytes);
ab2c0672 619 if (ret < 0) {
3ff99164 620 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 621 return ret;
622 }
8316f337
DF		 623
624 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
625 case AUX_NATIVE_REPLY_ACK:
626 /* I2C-over-AUX Reply field is only valid
627 * when paired with AUX ACK.
628 */
629 break;
630 case AUX_NATIVE_REPLY_NACK:
631 DRM_DEBUG_KMS("aux_ch native nack\n");
632 return -EREMOTEIO;
633 case AUX_NATIVE_REPLY_DEFER:
634 udelay(100);
635 continue;
636 default:
637 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
638 reply[0]);
639 return -EREMOTEIO;
640 }
641
ab2c0672
DA		 642 switch (reply[0] & AUX_I2C_REPLY_MASK) {
643 case AUX_I2C_REPLY_ACK:
644 if (mode == MODE_I2C_READ) {
645 *read_byte = reply[1];
646 }
647 return reply_bytes - 1;
648 case AUX_I2C_REPLY_NACK:
8316f337 649 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 650 return -EREMOTEIO;
651 case AUX_I2C_REPLY_DEFER:
8316f337 652 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 653 udelay(100);
654 break;
655 default:
8316f337 656 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 657 return -EREMOTEIO;
658 }
659 }
8316f337
DF		 660
661 DRM_ERROR("too many retries, giving up\n");
662 return -EREMOTEIO;
a4fc5ed6
KP		 663}
664
0b5c541b 665static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
bd943159 666static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
0b5c541b 667
a4fc5ed6 668static int
ea5b213a 669intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 670 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 671{
0b5c541b
KP		 672 int ret;
673
d54e9d28 674 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 675 intel_dp->algo.running = false;
676 intel_dp->algo.address = 0;
677 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
678
0206e353 679 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 680 intel_dp->adapter.owner = THIS_MODULE;
681 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 682 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 683 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
684 intel_dp->adapter.algo_data = &intel_dp->algo;
685 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
686
0b5c541b
KP		 687 ironlake_edp_panel_vdd_on(intel_dp);
688 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 689 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 690 return ret;
a4fc5ed6
KP		 691}
692
693static bool
694intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
695 struct drm_display_mode *adjusted_mode)
696{
0d3a1bee 697 struct drm_device *dev = encoder->dev;
ea5b213a 698 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
a4fc5ed6 699 int lane_count, clock;
ea5b213a
CW		 700 int max_lane_count = intel_dp_max_lane_count(intel_dp);
701 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 702 int bpp, mode_rate;
a4fc5ed6
KP		 703 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
704
d15456de
KP		 705 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
706 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
1d8e1c75
CW		 707 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
708 mode, adjusted_mode);
0d3a1bee
ZY		 709 /*
710 * the mode->clock is used to calculate the Data&Link M/N
711 * of the pipe. For the eDP the fixed clock should be used.
712 */
d15456de 713 mode->clock = intel_dp->panel_fixed_mode->clock;
0d3a1bee
ZY		 714 }
715
0af78a2b
DV		 716 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
717 return false;
718
083f9560
DV		 719 DRM_DEBUG_KMS("DP link computation with max lane count %i "
720 "max bw %02x pixel clock %iKHz\n",
721 max_lane_count, bws[max_clock], mode->clock);
722
c4867936
DV		 723 if (!intel_dp_adjust_dithering(intel_dp, mode, adjusted_mode))
724 return false;
725
726 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
083f9560 727 mode_rate = intel_dp_link_required(mode->clock, bpp);
c4867936 728
a4fc5ed6
KP		 729 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
730 for (clock = 0; clock <= max_clock; clock++) {
fe27d53e 731 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
a4fc5ed6 732
083f9560 733 if (mode_rate <= link_avail) {
ea5b213a
CW		 734 intel_dp->link_bw = bws[clock];
735 intel_dp->lane_count = lane_count;
736 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
083f9560
DV		 737 DRM_DEBUG_KMS("DP link bw %02x lane "
738 "count %d clock %d bpp %d\n",
ea5b213a 739 intel_dp->link_bw, intel_dp->lane_count,
083f9560
DV		 740 adjusted_mode->clock, bpp);
741 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
742 mode_rate, link_avail);
a4fc5ed6
KP		 743 return true;
744 }
745 }
746 }
fe27d53e 747
a4fc5ed6
KP		 748 return false;
749}
750
751struct intel_dp_m_n {
752 uint32_t tu;
753 uint32_t gmch_m;
754 uint32_t gmch_n;
755 uint32_t link_m;
756 uint32_t link_n;
757};
758
759static void
760intel_reduce_ratio(uint32_t *num, uint32_t *den)
761{
762 while (*num > 0xffffff || *den > 0xffffff) {
763 *num >>= 1;
764 *den >>= 1;
765 }
766}
767
768static void
36e83a18 769intel_dp_compute_m_n(int bpp,
a4fc5ed6
KP		 770 int nlanes,
771 int pixel_clock,
772 int link_clock,
773 struct intel_dp_m_n *m_n)
774{
775 m_n->tu = 64;
36e83a18 776 m_n->gmch_m = (pixel_clock * bpp) >> 3;
a4fc5ed6
KP		 777 m_n->gmch_n = link_clock * nlanes;
778 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
779 m_n->link_m = pixel_clock;
780 m_n->link_n = link_clock;
781 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
782}
783
784void
785intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
786 struct drm_display_mode *adjusted_mode)
787{
788 struct drm_device *dev = crtc->dev;
789 struct drm_mode_config *mode_config = &dev->mode_config;
55f78c43 790 struct drm_encoder *encoder;
a4fc5ed6
KP		 791 struct drm_i915_private *dev_priv = dev->dev_private;
792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
858fa035 793 int lane_count = 4;
a4fc5ed6 794 struct intel_dp_m_n m_n;
9db4a9c7 795 int pipe = intel_crtc->pipe;
a4fc5ed6
KP		 796
797 /*
21d40d37 798 * Find the lane count in the intel_encoder private
a4fc5ed6 799 */
55f78c43 800 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
ea5b213a 801 struct intel_dp *intel_dp;
a4fc5ed6 802
d8201ab6 803 if (encoder->crtc != crtc)
a4fc5ed6
KP		 804 continue;
805
ea5b213a 806 intel_dp = enc_to_intel_dp(encoder);
9a10f401
KP		 807 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
808 intel_dp->base.type == INTEL_OUTPUT_EDP)
809 {
ea5b213a 810 lane_count = intel_dp->lane_count;
51190667 811 break;
a4fc5ed6
KP		 812 }
813 }
814
815 /*
816 * Compute the GMCH and Link ratios. The '3' here is
817 * the number of bytes_per_pixel post-LUT, which we always
818 * set up for 8-bits of R/G/B, or 3 bytes total.
819 */
858fa035 820 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
a4fc5ed6
KP		 821 mode->clock, adjusted_mode->clock, &m_n);
822
c619eed4 823 if (HAS_PCH_SPLIT(dev)) {
9db4a9c7
JB		 824 I915_WRITE(TRANSDATA_M1(pipe),
825 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
826 m_n.gmch_m);
827 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
828 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
829 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
a4fc5ed6 830 } else {
9db4a9c7
JB		 831 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
832 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
833 m_n.gmch_m);
834 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
835 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
836 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
a4fc5ed6
KP		 837 }
838}
839
f01eca2e
KP		 840static void ironlake_edp_pll_on(struct drm_encoder *encoder);
841static void ironlake_edp_pll_off(struct drm_encoder *encoder);
842
a4fc5ed6
KP		 843static void
844intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
845 struct drm_display_mode *adjusted_mode)
846{
e3421a18 847 struct drm_device *dev = encoder->dev;
417e822d 848 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 849 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4ef69c7a 850 struct drm_crtc *crtc = intel_dp->base.base.crtc;
a4fc5ed6
KP		 851 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
852
f01eca2e
KP		 853 /* Turn on the eDP PLL if needed */
854 if (is_edp(intel_dp)) {
855 if (!is_pch_edp(intel_dp))
856 ironlake_edp_pll_on(encoder);
857 else
858 ironlake_edp_pll_off(encoder);
859 }
860
417e822d 861 /*
1a2eb460 862 * There are four kinds of DP registers:
417e822d
KP		 863 *
864 * IBX PCH
1a2eb460
KP		 865 * SNB CPU
866 * IVB CPU
417e822d
KP		 867 * CPT PCH
868 *
869 * IBX PCH and CPU are the same for almost everything,
870 * except that the CPU DP PLL is configured in this
871 * register
872 *
873 * CPT PCH is quite different, having many bits moved
874 * to the TRANS_DP_CTL register instead. That
875 * configuration happens (oddly) in ironlake_pch_enable
876 */
9c9e7927 877
417e822d
KP		 878 /* Preserve the BIOS-computed detected bit. This is
879 * supposed to be read-only.
880 */
881 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
882 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 883
417e822d
KP		 884 /* Handle DP bits in common between all three register formats */
885
886 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 887
ea5b213a 888 switch (intel_dp->lane_count) {
a4fc5ed6 889 case 1:
ea5b213a 890 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 891 break;
892 case 2:
ea5b213a 893 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 894 break;
895 case 4:
ea5b213a 896 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 897 break;
898 }
e0dac65e
WF		 899 if (intel_dp->has_audio) {
900 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
901 pipe_name(intel_crtc->pipe));
ea5b213a 902 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 903 intel_write_eld(encoder, adjusted_mode);
904 }
ea5b213a
CW		 905 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
906 intel_dp->link_configuration[0] = intel_dp->link_bw;
907 intel_dp->link_configuration[1] = intel_dp->lane_count;
a2cab1b2 908 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
a4fc5ed6 909 /*
9962c925 910 * Check for DPCD version > 1.1 and enhanced framing support
a4fc5ed6 911 */
7183dc29
JB		 912 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
913 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
ea5b213a 914 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
a4fc5ed6
KP		 915 }
916
417e822d 917 /* Split out the IBX/CPU vs CPT settings */
32f9d658 918
1a2eb460
KP		 919 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
920 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
921 intel_dp->DP |= DP_SYNC_HS_HIGH;
922 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
923 intel_dp->DP |= DP_SYNC_VS_HIGH;
924 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
925
926 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
927 intel_dp->DP |= DP_ENHANCED_FRAMING;
928
929 intel_dp->DP |= intel_crtc->pipe << 29;
930
931 /* don't miss out required setting for eDP */
932 intel_dp->DP |= DP_PLL_ENABLE;
933 if (adjusted_mode->clock < 200000)
934 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
935 else
936 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
937 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
417e822d
KP		 938 intel_dp->DP |= intel_dp->color_range;
939
940 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
941 intel_dp->DP |= DP_SYNC_HS_HIGH;
942 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
943 intel_dp->DP |= DP_SYNC_VS_HIGH;
944 intel_dp->DP |= DP_LINK_TRAIN_OFF;
945
946 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
947 intel_dp->DP |= DP_ENHANCED_FRAMING;
948
949 if (intel_crtc->pipe == 1)
950 intel_dp->DP |= DP_PIPEB_SELECT;
951
952 if (is_cpu_edp(intel_dp)) {
953 /* don't miss out required setting for eDP */
954 intel_dp->DP |= DP_PLL_ENABLE;
955 if (adjusted_mode->clock < 200000)
956 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
957 else
958 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
959 }
960 } else {
961 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 962 }
a4fc5ed6
KP		 963}
964
99ea7127
KP		 965#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
966#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
967
968#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
969#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
970
971#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
972#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
973
974static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
975 u32 mask,
976 u32 value)
bd943159 977{
99ea7127
KP		 978 struct drm_device *dev = intel_dp->base.base.dev;
979 struct drm_i915_private *dev_priv = dev->dev_private;
32ce697c 980
99ea7127
KP		 981 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
982 mask, value,
983 I915_READ(PCH_PP_STATUS),
984 I915_READ(PCH_PP_CONTROL));
32ce697c 985
99ea7127
KP		 986 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
987 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
988 I915_READ(PCH_PP_STATUS),
989 I915_READ(PCH_PP_CONTROL));
32ce697c 990 }
99ea7127 991}
32ce697c 992
99ea7127
KP		 993static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
994{
995 DRM_DEBUG_KMS("Wait for panel power on\n");
996 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 997}
998
99ea7127
KP		 999static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1000{
1001 DRM_DEBUG_KMS("Wait for panel power off time\n");
1002 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1003}
1004
1005static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1006{
1007 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1008 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1009}
1010
1011
832dd3c1
KP		 1012/* Read the current pp_control value, unlocking the register if it
1013 * is locked
1014 */
1015
1016static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1017{
1018 u32 control = I915_READ(PCH_PP_CONTROL);
1019
1020 control &= ~PANEL_UNLOCK_MASK;
1021 control |= PANEL_UNLOCK_REGS;
1022 return control;
bd943159
KP		 1023}
1024
5d613501
JB		 1025static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1026{
1027 struct drm_device *dev = intel_dp->base.base.dev;
1028 struct drm_i915_private *dev_priv = dev->dev_private;
1029 u32 pp;
1030
97af61f5
KP		 1031 if (!is_edp(intel_dp))
1032 return;
f01eca2e 1033 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 1034
bd943159
KP		 1035 WARN(intel_dp->want_panel_vdd,
1036 "eDP VDD already requested on\n");
1037
1038 intel_dp->want_panel_vdd = true;
99ea7127 1039
bd943159
KP		 1040 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1041 DRM_DEBUG_KMS("eDP VDD already on\n");
1042 return;
1043 }
1044
99ea7127
KP		 1045 if (!ironlake_edp_have_panel_power(intel_dp))
1046 ironlake_wait_panel_power_cycle(intel_dp);
1047
832dd3c1 1048 pp = ironlake_get_pp_control(dev_priv);
5d613501
JB		 1049 pp |= EDP_FORCE_VDD;
1050 I915_WRITE(PCH_PP_CONTROL, pp);
1051 POSTING_READ(PCH_PP_CONTROL);
f01eca2e
KP		 1052 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1053 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
ebf33b18
KP		 1054
1055 /*
1056 * If the panel wasn't on, delay before accessing aux channel
1057 */
1058 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1059 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1060 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1061 }
5d613501
JB		 1062}
1063
bd943159 1064static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501
JB		 1065{
1066 struct drm_device *dev = intel_dp->base.base.dev;
1067 struct drm_i915_private *dev_priv = dev->dev_private;
1068 u32 pp;
1069
bd943159 1070 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
832dd3c1 1071 pp = ironlake_get_pp_control(dev_priv);
bd943159
KP		 1072 pp &= ~EDP_FORCE_VDD;
1073 I915_WRITE(PCH_PP_CONTROL, pp);
1074 POSTING_READ(PCH_PP_CONTROL);
1075
1076 /* Make sure sequencer is idle before allowing subsequent activity */
1077 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1078 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
99ea7127
KP		 1079
1080 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1081 }
1082}
5d613501 1083
bd943159
KP		 1084static void ironlake_panel_vdd_work(struct work_struct *__work)
1085{
1086 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1087 struct intel_dp, panel_vdd_work);
1088 struct drm_device *dev = intel_dp->base.base.dev;
1089
627f7675 1090 mutex_lock(&dev->mode_config.mutex);
bd943159 1091 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1092 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1093}
1094
1095static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1096{
97af61f5
KP		 1097 if (!is_edp(intel_dp))
1098 return;
5d613501 1099
bd943159
KP		 1100 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1101 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1102
bd943159
KP		 1103 intel_dp->want_panel_vdd = false;
1104
1105 if (sync) {
1106 ironlake_panel_vdd_off_sync(intel_dp);
1107 } else {
1108 /*
1109 * Queue the timer to fire a long
1110 * time from now (relative to the power down delay)
1111 * to keep the panel power up across a sequence of operations
1112 */
1113 schedule_delayed_work(&intel_dp->panel_vdd_work,
1114 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1115 }
5d613501
JB		 1116}
1117
86a3073e 1118static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1119{
01cb9ea6 1120 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1121 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1122 u32 pp;
9934c132 1123
97af61f5 1124 if (!is_edp(intel_dp))
bd943159 1125 return;
99ea7127
KP		 1126
1127 DRM_DEBUG_KMS("Turn eDP power on\n");
1128
1129 if (ironlake_edp_have_panel_power(intel_dp)) {
1130 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1131 return;
99ea7127 1132 }
9934c132 1133
99ea7127 1134 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1135
99ea7127 1136 pp = ironlake_get_pp_control(dev_priv);
05ce1a49
KP		 1137 if (IS_GEN5(dev)) {
1138 /* ILK workaround: disable reset around power sequence */
1139 pp &= ~PANEL_POWER_RESET;
1140 I915_WRITE(PCH_PP_CONTROL, pp);
1141 POSTING_READ(PCH_PP_CONTROL);
1142 }
37c6c9b0 1143
1c0ae80a 1144 pp |= POWER_TARGET_ON;
99ea7127
KP		 1145 if (!IS_GEN5(dev))
1146 pp |= PANEL_POWER_RESET;
1147
9934c132 1148 I915_WRITE(PCH_PP_CONTROL, pp);
01cb9ea6 1149 POSTING_READ(PCH_PP_CONTROL);
9934c132 1150
99ea7127 1151 ironlake_wait_panel_on(intel_dp);
9934c132 1152
05ce1a49
KP		 1153 if (IS_GEN5(dev)) {
1154 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1155 I915_WRITE(PCH_PP_CONTROL, pp);
1156 POSTING_READ(PCH_PP_CONTROL);
1157 }
9934c132
JB		 1158}
1159
99ea7127 1160static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1161{
99ea7127 1162 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1163 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1164 u32 pp;
9934c132 1165
97af61f5
KP		 1166 if (!is_edp(intel_dp))
1167 return;
37c6c9b0 1168
99ea7127 1169 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1170
6cb49835 1171 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1172
99ea7127 1173 pp = ironlake_get_pp_control(dev_priv);
6cb49835 1174 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_BLC_ENABLE);
99ea7127
KP		 1175 I915_WRITE(PCH_PP_CONTROL, pp);
1176 POSTING_READ(PCH_PP_CONTROL);
9934c132 1177
99ea7127 1178 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1179}
1180
86a3073e 1181static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1182{
f01eca2e 1183 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1184 struct drm_i915_private *dev_priv = dev->dev_private;
1185 u32 pp;
1186
f01eca2e
KP		 1187 if (!is_edp(intel_dp))
1188 return;
1189
28c97730 1190 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1191 /*
1192 * If we enable the backlight right away following a panel power
1193 * on, we may see slight flicker as the panel syncs with the eDP
1194 * link. So delay a bit to make sure the image is solid before
1195 * allowing it to appear.
1196 */
f01eca2e 1197 msleep(intel_dp->backlight_on_delay);
832dd3c1 1198 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1199 pp |= EDP_BLC_ENABLE;
1200 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e 1201 POSTING_READ(PCH_PP_CONTROL);
32f9d658
ZW		 1202}
1203
86a3073e 1204static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1205{
f01eca2e 1206 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1207 struct drm_i915_private *dev_priv = dev->dev_private;
1208 u32 pp;
1209
f01eca2e
KP		 1210 if (!is_edp(intel_dp))
1211 return;
1212
28c97730 1213 DRM_DEBUG_KMS("\n");
832dd3c1 1214 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1215 pp &= ~EDP_BLC_ENABLE;
1216 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e
KP		 1217 POSTING_READ(PCH_PP_CONTROL);
1218 msleep(intel_dp->backlight_off_delay);
32f9d658 1219}
a4fc5ed6 1220
d240f20f
JB		 1221static void ironlake_edp_pll_on(struct drm_encoder *encoder)
1222{
1223 struct drm_device *dev = encoder->dev;
1224 struct drm_i915_private *dev_priv = dev->dev_private;
1225 u32 dpa_ctl;
1226
1227 DRM_DEBUG_KMS("\n");
1228 dpa_ctl = I915_READ(DP_A);
298b0b39 1229 dpa_ctl |= DP_PLL_ENABLE;
d240f20f 1230 I915_WRITE(DP_A, dpa_ctl);
298b0b39
JB		 1231 POSTING_READ(DP_A);
1232 udelay(200);
d240f20f
JB		 1233}
1234
1235static void ironlake_edp_pll_off(struct drm_encoder *encoder)
1236{
1237 struct drm_device *dev = encoder->dev;
1238 struct drm_i915_private *dev_priv = dev->dev_private;
1239 u32 dpa_ctl;
1240
1241 dpa_ctl = I915_READ(DP_A);
298b0b39 1242 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1243 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1244 POSTING_READ(DP_A);
d240f20f
JB		 1245 udelay(200);
1246}
1247
c7ad3810
JB		 1248/* If the sink supports it, try to set the power state appropriately */
1249static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1250{
1251 int ret, i;
1252
1253 /* Should have a valid DPCD by this point */
1254 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1255 return;
1256
1257 if (mode != DRM_MODE_DPMS_ON) {
1258 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1259 DP_SET_POWER_D3);
1260 if (ret != 1)
1261 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1262 } else {
1263 /*
1264 * When turning on, we need to retry for 1ms to give the sink
1265 * time to wake up.
1266 */
1267 for (i = 0; i < 3; i++) {
1268 ret = intel_dp_aux_native_write_1(intel_dp,
1269 DP_SET_POWER,
1270 DP_SET_POWER_D0);
1271 if (ret == 1)
1272 break;
1273 msleep(1);
1274 }
1275 }
1276}
1277
d240f20f
JB		 1278static void intel_dp_prepare(struct drm_encoder *encoder)
1279{
1280 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
d240f20f 1281
6cb49835
DV		 1282
1283 /* Make sure the panel is off before trying to change the mode. But also
1284 * ensure that we have vdd while we switch off the panel. */
1285 ironlake_edp_panel_vdd_on(intel_dp);
21264c63
KP		 1286 ironlake_edp_backlight_off(intel_dp);
1287 ironlake_edp_panel_off(intel_dp);
1288
c7ad3810 1289 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
21264c63 1290 intel_dp_link_down(intel_dp);
bd943159 1291 ironlake_edp_panel_vdd_off(intel_dp, false);
d240f20f
JB		 1292}
1293
1294static void intel_dp_commit(struct drm_encoder *encoder)
1295{
1296 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
d4270e57
JB		 1297 struct drm_device *dev = encoder->dev;
1298 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
5d613501 1299
97af61f5 1300 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1301 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1302 intel_dp_start_link_train(intel_dp);
97af61f5 1303 ironlake_edp_panel_on(intel_dp);
bd943159 1304 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1305 intel_dp_complete_link_train(intel_dp);
f01eca2e 1306 ironlake_edp_backlight_on(intel_dp);
d2b996ac
KP		 1307
1308 intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
d4270e57
JB		 1309
1310 if (HAS_PCH_CPT(dev))
1311 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
d240f20f
JB		 1312}
1313
a4fc5ed6
KP		 1314static void
1315intel_dp_dpms(struct drm_encoder *encoder, int mode)
1316{
ea5b213a 1317 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
55f78c43 1318 struct drm_device *dev = encoder->dev;
a4fc5ed6 1319 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 1320 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
a4fc5ed6
KP		 1321
1322 if (mode != DRM_MODE_DPMS_ON) {
6cb49835
DV		 1323 /* Switching the panel off requires vdd. */
1324 ironlake_edp_panel_vdd_on(intel_dp);
21264c63
KP		 1325 ironlake_edp_backlight_off(intel_dp);
1326 ironlake_edp_panel_off(intel_dp);
1327
c7ad3810 1328 intel_dp_sink_dpms(intel_dp, mode);
736085bc 1329 intel_dp_link_down(intel_dp);
bd943159 1330 ironlake_edp_panel_vdd_off(intel_dp, false);
21264c63
KP		 1331
1332 if (is_cpu_edp(intel_dp))
1333 ironlake_edp_pll_off(encoder);
a4fc5ed6 1334 } else {
21264c63
KP		 1335 if (is_cpu_edp(intel_dp))
1336 ironlake_edp_pll_on(encoder);
1337
97af61f5 1338 ironlake_edp_panel_vdd_on(intel_dp);
c7ad3810 1339 intel_dp_sink_dpms(intel_dp, mode);
32f9d658 1340 if (!(dp_reg & DP_PORT_EN)) {
01cb9ea6 1341 intel_dp_start_link_train(intel_dp);
97af61f5 1342 ironlake_edp_panel_on(intel_dp);
bd943159 1343 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1344 intel_dp_complete_link_train(intel_dp);
bee7eb2d 1345 } else
bd943159
KP		 1346 ironlake_edp_panel_vdd_off(intel_dp, false);
1347 ironlake_edp_backlight_on(intel_dp);
a4fc5ed6 1348 }
d2b996ac 1349 intel_dp->dpms_mode = mode;
a4fc5ed6
KP		 1350}
1351
1352/*
df0c237d
JB		 1353 * Native read with retry for link status and receiver capability reads for
1354 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1355 */
1356static bool
df0c237d
JB		 1357intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1358 uint8_t *recv, int recv_bytes)
a4fc5ed6 1359{
61da5fab
JB		 1360 int ret, i;
1361
df0c237d
JB		 1362 /*
1363 * Sinks are *supposed* to come up within 1ms from an off state,
1364 * but we're also supposed to retry 3 times per the spec.
1365 */
61da5fab 1366 for (i = 0; i < 3; i++) {
df0c237d
JB		 1367 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1368 recv_bytes);
1369 if (ret == recv_bytes)
61da5fab
JB		 1370 return true;
1371 msleep(1);
1372 }
a4fc5ed6 1373
61da5fab 1374 return false;
a4fc5ed6
KP		 1375}
1376
1377/*
1378 * Fetch AUX CH registers 0x202 - 0x207 which contain
1379 * link status information
1380 */
1381static bool
93f62dad 1382intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1383{
df0c237d
JB		 1384 return intel_dp_aux_native_read_retry(intel_dp,
1385 DP_LANE0_1_STATUS,
93f62dad 1386 link_status,
df0c237d 1387 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1388}
1389
1390static uint8_t
1391intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1392 int r)
1393{
1394 return link_status[r - DP_LANE0_1_STATUS];
1395}
1396
a4fc5ed6 1397static uint8_t
93f62dad 1398intel_get_adjust_request_voltage(uint8_t adjust_request[2],
a4fc5ed6
KP		 1399 int lane)
1400{
a4fc5ed6
KP		 1401 int s = ((lane & 1) ?
1402 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1403 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
93f62dad 1404 uint8_t l = adjust_request[lane>>1];
a4fc5ed6
KP		 1405
1406 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1407}
1408
1409static uint8_t
93f62dad 1410intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
a4fc5ed6
KP		 1411 int lane)
1412{
a4fc5ed6
KP		 1413 int s = ((lane & 1) ?
1414 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1415 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
93f62dad 1416 uint8_t l = adjust_request[lane>>1];
a4fc5ed6
KP		 1417
1418 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1419}
1420
1421
1422#if 0
1423static char *voltage_names[] = {
1424 "0.4V", "0.6V", "0.8V", "1.2V"
1425};
1426static char *pre_emph_names[] = {
1427 "0dB", "3.5dB", "6dB", "9.5dB"
1428};
1429static char *link_train_names[] = {
1430 "pattern 1", "pattern 2", "idle", "off"
1431};
1432#endif
1433
1434/*
1435 * These are source-specific values; current Intel hardware supports
1436 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1437 */
a4fc5ed6
KP		 1438
1439static uint8_t
1a2eb460 1440intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1441{
1a2eb460
KP		 1442 struct drm_device *dev = intel_dp->base.base.dev;
1443
1444 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1445 return DP_TRAIN_VOLTAGE_SWING_800;
1446 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1447 return DP_TRAIN_VOLTAGE_SWING_1200;
1448 else
1449 return DP_TRAIN_VOLTAGE_SWING_800;
1450}
1451
1452static uint8_t
1453intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1454{
1455 struct drm_device *dev = intel_dp->base.base.dev;
1456
1457 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1458 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1459 case DP_TRAIN_VOLTAGE_SWING_400:
1460 return DP_TRAIN_PRE_EMPHASIS_6;
1461 case DP_TRAIN_VOLTAGE_SWING_600:
1462 case DP_TRAIN_VOLTAGE_SWING_800:
1463 return DP_TRAIN_PRE_EMPHASIS_3_5;
1464 default:
1465 return DP_TRAIN_PRE_EMPHASIS_0;
1466 }
1467 } else {
1468 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1469 case DP_TRAIN_VOLTAGE_SWING_400:
1470 return DP_TRAIN_PRE_EMPHASIS_6;
1471 case DP_TRAIN_VOLTAGE_SWING_600:
1472 return DP_TRAIN_PRE_EMPHASIS_6;
1473 case DP_TRAIN_VOLTAGE_SWING_800:
1474 return DP_TRAIN_PRE_EMPHASIS_3_5;
1475 case DP_TRAIN_VOLTAGE_SWING_1200:
1476 default:
1477 return DP_TRAIN_PRE_EMPHASIS_0;
1478 }
a4fc5ed6
KP		 1479 }
1480}
1481
1482static void
93f62dad 1483intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1484{
1485 uint8_t v = 0;
1486 uint8_t p = 0;
1487 int lane;
93f62dad 1488 uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1a2eb460
KP		 1489 uint8_t voltage_max;
1490 uint8_t preemph_max;
a4fc5ed6 1491
33a34e4e 1492 for (lane = 0; lane < intel_dp->lane_count; lane++) {
93f62dad
KP		 1493 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1494 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
a4fc5ed6
KP		 1495
1496 if (this_v > v)
1497 v = this_v;
1498 if (this_p > p)
1499 p = this_p;
1500 }
1501
1a2eb460 1502 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1503 if (v >= voltage_max)
1504 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1505
1a2eb460
KP		 1506 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1507 if (p >= preemph_max)
1508 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1509
1510 for (lane = 0; lane < 4; lane++)
33a34e4e 1511 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1512}
1513
1514static uint32_t
93f62dad 1515intel_dp_signal_levels(uint8_t train_set)
a4fc5ed6 1516{
3cf2efb1 1517 uint32_t signal_levels = 0;
a4fc5ed6 1518
3cf2efb1 1519 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1520 case DP_TRAIN_VOLTAGE_SWING_400:
1521 default:
1522 signal_levels |= DP_VOLTAGE_0_4;
1523 break;
1524 case DP_TRAIN_VOLTAGE_SWING_600:
1525 signal_levels |= DP_VOLTAGE_0_6;
1526 break;
1527 case DP_TRAIN_VOLTAGE_SWING_800:
1528 signal_levels |= DP_VOLTAGE_0_8;
1529 break;
1530 case DP_TRAIN_VOLTAGE_SWING_1200:
1531 signal_levels |= DP_VOLTAGE_1_2;
1532 break;
1533 }
3cf2efb1 1534 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1535 case DP_TRAIN_PRE_EMPHASIS_0:
1536 default:
1537 signal_levels |= DP_PRE_EMPHASIS_0;
1538 break;
1539 case DP_TRAIN_PRE_EMPHASIS_3_5:
1540 signal_levels |= DP_PRE_EMPHASIS_3_5;
1541 break;
1542 case DP_TRAIN_PRE_EMPHASIS_6:
1543 signal_levels |= DP_PRE_EMPHASIS_6;
1544 break;
1545 case DP_TRAIN_PRE_EMPHASIS_9_5:
1546 signal_levels |= DP_PRE_EMPHASIS_9_5;
1547 break;
1548 }
1549 return signal_levels;
1550}
1551
e3421a18
ZW		 1552/* Gen6's DP voltage swing and pre-emphasis control */
1553static uint32_t
1554intel_gen6_edp_signal_levels(uint8_t train_set)
1555{
3c5a62b5
YL		 1556 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1557 DP_TRAIN_PRE_EMPHASIS_MASK);
1558 switch (signal_levels) {
e3421a18 1559 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1560 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1561 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1562 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1563 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1564 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1565 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1566 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1567 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1568 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1569 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1570 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1571 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1572 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1573 default:
3c5a62b5
YL		 1574 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1575 "0x%x\n", signal_levels);
1576 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1577 }
1578}
1579
1a2eb460
KP		 1580/* Gen7's DP voltage swing and pre-emphasis control */
1581static uint32_t
1582intel_gen7_edp_signal_levels(uint8_t train_set)
1583{
1584 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1585 DP_TRAIN_PRE_EMPHASIS_MASK);
1586 switch (signal_levels) {
1587 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1588 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1589 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1590 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1591 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1592 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1593
1594 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1595 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1596 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1597 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1598
1599 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1600 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1601 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1602 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1603
1604 default:
1605 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1606 "0x%x\n", signal_levels);
1607 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1608 }
1609}
1610
a4fc5ed6
KP		 1611static uint8_t
1612intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1613 int lane)
1614{
a4fc5ed6 1615 int s = (lane & 1) * 4;
93f62dad 1616 uint8_t l = link_status[lane>>1];
a4fc5ed6
KP		 1617
1618 return (l >> s) & 0xf;
1619}
1620
1621/* Check for clock recovery is done on all channels */
1622static bool
1623intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1624{
1625 int lane;
1626 uint8_t lane_status;
1627
1628 for (lane = 0; lane < lane_count; lane++) {
1629 lane_status = intel_get_lane_status(link_status, lane);
1630 if ((lane_status & DP_LANE_CR_DONE) == 0)
1631 return false;
1632 }
1633 return true;
1634}
1635
1636/* Check to see if channel eq is done on all channels */
1637#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1638 DP_LANE_CHANNEL_EQ_DONE|\
1639 DP_LANE_SYMBOL_LOCKED)
1640static bool
93f62dad 1641intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1642{
1643 uint8_t lane_align;
1644 uint8_t lane_status;
1645 int lane;
1646
93f62dad 1647 lane_align = intel_dp_link_status(link_status,
a4fc5ed6
KP		 1648 DP_LANE_ALIGN_STATUS_UPDATED);
1649 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1650 return false;
33a34e4e 1651 for (lane = 0; lane < intel_dp->lane_count; lane++) {
93f62dad 1652 lane_status = intel_get_lane_status(link_status, lane);
a4fc5ed6
KP		 1653 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1654 return false;
1655 }
1656 return true;
1657}
1658
1659static bool
ea5b213a 1660intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1661 uint32_t dp_reg_value,
58e10eb9 1662 uint8_t dp_train_pat)
a4fc5ed6 1663{
4ef69c7a 1664 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1665 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6
KP		 1666 int ret;
1667
ea5b213a
CW		 1668 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1669 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1670
ea5b213a 1671 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1672 DP_TRAINING_PATTERN_SET,
1673 dp_train_pat);
1674
ea5b213a 1675 ret = intel_dp_aux_native_write(intel_dp,
58e10eb9 1676 DP_TRAINING_LANE0_SET,
b34f1f09
KP		 1677 intel_dp->train_set,
1678 intel_dp->lane_count);
1679 if (ret != intel_dp->lane_count)
a4fc5ed6
KP		 1680 return false;
1681
1682 return true;
1683}
1684
33a34e4e 1685/* Enable corresponding port and start training pattern 1 */
a4fc5ed6 1686static void
33a34e4e 1687intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1688{
4ef69c7a 1689 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1690 struct drm_i915_private *dev_priv = dev->dev_private;
58e10eb9 1691 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
a4fc5ed6
KP		 1692 int i;
1693 uint8_t voltage;
1694 bool clock_recovery = false;
cdb0e95b 1695 int voltage_tries, loop_tries;
e3421a18 1696 u32 reg;
ea5b213a 1697 uint32_t DP = intel_dp->DP;
a4fc5ed6 1698
e8519464
AJ		 1699 /*
1700 * On CPT we have to enable the port in training pattern 1, which
1701 * will happen below in intel_dp_set_link_train. Otherwise, enable
1702 * the port and wait for it to become active.
1703 */
1704 if (!HAS_PCH_CPT(dev)) {
1705 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1706 POSTING_READ(intel_dp->output_reg);
1707 intel_wait_for_vblank(dev, intel_crtc->pipe);
1708 }
a4fc5ed6 1709
3cf2efb1
CW		 1710 /* Write the link configuration data */
1711 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1712 intel_dp->link_configuration,
1713 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1714
1715 DP |= DP_PORT_EN;
1a2eb460
KP		 1716
1717 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
e3421a18
ZW		 1718 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1719 else
1720 DP &= ~DP_LINK_TRAIN_MASK;
33a34e4e 1721 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 1722 voltage = 0xff;
cdb0e95b
KP		 1723 voltage_tries = 0;
1724 loop_tries = 0;
a4fc5ed6
KP		 1725 clock_recovery = false;
1726 for (;;) {
33a34e4e 1727 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 1728 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1729 uint32_t signal_levels;
417e822d 1730
1a2eb460
KP		 1731
1732 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1733 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1734 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1735 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1736 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1737 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1738 } else {
93f62dad
KP		 1739 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1740 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
e3421a18
ZW		 1741 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1742 }
a4fc5ed6 1743
1a2eb460 1744 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
e3421a18
ZW		 1745 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1746 else
1747 reg = DP | DP_LINK_TRAIN_PAT_1;
1748
ea5b213a 1749 if (!intel_dp_set_link_train(intel_dp, reg,
81055854
AJ		 1750 DP_TRAINING_PATTERN_1 |
1751 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 1752 break;
a4fc5ed6
KP		 1753 /* Set training pattern 1 */
1754
3cf2efb1 1755 udelay(100);
93f62dad
KP		 1756 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1757 DRM_ERROR("failed to get link status\n");
a4fc5ed6 1758 break;
93f62dad 1759 }
a4fc5ed6 1760
93f62dad
KP		 1761 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1762 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 1763 clock_recovery = true;
1764 break;
1765 }
1766
1767 /* Check to see if we've tried the max voltage */
1768 for (i = 0; i < intel_dp->lane_count; i++)
1769 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 1770 break;
cdb0e95b
KP		 1771 if (i == intel_dp->lane_count) {
1772 ++loop_tries;
1773 if (loop_tries == 5) {
1774 DRM_DEBUG_KMS("too many full retries, give up\n");
1775 break;
1776 }
1777 memset(intel_dp->train_set, 0, 4);
1778 voltage_tries = 0;
1779 continue;
1780 }
a4fc5ed6 1781
3cf2efb1
CW		 1782 /* Check to see if we've tried the same voltage 5 times */
1783 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
cdb0e95b
KP		 1784 ++voltage_tries;
1785 if (voltage_tries == 5) {
1786 DRM_DEBUG_KMS("too many voltage retries, give up\n");
a4fc5ed6 1787 break;
cdb0e95b 1788 }
3cf2efb1 1789 } else
cdb0e95b 1790 voltage_tries = 0;
3cf2efb1 1791 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 1792
3cf2efb1 1793 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1794 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 1795 }
1796
33a34e4e
JB		 1797 intel_dp->DP = DP;
1798}
1799
1800static void
1801intel_dp_complete_link_train(struct intel_dp *intel_dp)
1802{
4ef69c7a 1803 struct drm_device *dev = intel_dp->base.base.dev;
33a34e4e
JB		 1804 struct drm_i915_private *dev_priv = dev->dev_private;
1805 bool channel_eq = false;
37f80975 1806 int tries, cr_tries;
33a34e4e
JB		 1807 u32 reg;
1808 uint32_t DP = intel_dp->DP;
1809
a4fc5ed6
KP		 1810 /* channel equalization */
1811 tries = 0;
37f80975 1812 cr_tries = 0;
a4fc5ed6
KP		 1813 channel_eq = false;
1814 for (;;) {
33a34e4e 1815 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
e3421a18 1816 uint32_t signal_levels;
93f62dad 1817 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1818
37f80975
JB		 1819 if (cr_tries > 5) {
1820 DRM_ERROR("failed to train DP, aborting\n");
1821 intel_dp_link_down(intel_dp);
1822 break;
1823 }
1824
1a2eb460
KP		 1825 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1826 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1827 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1828 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1829 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1830 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1831 } else {
93f62dad 1832 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1833 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1834 }
1835
1a2eb460 1836 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
e3421a18
ZW		 1837 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1838 else
1839 reg = DP | DP_LINK_TRAIN_PAT_2;
a4fc5ed6
KP		 1840
1841 /* channel eq pattern */
ea5b213a 1842 if (!intel_dp_set_link_train(intel_dp, reg,
81055854
AJ		 1843 DP_TRAINING_PATTERN_2 |
1844 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 1845 break;
1846
3cf2efb1 1847 udelay(400);
93f62dad 1848 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 1849 break;
a4fc5ed6 1850
37f80975 1851 /* Make sure clock is still ok */
93f62dad 1852 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 1853 intel_dp_start_link_train(intel_dp);
1854 cr_tries++;
1855 continue;
1856 }
1857
93f62dad 1858 if (intel_channel_eq_ok(intel_dp, link_status)) {
3cf2efb1
CW		 1859 channel_eq = true;
1860 break;
1861 }
a4fc5ed6 1862
37f80975
JB		 1863 /* Try 5 times, then try clock recovery if that fails */
1864 if (tries > 5) {
1865 intel_dp_link_down(intel_dp);
1866 intel_dp_start_link_train(intel_dp);
1867 tries = 0;
1868 cr_tries++;
1869 continue;
1870 }
a4fc5ed6 1871
3cf2efb1 1872 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1873 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 1874 ++tries;
869184a6 1875 }
3cf2efb1 1876
1a2eb460 1877 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
e3421a18
ZW		 1878 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1879 else
1880 reg = DP | DP_LINK_TRAIN_OFF;
1881
ea5b213a
CW		 1882 I915_WRITE(intel_dp->output_reg, reg);
1883 POSTING_READ(intel_dp->output_reg);
1884 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1885 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1886}
1887
1888static void
ea5b213a 1889intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 1890{
4ef69c7a 1891 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1892 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 1893 uint32_t DP = intel_dp->DP;
a4fc5ed6 1894
1b39d6f3
CW		 1895 if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1896 return;
1897
28c97730 1898 DRM_DEBUG_KMS("\n");
32f9d658 1899
cfcb0fc9 1900 if (is_edp(intel_dp)) {
32f9d658 1901 DP &= ~DP_PLL_ENABLE;
ea5b213a
CW		 1902 I915_WRITE(intel_dp->output_reg, DP);
1903 POSTING_READ(intel_dp->output_reg);
32f9d658
ZW		 1904 udelay(100);
1905 }
1906
1a2eb460 1907 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 1908 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 1909 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 1910 } else {
1911 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 1912 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 1913 }
fe255d00 1914 POSTING_READ(intel_dp->output_reg);
5eb08b69 1915
fe255d00 1916 msleep(17);
5eb08b69 1917
417e822d 1918 if (is_edp(intel_dp)) {
1a2eb460 1919 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
417e822d
KP		 1920 DP |= DP_LINK_TRAIN_OFF_CPT;
1921 else
1922 DP |= DP_LINK_TRAIN_OFF;
1923 }
5bddd17f 1924
1b39d6f3
CW		 1925 if (!HAS_PCH_CPT(dev) &&
1926 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
31acbcc4
CW		 1927 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1928
5bddd17f
EA		 1929 /* Hardware workaround: leaving our transcoder select
1930 * set to transcoder B while it's off will prevent the
1931 * corresponding HDMI output on transcoder A.
1932 *
1933 * Combine this with another hardware workaround:
1934 * transcoder select bit can only be cleared while the
1935 * port is enabled.
1936 */
1937 DP &= ~DP_PIPEB_SELECT;
1938 I915_WRITE(intel_dp->output_reg, DP);
1939
1940 /* Changes to enable or select take place the vblank
1941 * after being written.
1942 */
31acbcc4
CW		 1943 if (crtc == NULL) {
1944 /* We can arrive here never having been attached
1945 * to a CRTC, for instance, due to inheriting
1946 * random state from the BIOS.
1947 *
1948 * If the pipe is not running, play safe and
1949 * wait for the clocks to stabilise before
1950 * continuing.
1951 */
1952 POSTING_READ(intel_dp->output_reg);
1953 msleep(50);
1954 } else
1955 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
5bddd17f
EA		 1956 }
1957
832afda6 1958 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 1959 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1960 POSTING_READ(intel_dp->output_reg);
f01eca2e 1961 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 1962}
1963
26d61aad
KP		 1964static bool
1965intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 1966{
92fd8fd1 1967 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
0206e353 1968 sizeof(intel_dp->dpcd)) &&
92fd8fd1 1969 (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
26d61aad 1970 return true;
92fd8fd1
KP		 1971 }
1972
26d61aad 1973 return false;
92fd8fd1
KP		 1974}
1975
0d198328
AJ		 1976static void
1977intel_dp_probe_oui(struct intel_dp *intel_dp)
1978{
1979 u8 buf[3];
1980
1981 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
1982 return;
1983
351cfc34
DV		 1984 ironlake_edp_panel_vdd_on(intel_dp);
1985
0d198328
AJ		 1986 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
1987 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
1988 buf[0], buf[1], buf[2]);
1989
1990 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
1991 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
1992 buf[0], buf[1], buf[2]);
351cfc34
DV		 1993
1994 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 1995}
1996
a60f0e38
JB		 1997static bool
1998intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
1999{
2000 int ret;
2001
2002 ret = intel_dp_aux_native_read_retry(intel_dp,
2003 DP_DEVICE_SERVICE_IRQ_VECTOR,
2004 sink_irq_vector, 1);
2005 if (!ret)
2006 return false;
2007
2008 return true;
2009}
2010
2011static void
2012intel_dp_handle_test_request(struct intel_dp *intel_dp)
2013{
2014 /* NAK by default */
2015 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
2016}
2017
a4fc5ed6
KP		 2018/*
2019 * According to DP spec
2020 * 5.1.2:
2021 * 1. Read DPCD
2022 * 2. Configure link according to Receiver Capabilities
2023 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2024 * 4. Check link status on receipt of hot-plug interrupt
2025 */
2026
2027static void
ea5b213a 2028intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2029{
a60f0e38 2030 u8 sink_irq_vector;
93f62dad 2031 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2032
d2b996ac
KP		 2033 if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
2034 return;
59cd09e1 2035
4ef69c7a 2036 if (!intel_dp->base.base.crtc)
a4fc5ed6
KP		 2037 return;
2038
92fd8fd1 2039 /* Try to read receiver status if the link appears to be up */
93f62dad 2040 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2041 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2042 return;
2043 }
2044
92fd8fd1 2045 /* Now read the DPCD to see if it's actually running */
26d61aad 2046 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2047 intel_dp_link_down(intel_dp);
2048 return;
2049 }
2050
a60f0e38
JB		 2051 /* Try to read the source of the interrupt */
2052 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2053 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2054 /* Clear interrupt source */
2055 intel_dp_aux_native_write_1(intel_dp,
2056 DP_DEVICE_SERVICE_IRQ_VECTOR,
2057 sink_irq_vector);
2058
2059 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2060 intel_dp_handle_test_request(intel_dp);
2061 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2062 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2063 }
2064
93f62dad 2065 if (!intel_channel_eq_ok(intel_dp, link_status)) {
92fd8fd1
KP		 2066 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2067 drm_get_encoder_name(&intel_dp->base.base));
33a34e4e
JB		 2068 intel_dp_start_link_train(intel_dp);
2069 intel_dp_complete_link_train(intel_dp);
2070 }
a4fc5ed6 2071}
a4fc5ed6 2072
71ba9000 2073static enum drm_connector_status
26d61aad 2074intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2075{
26d61aad
KP		 2076 if (intel_dp_get_dpcd(intel_dp))
2077 return connector_status_connected;
2078 return connector_status_disconnected;
71ba9000
AJ		 2079}
2080
5eb08b69 2081static enum drm_connector_status
a9756bb5 2082ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2083{
5eb08b69
ZW		 2084 enum drm_connector_status status;
2085
fe16d949
CW		 2086 /* Can't disconnect eDP, but you can close the lid... */
2087 if (is_edp(intel_dp)) {
2088 status = intel_panel_detect(intel_dp->base.base.dev);
2089 if (status == connector_status_unknown)
2090 status = connector_status_connected;
2091 return status;
2092 }
01cb9ea6 2093
26d61aad 2094 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2095}
2096
a4fc5ed6 2097static enum drm_connector_status
a9756bb5 2098g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2099{
4ef69c7a 2100 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 2101 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 2102 uint32_t temp, bit;
5eb08b69 2103
ea5b213a 2104 switch (intel_dp->output_reg) {
a4fc5ed6
KP		 2105 case DP_B:
2106 bit = DPB_HOTPLUG_INT_STATUS;
2107 break;
2108 case DP_C:
2109 bit = DPC_HOTPLUG_INT_STATUS;
2110 break;
2111 case DP_D:
2112 bit = DPD_HOTPLUG_INT_STATUS;
2113 break;
2114 default:
2115 return connector_status_unknown;
2116 }
2117
2118 temp = I915_READ(PORT_HOTPLUG_STAT);
2119
2120 if ((temp & bit) == 0)
2121 return connector_status_disconnected;
2122
26d61aad 2123 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2124}
2125
8c241fef
KP		 2126static struct edid *
2127intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2128{
2129 struct intel_dp *intel_dp = intel_attached_dp(connector);
2130 struct edid *edid;
d6f24d0f
JB		 2131 int size;
2132
2133 if (is_edp(intel_dp)) {
2134 if (!intel_dp->edid)
2135 return NULL;
2136
2137 size = (intel_dp->edid->extensions + 1) * EDID_LENGTH;
2138 edid = kmalloc(size, GFP_KERNEL);
2139 if (!edid)
2140 return NULL;
2141
2142 memcpy(edid, intel_dp->edid, size);
2143 return edid;
2144 }
8c241fef 2145
8c241fef 2146 edid = drm_get_edid(connector, adapter);
8c241fef
KP		 2147 return edid;
2148}
2149
2150static int
2151intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2152{
2153 struct intel_dp *intel_dp = intel_attached_dp(connector);
2154 int ret;
2155
d6f24d0f
JB		 2156 if (is_edp(intel_dp)) {
2157 drm_mode_connector_update_edid_property(connector,
2158 intel_dp->edid);
2159 ret = drm_add_edid_modes(connector, intel_dp->edid);
2160 drm_edid_to_eld(connector,
2161 intel_dp->edid);
2162 connector->display_info.raw_edid = NULL;
2163 return intel_dp->edid_mode_count;
2164 }
2165
8c241fef 2166 ret = intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2167 return ret;
2168}
2169
2170
a9756bb5
ZW		 2171/**
2172 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2173 *
2174 * \return true if DP port is connected.
2175 * \return false if DP port is disconnected.
2176 */
2177static enum drm_connector_status
2178intel_dp_detect(struct drm_connector *connector, bool force)
2179{
2180 struct intel_dp *intel_dp = intel_attached_dp(connector);
2181 struct drm_device *dev = intel_dp->base.base.dev;
2182 enum drm_connector_status status;
2183 struct edid *edid = NULL;
2184
2185 intel_dp->has_audio = false;
2186
2187 if (HAS_PCH_SPLIT(dev))
2188 status = ironlake_dp_detect(intel_dp);
2189 else
2190 status = g4x_dp_detect(intel_dp);
1b9be9d0 2191
ac66ae83
AJ		 2192 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2193 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2194 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2195 intel_dp->dpcd[6], intel_dp->dpcd[7]);
1b9be9d0 2196
a9756bb5
ZW		 2197 if (status != connector_status_connected)
2198 return status;
2199
0d198328
AJ		 2200 intel_dp_probe_oui(intel_dp);
2201
c3e5f67b
DV		 2202 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2203 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2204 } else {
8c241fef 2205 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2206 if (edid) {
2207 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2208 connector->display_info.raw_edid = NULL;
2209 kfree(edid);
2210 }
a9756bb5
ZW		 2211 }
2212
2213 return connector_status_connected;
a4fc5ed6
KP		 2214}
2215
2216static int intel_dp_get_modes(struct drm_connector *connector)
2217{
df0e9248 2218 struct intel_dp *intel_dp = intel_attached_dp(connector);
4ef69c7a 2219 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 2220 struct drm_i915_private *dev_priv = dev->dev_private;
2221 int ret;
a4fc5ed6
KP		 2222
2223 /* We should parse the EDID data and find out if it has an audio sink
2224 */
2225
8c241fef 2226 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
b9efc480 2227 if (ret) {
d15456de 2228 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
b9efc480
ZY		 2229 struct drm_display_mode *newmode;
2230 list_for_each_entry(newmode, &connector->probed_modes,
2231 head) {
d15456de
KP		 2232 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2233 intel_dp->panel_fixed_mode =
b9efc480
ZY		 2234 drm_mode_duplicate(dev, newmode);
2235 break;
2236 }
2237 }
2238 }
32f9d658 2239 return ret;
b9efc480 2240 }
32f9d658
ZW		 2241
2242 /* if eDP has no EDID, try to use fixed panel mode from VBT */
4d926461 2243 if (is_edp(intel_dp)) {
47f0eb22 2244 /* initialize panel mode from VBT if available for eDP */
d15456de
KP		 2245 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2246 intel_dp->panel_fixed_mode =
47f0eb22 2247 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
d15456de
KP		 2248 if (intel_dp->panel_fixed_mode) {
2249 intel_dp->panel_fixed_mode->type |=
47f0eb22
KP		 2250 DRM_MODE_TYPE_PREFERRED;
2251 }
2252 }
d15456de 2253 if (intel_dp->panel_fixed_mode) {
32f9d658 2254 struct drm_display_mode *mode;
d15456de 2255 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
32f9d658
ZW		 2256 drm_mode_probed_add(connector, mode);
2257 return 1;
2258 }
2259 }
2260 return 0;
a4fc5ed6
KP		 2261}
2262
1aad7ac0
CW		 2263static bool
2264intel_dp_detect_audio(struct drm_connector *connector)
2265{
2266 struct intel_dp *intel_dp = intel_attached_dp(connector);
2267 struct edid *edid;
2268 bool has_audio = false;
2269
8c241fef 2270 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2271 if (edid) {
2272 has_audio = drm_detect_monitor_audio(edid);
2273
2274 connector->display_info.raw_edid = NULL;
2275 kfree(edid);
2276 }
2277
2278 return has_audio;
2279}
2280
f684960e
CW		 2281static int
2282intel_dp_set_property(struct drm_connector *connector,
2283 struct drm_property *property,
2284 uint64_t val)
2285{
e953fd7b 2286 struct drm_i915_private *dev_priv = connector->dev->dev_private;
f684960e
CW		 2287 struct intel_dp *intel_dp = intel_attached_dp(connector);
2288 int ret;
2289
2290 ret = drm_connector_property_set_value(connector, property, val);
2291 if (ret)
2292 return ret;
2293
3f43c48d 2294 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2295 int i = val;
2296 bool has_audio;
2297
2298 if (i == intel_dp->force_audio)
f684960e
CW		 2299 return 0;
2300
1aad7ac0 2301 intel_dp->force_audio = i;
f684960e 2302
c3e5f67b 2303 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2304 has_audio = intel_dp_detect_audio(connector);
2305 else
c3e5f67b 2306 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2307
2308 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2309 return 0;
2310
1aad7ac0 2311 intel_dp->has_audio = has_audio;
f684960e
CW		 2312 goto done;
2313 }
2314
e953fd7b
CW		 2315 if (property == dev_priv->broadcast_rgb_property) {
2316 if (val == !!intel_dp->color_range)
2317 return 0;
2318
2319 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2320 goto done;
2321 }
2322
f684960e
CW		 2323 return -EINVAL;
2324
2325done:
2326 if (intel_dp->base.base.crtc) {
2327 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2328 drm_crtc_helper_set_mode(crtc, &crtc->mode,
2329 crtc->x, crtc->y,
2330 crtc->fb);
2331 }
2332
2333 return 0;
2334}
2335
a4fc5ed6 2336static void
0206e353 2337intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2338{
aaa6fd2a
MG		 2339 struct drm_device *dev = connector->dev;
2340
2341 if (intel_dpd_is_edp(dev))
2342 intel_panel_destroy_backlight(dev);
2343
a4fc5ed6
KP		 2344 drm_sysfs_connector_remove(connector);
2345 drm_connector_cleanup(connector);
55f78c43 2346 kfree(connector);
a4fc5ed6
KP		 2347}
2348
24d05927
DV		 2349static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2350{
2351 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2352
2353 i2c_del_adapter(&intel_dp->adapter);
2354 drm_encoder_cleanup(encoder);
bd943159 2355 if (is_edp(intel_dp)) {
d6f24d0f 2356 kfree(intel_dp->edid);
bd943159
KP		 2357 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2358 ironlake_panel_vdd_off_sync(intel_dp);
2359 }
24d05927
DV		 2360 kfree(intel_dp);
2361}
2362
a4fc5ed6
KP		 2363static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2364 .dpms = intel_dp_dpms,
2365 .mode_fixup = intel_dp_mode_fixup,
d240f20f 2366 .prepare = intel_dp_prepare,
a4fc5ed6 2367 .mode_set = intel_dp_mode_set,
d240f20f 2368 .commit = intel_dp_commit,
a4fc5ed6
KP		 2369};
2370
2371static const struct drm_connector_funcs intel_dp_connector_funcs = {
2372 .dpms = drm_helper_connector_dpms,
a4fc5ed6
KP		 2373 .detect = intel_dp_detect,
2374 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2375 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2376 .destroy = intel_dp_destroy,
2377};
2378
2379static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2380 .get_modes = intel_dp_get_modes,
2381 .mode_valid = intel_dp_mode_valid,
df0e9248 2382 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2383};
2384
a4fc5ed6 2385static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2386 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2387};
2388
995b6762 2389static void
21d40d37 2390intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2391{
ea5b213a 2392 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
c8110e52 2393
885a5014 2394 intel_dp_check_link_status(intel_dp);
c8110e52 2395}
6207937d 2396
e3421a18
ZW		 2397/* Return which DP Port should be selected for Transcoder DP control */
2398int
0206e353 2399intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2400{
2401 struct drm_device *dev = crtc->dev;
2402 struct drm_mode_config *mode_config = &dev->mode_config;
2403 struct drm_encoder *encoder;
e3421a18
ZW		 2404
2405 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
ea5b213a
CW		 2406 struct intel_dp *intel_dp;
2407
d8201ab6 2408 if (encoder->crtc != crtc)
e3421a18
ZW		 2409 continue;
2410
ea5b213a 2411 intel_dp = enc_to_intel_dp(encoder);
417e822d
KP		 2412 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2413 intel_dp->base.type == INTEL_OUTPUT_EDP)
ea5b213a 2414 return intel_dp->output_reg;
e3421a18 2415 }
ea5b213a 2416
e3421a18
ZW		 2417 return -1;
2418}
2419
36e83a18 2420/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2421bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2422{
2423 struct drm_i915_private *dev_priv = dev->dev_private;
2424 struct child_device_config *p_child;
2425 int i;
2426
2427 if (!dev_priv->child_dev_num)
2428 return false;
2429
2430 for (i = 0; i < dev_priv->child_dev_num; i++) {
2431 p_child = dev_priv->child_dev + i;
2432
2433 if (p_child->dvo_port == PORT_IDPD &&
2434 p_child->device_type == DEVICE_TYPE_eDP)
2435 return true;
2436 }
2437 return false;
2438}
2439
f684960e
CW		 2440static void
2441intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2442{
3f43c48d 2443 intel_attach_force_audio_property(connector);
e953fd7b 2444 intel_attach_broadcast_rgb_property(connector);
f684960e
CW		 2445}
2446
a4fc5ed6
KP		 2447void
2448intel_dp_init(struct drm_device *dev, int output_reg)
2449{
2450 struct drm_i915_private *dev_priv = dev->dev_private;
2451 struct drm_connector *connector;
ea5b213a 2452 struct intel_dp *intel_dp;
21d40d37 2453 struct intel_encoder *intel_encoder;
55f78c43 2454 struct intel_connector *intel_connector;
5eb08b69 2455 const char *name = NULL;
b329530c 2456 int type;
a4fc5ed6 2457
ea5b213a
CW		 2458 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2459 if (!intel_dp)
a4fc5ed6
KP		 2460 return;
2461
3d3dc149 2462 intel_dp->output_reg = output_reg;
d2b996ac 2463 intel_dp->dpms_mode = -1;
3d3dc149 2464
55f78c43
ZW		 2465 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2466 if (!intel_connector) {
ea5b213a 2467 kfree(intel_dp);
55f78c43
ZW		 2468 return;
2469 }
ea5b213a 2470 intel_encoder = &intel_dp->base;
55f78c43 2471
ea5b213a 2472 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
b329530c 2473 if (intel_dpd_is_edp(dev))
ea5b213a 2474 intel_dp->is_pch_edp = true;
b329530c 2475
cfcb0fc9 2476 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
b329530c
AJ		 2477 type = DRM_MODE_CONNECTOR_eDP;
2478 intel_encoder->type = INTEL_OUTPUT_EDP;
2479 } else {
2480 type = DRM_MODE_CONNECTOR_DisplayPort;
2481 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2482 }
2483
55f78c43 2484 connector = &intel_connector->base;
b329530c 2485 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 2486 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2487
eb1f8e4f
DA		 2488 connector->polled = DRM_CONNECTOR_POLL_HPD;
2489
652af9d7 2490 if (output_reg == DP_B || output_reg == PCH_DP_B)
21d40d37 2491 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
652af9d7 2492 else if (output_reg == DP_C || output_reg == PCH_DP_C)
21d40d37 2493 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
652af9d7 2494 else if (output_reg == DP_D || output_reg == PCH_DP_D)
21d40d37 2495 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
f8aed700 2496
bd943159 2497 if (is_edp(intel_dp)) {
21d40d37 2498 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
bd943159
KP		 2499 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2500 ironlake_panel_vdd_work);
2501 }
6251ec0a 2502
27f8227b 2503 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
ee7b9f93 2504
a4fc5ed6
KP		 2505 connector->interlace_allowed = true;
2506 connector->doublescan_allowed = 0;
2507
4ef69c7a 2508 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
a4fc5ed6 2509 DRM_MODE_ENCODER_TMDS);
4ef69c7a 2510 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
a4fc5ed6 2511
df0e9248 2512 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 2513 drm_sysfs_connector_add(connector);
2514
2515 /* Set up the DDC bus. */
5eb08b69 2516 switch (output_reg) {
32f9d658
ZW		 2517 case DP_A:
2518 name = "DPDDC-A";
2519 break;
5eb08b69
ZW		 2520 case DP_B:
2521 case PCH_DP_B:
b01f2c3a
JB		 2522 dev_priv->hotplug_supported_mask |=
2523 HDMIB_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 2524 name = "DPDDC-B";
2525 break;
2526 case DP_C:
2527 case PCH_DP_C:
b01f2c3a
JB		 2528 dev_priv->hotplug_supported_mask |=
2529 HDMIC_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 2530 name = "DPDDC-C";
2531 break;
2532 case DP_D:
2533 case PCH_DP_D:
b01f2c3a
JB		 2534 dev_priv->hotplug_supported_mask |=
2535 HDMID_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 2536 name = "DPDDC-D";
2537 break;
2538 }
2539
d6f24d0f
JB		 2540 intel_dp_i2c_init(intel_dp, intel_connector, name);
2541
89667383
JB		 2542 /* Cache some DPCD data in the eDP case */
2543 if (is_edp(intel_dp)) {
59f3e272 2544 bool ret;
f01eca2e
KP		 2545 struct edp_power_seq cur, vbt;
2546 u32 pp_on, pp_off, pp_div;
d6f24d0f 2547 struct edid *edid;
5d613501
JB		 2548
2549 pp_on = I915_READ(PCH_PP_ON_DELAYS);
f01eca2e 2550 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
5d613501 2551 pp_div = I915_READ(PCH_PP_DIVISOR);
89667383 2552
bfa3384a
JB		 2553 if (!pp_on || !pp_off || !pp_div) {
2554 DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2555 intel_dp_encoder_destroy(&intel_dp->base.base);
2556 intel_dp_destroy(&intel_connector->base);
2557 return;
2558 }
2559
f01eca2e
KP		 2560 /* Pull timing values out of registers */
2561 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2562 PANEL_POWER_UP_DELAY_SHIFT;
2563
2564 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2565 PANEL_LIGHT_ON_DELAY_SHIFT;
f2e8b18a 2566
f01eca2e
KP		 2567 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2568 PANEL_LIGHT_OFF_DELAY_SHIFT;
2569
2570 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2571 PANEL_POWER_DOWN_DELAY_SHIFT;
2572
2573 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2574 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2575
2576 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2577 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2578
2579 vbt = dev_priv->edp.pps;
2580
2581 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2582 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2583
2584#define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2585
2586 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2587 intel_dp->backlight_on_delay = get_delay(t8);
2588 intel_dp->backlight_off_delay = get_delay(t9);
2589 intel_dp->panel_power_down_delay = get_delay(t10);
2590 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2591
2592 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2593 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2594 intel_dp->panel_power_cycle_delay);
2595
2596 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2597 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5d613501
JB		 2598
2599 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 2600 ret = intel_dp_get_dpcd(intel_dp);
bd943159 2601 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 2602
59f3e272 2603 if (ret) {
7183dc29
JB		 2604 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2605 dev_priv->no_aux_handshake =
2606 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 2607 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2608 } else {
3d3dc149 2609 /* if this fails, presume the device is a ghost */
48898b03 2610 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3d3dc149 2611 intel_dp_encoder_destroy(&intel_dp->base.base);
48898b03 2612 intel_dp_destroy(&intel_connector->base);
3d3dc149 2613 return;
89667383 2614 }
89667383 2615
d6f24d0f
JB		 2616 ironlake_edp_panel_vdd_on(intel_dp);
2617 edid = drm_get_edid(connector, &intel_dp->adapter);
2618 if (edid) {
2619 drm_mode_connector_update_edid_property(connector,
2620 edid);
2621 intel_dp->edid_mode_count =
2622 drm_add_edid_modes(connector, edid);
2623 drm_edid_to_eld(connector, edid);
2624 intel_dp->edid = edid;
2625 }
2626 ironlake_edp_panel_vdd_off(intel_dp, false);
2627 }
552fb0b7 2628
21d40d37 2629 intel_encoder->hot_plug = intel_dp_hot_plug;
a4fc5ed6 2630
4d926461 2631 if (is_edp(intel_dp)) {
aaa6fd2a
MG		 2632 dev_priv->int_edp_connector = connector;
2633 intel_panel_setup_backlight(dev);
32f9d658
ZW		 2634 }
2635
f684960e
CW		 2636 intel_dp_add_properties(intel_dp, connector);
2637
a4fc5ed6
KP		 2638 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2639 * 0xd. Failure to do so will result in spurious interrupts being
2640 * generated on the port when a cable is not attached.
2641 */
2642 if (IS_G4X(dev) && !IS_GM45(dev)) {
2643 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2644 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2645 }
2646}
Linux kernel - Deliverables
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