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drm/i915: Extend BIOS stolen mem handling to all platform
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 114static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 116
0e32b39c 117int
ea5b213a 118intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 119{
7183dc29 120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 121 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 122
123 switch (max_link_bw) {
124 case DP_LINK_BW_1_62:
125 case DP_LINK_BW_2_7:
126 break;
d4eead50 127 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 128 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
129 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 130 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
131 max_link_bw = DP_LINK_BW_5_4;
132 else
133 max_link_bw = DP_LINK_BW_2_7;
d4eead50 134 break;
a4fc5ed6 135 default:
d4eead50
ID		 136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
137 max_link_bw);
a4fc5ed6
KP		 138 max_link_bw = DP_LINK_BW_1_62;
139 break;
140 }
141 return max_link_bw;
142}
143
eeb6324d
PZ		 144static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
145{
146 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
147 struct drm_device *dev = intel_dig_port->base.base.dev;
148 u8 source_max, sink_max;
149
150 source_max = 4;
151 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
152 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
153 source_max = 2;
154
155 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
156
157 return min(source_max, sink_max);
158}
159
cd9dde44
AJ		 160/*
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
163 *
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
165 *
166 * 270000 * 1 * 8 / 10 == 216000
167 *
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
172 *
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
175 */
176
a4fc5ed6 177static int
c898261c 178intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 179{
cd9dde44 180 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 181}
182
fe27d53e
DA		 183static int
184intel_dp_max_data_rate(int max_link_clock, int max_lanes)
185{
186 return (max_link_clock * max_lanes * 8) / 10;
187}
188
c19de8eb 189static enum drm_mode_status
a4fc5ed6
KP		 190intel_dp_mode_valid(struct drm_connector *connector,
191 struct drm_display_mode *mode)
192{
df0e9248 193 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 194 struct intel_connector *intel_connector = to_intel_connector(connector);
195 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 196 int target_clock = mode->clock;
197 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 198
dd06f90e
JN		 199 if (is_edp(intel_dp) && fixed_mode) {
200 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 201 return MODE_PANEL;
202
dd06f90e 203 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 204 return MODE_PANEL;
03afc4a2
DV		 205
206 target_clock = fixed_mode->clock;
7de56f43
ZY		 207 }
208
36008365 209 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 210 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 211
212 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
213 mode_rate = intel_dp_link_required(target_clock, 18);
214
215 if (mode_rate > max_rate)
c4867936 216 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 217
218 if (mode->clock < 10000)
219 return MODE_CLOCK_LOW;
220
0af78a2b
DV		 221 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
222 return MODE_H_ILLEGAL;
223
a4fc5ed6
KP		 224 return MODE_OK;
225}
226
227static uint32_t
228pack_aux(uint8_t *src, int src_bytes)
229{
230 int i;
231 uint32_t v = 0;
232
233 if (src_bytes > 4)
234 src_bytes = 4;
235 for (i = 0; i < src_bytes; i++)
236 v |= ((uint32_t) src[i]) << ((3-i) * 8);
237 return v;
238}
239
240static void
241unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
242{
243 int i;
244 if (dst_bytes > 4)
245 dst_bytes = 4;
246 for (i = 0; i < dst_bytes; i++)
247 dst[i] = src >> ((3-i) * 8);
248}
249
fb0f8fbf
KP		 250/* hrawclock is 1/4 the FSB frequency */
251static int
252intel_hrawclk(struct drm_device *dev)
253{
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 uint32_t clkcfg;
256
9473c8f4
VP		 257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev))
259 return 200;
260
fb0f8fbf
KP		 261 clkcfg = I915_READ(CLKCFG);
262 switch (clkcfg & CLKCFG_FSB_MASK) {
263 case CLKCFG_FSB_400:
264 return 100;
265 case CLKCFG_FSB_533:
266 return 133;
267 case CLKCFG_FSB_667:
268 return 166;
269 case CLKCFG_FSB_800:
270 return 200;
271 case CLKCFG_FSB_1067:
272 return 266;
273 case CLKCFG_FSB_1333:
274 return 333;
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600:
277 case CLKCFG_FSB_1600_ALT:
278 return 400;
279 default:
280 return 133;
281 }
282}
283
bf13e81b
JN		 284static void
285intel_dp_init_panel_power_sequencer(struct drm_device *dev,
286 struct intel_dp *intel_dp,
287 struct edp_power_seq *out);
288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
290 struct intel_dp *intel_dp,
291 struct edp_power_seq *out);
292
773538e8
VS		 293static void pps_lock(struct intel_dp *intel_dp)
294{
295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
296 struct intel_encoder *encoder = &intel_dig_port->base;
297 struct drm_device *dev = encoder->base.dev;
298 struct drm_i915_private *dev_priv = dev->dev_private;
299 enum intel_display_power_domain power_domain;
300
301 /*
302 * See vlv_power_sequencer_reset() why we need
303 * a power domain reference here.
304 */
305 power_domain = intel_display_port_power_domain(encoder);
306 intel_display_power_get(dev_priv, power_domain);
307
308 mutex_lock(&dev_priv->pps_mutex);
309}
310
311static void pps_unlock(struct intel_dp *intel_dp)
312{
313 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
314 struct intel_encoder *encoder = &intel_dig_port->base;
315 struct drm_device *dev = encoder->base.dev;
316 struct drm_i915_private *dev_priv = dev->dev_private;
317 enum intel_display_power_domain power_domain;
318
319 mutex_unlock(&dev_priv->pps_mutex);
320
321 power_domain = intel_display_port_power_domain(encoder);
322 intel_display_power_put(dev_priv, power_domain);
323}
324
bf13e81b
JN		 325static enum pipe
326vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
327{
328 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 329 struct drm_device *dev = intel_dig_port->base.base.dev;
330 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 331 struct intel_encoder *encoder;
332 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
333 struct edp_power_seq power_seq;
bf13e81b 334
e39b999a
VS		 335 lockdep_assert_held(&dev_priv->pps_mutex);
336
a4a5d2f8
VS		 337 if (intel_dp->pps_pipe != INVALID_PIPE)
338 return intel_dp->pps_pipe;
339
340 /*
341 * We don't have power sequencer currently.
342 * Pick one that's not used by other ports.
343 */
344 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
345 base.head) {
346 struct intel_dp *tmp;
347
348 if (encoder->type != INTEL_OUTPUT_EDP)
349 continue;
350
351 tmp = enc_to_intel_dp(&encoder->base);
352
353 if (tmp->pps_pipe != INVALID_PIPE)
354 pipes &= ~(1 << tmp->pps_pipe);
355 }
356
357 /*
358 * Didn't find one. This should not happen since there
359 * are two power sequencers and up to two eDP ports.
360 */
361 if (WARN_ON(pipes == 0))
362 return PIPE_A;
363
364 intel_dp->pps_pipe = ffs(pipes) - 1;
365
366 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
367 pipe_name(intel_dp->pps_pipe),
368 port_name(intel_dig_port->port));
369
370 /* init power sequencer on this pipe and port */
371 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
372 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
373 &power_seq);
374
375 return intel_dp->pps_pipe;
376}
377
6491ab27
VS		 378typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
379 enum pipe pipe);
380
381static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
382 enum pipe pipe)
383{
384 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
385}
386
387static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
388 enum pipe pipe)
389{
390 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
391}
392
393static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
394 enum pipe pipe)
395{
396 return true;
397}
bf13e81b 398
a4a5d2f8 399static enum pipe
6491ab27
VS		 400vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
401 enum port port,
402 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 403{
404 enum pipe pipe;
bf13e81b 405
bf13e81b
JN		 406 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
407 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
408 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 409
410 if (port_sel != PANEL_PORT_SELECT_VLV(port))
411 continue;
412
6491ab27
VS		 413 if (!pipe_check(dev_priv, pipe))
414 continue;
415
a4a5d2f8 416 return pipe;
bf13e81b
JN		 417 }
418
a4a5d2f8
VS		 419 return INVALID_PIPE;
420}
421
422static void
423vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
424{
425 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
426 struct drm_device *dev = intel_dig_port->base.base.dev;
427 struct drm_i915_private *dev_priv = dev->dev_private;
428 struct edp_power_seq power_seq;
429 enum port port = intel_dig_port->port;
430
431 lockdep_assert_held(&dev_priv->pps_mutex);
432
433 /* try to find a pipe with this port selected */
6491ab27
VS		 434 /* first pick one where the panel is on */
435 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
436 vlv_pipe_has_pp_on);
437 /* didn't find one? pick one where vdd is on */
438 if (intel_dp->pps_pipe == INVALID_PIPE)
439 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
440 vlv_pipe_has_vdd_on);
441 /* didn't find one? pick one with just the correct port */
442 if (intel_dp->pps_pipe == INVALID_PIPE)
443 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
444 vlv_pipe_any);
a4a5d2f8
VS		 445
446 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
447 if (intel_dp->pps_pipe == INVALID_PIPE) {
448 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
449 port_name(port));
450 return;
bf13e81b
JN		 451 }
452
a4a5d2f8
VS		 453 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
454 port_name(port), pipe_name(intel_dp->pps_pipe));
455
456 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
457 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
458 &power_seq);
bf13e81b
JN		 459}
460
773538e8
VS		 461void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
462{
463 struct drm_device *dev = dev_priv->dev;
464 struct intel_encoder *encoder;
465
466 if (WARN_ON(!IS_VALLEYVIEW(dev)))
467 return;
468
469 /*
470 * We can't grab pps_mutex here due to deadlock with power_domain
471 * mutex when power_domain functions are called while holding pps_mutex.
472 * That also means that in order to use pps_pipe the code needs to
473 * hold both a power domain reference and pps_mutex, and the power domain
474 * reference get/put must be done while _not_ holding pps_mutex.
475 * pps_{lock,unlock}() do these steps in the correct order, so one
476 * should use them always.
477 */
478
479 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
480 struct intel_dp *intel_dp;
481
482 if (encoder->type != INTEL_OUTPUT_EDP)
483 continue;
484
485 intel_dp = enc_to_intel_dp(&encoder->base);
486 intel_dp->pps_pipe = INVALID_PIPE;
487 }
bf13e81b
JN		 488}
489
490static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
491{
492 struct drm_device *dev = intel_dp_to_dev(intel_dp);
493
494 if (HAS_PCH_SPLIT(dev))
495 return PCH_PP_CONTROL;
496 else
497 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
498}
499
500static u32 _pp_stat_reg(struct intel_dp *intel_dp)
501{
502 struct drm_device *dev = intel_dp_to_dev(intel_dp);
503
504 if (HAS_PCH_SPLIT(dev))
505 return PCH_PP_STATUS;
506 else
507 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
508}
509
01527b31
CT		 510/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
511 This function only applicable when panel PM state is not to be tracked */
512static int edp_notify_handler(struct notifier_block *this, unsigned long code,
513 void *unused)
514{
515 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
516 edp_notifier);
517 struct drm_device *dev = intel_dp_to_dev(intel_dp);
518 struct drm_i915_private *dev_priv = dev->dev_private;
519 u32 pp_div;
520 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 521
522 if (!is_edp(intel_dp) || code != SYS_RESTART)
523 return 0;
524
773538e8 525 pps_lock(intel_dp);
e39b999a 526
01527b31 527 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 528 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
529
01527b31
CT		 530 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
531 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
532 pp_div = I915_READ(pp_div_reg);
533 pp_div &= PP_REFERENCE_DIVIDER_MASK;
534
535 /* 0x1F write to PP_DIV_REG sets max cycle delay */
536 I915_WRITE(pp_div_reg, pp_div | 0x1F);
537 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
538 msleep(intel_dp->panel_power_cycle_delay);
539 }
540
773538e8 541 pps_unlock(intel_dp);
e39b999a 542
01527b31
CT		 543 return 0;
544}
545
4be73780 546static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 547{
30add22d 548 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 549 struct drm_i915_private *dev_priv = dev->dev_private;
550
e39b999a
VS		 551 lockdep_assert_held(&dev_priv->pps_mutex);
552
bf13e81b 553 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 554}
555
4be73780 556static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 557{
30add22d 558 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 559 struct drm_i915_private *dev_priv = dev->dev_private;
560
e39b999a
VS		 561 lockdep_assert_held(&dev_priv->pps_mutex);
562
773538e8 563 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 564}
565
9b984dae
KP		 566static void
567intel_dp_check_edp(struct intel_dp *intel_dp)
568{
30add22d 569 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 570 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 571
9b984dae
KP		 572 if (!is_edp(intel_dp))
573 return;
453c5420 574
4be73780 575 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 576 WARN(1, "eDP powered off while attempting aux channel communication.\n");
577 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 578 I915_READ(_pp_stat_reg(intel_dp)),
579 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 580 }
581}
582
9ee32fea
DV		 583static uint32_t
584intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
585{
586 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
587 struct drm_device *dev = intel_dig_port->base.base.dev;
588 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 589 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 590 uint32_t status;
591 bool done;
592
ef04f00d 593#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 594 if (has_aux_irq)
b18ac466 595 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 596 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 597 else
598 done = wait_for_atomic(C, 10) == 0;
599 if (!done)
600 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
601 has_aux_irq);
602#undef C
603
604 return status;
605}
606
ec5b01dd 607static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 608{
174edf1f
PZ		 609 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
610 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 611
ec5b01dd
DL		 612 /*
613 * The clock divider is based off the hrawclk, and would like to run at
614 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 615 */
ec5b01dd
DL		 616 return index ? 0 : intel_hrawclk(dev) / 2;
617}
618
619static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
620{
621 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
622 struct drm_device *dev = intel_dig_port->base.base.dev;
623
624 if (index)
625 return 0;
626
627 if (intel_dig_port->port == PORT_A) {
628 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 629 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 630 else
b84a1cf8 631 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 632 } else {
633 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
634 }
635}
636
637static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
638{
639 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
640 struct drm_device *dev = intel_dig_port->base.base.dev;
641 struct drm_i915_private *dev_priv = dev->dev_private;
642
643 if (intel_dig_port->port == PORT_A) {
644 if (index)
645 return 0;
646 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 647 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
648 /* Workaround for non-ULT HSW */
bc86625a
CW		 649 switch (index) {
650 case 0: return 63;
651 case 1: return 72;
652 default: return 0;
653 }
ec5b01dd 654 } else {
bc86625a 655 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 656 }
b84a1cf8
RV		 657}
658
ec5b01dd
DL		 659static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
660{
661 return index ? 0 : 100;
662}
663
5ed12a19
DL		 664static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
665 bool has_aux_irq,
666 int send_bytes,
667 uint32_t aux_clock_divider)
668{
669 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
670 struct drm_device *dev = intel_dig_port->base.base.dev;
671 uint32_t precharge, timeout;
672
673 if (IS_GEN6(dev))
674 precharge = 3;
675 else
676 precharge = 5;
677
678 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
679 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
680 else
681 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
682
683 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 684 DP_AUX_CH_CTL_DONE |
5ed12a19 685 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 686 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 687 timeout |
788d4433 688 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 689 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
690 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 691 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 692}
693
b84a1cf8
RV		 694static int
695intel_dp_aux_ch(struct intel_dp *intel_dp,
696 uint8_t *send, int send_bytes,
697 uint8_t *recv, int recv_size)
698{
699 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
700 struct drm_device *dev = intel_dig_port->base.base.dev;
701 struct drm_i915_private *dev_priv = dev->dev_private;
702 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
703 uint32_t ch_data = ch_ctl + 4;
bc86625a 704 uint32_t aux_clock_divider;
b84a1cf8
RV		 705 int i, ret, recv_bytes;
706 uint32_t status;
5ed12a19 707 int try, clock = 0;
4e6b788c 708 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 709 bool vdd;
710
773538e8 711 pps_lock(intel_dp);
e39b999a 712
72c3500a
VS		 713 /*
714 * We will be called with VDD already enabled for dpcd/edid/oui reads.
715 * In such cases we want to leave VDD enabled and it's up to upper layers
716 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
717 * ourselves.
718 */
1e0560e0 719 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 720
721 /* dp aux is extremely sensitive to irq latency, hence request the
722 * lowest possible wakeup latency and so prevent the cpu from going into
723 * deep sleep states.
724 */
725 pm_qos_update_request(&dev_priv->pm_qos, 0);
726
727 intel_dp_check_edp(intel_dp);
5eb08b69 728
c67a470b
PZ		 729 intel_aux_display_runtime_get(dev_priv);
730
11bee43e
JB		 731 /* Try to wait for any previous AUX channel activity */
732 for (try = 0; try < 3; try++) {
ef04f00d 733 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 734 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
735 break;
736 msleep(1);
737 }
738
739 if (try == 3) {
740 WARN(1, "dp_aux_ch not started status 0x%08x\n",
741 I915_READ(ch_ctl));
9ee32fea
DV		 742 ret = -EBUSY;
743 goto out;
4f7f7b7e
CW		 744 }
745
46a5ae9f
PZ		 746 /* Only 5 data registers! */
747 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
748 ret = -E2BIG;
749 goto out;
750 }
751
ec5b01dd 752 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 753 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
754 has_aux_irq,
755 send_bytes,
756 aux_clock_divider);
5ed12a19 757
bc86625a
CW		 758 /* Must try at least 3 times according to DP spec */
759 for (try = 0; try < 5; try++) {
760 /* Load the send data into the aux channel data registers */
761 for (i = 0; i < send_bytes; i += 4)
762 I915_WRITE(ch_data + i,
763 pack_aux(send + i, send_bytes - i));
764
765 /* Send the command and wait for it to complete */
5ed12a19 766 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 767
768 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
769
770 /* Clear done status and any errors */
771 I915_WRITE(ch_ctl,
772 status |
773 DP_AUX_CH_CTL_DONE |
774 DP_AUX_CH_CTL_TIME_OUT_ERROR |
775 DP_AUX_CH_CTL_RECEIVE_ERROR);
776
777 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
778 DP_AUX_CH_CTL_RECEIVE_ERROR))
779 continue;
780 if (status & DP_AUX_CH_CTL_DONE)
781 break;
782 }
4f7f7b7e 783 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 784 break;
785 }
786
a4fc5ed6 787 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 788 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 789 ret = -EBUSY;
790 goto out;
a4fc5ed6
KP		 791 }
792
793 /* Check for timeout or receive error.
794 * Timeouts occur when the sink is not connected
795 */
a5b3da54 796 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 797 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 798 ret = -EIO;
799 goto out;
a5b3da54 800 }
1ae8c0a5
KP		 801
802 /* Timeouts occur when the device isn't connected, so they're
803 * "normal" -- don't fill the kernel log with these */
a5b3da54 804 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 805 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 806 ret = -ETIMEDOUT;
807 goto out;
a4fc5ed6
KP		 808 }
809
810 /* Unload any bytes sent back from the other side */
811 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
812 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 813 if (recv_bytes > recv_size)
814 recv_bytes = recv_size;
0206e353 815
4f7f7b7e
CW		 816 for (i = 0; i < recv_bytes; i += 4)
817 unpack_aux(I915_READ(ch_data + i),
818 recv + i, recv_bytes - i);
a4fc5ed6 819
9ee32fea
DV		 820 ret = recv_bytes;
821out:
822 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 823 intel_aux_display_runtime_put(dev_priv);
9ee32fea 824
884f19e9
JN		 825 if (vdd)
826 edp_panel_vdd_off(intel_dp, false);
827
773538e8 828 pps_unlock(intel_dp);
e39b999a 829
9ee32fea 830 return ret;
a4fc5ed6
KP		 831}
832
a6c8aff0
JN		 833#define BARE_ADDRESS_SIZE 3
834#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 835static ssize_t
836intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 837{
9d1a1031
JN		 838 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
839 uint8_t txbuf[20], rxbuf[20];
840 size_t txsize, rxsize;
a4fc5ed6 841 int ret;
a4fc5ed6 842
9d1a1031
JN		 843 txbuf[0] = msg->request << 4;
844 txbuf[1] = msg->address >> 8;
845 txbuf[2] = msg->address & 0xff;
846 txbuf[3] = msg->size - 1;
46a5ae9f 847
9d1a1031
JN		 848 switch (msg->request & ~DP_AUX_I2C_MOT) {
849 case DP_AUX_NATIVE_WRITE:
850 case DP_AUX_I2C_WRITE:
a6c8aff0 851 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 852 rxsize = 1;
f51a44b9 853
9d1a1031
JN		 854 if (WARN_ON(txsize > 20))
855 return -E2BIG;
a4fc5ed6 856
9d1a1031 857 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 858
9d1a1031
JN		 859 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
860 if (ret > 0) {
861 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 862
9d1a1031
JN		 863 /* Return payload size. */
864 ret = msg->size;
865 }
866 break;
46a5ae9f 867
9d1a1031
JN		 868 case DP_AUX_NATIVE_READ:
869 case DP_AUX_I2C_READ:
a6c8aff0 870 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 871 rxsize = msg->size + 1;
a4fc5ed6 872
9d1a1031
JN		 873 if (WARN_ON(rxsize > 20))
874 return -E2BIG;
a4fc5ed6 875
9d1a1031
JN		 876 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
877 if (ret > 0) {
878 msg->reply = rxbuf[0] >> 4;
879 /*
880 * Assume happy day, and copy the data. The caller is
881 * expected to check msg->reply before touching it.
882 *
883 * Return payload size.
884 */
885 ret--;
886 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 887 }
9d1a1031
JN		 888 break;
889
890 default:
891 ret = -EINVAL;
892 break;
a4fc5ed6 893 }
f51a44b9 894
9d1a1031 895 return ret;
a4fc5ed6
KP		 896}
897
9d1a1031
JN		 898static void
899intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
900{
901 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 902 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
903 enum port port = intel_dig_port->port;
0b99836f 904 const char *name = NULL;
ab2c0672
DA		 905 int ret;
906
33ad6626
JN		 907 switch (port) {
908 case PORT_A:
909 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 910 name = "DPDDC-A";
ab2c0672 911 break;
33ad6626
JN		 912 case PORT_B:
913 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 914 name = "DPDDC-B";
ab2c0672 915 break;
33ad6626
JN		 916 case PORT_C:
917 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 918 name = "DPDDC-C";
ab2c0672 919 break;
33ad6626
JN		 920 case PORT_D:
921 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 922 name = "DPDDC-D";
33ad6626
JN		 923 break;
924 default:
925 BUG();
ab2c0672
DA		 926 }
927
33ad6626
JN		 928 if (!HAS_DDI(dev))
929 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 930
0b99836f 931 intel_dp->aux.name = name;
9d1a1031
JN		 932 intel_dp->aux.dev = dev->dev;
933 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 934
0b99836f
JN		 935 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
936 connector->base.kdev->kobj.name);
8316f337 937
4f71d0cb 938 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 939 if (ret < 0) {
4f71d0cb 940 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 941 name, ret);
942 return;
ab2c0672 943 }
8a5e6aeb 944
0b99836f
JN		 945 ret = sysfs_create_link(&connector->base.kdev->kobj,
946 &intel_dp->aux.ddc.dev.kobj,
947 intel_dp->aux.ddc.dev.kobj.name);
948 if (ret < 0) {
949 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 950 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 951 }
a4fc5ed6
KP		 952}
953
80f65de3
ID		 954static void
955intel_dp_connector_unregister(struct intel_connector *intel_connector)
956{
957 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
958
0e32b39c
DA		 959 if (!intel_connector->mst_port)
960 sysfs_remove_link(&intel_connector->base.kdev->kobj,
961 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 962 intel_connector_unregister(intel_connector);
963}
964
0e50338c
DV		 965static void
966hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
967{
968 switch (link_bw) {
969 case DP_LINK_BW_1_62:
970 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
971 break;
972 case DP_LINK_BW_2_7:
973 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
974 break;
975 case DP_LINK_BW_5_4:
976 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
977 break;
978 }
979}
980
c6bb3538
DV		 981static void
982intel_dp_set_clock(struct intel_encoder *encoder,
983 struct intel_crtc_config *pipe_config, int link_bw)
984{
985 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 986 const struct dp_link_dpll *divisor = NULL;
987 int i, count = 0;
c6bb3538
DV		 988
989 if (IS_G4X(dev)) {
9dd4ffdf
CML		 990 divisor = gen4_dpll;
991 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 992 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 993 divisor = pch_dpll;
994 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 995 } else if (IS_CHERRYVIEW(dev)) {
996 divisor = chv_dpll;
997 count = ARRAY_SIZE(chv_dpll);
c6bb3538 998 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 999 divisor = vlv_dpll;
1000 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1001 }
9dd4ffdf
CML		 1002
1003 if (divisor && count) {
1004 for (i = 0; i < count; i++) {
1005 if (link_bw == divisor[i].link_bw) {
1006 pipe_config->dpll = divisor[i].dpll;
1007 pipe_config->clock_set = true;
1008 break;
1009 }
1010 }
c6bb3538
DV		 1011 }
1012}
1013
00c09d70 1014bool
5bfe2ac0
DV		 1015intel_dp_compute_config(struct intel_encoder *encoder,
1016 struct intel_crtc_config *pipe_config)
a4fc5ed6 1017{
5bfe2ac0 1018 struct drm_device *dev = encoder->base.dev;
36008365 1019 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 1020 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 1021 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1022 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 1023 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 1024 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1025 int lane_count, clock;
56071a20 1026 int min_lane_count = 1;
eeb6324d 1027 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1028 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1029 int min_clock = 0;
06ea66b6 1030 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 1031 int bpp, mode_rate;
06ea66b6 1032 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 1033 int link_avail, link_clock;
a4fc5ed6 1034
bc7d38a4 1035 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1036 pipe_config->has_pch_encoder = true;
1037
03afc4a2 1038 pipe_config->has_dp_encoder = true;
f769cd24 1039 pipe_config->has_drrs = false;
9ed109a7 1040 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 1041
dd06f90e
JN		 1042 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1043 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1044 adjusted_mode);
2dd24552
JB		 1045 if (!HAS_PCH_SPLIT(dev))
1046 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1047 intel_connector->panel.fitting_mode);
1048 else
b074cec8
JB		 1049 intel_pch_panel_fitting(intel_crtc, pipe_config,
1050 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1051 }
1052
cb1793ce 1053 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1054 return false;
1055
083f9560
DV		 1056 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1057 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 1058 max_lane_count, bws[max_clock],
1059 adjusted_mode->crtc_clock);
083f9560 1060
36008365
DV		 1061 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1062 * bpc in between. */
3e7ca985 1063 bpp = pipe_config->pipe_bpp;
56071a20
JN		 1064 if (is_edp(intel_dp)) {
1065 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1066 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1067 dev_priv->vbt.edp_bpp);
1068 bpp = dev_priv->vbt.edp_bpp;
1069 }
1070
344c5bbc
JN		 1071 /*
1072 * Use the maximum clock and number of lanes the eDP panel
1073 * advertizes being capable of. The panels are generally
1074 * designed to support only a single clock and lane
1075 * configuration, and typically these values correspond to the
1076 * native resolution of the panel.
1077 */
1078 min_lane_count = max_lane_count;
1079 min_clock = max_clock;
7984211e 1080 }
657445fe 1081
36008365 1082 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1083 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1084 bpp);
36008365 1085
c6930992
DA		 1086 for (clock = min_clock; clock <= max_clock; clock++) {
1087 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 1088 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1089 link_avail = intel_dp_max_data_rate(link_clock,
1090 lane_count);
1091
1092 if (mode_rate <= link_avail) {
1093 goto found;
1094 }
1095 }
1096 }
1097 }
c4867936 1098
36008365 1099 return false;
3685a8f3 1100
36008365 1101found:
55bc60db
VS		 1102 if (intel_dp->color_range_auto) {
1103 /*
1104 * See:
1105 * CEA-861-E - 5.1 Default Encoding Parameters
1106 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1107 */
18316c8c 1108 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 1109 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1110 else
1111 intel_dp->color_range = 0;
1112 }
1113
3685a8f3 1114 if (intel_dp->color_range)
50f3b016 1115 pipe_config->limited_color_range = true;
a4fc5ed6 1116
36008365
DV		 1117 intel_dp->link_bw = bws[clock];
1118 intel_dp->lane_count = lane_count;
657445fe 1119 pipe_config->pipe_bpp = bpp;
ff9a6750 1120 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 1121
36008365
DV		 1122 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1123 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 1124 pipe_config->port_clock, bpp);
36008365
DV		 1125 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1126 mode_rate, link_avail);
a4fc5ed6 1127
03afc4a2 1128 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1129 adjusted_mode->crtc_clock,
1130 pipe_config->port_clock,
03afc4a2 1131 &pipe_config->dp_m_n);
9d1a455b 1132
439d7ac0
PB		 1133 if (intel_connector->panel.downclock_mode != NULL &&
1134 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1135 pipe_config->has_drrs = true;
439d7ac0
PB		 1136 intel_link_compute_m_n(bpp, lane_count,
1137 intel_connector->panel.downclock_mode->clock,
1138 pipe_config->port_clock,
1139 &pipe_config->dp_m2_n2);
1140 }
1141
ea155f32 1142 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 1143 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1144 else
1145 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 1146
03afc4a2 1147 return true;
a4fc5ed6
KP		 1148}
1149
7c62a164 1150static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1151{
7c62a164
DV		 1152 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1153 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1154 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1155 struct drm_i915_private *dev_priv = dev->dev_private;
1156 u32 dpa_ctl;
1157
ff9a6750 1158 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 1159 dpa_ctl = I915_READ(DP_A);
1160 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1161
ff9a6750 1162 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 1163 /* For a long time we've carried around a ILK-DevA w/a for the
1164 * 160MHz clock. If we're really unlucky, it's still required.
1165 */
1166 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1167 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1168 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1169 } else {
1170 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1171 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1172 }
1ce17038 1173
ea9b6006
DV		 1174 I915_WRITE(DP_A, dpa_ctl);
1175
1176 POSTING_READ(DP_A);
1177 udelay(500);
1178}
1179
8ac33ed3 1180static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1181{
b934223d 1182 struct drm_device *dev = encoder->base.dev;
417e822d 1183 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1184 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1185 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1186 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1187 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1188
417e822d 1189 /*
1a2eb460 1190 * There are four kinds of DP registers:
417e822d
KP		 1191 *
1192 * IBX PCH
1a2eb460
KP		 1193 * SNB CPU
1194 * IVB CPU
417e822d
KP		 1195 * CPT PCH
1196 *
1197 * IBX PCH and CPU are the same for almost everything,
1198 * except that the CPU DP PLL is configured in this
1199 * register
1200 *
1201 * CPT PCH is quite different, having many bits moved
1202 * to the TRANS_DP_CTL register instead. That
1203 * configuration happens (oddly) in ironlake_pch_enable
1204 */
9c9e7927 1205
417e822d
KP		 1206 /* Preserve the BIOS-computed detected bit. This is
1207 * supposed to be read-only.
1208 */
1209 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1210
417e822d 1211 /* Handle DP bits in common between all three register formats */
417e822d 1212 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1213 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1214
9ed109a7 1215 if (crtc->config.has_audio) {
e0dac65e 1216 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1217 pipe_name(crtc->pipe));
ea5b213a 1218 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1219 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1220 }
247d89f6 1221
417e822d 1222 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1223
bc7d38a4 1224 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1225 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1226 intel_dp->DP |= DP_SYNC_HS_HIGH;
1227 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1228 intel_dp->DP |= DP_SYNC_VS_HIGH;
1229 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1230
6aba5b6c 1231 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1232 intel_dp->DP |= DP_ENHANCED_FRAMING;
1233
7c62a164 1234 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1235 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1236 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1237 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1238
1239 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1240 intel_dp->DP |= DP_SYNC_HS_HIGH;
1241 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1242 intel_dp->DP |= DP_SYNC_VS_HIGH;
1243 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1244
6aba5b6c 1245 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1246 intel_dp->DP |= DP_ENHANCED_FRAMING;
1247
44f37d1f
CML		 1248 if (!IS_CHERRYVIEW(dev)) {
1249 if (crtc->pipe == 1)
1250 intel_dp->DP |= DP_PIPEB_SELECT;
1251 } else {
1252 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1253 }
417e822d
KP		 1254 } else {
1255 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1256 }
a4fc5ed6
KP		 1257}
1258
ffd6749d
PZ		 1259#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1260#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1261
1a5ef5b7
PZ		 1262#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1263#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1264
ffd6749d
PZ		 1265#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1266#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1267
4be73780 1268static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1269 u32 mask,
1270 u32 value)
bd943159 1271{
30add22d 1272 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1273 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1274 u32 pp_stat_reg, pp_ctrl_reg;
1275
e39b999a
VS		 1276 lockdep_assert_held(&dev_priv->pps_mutex);
1277
bf13e81b
JN		 1278 pp_stat_reg = _pp_stat_reg(intel_dp);
1279 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1280
99ea7127 1281 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1282 mask, value,
1283 I915_READ(pp_stat_reg),
1284 I915_READ(pp_ctrl_reg));
32ce697c 1285
453c5420 1286 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1287 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1288 I915_READ(pp_stat_reg),
1289 I915_READ(pp_ctrl_reg));
32ce697c 1290 }
54c136d4
CW		 1291
1292 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1293}
32ce697c 1294
4be73780 1295static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1296{
1297 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1298 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1299}
1300
4be73780 1301static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1302{
1303 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1304 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1305}
1306
4be73780 1307static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1308{
1309 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1310
1311 /* When we disable the VDD override bit last we have to do the manual
1312 * wait. */
1313 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1314 intel_dp->panel_power_cycle_delay);
1315
4be73780 1316 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1317}
1318
4be73780 1319static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1320{
1321 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1322 intel_dp->backlight_on_delay);
1323}
1324
4be73780 1325static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1326{
1327 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1328 intel_dp->backlight_off_delay);
1329}
99ea7127 1330
832dd3c1
KP		 1331/* Read the current pp_control value, unlocking the register if it
1332 * is locked
1333 */
1334
453c5420 1335static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1336{
453c5420
JB		 1337 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1338 struct drm_i915_private *dev_priv = dev->dev_private;
1339 u32 control;
832dd3c1 1340
e39b999a
VS		 1341 lockdep_assert_held(&dev_priv->pps_mutex);
1342
bf13e81b 1343 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1344 control &= ~PANEL_UNLOCK_MASK;
1345 control |= PANEL_UNLOCK_REGS;
1346 return control;
bd943159
KP		 1347}
1348
951468f3
VS		 1349/*
1350 * Must be paired with edp_panel_vdd_off().
1351 * Must hold pps_mutex around the whole on/off sequence.
1352 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1353 */
1e0560e0 1354static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1355{
30add22d 1356 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1357 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1358 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1359 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1360 enum intel_display_power_domain power_domain;
5d613501 1361 u32 pp;
453c5420 1362 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1363 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1364
e39b999a
VS		 1365 lockdep_assert_held(&dev_priv->pps_mutex);
1366
97af61f5 1367 if (!is_edp(intel_dp))
adddaaf4 1368 return false;
bd943159
KP		 1369
1370 intel_dp->want_panel_vdd = true;
99ea7127 1371
4be73780 1372 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1373 return need_to_disable;
b0665d57 1374
4e6e1a54
ID		 1375 power_domain = intel_display_port_power_domain(intel_encoder);
1376 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1377
b0665d57 1378 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1379
4be73780
DV		 1380 if (!edp_have_panel_power(intel_dp))
1381 wait_panel_power_cycle(intel_dp);
99ea7127 1382
453c5420 1383 pp = ironlake_get_pp_control(intel_dp);
5d613501 1384 pp |= EDP_FORCE_VDD;
ebf33b18 1385
bf13e81b
JN		 1386 pp_stat_reg = _pp_stat_reg(intel_dp);
1387 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1388
1389 I915_WRITE(pp_ctrl_reg, pp);
1390 POSTING_READ(pp_ctrl_reg);
1391 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1392 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1393 /*
1394 * If the panel wasn't on, delay before accessing aux channel
1395 */
4be73780 1396 if (!edp_have_panel_power(intel_dp)) {
bd943159 1397 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1398 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1399 }
adddaaf4
JN		 1400
1401 return need_to_disable;
1402}
1403
951468f3
VS		 1404/*
1405 * Must be paired with intel_edp_panel_vdd_off() or
1406 * intel_edp_panel_off().
1407 * Nested calls to these functions are not allowed since
1408 * we drop the lock. Caller must use some higher level
1409 * locking to prevent nested calls from other threads.
1410 */
b80d6c78 1411void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1412{
c695b6b6 1413 bool vdd;
adddaaf4 1414
c695b6b6
VS		 1415 if (!is_edp(intel_dp))
1416 return;
1417
773538e8 1418 pps_lock(intel_dp);
c695b6b6 1419 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1420 pps_unlock(intel_dp);
c695b6b6
VS		 1421
1422 WARN(!vdd, "eDP VDD already requested on\n");
5d613501
JB		 1423}
1424
4be73780 1425static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1426{
30add22d 1427 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1428 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1429 struct intel_digital_port *intel_dig_port =
1430 dp_to_dig_port(intel_dp);
1431 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1432 enum intel_display_power_domain power_domain;
5d613501 1433 u32 pp;
453c5420 1434 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1435
e39b999a 1436 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1437
15e899a0 1438 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1439
15e899a0 1440 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1441 return;
b0665d57 1442
be2c9196 1443 DRM_DEBUG_KMS("Turning eDP VDD off\n");
bd943159 1444
be2c9196
VS		 1445 pp = ironlake_get_pp_control(intel_dp);
1446 pp &= ~EDP_FORCE_VDD;
453c5420 1447
be2c9196
VS		 1448 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1449 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420 1450
be2c9196
VS		 1451 I915_WRITE(pp_ctrl_reg, pp);
1452 POSTING_READ(pp_ctrl_reg);
99ea7127 1453
be2c9196
VS		 1454 /* Make sure sequencer is idle before allowing subsequent activity */
1455 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1456 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c 1457
be2c9196
VS		 1458 if ((pp & POWER_TARGET_ON) == 0)
1459 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1460
be2c9196
VS		 1461 power_domain = intel_display_port_power_domain(intel_encoder);
1462 intel_display_power_put(dev_priv, power_domain);
bd943159 1463}
5d613501 1464
4be73780 1465static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1466{
1467 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1468 struct intel_dp, panel_vdd_work);
bd943159 1469
773538e8 1470 pps_lock(intel_dp);
15e899a0
VS		 1471 if (!intel_dp->want_panel_vdd)
1472 edp_panel_vdd_off_sync(intel_dp);
773538e8 1473 pps_unlock(intel_dp);
bd943159
KP		 1474}
1475
aba86890
ID		 1476static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1477{
1478 unsigned long delay;
1479
1480 /*
1481 * Queue the timer to fire a long time from now (relative to the power
1482 * down delay) to keep the panel power up across a sequence of
1483 * operations.
1484 */
1485 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1486 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1487}
1488
951468f3
VS		 1489/*
1490 * Must be paired with edp_panel_vdd_on().
1491 * Must hold pps_mutex around the whole on/off sequence.
1492 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1493 */
4be73780 1494static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1495{
e39b999a
VS		 1496 struct drm_i915_private *dev_priv =
1497 intel_dp_to_dev(intel_dp)->dev_private;
1498
1499 lockdep_assert_held(&dev_priv->pps_mutex);
1500
97af61f5
KP		 1501 if (!is_edp(intel_dp))
1502 return;
5d613501 1503
bd943159 1504 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1505
bd943159
KP		 1506 intel_dp->want_panel_vdd = false;
1507
aba86890 1508 if (sync)
4be73780 1509 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1510 else
1511 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1512}
1513
951468f3
VS		 1514/*
1515 * Must be paired with intel_edp_panel_vdd_on().
1516 * Nested calls to these functions are not allowed since
1517 * we drop the lock. Caller must use some higher level
1518 * locking to prevent nested calls from other threads.
1519 */
1e0560e0
VS		 1520static void intel_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1521{
e39b999a
VS		 1522 if (!is_edp(intel_dp))
1523 return;
1524
773538e8 1525 pps_lock(intel_dp);
1e0560e0 1526 edp_panel_vdd_off(intel_dp, sync);
773538e8 1527 pps_unlock(intel_dp);
1e0560e0
VS		 1528}
1529
4be73780 1530void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1531{
30add22d 1532 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1533 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1534 u32 pp;
453c5420 1535 u32 pp_ctrl_reg;
9934c132 1536
97af61f5 1537 if (!is_edp(intel_dp))
bd943159 1538 return;
99ea7127
KP		 1539
1540 DRM_DEBUG_KMS("Turn eDP power on\n");
1541
773538e8 1542 pps_lock(intel_dp);
e39b999a 1543
4be73780 1544 if (edp_have_panel_power(intel_dp)) {
99ea7127 1545 DRM_DEBUG_KMS("eDP power already on\n");
e39b999a 1546 goto out;
99ea7127 1547 }
9934c132 1548
4be73780 1549 wait_panel_power_cycle(intel_dp);
37c6c9b0 1550
bf13e81b 1551 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1552 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1553 if (IS_GEN5(dev)) {
1554 /* ILK workaround: disable reset around power sequence */
1555 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1556 I915_WRITE(pp_ctrl_reg, pp);
1557 POSTING_READ(pp_ctrl_reg);
05ce1a49 1558 }
37c6c9b0 1559
1c0ae80a 1560 pp |= POWER_TARGET_ON;
99ea7127
KP		 1561 if (!IS_GEN5(dev))
1562 pp |= PANEL_POWER_RESET;
1563
453c5420
JB		 1564 I915_WRITE(pp_ctrl_reg, pp);
1565 POSTING_READ(pp_ctrl_reg);
9934c132 1566
4be73780 1567 wait_panel_on(intel_dp);
dce56b3c 1568 intel_dp->last_power_on = jiffies;
9934c132 1569
05ce1a49
KP		 1570 if (IS_GEN5(dev)) {
1571 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1572 I915_WRITE(pp_ctrl_reg, pp);
1573 POSTING_READ(pp_ctrl_reg);
05ce1a49 1574 }
e39b999a
VS		 1575
1576 out:
773538e8 1577 pps_unlock(intel_dp);
9934c132
JB		 1578}
1579
4be73780 1580void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1581{
4e6e1a54
ID		 1582 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1583 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1584 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1585 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1586 enum intel_display_power_domain power_domain;
99ea7127 1587 u32 pp;
453c5420 1588 u32 pp_ctrl_reg;
9934c132 1589
97af61f5
KP		 1590 if (!is_edp(intel_dp))
1591 return;
37c6c9b0 1592
99ea7127 1593 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1594
773538e8 1595 pps_lock(intel_dp);
e39b999a 1596
24f3e092
JN		 1597 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1598
453c5420 1599 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1600 /* We need to switch off panel power _and_ force vdd, for otherwise some
1601 * panels get very unhappy and cease to work. */
b3064154
PJ		 1602 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1603 EDP_BLC_ENABLE);
453c5420 1604
bf13e81b 1605 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1606
849e39f5
PZ		 1607 intel_dp->want_panel_vdd = false;
1608
453c5420
JB		 1609 I915_WRITE(pp_ctrl_reg, pp);
1610 POSTING_READ(pp_ctrl_reg);
9934c132 1611
dce56b3c 1612 intel_dp->last_power_cycle = jiffies;
4be73780 1613 wait_panel_off(intel_dp);
849e39f5
PZ		 1614
1615 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1616 power_domain = intel_display_port_power_domain(intel_encoder);
1617 intel_display_power_put(dev_priv, power_domain);
e39b999a 1618
773538e8 1619 pps_unlock(intel_dp);
9934c132
JB		 1620}
1621
1250d107
JN		 1622/* Enable backlight in the panel power control. */
1623static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1624{
da63a9f2
PZ		 1625 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1626 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1627 struct drm_i915_private *dev_priv = dev->dev_private;
1628 u32 pp;
453c5420 1629 u32 pp_ctrl_reg;
32f9d658 1630
01cb9ea6
JB		 1631 /*
1632 * If we enable the backlight right away following a panel power
1633 * on, we may see slight flicker as the panel syncs with the eDP
1634 * link. So delay a bit to make sure the image is solid before
1635 * allowing it to appear.
1636 */
4be73780 1637 wait_backlight_on(intel_dp);
e39b999a 1638
773538e8 1639 pps_lock(intel_dp);
e39b999a 1640
453c5420 1641 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1642 pp |= EDP_BLC_ENABLE;
453c5420 1643
bf13e81b 1644 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1645
1646 I915_WRITE(pp_ctrl_reg, pp);
1647 POSTING_READ(pp_ctrl_reg);
e39b999a 1648
773538e8 1649 pps_unlock(intel_dp);
32f9d658
ZW		 1650}
1651
1250d107
JN		 1652/* Enable backlight PWM and backlight PP control. */
1653void intel_edp_backlight_on(struct intel_dp *intel_dp)
1654{
1655 if (!is_edp(intel_dp))
1656 return;
1657
1658 DRM_DEBUG_KMS("\n");
1659
1660 intel_panel_enable_backlight(intel_dp->attached_connector);
1661 _intel_edp_backlight_on(intel_dp);
1662}
1663
1664/* Disable backlight in the panel power control. */
1665static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1666{
30add22d 1667 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1668 struct drm_i915_private *dev_priv = dev->dev_private;
1669 u32 pp;
453c5420 1670 u32 pp_ctrl_reg;
32f9d658 1671
f01eca2e
KP		 1672 if (!is_edp(intel_dp))
1673 return;
1674
773538e8 1675 pps_lock(intel_dp);
e39b999a 1676
453c5420 1677 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1678 pp &= ~EDP_BLC_ENABLE;
453c5420 1679
bf13e81b 1680 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1681
1682 I915_WRITE(pp_ctrl_reg, pp);
1683 POSTING_READ(pp_ctrl_reg);
f7d2323c 1684
773538e8 1685 pps_unlock(intel_dp);
e39b999a
VS		 1686
1687 intel_dp->last_backlight_off = jiffies;
f7d2323c 1688 edp_wait_backlight_off(intel_dp);
1250d107 1689}
f7d2323c 1690
1250d107
JN		 1691/* Disable backlight PP control and backlight PWM. */
1692void intel_edp_backlight_off(struct intel_dp *intel_dp)
1693{
1694 if (!is_edp(intel_dp))
1695 return;
1696
1697 DRM_DEBUG_KMS("\n");
f7d2323c 1698
1250d107 1699 _intel_edp_backlight_off(intel_dp);
f7d2323c 1700 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1701}
a4fc5ed6 1702
73580fb7
JN		 1703/*
1704 * Hook for controlling the panel power control backlight through the bl_power
1705 * sysfs attribute. Take care to handle multiple calls.
1706 */
1707static void intel_edp_backlight_power(struct intel_connector *connector,
1708 bool enable)
1709{
1710 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 1711 bool is_enabled;
1712
773538e8 1713 pps_lock(intel_dp);
e39b999a 1714 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 1715 pps_unlock(intel_dp);
73580fb7
JN		 1716
1717 if (is_enabled == enable)
1718 return;
1719
23ba9373
JN		 1720 DRM_DEBUG_KMS("panel power control backlight %s\n",
1721 enable ? "enable" : "disable");
73580fb7
JN		 1722
1723 if (enable)
1724 _intel_edp_backlight_on(intel_dp);
1725 else
1726 _intel_edp_backlight_off(intel_dp);
1727}
1728
2bd2ad64 1729static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1730{
da63a9f2
PZ		 1731 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1732 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1733 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1734 struct drm_i915_private *dev_priv = dev->dev_private;
1735 u32 dpa_ctl;
1736
2bd2ad64
DV		 1737 assert_pipe_disabled(dev_priv,
1738 to_intel_crtc(crtc)->pipe);
1739
d240f20f
JB		 1740 DRM_DEBUG_KMS("\n");
1741 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1742 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1743 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1744
1745 /* We don't adjust intel_dp->DP while tearing down the link, to
1746 * facilitate link retraining (e.g. after hotplug). Hence clear all
1747 * enable bits here to ensure that we don't enable too much. */
1748 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1749 intel_dp->DP |= DP_PLL_ENABLE;
1750 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1751 POSTING_READ(DP_A);
1752 udelay(200);
d240f20f
JB		 1753}
1754
2bd2ad64 1755static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1756{
da63a9f2
PZ		 1757 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1758 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1759 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1760 struct drm_i915_private *dev_priv = dev->dev_private;
1761 u32 dpa_ctl;
1762
2bd2ad64
DV		 1763 assert_pipe_disabled(dev_priv,
1764 to_intel_crtc(crtc)->pipe);
1765
d240f20f 1766 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1767 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1768 "dp pll off, should be on\n");
1769 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1770
1771 /* We can't rely on the value tracked for the DP register in
1772 * intel_dp->DP because link_down must not change that (otherwise link
1773 * re-training will fail. */
298b0b39 1774 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1775 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1776 POSTING_READ(DP_A);
d240f20f
JB		 1777 udelay(200);
1778}
1779
c7ad3810 1780/* If the sink supports it, try to set the power state appropriately */
c19b0669 1781void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1782{
1783 int ret, i;
1784
1785 /* Should have a valid DPCD by this point */
1786 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1787 return;
1788
1789 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1790 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1791 DP_SET_POWER_D3);
c7ad3810
JB		 1792 } else {
1793 /*
1794 * When turning on, we need to retry for 1ms to give the sink
1795 * time to wake up.
1796 */
1797 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1798 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1799 DP_SET_POWER_D0);
c7ad3810
JB		 1800 if (ret == 1)
1801 break;
1802 msleep(1);
1803 }
1804 }
f9cac721
JN		 1805
1806 if (ret != 1)
1807 DRM_DEBUG_KMS("failed to %s sink power state\n",
1808 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 1809}
1810
19d8fe15
DV		 1811static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1812 enum pipe *pipe)
d240f20f 1813{
19d8fe15 1814 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1815 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1816 struct drm_device *dev = encoder->base.dev;
1817 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1818 enum intel_display_power_domain power_domain;
1819 u32 tmp;
1820
1821 power_domain = intel_display_port_power_domain(encoder);
1822 if (!intel_display_power_enabled(dev_priv, power_domain))
1823 return false;
1824
1825 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1826
1827 if (!(tmp & DP_PORT_EN))
1828 return false;
1829
bc7d38a4 1830 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1831 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1832 } else if (IS_CHERRYVIEW(dev)) {
1833 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1834 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1835 *pipe = PORT_TO_PIPE(tmp);
1836 } else {
1837 u32 trans_sel;
1838 u32 trans_dp;
1839 int i;
1840
1841 switch (intel_dp->output_reg) {
1842 case PCH_DP_B:
1843 trans_sel = TRANS_DP_PORT_SEL_B;
1844 break;
1845 case PCH_DP_C:
1846 trans_sel = TRANS_DP_PORT_SEL_C;
1847 break;
1848 case PCH_DP_D:
1849 trans_sel = TRANS_DP_PORT_SEL_D;
1850 break;
1851 default:
1852 return true;
1853 }
1854
055e393f 1855 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 1856 trans_dp = I915_READ(TRANS_DP_CTL(i));
1857 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1858 *pipe = i;
1859 return true;
1860 }
1861 }
19d8fe15 1862
4a0833ec
DV		 1863 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1864 intel_dp->output_reg);
1865 }
d240f20f 1866
19d8fe15
DV		 1867 return true;
1868}
d240f20f 1869
045ac3b5
JB		 1870static void intel_dp_get_config(struct intel_encoder *encoder,
1871 struct intel_crtc_config *pipe_config)
1872{
1873 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1874 u32 tmp, flags = 0;
63000ef6
XZ		 1875 struct drm_device *dev = encoder->base.dev;
1876 struct drm_i915_private *dev_priv = dev->dev_private;
1877 enum port port = dp_to_dig_port(intel_dp)->port;
1878 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1879 int dotclock;
045ac3b5 1880
9ed109a7
DV		 1881 tmp = I915_READ(intel_dp->output_reg);
1882 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1883 pipe_config->has_audio = true;
1884
63000ef6 1885 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1886 if (tmp & DP_SYNC_HS_HIGH)
1887 flags |= DRM_MODE_FLAG_PHSYNC;
1888 else
1889 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1890
63000ef6
XZ		 1891 if (tmp & DP_SYNC_VS_HIGH)
1892 flags |= DRM_MODE_FLAG_PVSYNC;
1893 else
1894 flags |= DRM_MODE_FLAG_NVSYNC;
1895 } else {
1896 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1897 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1898 flags |= DRM_MODE_FLAG_PHSYNC;
1899 else
1900 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1901
63000ef6
XZ		 1902 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1903 flags |= DRM_MODE_FLAG_PVSYNC;
1904 else
1905 flags |= DRM_MODE_FLAG_NVSYNC;
1906 }
045ac3b5
JB		 1907
1908 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1909
eb14cb74
VS		 1910 pipe_config->has_dp_encoder = true;
1911
1912 intel_dp_get_m_n(crtc, pipe_config);
1913
18442d08 1914 if (port == PORT_A) {
f1f644dc
JB		 1915 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1916 pipe_config->port_clock = 162000;
1917 else
1918 pipe_config->port_clock = 270000;
1919 }
18442d08
VS		 1920
1921 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1922 &pipe_config->dp_m_n);
1923
1924 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1925 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1926
241bfc38 1927 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1928
c6cd2ee2
JN		 1929 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1930 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1931 /*
1932 * This is a big fat ugly hack.
1933 *
1934 * Some machines in UEFI boot mode provide us a VBT that has 18
1935 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1936 * unknown we fail to light up. Yet the same BIOS boots up with
1937 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1938 * max, not what it tells us to use.
1939 *
1940 * Note: This will still be broken if the eDP panel is not lit
1941 * up by the BIOS, and thus we can't get the mode at module
1942 * load.
1943 */
1944 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1945 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1946 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1947 }
045ac3b5
JB		 1948}
1949
34eb7579 1950static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 1951{
34eb7579 1952 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 1953}
1954
2b28bb1b
RV		 1955static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1956{
1957 struct drm_i915_private *dev_priv = dev->dev_private;
1958
18b5992c 1959 if (!HAS_PSR(dev))
2b28bb1b
RV		 1960 return false;
1961
18b5992c 1962 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1963}
1964
1965static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1966 struct edp_vsc_psr *vsc_psr)
1967{
1968 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1969 struct drm_device *dev = dig_port->base.base.dev;
1970 struct drm_i915_private *dev_priv = dev->dev_private;
1971 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1972 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1973 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1974 uint32_t *data = (uint32_t *) vsc_psr;
1975 unsigned int i;
1976
1977 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1978 the video DIP being updated before program video DIP data buffer
1979 registers for DIP being updated. */
1980 I915_WRITE(ctl_reg, 0);
1981 POSTING_READ(ctl_reg);
1982
1983 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1984 if (i < sizeof(struct edp_vsc_psr))
1985 I915_WRITE(data_reg + i, *data++);
1986 else
1987 I915_WRITE(data_reg + i, 0);
1988 }
1989
1990 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1991 POSTING_READ(ctl_reg);
1992}
1993
1994static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1995{
1996 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1997 struct drm_i915_private *dev_priv = dev->dev_private;
1998 struct edp_vsc_psr psr_vsc;
1999
2b28bb1b
RV		 2000 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
2001 memset(&psr_vsc, 0, sizeof(psr_vsc));
2002 psr_vsc.sdp_header.HB0 = 0;
2003 psr_vsc.sdp_header.HB1 = 0x7;
2004 psr_vsc.sdp_header.HB2 = 0x2;
2005 psr_vsc.sdp_header.HB3 = 0x8;
2006 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
2007
2008 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 2009 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 2010 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 2011}
2012
2013static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
2014{
0e0ae652
RV		 2015 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2016 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 2017 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 2018 uint32_t aux_clock_divider;
2b28bb1b
RV		 2019 int precharge = 0x3;
2020 int msg_size = 5; /* Header(4) + Message(1) */
0e0ae652 2021 bool only_standby = false;
2b28bb1b 2022
ec5b01dd
DL		 2023 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
2024
0e0ae652
RV		 2025 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2026 only_standby = true;
2027
2b28bb1b 2028 /* Enable PSR in sink */
0e0ae652 2029 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 2030 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2031 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 2032 else
9d1a1031
JN		 2033 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2034 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 2035
2036 /* Setup AUX registers */
18b5992c
BW		 2037 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
2038 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
2039 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 2040 DP_AUX_CH_CTL_TIME_OUT_400us |
2041 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
2042 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
2043 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
2044}
2045
2046static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
2047{
0e0ae652
RV		 2048 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2049 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 2050 struct drm_i915_private *dev_priv = dev->dev_private;
2051 uint32_t max_sleep_time = 0x1f;
2052 uint32_t idle_frames = 1;
2053 uint32_t val = 0x0;
ed8546ac 2054 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 2055 bool only_standby = false;
2056
2057 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2058 only_standby = true;
2b28bb1b 2059
0e0ae652 2060 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 2061 val |= EDP_PSR_LINK_STANDBY;
2062 val |= EDP_PSR_TP2_TP3_TIME_0us;
2063 val |= EDP_PSR_TP1_TIME_0us;
2064 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 2065 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 2066 } else
2067 val |= EDP_PSR_LINK_DISABLE;
2068
18b5992c 2069 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 2070 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 2071 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
2072 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
2073 EDP_PSR_ENABLE);
2074}
2075
3f51e471
RV		 2076static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
2077{
2078 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2079 struct drm_device *dev = dig_port->base.base.dev;
2080 struct drm_i915_private *dev_priv = dev->dev_private;
2081 struct drm_crtc *crtc = dig_port->base.base.crtc;
2082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3f51e471 2083
f0355c4a 2084 lockdep_assert_held(&dev_priv->psr.lock);
f0355c4a
DV		 2085 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
2086 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
2087
a031d709
RV		 2088 dev_priv->psr.source_ok = false;
2089
9ca15301 2090 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
3f51e471 2091 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 2092 return false;
2093 }
2094
d330a953 2095 if (!i915.enable_psr) {
105b7c11 2096 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 2097 return false;
2098 }
2099
4c8c7000
RV		 2100 /* Below limitations aren't valid for Broadwell */
2101 if (IS_BROADWELL(dev))
2102 goto out;
2103
3f51e471
RV		 2104 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
2105 S3D_ENABLE) {
2106 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 2107 return false;
2108 }
2109
ca73b4f0 2110 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 2111 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 2112 return false;
2113 }
2114
4c8c7000 2115 out:
a031d709 2116 dev_priv->psr.source_ok = true;
3f51e471
RV		 2117 return true;
2118}
2119
3d739d92 2120static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 2121{
7c8f8a70
RV		 2122 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2123 struct drm_device *dev = intel_dig_port->base.base.dev;
2124 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 2125
3638379c
DV		 2126 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2127 WARN_ON(dev_priv->psr.active);
f0355c4a 2128 lockdep_assert_held(&dev_priv->psr.lock);
2b28bb1b 2129
2b28bb1b
RV		 2130 /* Enable PSR on the panel */
2131 intel_edp_psr_enable_sink(intel_dp);
2132
2133 /* Enable PSR on the host */
2134 intel_edp_psr_enable_source(intel_dp);
7c8f8a70 2135
7c8f8a70 2136 dev_priv->psr.active = true;
2b28bb1b
RV		 2137}
2138
3d739d92
RV		 2139void intel_edp_psr_enable(struct intel_dp *intel_dp)
2140{
2141 struct drm_device *dev = intel_dp_to_dev(intel_dp);
109fc2ad 2142 struct drm_i915_private *dev_priv = dev->dev_private;
3d739d92 2143
4704c573
RV		 2144 if (!HAS_PSR(dev)) {
2145 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2146 return;
2147 }
2148
34eb7579
RV		 2149 if (!is_edp_psr(intel_dp)) {
2150 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2151 return;
2152 }
2153
f0355c4a 2154 mutex_lock(&dev_priv->psr.lock);
109fc2ad
DV		 2155 if (dev_priv->psr.enabled) {
2156 DRM_DEBUG_KMS("PSR already in use\n");
f0355c4a 2157 mutex_unlock(&dev_priv->psr.lock);
109fc2ad
DV		 2158 return;
2159 }
2160
9ca15301
DV		 2161 dev_priv->psr.busy_frontbuffer_bits = 0;
2162
16487254
RV		 2163 /* Setup PSR once */
2164 intel_edp_psr_setup(intel_dp);
2165
7c8f8a70 2166 if (intel_edp_psr_match_conditions(intel_dp))
9ca15301 2167 dev_priv->psr.enabled = intel_dp;
f0355c4a 2168 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2169}
2170
2b28bb1b
RV		 2171void intel_edp_psr_disable(struct intel_dp *intel_dp)
2172{
2173 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2174 struct drm_i915_private *dev_priv = dev->dev_private;
2175
f0355c4a
DV		 2176 mutex_lock(&dev_priv->psr.lock);
2177 if (!dev_priv->psr.enabled) {
2178 mutex_unlock(&dev_priv->psr.lock);
2179 return;
2180 }
2181
3638379c
DV		 2182 if (dev_priv->psr.active) {
2183 I915_WRITE(EDP_PSR_CTL(dev),
2184 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2185
2186 /* Wait till PSR is idle */
2187 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2188 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
2189 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2b28bb1b 2190
3638379c
DV		 2191 dev_priv->psr.active = false;
2192 } else {
2193 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2194 }
7c8f8a70 2195
2807cf69 2196 dev_priv->psr.enabled = NULL;
f0355c4a 2197 mutex_unlock(&dev_priv->psr.lock);
9ca15301
DV		 2198
2199 cancel_delayed_work_sync(&dev_priv->psr.work);
2b28bb1b
RV		 2200}
2201
f02a326e 2202static void intel_edp_psr_work(struct work_struct *work)
7c8f8a70
RV		 2203{
2204 struct drm_i915_private *dev_priv =
2205 container_of(work, typeof(*dev_priv), psr.work.work);
2807cf69
DV		 2206 struct intel_dp *intel_dp = dev_priv->psr.enabled;
2207
f0355c4a
DV		 2208 mutex_lock(&dev_priv->psr.lock);
2209 intel_dp = dev_priv->psr.enabled;
2210
2807cf69 2211 if (!intel_dp)
f0355c4a 2212 goto unlock;
2807cf69 2213
9ca15301
DV		 2214 /*
2215 * The delayed work can race with an invalidate hence we need to
2216 * recheck. Since psr_flush first clears this and then reschedules we
2217 * won't ever miss a flush when bailing out here.
2218 */
2219 if (dev_priv->psr.busy_frontbuffer_bits)
2220 goto unlock;
2221
2222 intel_edp_psr_do_enable(intel_dp);
f0355c4a
DV		 2223unlock:
2224 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2225}
2226
9ca15301 2227static void intel_edp_psr_do_exit(struct drm_device *dev)
7c8f8a70
RV		 2228{
2229 struct drm_i915_private *dev_priv = dev->dev_private;
2230
3638379c
DV		 2231 if (dev_priv->psr.active) {
2232 u32 val = I915_READ(EDP_PSR_CTL(dev));
2233
2234 WARN_ON(!(val & EDP_PSR_ENABLE));
2235
2236 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
2237
2238 dev_priv->psr.active = false;
2239 }
7c8f8a70 2240
9ca15301
DV		 2241}
2242
2243void intel_edp_psr_invalidate(struct drm_device *dev,
2244 unsigned frontbuffer_bits)
2245{
2246 struct drm_i915_private *dev_priv = dev->dev_private;
2247 struct drm_crtc *crtc;
2248 enum pipe pipe;
2249
9ca15301
DV		 2250 mutex_lock(&dev_priv->psr.lock);
2251 if (!dev_priv->psr.enabled) {
2252 mutex_unlock(&dev_priv->psr.lock);
2253 return;
2254 }
2255
2256 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2257 pipe = to_intel_crtc(crtc)->pipe;
2258
2259 intel_edp_psr_do_exit(dev);
2260
2261 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2262
2263 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2264 mutex_unlock(&dev_priv->psr.lock);
2265}
2266
2267void intel_edp_psr_flush(struct drm_device *dev,
2268 unsigned frontbuffer_bits)
2269{
2270 struct drm_i915_private *dev_priv = dev->dev_private;
2271 struct drm_crtc *crtc;
2272 enum pipe pipe;
2273
9ca15301
DV		 2274 mutex_lock(&dev_priv->psr.lock);
2275 if (!dev_priv->psr.enabled) {
2276 mutex_unlock(&dev_priv->psr.lock);
2277 return;
2278 }
2279
2280 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2281 pipe = to_intel_crtc(crtc)->pipe;
2282 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2283
2284 /*
2285 * On Haswell sprite plane updates don't result in a psr invalidating
2286 * signal in the hardware. Which means we need to manually fake this in
2287 * software for all flushes, not just when we've seen a preceding
2288 * invalidation through frontbuffer rendering.
2289 */
2290 if (IS_HASWELL(dev) &&
2291 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2292 intel_edp_psr_do_exit(dev);
2293
2294 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2295 schedule_delayed_work(&dev_priv->psr.work,
2296 msecs_to_jiffies(100));
f0355c4a 2297 mutex_unlock(&dev_priv->psr.lock);
7c8f8a70
RV		 2298}
2299
2300void intel_edp_psr_init(struct drm_device *dev)
2301{
2302 struct drm_i915_private *dev_priv = dev->dev_private;
2303
7c8f8a70 2304 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
f0355c4a 2305 mutex_init(&dev_priv->psr.lock);
7c8f8a70
RV		 2306}
2307
e8cb4558 2308static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2309{
e8cb4558 2310 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2311 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 2312
2313 /* Make sure the panel is off before trying to change the mode. But also
2314 * ensure that we have vdd while we switch off the panel. */
24f3e092 2315 intel_edp_panel_vdd_on(intel_dp);
4be73780 2316 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2317 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2318 intel_edp_panel_off(intel_dp);
3739850b 2319
08aff3fe
VS		 2320 /* disable the port before the pipe on g4x */
2321 if (INTEL_INFO(dev)->gen < 5)
3739850b 2322 intel_dp_link_down(intel_dp);
d240f20f
JB		 2323}
2324
08aff3fe 2325static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2326{
2bd2ad64 2327 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2328 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2329
49277c31 2330 intel_dp_link_down(intel_dp);
08aff3fe
VS		 2331 if (port == PORT_A)
2332 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2333}
2334
2335static void vlv_post_disable_dp(struct intel_encoder *encoder)
2336{
2337 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2338
2339 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2340}
2341
580d3811
VS		 2342static void chv_post_disable_dp(struct intel_encoder *encoder)
2343{
2344 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2345 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2346 struct drm_device *dev = encoder->base.dev;
2347 struct drm_i915_private *dev_priv = dev->dev_private;
2348 struct intel_crtc *intel_crtc =
2349 to_intel_crtc(encoder->base.crtc);
2350 enum dpio_channel ch = vlv_dport_to_channel(dport);
2351 enum pipe pipe = intel_crtc->pipe;
2352 u32 val;
2353
2354 intel_dp_link_down(intel_dp);
2355
2356 mutex_lock(&dev_priv->dpio_lock);
2357
2358 /* Propagate soft reset to data lane reset */
97fd4d5c 2359 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2360 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2361 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2362
97fd4d5c
VS		 2363 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2364 val |= CHV_PCS_REQ_SOFTRESET_EN;
2365 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2366
2367 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2368 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2369 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2370
2371 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2372 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2373 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2374
2375 mutex_unlock(&dev_priv->dpio_lock);
2376}
2377
7b13b58a
VS		 2378static void
2379_intel_dp_set_link_train(struct intel_dp *intel_dp,
2380 uint32_t *DP,
2381 uint8_t dp_train_pat)
2382{
2383 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2384 struct drm_device *dev = intel_dig_port->base.base.dev;
2385 struct drm_i915_private *dev_priv = dev->dev_private;
2386 enum port port = intel_dig_port->port;
2387
2388 if (HAS_DDI(dev)) {
2389 uint32_t temp = I915_READ(DP_TP_CTL(port));
2390
2391 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2392 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2393 else
2394 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2395
2396 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2397 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2398 case DP_TRAINING_PATTERN_DISABLE:
2399 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2400
2401 break;
2402 case DP_TRAINING_PATTERN_1:
2403 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2404 break;
2405 case DP_TRAINING_PATTERN_2:
2406 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2407 break;
2408 case DP_TRAINING_PATTERN_3:
2409 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2410 break;
2411 }
2412 I915_WRITE(DP_TP_CTL(port), temp);
2413
2414 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2415 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2416
2417 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2418 case DP_TRAINING_PATTERN_DISABLE:
2419 *DP |= DP_LINK_TRAIN_OFF_CPT;
2420 break;
2421 case DP_TRAINING_PATTERN_1:
2422 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2423 break;
2424 case DP_TRAINING_PATTERN_2:
2425 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2426 break;
2427 case DP_TRAINING_PATTERN_3:
2428 DRM_ERROR("DP training pattern 3 not supported\n");
2429 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2430 break;
2431 }
2432
2433 } else {
2434 if (IS_CHERRYVIEW(dev))
2435 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2436 else
2437 *DP &= ~DP_LINK_TRAIN_MASK;
2438
2439 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2440 case DP_TRAINING_PATTERN_DISABLE:
2441 *DP |= DP_LINK_TRAIN_OFF;
2442 break;
2443 case DP_TRAINING_PATTERN_1:
2444 *DP |= DP_LINK_TRAIN_PAT_1;
2445 break;
2446 case DP_TRAINING_PATTERN_2:
2447 *DP |= DP_LINK_TRAIN_PAT_2;
2448 break;
2449 case DP_TRAINING_PATTERN_3:
2450 if (IS_CHERRYVIEW(dev)) {
2451 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2452 } else {
2453 DRM_ERROR("DP training pattern 3 not supported\n");
2454 *DP |= DP_LINK_TRAIN_PAT_2;
2455 }
2456 break;
2457 }
2458 }
2459}
2460
2461static void intel_dp_enable_port(struct intel_dp *intel_dp)
2462{
2463 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2464 struct drm_i915_private *dev_priv = dev->dev_private;
2465
2466 intel_dp->DP |= DP_PORT_EN;
2467
2468 /* enable with pattern 1 (as per spec) */
2469 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2470 DP_TRAINING_PATTERN_1);
2471
2472 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2473 POSTING_READ(intel_dp->output_reg);
2474}
2475
e8cb4558 2476static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2477{
e8cb4558
DV		 2478 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2479 struct drm_device *dev = encoder->base.dev;
2480 struct drm_i915_private *dev_priv = dev->dev_private;
2481 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2482
0c33d8d7
DV		 2483 if (WARN_ON(dp_reg & DP_PORT_EN))
2484 return;
5d613501 2485
7b13b58a 2486 intel_dp_enable_port(intel_dp);
24f3e092 2487 intel_edp_panel_vdd_on(intel_dp);
4be73780 2488 intel_edp_panel_on(intel_dp);
1e0560e0 2489 intel_edp_panel_vdd_off(intel_dp, true);
f01eca2e 2490 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2491 intel_dp_start_link_train(intel_dp);
33a34e4e 2492 intel_dp_complete_link_train(intel_dp);
3ab9c637 2493 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2494}
89b667f8 2495
ecff4f3b
JN		 2496static void g4x_enable_dp(struct intel_encoder *encoder)
2497{
828f5c6e
JN		 2498 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2499
ecff4f3b 2500 intel_enable_dp(encoder);
4be73780 2501 intel_edp_backlight_on(intel_dp);
ab1f90f9 2502}
89b667f8 2503
ab1f90f9
JN		 2504static void vlv_enable_dp(struct intel_encoder *encoder)
2505{
828f5c6e
JN		 2506 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2507
4be73780 2508 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2509}
2510
ecff4f3b 2511static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2512{
2513 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2514 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2515
8ac33ed3
DV		 2516 intel_dp_prepare(encoder);
2517
d41f1efb
DV		 2518 /* Only ilk+ has port A */
2519 if (dport->port == PORT_A) {
2520 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2521 ironlake_edp_pll_on(intel_dp);
d41f1efb 2522 }
ab1f90f9
JN		 2523}
2524
a4a5d2f8
VS		 2525static void vlv_steal_power_sequencer(struct drm_device *dev,
2526 enum pipe pipe)
2527{
2528 struct drm_i915_private *dev_priv = dev->dev_private;
2529 struct intel_encoder *encoder;
2530
2531 lockdep_assert_held(&dev_priv->pps_mutex);
2532
2533 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2534 base.head) {
2535 struct intel_dp *intel_dp;
773538e8 2536 enum port port;
a4a5d2f8
VS		 2537
2538 if (encoder->type != INTEL_OUTPUT_EDP)
2539 continue;
2540
2541 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2542 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2543
2544 if (intel_dp->pps_pipe != pipe)
2545 continue;
2546
2547 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2548 pipe_name(pipe), port_name(port));
a4a5d2f8
VS		 2549
2550 /* make sure vdd is off before we steal it */
2551 edp_panel_vdd_off_sync(intel_dp);
2552
2553 intel_dp->pps_pipe = INVALID_PIPE;
2554 }
2555}
2556
2557static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2558{
2559 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2560 struct intel_encoder *encoder = &intel_dig_port->base;
2561 struct drm_device *dev = encoder->base.dev;
2562 struct drm_i915_private *dev_priv = dev->dev_private;
2563 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2564 struct edp_power_seq power_seq;
2565
2566 lockdep_assert_held(&dev_priv->pps_mutex);
2567
2568 if (intel_dp->pps_pipe == crtc->pipe)
2569 return;
2570
2571 /*
2572 * If another power sequencer was being used on this
2573 * port previously make sure to turn off vdd there while
2574 * we still have control of it.
2575 */
2576 if (intel_dp->pps_pipe != INVALID_PIPE)
2577 edp_panel_vdd_off_sync(intel_dp);
2578
2579 /*
2580 * We may be stealing the power
2581 * sequencer from another port.
2582 */
2583 vlv_steal_power_sequencer(dev, crtc->pipe);
2584
2585 /* now it's all ours */
2586 intel_dp->pps_pipe = crtc->pipe;
2587
2588 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2589 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2590
2591 /* init power sequencer on this pipe and port */
2592 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2593 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2594 &power_seq);
2595}
2596
ab1f90f9 2597static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2598{
2bd2ad64 2599 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2600 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2601 struct drm_device *dev = encoder->base.dev;
89b667f8 2602 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2603 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2604 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2605 int pipe = intel_crtc->pipe;
2606 u32 val;
a4fc5ed6 2607
ab1f90f9 2608 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2609
ab3c759a 2610 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2611 val = 0;
2612 if (pipe)
2613 val |= (1<<21);
2614 else
2615 val &= ~(1<<21);
2616 val |= 0x001000c4;
ab3c759a
CML		 2617 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2618 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2619 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2620
ab1f90f9
JN		 2621 mutex_unlock(&dev_priv->dpio_lock);
2622
2cac613b 2623 if (is_edp(intel_dp)) {
773538e8 2624 pps_lock(intel_dp);
a4a5d2f8 2625 vlv_init_panel_power_sequencer(intel_dp);
773538e8 2626 pps_unlock(intel_dp);
2cac613b 2627 }
bf13e81b 2628
ab1f90f9
JN		 2629 intel_enable_dp(encoder);
2630
e4607fcf 2631 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 2632}
2633
ecff4f3b 2634static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2635{
2636 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2637 struct drm_device *dev = encoder->base.dev;
2638 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2639 struct intel_crtc *intel_crtc =
2640 to_intel_crtc(encoder->base.crtc);
e4607fcf 2641 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2642 int pipe = intel_crtc->pipe;
89b667f8 2643
8ac33ed3
DV		 2644 intel_dp_prepare(encoder);
2645
89b667f8 2646 /* Program Tx lane resets to default */
0980a60f 2647 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2648 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2649 DPIO_PCS_TX_LANE2_RESET |
2650 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2651 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2652 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2653 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2654 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2655 DPIO_PCS_CLK_SOFT_RESET);
2656
2657 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2658 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2659 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2660 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2661 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2662}
2663
e4a1d846
CML		 2664static void chv_pre_enable_dp(struct intel_encoder *encoder)
2665{
2666 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2667 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2668 struct drm_device *dev = encoder->base.dev;
2669 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2670 struct intel_crtc *intel_crtc =
2671 to_intel_crtc(encoder->base.crtc);
2672 enum dpio_channel ch = vlv_dport_to_channel(dport);
2673 int pipe = intel_crtc->pipe;
2674 int data, i;
949c1d43 2675 u32 val;
e4a1d846 2676
e4a1d846 2677 mutex_lock(&dev_priv->dpio_lock);
949c1d43
VS		 2678
2679 /* Deassert soft data lane reset*/
97fd4d5c 2680 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2681 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2682 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2683
2684 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2685 val |= CHV_PCS_REQ_SOFTRESET_EN;
2686 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2687
2688 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2689 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2690 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2691
97fd4d5c 2692 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2693 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2694 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2695
2696 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2697 for (i = 0; i < 4; i++) {
2698 /* Set the latency optimal bit */
2699 data = (i == 1) ? 0x0 : 0x6;
2700 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2701 data << DPIO_FRC_LATENCY_SHFIT);
2702
2703 /* Set the upar bit */
2704 data = (i == 1) ? 0x0 : 0x1;
2705 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2706 data << DPIO_UPAR_SHIFT);
2707 }
2708
2709 /* Data lane stagger programming */
2710 /* FIXME: Fix up value only after power analysis */
2711
2712 mutex_unlock(&dev_priv->dpio_lock);
2713
2714 if (is_edp(intel_dp)) {
773538e8 2715 pps_lock(intel_dp);
a4a5d2f8 2716 vlv_init_panel_power_sequencer(intel_dp);
773538e8 2717 pps_unlock(intel_dp);
e4a1d846
CML		 2718 }
2719
2720 intel_enable_dp(encoder);
2721
2722 vlv_wait_port_ready(dev_priv, dport);
2723}
2724
9197c88b
VS		 2725static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2726{
2727 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2728 struct drm_device *dev = encoder->base.dev;
2729 struct drm_i915_private *dev_priv = dev->dev_private;
2730 struct intel_crtc *intel_crtc =
2731 to_intel_crtc(encoder->base.crtc);
2732 enum dpio_channel ch = vlv_dport_to_channel(dport);
2733 enum pipe pipe = intel_crtc->pipe;
2734 u32 val;
2735
625695f8
VS		 2736 intel_dp_prepare(encoder);
2737
9197c88b
VS		 2738 mutex_lock(&dev_priv->dpio_lock);
2739
b9e5ac3c
VS		 2740 /* program left/right clock distribution */
2741 if (pipe != PIPE_B) {
2742 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2743 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2744 if (ch == DPIO_CH0)
2745 val |= CHV_BUFLEFTENA1_FORCE;
2746 if (ch == DPIO_CH1)
2747 val |= CHV_BUFRIGHTENA1_FORCE;
2748 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2749 } else {
2750 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2751 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2752 if (ch == DPIO_CH0)
2753 val |= CHV_BUFLEFTENA2_FORCE;
2754 if (ch == DPIO_CH1)
2755 val |= CHV_BUFRIGHTENA2_FORCE;
2756 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2757 }
2758
9197c88b
VS		 2759 /* program clock channel usage */
2760 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2761 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2762 if (pipe != PIPE_B)
2763 val &= ~CHV_PCS_USEDCLKCHANNEL;
2764 else
2765 val |= CHV_PCS_USEDCLKCHANNEL;
2766 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2767
2768 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2769 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2770 if (pipe != PIPE_B)
2771 val &= ~CHV_PCS_USEDCLKCHANNEL;
2772 else
2773 val |= CHV_PCS_USEDCLKCHANNEL;
2774 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2775
2776 /*
2777 * This a a bit weird since generally CL
2778 * matches the pipe, but here we need to
2779 * pick the CL based on the port.
2780 */
2781 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2782 if (pipe != PIPE_B)
2783 val &= ~CHV_CMN_USEDCLKCHANNEL;
2784 else
2785 val |= CHV_CMN_USEDCLKCHANNEL;
2786 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2787
2788 mutex_unlock(&dev_priv->dpio_lock);
2789}
2790
a4fc5ed6 2791/*
df0c237d
JB		 2792 * Native read with retry for link status and receiver capability reads for
2793 * cases where the sink may still be asleep.
9d1a1031
JN		 2794 *
2795 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2796 * supposed to retry 3 times per the spec.
a4fc5ed6 2797 */
9d1a1031
JN		 2798static ssize_t
2799intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2800 void *buffer, size_t size)
a4fc5ed6 2801{
9d1a1031
JN		 2802 ssize_t ret;
2803 int i;
61da5fab 2804
61da5fab 2805 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2806 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2807 if (ret == size)
2808 return ret;
61da5fab
JB		 2809 msleep(1);
2810 }
a4fc5ed6 2811
9d1a1031 2812 return ret;
a4fc5ed6
KP		 2813}
2814
2815/*
2816 * Fetch AUX CH registers 0x202 - 0x207 which contain
2817 * link status information
2818 */
2819static bool
93f62dad 2820intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2821{
9d1a1031
JN		 2822 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2823 DP_LANE0_1_STATUS,
2824 link_status,
2825 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2826}
2827
1100244e 2828/* These are source-specific values. */
a4fc5ed6 2829static uint8_t
1a2eb460 2830intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2831{
30add22d 2832 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2833 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2834
9576c27f 2835 if (IS_VALLEYVIEW(dev))
bd60018a 2836 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2837 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2838 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2839 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2840 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2841 else
bd60018a 2842 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2843}
2844
2845static uint8_t
2846intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2847{
30add22d 2848 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2849 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2850
9576c27f 2851 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2852 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2853 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2854 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2855 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2856 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2857 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2858 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2859 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2860 default:
bd60018a 2861 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2862 }
e2fa6fba
P		 2863 } else if (IS_VALLEYVIEW(dev)) {
2864 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2865 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2866 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2867 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2868 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2869 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2870 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2871 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2872 default:
bd60018a 2873 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2874 }
bc7d38a4 2875 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2876 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2877 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2878 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2879 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2880 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2881 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2882 default:
bd60018a 2883 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 2884 }
2885 } else {
2886 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2887 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2888 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2889 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2890 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2891 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2892 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2893 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 2894 default:
bd60018a 2895 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 2896 }
a4fc5ed6
KP		 2897 }
2898}
2899
e2fa6fba
P		 2900static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2901{
2902 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2903 struct drm_i915_private *dev_priv = dev->dev_private;
2904 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2905 struct intel_crtc *intel_crtc =
2906 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2907 unsigned long demph_reg_value, preemph_reg_value,
2908 uniqtranscale_reg_value;
2909 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2910 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2911 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2912
2913 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2914 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 2915 preemph_reg_value = 0x0004000;
2916 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2917 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2918 demph_reg_value = 0x2B405555;
2919 uniqtranscale_reg_value = 0x552AB83A;
2920 break;
bd60018a 2921 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2922 demph_reg_value = 0x2B404040;
2923 uniqtranscale_reg_value = 0x5548B83A;
2924 break;
bd60018a 2925 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2926 demph_reg_value = 0x2B245555;
2927 uniqtranscale_reg_value = 0x5560B83A;
2928 break;
bd60018a 2929 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 2930 demph_reg_value = 0x2B405555;
2931 uniqtranscale_reg_value = 0x5598DA3A;
2932 break;
2933 default:
2934 return 0;
2935 }
2936 break;
bd60018a 2937 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 2938 preemph_reg_value = 0x0002000;
2939 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2940 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2941 demph_reg_value = 0x2B404040;
2942 uniqtranscale_reg_value = 0x5552B83A;
2943 break;
bd60018a 2944 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2945 demph_reg_value = 0x2B404848;
2946 uniqtranscale_reg_value = 0x5580B83A;
2947 break;
bd60018a 2948 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2949 demph_reg_value = 0x2B404040;
2950 uniqtranscale_reg_value = 0x55ADDA3A;
2951 break;
2952 default:
2953 return 0;
2954 }
2955 break;
bd60018a 2956 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 2957 preemph_reg_value = 0x0000000;
2958 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2959 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2960 demph_reg_value = 0x2B305555;
2961 uniqtranscale_reg_value = 0x5570B83A;
2962 break;
bd60018a 2963 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2964 demph_reg_value = 0x2B2B4040;
2965 uniqtranscale_reg_value = 0x55ADDA3A;
2966 break;
2967 default:
2968 return 0;
2969 }
2970 break;
bd60018a 2971 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 2972 preemph_reg_value = 0x0006000;
2973 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2974 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2975 demph_reg_value = 0x1B405555;
2976 uniqtranscale_reg_value = 0x55ADDA3A;
2977 break;
2978 default:
2979 return 0;
2980 }
2981 break;
2982 default:
2983 return 0;
2984 }
2985
0980a60f 2986 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2987 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2988 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2989 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2990 uniqtranscale_reg_value);
ab3c759a
CML		 2991 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2992 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2993 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2994 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2995 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2996
2997 return 0;
2998}
2999
e4a1d846
CML		 3000static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
3001{
3002 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3003 struct drm_i915_private *dev_priv = dev->dev_private;
3004 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3005 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 3006 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 3007 uint8_t train_set = intel_dp->train_set[0];
3008 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 3009 enum pipe pipe = intel_crtc->pipe;
3010 int i;
e4a1d846
CML		 3011
3012 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3013 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3014 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3015 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3016 deemph_reg_value = 128;
3017 margin_reg_value = 52;
3018 break;
bd60018a 3019 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3020 deemph_reg_value = 128;
3021 margin_reg_value = 77;
3022 break;
bd60018a 3023 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3024 deemph_reg_value = 128;
3025 margin_reg_value = 102;
3026 break;
bd60018a 3027 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3028 deemph_reg_value = 128;
3029 margin_reg_value = 154;
3030 /* FIXME extra to set for 1200 */
3031 break;
3032 default:
3033 return 0;
3034 }
3035 break;
bd60018a 3036 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3037 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3038 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3039 deemph_reg_value = 85;
3040 margin_reg_value = 78;
3041 break;
bd60018a 3042 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3043 deemph_reg_value = 85;
3044 margin_reg_value = 116;
3045 break;
bd60018a 3046 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3047 deemph_reg_value = 85;
3048 margin_reg_value = 154;
3049 break;
3050 default:
3051 return 0;
3052 }
3053 break;
bd60018a 3054 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3055 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3056 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3057 deemph_reg_value = 64;
3058 margin_reg_value = 104;
3059 break;
bd60018a 3060 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3061 deemph_reg_value = 64;
3062 margin_reg_value = 154;
3063 break;
3064 default:
3065 return 0;
3066 }
3067 break;
bd60018a 3068 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3069 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3070 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3071 deemph_reg_value = 43;
3072 margin_reg_value = 154;
3073 break;
3074 default:
3075 return 0;
3076 }
3077 break;
3078 default:
3079 return 0;
3080 }
3081
3082 mutex_lock(&dev_priv->dpio_lock);
3083
3084 /* Clear calc init */
1966e59e
VS		 3085 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3086 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3087 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3088
3089 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3090 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3091 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3092
3093 /* Program swing deemph */
f72df8db
VS		 3094 for (i = 0; i < 4; i++) {
3095 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3096 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3097 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3098 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3099 }
e4a1d846
CML		 3100
3101 /* Program swing margin */
f72df8db
VS		 3102 for (i = 0; i < 4; i++) {
3103 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 3104 val &= ~DPIO_SWING_MARGIN000_MASK;
3105 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 3106 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3107 }
e4a1d846
CML		 3108
3109 /* Disable unique transition scale */
f72df8db
VS		 3110 for (i = 0; i < 4; i++) {
3111 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3112 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3113 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3114 }
e4a1d846
CML		 3115
3116 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 3117 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 3118 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 3119 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 3120
3121 /*
3122 * The document said it needs to set bit 27 for ch0 and bit 26
3123 * for ch1. Might be a typo in the doc.
3124 * For now, for this unique transition scale selection, set bit
3125 * 27 for ch0 and ch1.
3126 */
f72df8db
VS		 3127 for (i = 0; i < 4; i++) {
3128 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3129 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3130 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3131 }
e4a1d846 3132
f72df8db
VS		 3133 for (i = 0; i < 4; i++) {
3134 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3135 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3136 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3137 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3138 }
e4a1d846
CML		 3139 }
3140
3141 /* Start swing calculation */
1966e59e
VS		 3142 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3143 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3144 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3145
3146 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3147 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3148 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3149
3150 /* LRC Bypass */
3151 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3152 val |= DPIO_LRC_BYPASS;
3153 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3154
3155 mutex_unlock(&dev_priv->dpio_lock);
3156
3157 return 0;
3158}
3159
a4fc5ed6 3160static void
0301b3ac
JN		 3161intel_get_adjust_train(struct intel_dp *intel_dp,
3162 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 3163{
3164 uint8_t v = 0;
3165 uint8_t p = 0;
3166 int lane;
1a2eb460
KP		 3167 uint8_t voltage_max;
3168 uint8_t preemph_max;
a4fc5ed6 3169
33a34e4e 3170 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 3171 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3172 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 3173
3174 if (this_v > v)
3175 v = this_v;
3176 if (this_p > p)
3177 p = this_p;
3178 }
3179
1a2eb460 3180 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 3181 if (v >= voltage_max)
3182 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 3183
1a2eb460
KP		 3184 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3185 if (p >= preemph_max)
3186 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 3187
3188 for (lane = 0; lane < 4; lane++)
33a34e4e 3189 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 3190}
3191
3192static uint32_t
f0a3424e 3193intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3194{
3cf2efb1 3195 uint32_t signal_levels = 0;
a4fc5ed6 3196
3cf2efb1 3197 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3198 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3199 default:
3200 signal_levels |= DP_VOLTAGE_0_4;
3201 break;
bd60018a 3202 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3203 signal_levels |= DP_VOLTAGE_0_6;
3204 break;
bd60018a 3205 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3206 signal_levels |= DP_VOLTAGE_0_8;
3207 break;
bd60018a 3208 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3209 signal_levels |= DP_VOLTAGE_1_2;
3210 break;
3211 }
3cf2efb1 3212 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3213 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3214 default:
3215 signal_levels |= DP_PRE_EMPHASIS_0;
3216 break;
bd60018a 3217 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3218 signal_levels |= DP_PRE_EMPHASIS_3_5;
3219 break;
bd60018a 3220 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3221 signal_levels |= DP_PRE_EMPHASIS_6;
3222 break;
bd60018a 3223 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3224 signal_levels |= DP_PRE_EMPHASIS_9_5;
3225 break;
3226 }
3227 return signal_levels;
3228}
3229
e3421a18
ZW		 3230/* Gen6's DP voltage swing and pre-emphasis control */
3231static uint32_t
3232intel_gen6_edp_signal_levels(uint8_t train_set)
3233{
3c5a62b5
YL		 3234 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3235 DP_TRAIN_PRE_EMPHASIS_MASK);
3236 switch (signal_levels) {
bd60018a
SJ		 3237 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3238 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3239 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3240 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3241 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3242 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3243 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3244 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3245 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3246 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3247 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3248 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3249 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3250 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3251 default:
3c5a62b5
YL		 3252 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3253 "0x%x\n", signal_levels);
3254 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3255 }
3256}
3257
1a2eb460
KP		 3258/* Gen7's DP voltage swing and pre-emphasis control */
3259static uint32_t
3260intel_gen7_edp_signal_levels(uint8_t train_set)
3261{
3262 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3263 DP_TRAIN_PRE_EMPHASIS_MASK);
3264 switch (signal_levels) {
bd60018a 3265 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3266 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3267 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3268 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3269 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3270 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3271
bd60018a 3272 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3273 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3274 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3275 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3276
bd60018a 3277 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3278 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3279 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3280 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3281
3282 default:
3283 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3284 "0x%x\n", signal_levels);
3285 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3286 }
3287}
3288
d6c0d722
PZ		 3289/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3290static uint32_t
f0a3424e 3291intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 3292{
d6c0d722
PZ		 3293 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3294 DP_TRAIN_PRE_EMPHASIS_MASK);
3295 switch (signal_levels) {
bd60018a 3296 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3297 return DDI_BUF_TRANS_SELECT(0);
bd60018a 3298 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3299 return DDI_BUF_TRANS_SELECT(1);
bd60018a 3300 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3301 return DDI_BUF_TRANS_SELECT(2);
bd60018a 3302 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
c5fe6a06 3303 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 3304
bd60018a 3305 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3306 return DDI_BUF_TRANS_SELECT(4);
bd60018a 3307 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3308 return DDI_BUF_TRANS_SELECT(5);
bd60018a 3309 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3310 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 3311
bd60018a 3312 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3313 return DDI_BUF_TRANS_SELECT(7);
bd60018a 3314 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3315 return DDI_BUF_TRANS_SELECT(8);
d6c0d722
PZ		 3316 default:
3317 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3318 "0x%x\n", signal_levels);
c5fe6a06 3319 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 3320 }
a4fc5ed6
KP		 3321}
3322
f0a3424e
PZ		 3323/* Properly updates "DP" with the correct signal levels. */
3324static void
3325intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3326{
3327 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3328 enum port port = intel_dig_port->port;
f0a3424e
PZ		 3329 struct drm_device *dev = intel_dig_port->base.base.dev;
3330 uint32_t signal_levels, mask;
3331 uint8_t train_set = intel_dp->train_set[0];
3332
9576c27f 3333 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
f0a3424e
PZ		 3334 signal_levels = intel_hsw_signal_levels(train_set);
3335 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 3336 } else if (IS_CHERRYVIEW(dev)) {
3337 signal_levels = intel_chv_signal_levels(intel_dp);
3338 mask = 0;
e2fa6fba
P		 3339 } else if (IS_VALLEYVIEW(dev)) {
3340 signal_levels = intel_vlv_signal_levels(intel_dp);
3341 mask = 0;
bc7d38a4 3342 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 3343 signal_levels = intel_gen7_edp_signal_levels(train_set);
3344 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3345 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 3346 signal_levels = intel_gen6_edp_signal_levels(train_set);
3347 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3348 } else {
3349 signal_levels = intel_gen4_signal_levels(train_set);
3350 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3351 }
3352
3353 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3354
3355 *DP = (*DP & ~mask) | signal_levels;
3356}
3357
a4fc5ed6 3358static bool
ea5b213a 3359intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3360 uint32_t *DP,
58e10eb9 3361 uint8_t dp_train_pat)
a4fc5ed6 3362{
174edf1f
PZ		 3363 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3364 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3365 struct drm_i915_private *dev_priv = dev->dev_private;
2cdfe6c8
JN		 3366 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3367 int ret, len;
a4fc5ed6 3368
7b13b58a 3369 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
47ea7542 3370
70aff66c 3371 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3372 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3373
2cdfe6c8
JN		 3374 buf[0] = dp_train_pat;
3375 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3376 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3377 /* don't write DP_TRAINING_LANEx_SET on disable */
3378 len = 1;
3379 } else {
3380 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3381 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3382 len = intel_dp->lane_count + 1;
47ea7542 3383 }
a4fc5ed6 3384
9d1a1031
JN		 3385 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3386 buf, len);
2cdfe6c8
JN		 3387
3388 return ret == len;
a4fc5ed6
KP		 3389}
3390
70aff66c
JN		 3391static bool
3392intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3393 uint8_t dp_train_pat)
3394{
953d22e8 3395 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3396 intel_dp_set_signal_levels(intel_dp, DP);
3397 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3398}
3399
3400static bool
3401intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3402 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3403{
3404 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3405 struct drm_device *dev = intel_dig_port->base.base.dev;
3406 struct drm_i915_private *dev_priv = dev->dev_private;
3407 int ret;
3408
3409 intel_get_adjust_train(intel_dp, link_status);
3410 intel_dp_set_signal_levels(intel_dp, DP);
3411
3412 I915_WRITE(intel_dp->output_reg, *DP);
3413 POSTING_READ(intel_dp->output_reg);
3414
9d1a1031
JN		 3415 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3416 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3417
3418 return ret == intel_dp->lane_count;
3419}
3420
3ab9c637
ID		 3421static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3422{
3423 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3424 struct drm_device *dev = intel_dig_port->base.base.dev;
3425 struct drm_i915_private *dev_priv = dev->dev_private;
3426 enum port port = intel_dig_port->port;
3427 uint32_t val;
3428
3429 if (!HAS_DDI(dev))
3430 return;
3431
3432 val = I915_READ(DP_TP_CTL(port));
3433 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3434 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3435 I915_WRITE(DP_TP_CTL(port), val);
3436
3437 /*
3438 * On PORT_A we can have only eDP in SST mode. There the only reason
3439 * we need to set idle transmission mode is to work around a HW issue
3440 * where we enable the pipe while not in idle link-training mode.
3441 * In this case there is requirement to wait for a minimum number of
3442 * idle patterns to be sent.
3443 */
3444 if (port == PORT_A)
3445 return;
3446
3447 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3448 1))
3449 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3450}
3451
33a34e4e 3452/* Enable corresponding port and start training pattern 1 */
c19b0669 3453void
33a34e4e 3454intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3455{
da63a9f2 3456 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3457 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3458 int i;
3459 uint8_t voltage;
cdb0e95b 3460 int voltage_tries, loop_tries;
ea5b213a 3461 uint32_t DP = intel_dp->DP;
6aba5b6c 3462 uint8_t link_config[2];
a4fc5ed6 3463
affa9354 3464 if (HAS_DDI(dev))
c19b0669
PZ		 3465 intel_ddi_prepare_link_retrain(encoder);
3466
3cf2efb1 3467 /* Write the link configuration data */
6aba5b6c
JN		 3468 link_config[0] = intel_dp->link_bw;
3469 link_config[1] = intel_dp->lane_count;
3470 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3471 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3472 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3473
3474 link_config[0] = 0;
3475 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3476 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3477
3478 DP |= DP_PORT_EN;
1a2eb460 3479
70aff66c
JN		 3480 /* clock recovery */
3481 if (!intel_dp_reset_link_train(intel_dp, &DP,
3482 DP_TRAINING_PATTERN_1 |
3483 DP_LINK_SCRAMBLING_DISABLE)) {
3484 DRM_ERROR("failed to enable link training\n");
3485 return;
3486 }
3487
a4fc5ed6 3488 voltage = 0xff;
cdb0e95b
KP		 3489 voltage_tries = 0;
3490 loop_tries = 0;
a4fc5ed6 3491 for (;;) {
70aff66c 3492 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3493
a7c9655f 3494 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3495 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3496 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3497 break;
93f62dad 3498 }
a4fc5ed6 3499
01916270 3500 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3501 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3502 break;
3503 }
3504
3505 /* Check to see if we've tried the max voltage */
3506 for (i = 0; i < intel_dp->lane_count; i++)
3507 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3508 break;
3b4f819d 3509 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3510 ++loop_tries;
3511 if (loop_tries == 5) {
3def84b3 3512 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3513 break;
3514 }
70aff66c
JN		 3515 intel_dp_reset_link_train(intel_dp, &DP,
3516 DP_TRAINING_PATTERN_1 |
3517 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3518 voltage_tries = 0;
3519 continue;
3520 }
a4fc5ed6 3521
3cf2efb1 3522 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3523 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3524 ++voltage_tries;
b06fbda3 3525 if (voltage_tries == 5) {
3def84b3 3526 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3527 break;
3528 }
3529 } else
3530 voltage_tries = 0;
3531 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3532
70aff66c
JN		 3533 /* Update training set as requested by target */
3534 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3535 DRM_ERROR("failed to update link training\n");
3536 break;
3537 }
a4fc5ed6
KP		 3538 }
3539
33a34e4e
JB		 3540 intel_dp->DP = DP;
3541}
3542
c19b0669 3543void
33a34e4e
JB		 3544intel_dp_complete_link_train(struct intel_dp *intel_dp)
3545{
33a34e4e 3546 bool channel_eq = false;
37f80975 3547 int tries, cr_tries;
33a34e4e 3548 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3549 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3550
3551 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3552 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3553 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3554
a4fc5ed6 3555 /* channel equalization */
70aff66c 3556 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3557 training_pattern |
70aff66c
JN		 3558 DP_LINK_SCRAMBLING_DISABLE)) {
3559 DRM_ERROR("failed to start channel equalization\n");
3560 return;
3561 }
3562
a4fc5ed6 3563 tries = 0;
37f80975 3564 cr_tries = 0;
a4fc5ed6
KP		 3565 channel_eq = false;
3566 for (;;) {
70aff66c 3567 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3568
37f80975
JB		 3569 if (cr_tries > 5) {
3570 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3571 break;
3572 }
3573
a7c9655f 3574 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3575 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3576 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3577 break;
70aff66c 3578 }
a4fc5ed6 3579
37f80975 3580 /* Make sure clock is still ok */
01916270 3581 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3582 intel_dp_start_link_train(intel_dp);
70aff66c 3583 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3584 training_pattern |
70aff66c 3585 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3586 cr_tries++;
3587 continue;
3588 }
3589
1ffdff13 3590 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3591 channel_eq = true;
3592 break;
3593 }
a4fc5ed6 3594
37f80975
JB		 3595 /* Try 5 times, then try clock recovery if that fails */
3596 if (tries > 5) {
3597 intel_dp_link_down(intel_dp);
3598 intel_dp_start_link_train(intel_dp);
70aff66c 3599 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3600 training_pattern |
70aff66c 3601 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3602 tries = 0;
3603 cr_tries++;
3604 continue;
3605 }
a4fc5ed6 3606
70aff66c
JN		 3607 /* Update training set as requested by target */
3608 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3609 DRM_ERROR("failed to update link training\n");
3610 break;
3611 }
3cf2efb1 3612 ++tries;
869184a6 3613 }
3cf2efb1 3614
3ab9c637
ID		 3615 intel_dp_set_idle_link_train(intel_dp);
3616
3617 intel_dp->DP = DP;
3618
d6c0d722 3619 if (channel_eq)
07f42258 3620 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3621
3ab9c637
ID		 3622}
3623
3624void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3625{
70aff66c 3626 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3627 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3628}
3629
3630static void
ea5b213a 3631intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3632{
da63a9f2 3633 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3634 enum port port = intel_dig_port->port;
da63a9f2 3635 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3636 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3637 struct intel_crtc *intel_crtc =
3638 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3639 uint32_t DP = intel_dp->DP;
a4fc5ed6 3640
bc76e320 3641 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3642 return;
3643
0c33d8d7 3644 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3645 return;
3646
28c97730 3647 DRM_DEBUG_KMS("\n");
32f9d658 3648
bc7d38a4 3649 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3650 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3651 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3652 } else {
aad3d14d
VS		 3653 if (IS_CHERRYVIEW(dev))
3654 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3655 else
3656 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3657 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3658 }
fe255d00 3659 POSTING_READ(intel_dp->output_reg);
5eb08b69 3660
493a7081 3661 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3662 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3663 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3664
5bddd17f
EA		 3665 /* Hardware workaround: leaving our transcoder select
3666 * set to transcoder B while it's off will prevent the
3667 * corresponding HDMI output on transcoder A.
3668 *
3669 * Combine this with another hardware workaround:
3670 * transcoder select bit can only be cleared while the
3671 * port is enabled.
3672 */
3673 DP &= ~DP_PIPEB_SELECT;
3674 I915_WRITE(intel_dp->output_reg, DP);
3675
3676 /* Changes to enable or select take place the vblank
3677 * after being written.
3678 */
ff50afe9
DV		 3679 if (WARN_ON(crtc == NULL)) {
3680 /* We should never try to disable a port without a crtc
3681 * attached. For paranoia keep the code around for a
3682 * bit. */
31acbcc4
CW		 3683 POSTING_READ(intel_dp->output_reg);
3684 msleep(50);
3685 } else
ab527efc 3686 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3687 }
3688
832afda6 3689 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3690 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3691 POSTING_READ(intel_dp->output_reg);
f01eca2e 3692 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3693}
3694
26d61aad
KP		 3695static bool
3696intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3697{
a031d709
RV		 3698 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3699 struct drm_device *dev = dig_port->base.base.dev;
3700 struct drm_i915_private *dev_priv = dev->dev_private;
3701
9d1a1031
JN		 3702 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3703 sizeof(intel_dp->dpcd)) < 0)
edb39244 3704 return false; /* aux transfer failed */
92fd8fd1 3705
a8e98153 3706 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3707
edb39244
AJ		 3708 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3709 return false; /* DPCD not present */
3710
2293bb5c
SK		 3711 /* Check if the panel supports PSR */
3712 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3713 if (is_edp(intel_dp)) {
9d1a1031
JN		 3714 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3715 intel_dp->psr_dpcd,
3716 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3717 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3718 dev_priv->psr.sink_support = true;
50003939 3719 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3720 }
50003939
JN		 3721 }
3722
06ea66b6
TP		 3723 /* Training Pattern 3 support */
3724 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3725 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3726 intel_dp->use_tps3 = true;
f8d8a672 3727 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
06ea66b6
TP		 3728 } else
3729 intel_dp->use_tps3 = false;
3730
edb39244
AJ		 3731 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3732 DP_DWN_STRM_PORT_PRESENT))
3733 return true; /* native DP sink */
3734
3735 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3736 return true; /* no per-port downstream info */
3737
9d1a1031
JN		 3738 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3739 intel_dp->downstream_ports,
3740 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3741 return false; /* downstream port status fetch failed */
3742
3743 return true;
92fd8fd1
KP		 3744}
3745
0d198328
AJ		 3746static void
3747intel_dp_probe_oui(struct intel_dp *intel_dp)
3748{
3749 u8 buf[3];
3750
3751 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3752 return;
3753
24f3e092 3754 intel_edp_panel_vdd_on(intel_dp);
351cfc34 3755
9d1a1031 3756 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3757 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3758 buf[0], buf[1], buf[2]);
3759
9d1a1031 3760 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3761 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3762 buf[0], buf[1], buf[2]);
351cfc34 3763
1e0560e0 3764 intel_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 3765}
3766
0e32b39c
DA		 3767static bool
3768intel_dp_probe_mst(struct intel_dp *intel_dp)
3769{
3770 u8 buf[1];
3771
3772 if (!intel_dp->can_mst)
3773 return false;
3774
3775 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3776 return false;
3777
d337a341 3778 intel_edp_panel_vdd_on(intel_dp);
0e32b39c
DA		 3779 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3780 if (buf[0] & DP_MST_CAP) {
3781 DRM_DEBUG_KMS("Sink is MST capable\n");
3782 intel_dp->is_mst = true;
3783 } else {
3784 DRM_DEBUG_KMS("Sink is not MST capable\n");
3785 intel_dp->is_mst = false;
3786 }
3787 }
1e0560e0 3788 intel_edp_panel_vdd_off(intel_dp, false);
0e32b39c
DA		 3789
3790 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3791 return intel_dp->is_mst;
3792}
3793
d2e216d0
RV		 3794int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3795{
3796 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3797 struct drm_device *dev = intel_dig_port->base.base.dev;
3798 struct intel_crtc *intel_crtc =
3799 to_intel_crtc(intel_dig_port->base.base.crtc);
3800 u8 buf[1];
3801
9d1a1031 3802 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 3803 return -EAGAIN;
3804
3805 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3806 return -ENOTTY;
3807
9d1a1031
JN		 3808 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3809 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 3810 return -EAGAIN;
3811
3812 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3813 intel_wait_for_vblank(dev, intel_crtc->pipe);
3814 intel_wait_for_vblank(dev, intel_crtc->pipe);
3815
9d1a1031 3816 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 3817 return -EAGAIN;
3818
9d1a1031 3819 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 3820 return 0;
3821}
3822
a60f0e38
JB		 3823static bool
3824intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3825{
9d1a1031
JN		 3826 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3827 DP_DEVICE_SERVICE_IRQ_VECTOR,
3828 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3829}
3830
0e32b39c
DA		 3831static bool
3832intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3833{
3834 int ret;
3835
3836 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3837 DP_SINK_COUNT_ESI,
3838 sink_irq_vector, 14);
3839 if (ret != 14)
3840 return false;
3841
3842 return true;
3843}
3844
a60f0e38
JB		 3845static void
3846intel_dp_handle_test_request(struct intel_dp *intel_dp)
3847{
3848 /* NAK by default */
9d1a1031 3849 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3850}
3851
0e32b39c
DA		 3852static int
3853intel_dp_check_mst_status(struct intel_dp *intel_dp)
3854{
3855 bool bret;
3856
3857 if (intel_dp->is_mst) {
3858 u8 esi[16] = { 0 };
3859 int ret = 0;
3860 int retry;
3861 bool handled;
3862 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3863go_again:
3864 if (bret == true) {
3865
3866 /* check link status - esi[10] = 0x200c */
3867 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3868 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3869 intel_dp_start_link_train(intel_dp);
3870 intel_dp_complete_link_train(intel_dp);
3871 intel_dp_stop_link_train(intel_dp);
3872 }
3873
3874 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3875 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3876
3877 if (handled) {
3878 for (retry = 0; retry < 3; retry++) {
3879 int wret;
3880 wret = drm_dp_dpcd_write(&intel_dp->aux,
3881 DP_SINK_COUNT_ESI+1,
3882 &esi[1], 3);
3883 if (wret == 3) {
3884 break;
3885 }
3886 }
3887
3888 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3889 if (bret == true) {
3890 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3891 goto go_again;
3892 }
3893 } else
3894 ret = 0;
3895
3896 return ret;
3897 } else {
3898 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3899 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3900 intel_dp->is_mst = false;
3901 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3902 /* send a hotplug event */
3903 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3904 }
3905 }
3906 return -EINVAL;
3907}
3908
a4fc5ed6
KP		 3909/*
3910 * According to DP spec
3911 * 5.1.2:
3912 * 1. Read DPCD
3913 * 2. Configure link according to Receiver Capabilities
3914 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3915 * 4. Check link status on receipt of hot-plug interrupt
3916 */
00c09d70 3917void
ea5b213a 3918intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3919{
5b215bcf 3920 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 3921 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3922 u8 sink_irq_vector;
93f62dad 3923 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3924
5b215bcf
DA		 3925 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3926
da63a9f2 3927 if (!intel_encoder->connectors_active)
d2b996ac 3928 return;
59cd09e1 3929
da63a9f2 3930 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3931 return;
3932
1a125d8a
ID		 3933 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3934 return;
3935
92fd8fd1 3936 /* Try to read receiver status if the link appears to be up */
93f62dad 3937 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3938 return;
3939 }
3940
92fd8fd1 3941 /* Now read the DPCD to see if it's actually running */
26d61aad 3942 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3943 return;
3944 }
3945
a60f0e38
JB		 3946 /* Try to read the source of the interrupt */
3947 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3948 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3949 /* Clear interrupt source */
9d1a1031
JN		 3950 drm_dp_dpcd_writeb(&intel_dp->aux,
3951 DP_DEVICE_SERVICE_IRQ_VECTOR,
3952 sink_irq_vector);
a60f0e38
JB		 3953
3954 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3955 intel_dp_handle_test_request(intel_dp);
3956 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3957 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3958 }
3959
1ffdff13 3960 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3961 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 3962 intel_encoder->base.name);
33a34e4e
JB		 3963 intel_dp_start_link_train(intel_dp);
3964 intel_dp_complete_link_train(intel_dp);
3ab9c637 3965 intel_dp_stop_link_train(intel_dp);
33a34e4e 3966 }
a4fc5ed6 3967}
a4fc5ed6 3968
caf9ab24 3969/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3970static enum drm_connector_status
26d61aad 3971intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3972{
caf9ab24 3973 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3974 uint8_t type;
3975
3976 if (!intel_dp_get_dpcd(intel_dp))
3977 return connector_status_disconnected;
3978
3979 /* if there's no downstream port, we're done */
3980 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3981 return connector_status_connected;
caf9ab24
AJ		 3982
3983 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3984 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3985 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3986 uint8_t reg;
9d1a1031
JN		 3987
3988 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3989 &reg, 1) < 0)
caf9ab24 3990 return connector_status_unknown;
9d1a1031 3991
23235177
AJ		 3992 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3993 : connector_status_disconnected;
caf9ab24
AJ		 3994 }
3995
3996 /* If no HPD, poke DDC gently */
0b99836f 3997 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3998 return connector_status_connected;
caf9ab24
AJ		 3999
4000 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4001 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4002 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4003 if (type == DP_DS_PORT_TYPE_VGA ||
4004 type == DP_DS_PORT_TYPE_NON_EDID)
4005 return connector_status_unknown;
4006 } else {
4007 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4008 DP_DWN_STRM_PORT_TYPE_MASK;
4009 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4010 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4011 return connector_status_unknown;
4012 }
caf9ab24
AJ		 4013
4014 /* Anything else is out of spec, warn and ignore */
4015 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4016 return connector_status_disconnected;
71ba9000
AJ		 4017}
4018
d410b56d
CW		 4019static enum drm_connector_status
4020edp_detect(struct intel_dp *intel_dp)
4021{
4022 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4023 enum drm_connector_status status;
4024
4025 status = intel_panel_detect(dev);
4026 if (status == connector_status_unknown)
4027 status = connector_status_connected;
4028
4029 return status;
4030}
4031
5eb08b69 4032static enum drm_connector_status
a9756bb5 4033ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 4034{
30add22d 4035 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 4036 struct drm_i915_private *dev_priv = dev->dev_private;
4037 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 4038
1b469639
DL		 4039 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4040 return connector_status_disconnected;
4041
26d61aad 4042 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 4043}
4044
2a592bec
DA		 4045static int g4x_digital_port_connected(struct drm_device *dev,
4046 struct intel_digital_port *intel_dig_port)
a4fc5ed6 4047{
a4fc5ed6 4048 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 4049 uint32_t bit;
5eb08b69 4050
232a6ee9
TP		 4051 if (IS_VALLEYVIEW(dev)) {
4052 switch (intel_dig_port->port) {
4053 case PORT_B:
4054 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4055 break;
4056 case PORT_C:
4057 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4058 break;
4059 case PORT_D:
4060 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4061 break;
4062 default:
2a592bec 4063 return -EINVAL;
232a6ee9
TP		 4064 }
4065 } else {
4066 switch (intel_dig_port->port) {
4067 case PORT_B:
4068 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4069 break;
4070 case PORT_C:
4071 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4072 break;
4073 case PORT_D:
4074 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4075 break;
4076 default:
2a592bec 4077 return -EINVAL;
232a6ee9 4078 }
a4fc5ed6
KP		 4079 }
4080
10f76a38 4081 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2a592bec
DA		 4082 return 0;
4083 return 1;
4084}
4085
4086static enum drm_connector_status
4087g4x_dp_detect(struct intel_dp *intel_dp)
4088{
4089 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4090 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4091 int ret;
4092
4093 /* Can't disconnect eDP, but you can close the lid... */
4094 if (is_edp(intel_dp)) {
4095 enum drm_connector_status status;
4096
4097 status = intel_panel_detect(dev);
4098 if (status == connector_status_unknown)
4099 status = connector_status_connected;
4100 return status;
4101 }
4102
4103 ret = g4x_digital_port_connected(dev, intel_dig_port);
4104 if (ret == -EINVAL)
4105 return connector_status_unknown;
4106 else if (ret == 0)
a4fc5ed6
KP		 4107 return connector_status_disconnected;
4108
26d61aad 4109 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4110}
4111
8c241fef 4112static struct edid *
beb60608 4113intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4114{
beb60608 4115 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4116
9cd300e0
JN		 4117 /* use cached edid if we have one */
4118 if (intel_connector->edid) {
9cd300e0
JN		 4119 /* invalid edid */
4120 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4121 return NULL;
4122
55e9edeb 4123 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4124 } else
4125 return drm_get_edid(&intel_connector->base,
4126 &intel_dp->aux.ddc);
4127}
8c241fef 4128
beb60608
CW		 4129static void
4130intel_dp_set_edid(struct intel_dp *intel_dp)
4131{
4132 struct intel_connector *intel_connector = intel_dp->attached_connector;
4133 struct edid *edid;
8c241fef 4134
beb60608
CW		 4135 edid = intel_dp_get_edid(intel_dp);
4136 intel_connector->detect_edid = edid;
4137
4138 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4139 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4140 else
4141 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4142}
4143
beb60608
CW		 4144static void
4145intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4146{
beb60608 4147 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4148
beb60608
CW		 4149 kfree(intel_connector->detect_edid);
4150 intel_connector->detect_edid = NULL;
9cd300e0 4151
beb60608
CW		 4152 intel_dp->has_audio = false;
4153}
d6f24d0f 4154
beb60608
CW		 4155static enum intel_display_power_domain
4156intel_dp_power_get(struct intel_dp *dp)
4157{
4158 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4159 enum intel_display_power_domain power_domain;
4160
4161 power_domain = intel_display_port_power_domain(encoder);
4162 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4163
4164 return power_domain;
4165}
d6f24d0f 4166
beb60608
CW		 4167static void
4168intel_dp_power_put(struct intel_dp *dp,
4169 enum intel_display_power_domain power_domain)
4170{
4171 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4172 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4173}
4174
a9756bb5
ZW		 4175static enum drm_connector_status
4176intel_dp_detect(struct drm_connector *connector, bool force)
4177{
4178 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4179 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4180 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4181 struct drm_device *dev = connector->dev;
a9756bb5 4182 enum drm_connector_status status;
671dedd2 4183 enum intel_display_power_domain power_domain;
0e32b39c 4184 bool ret;
a9756bb5 4185
164c8598 4186 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4187 connector->base.id, connector->name);
beb60608 4188 intel_dp_unset_edid(intel_dp);
164c8598 4189
0e32b39c
DA		 4190 if (intel_dp->is_mst) {
4191 /* MST devices are disconnected from a monitor POV */
4192 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4193 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4194 return connector_status_disconnected;
0e32b39c
DA		 4195 }
4196
beb60608 4197 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4198
d410b56d
CW		 4199 /* Can't disconnect eDP, but you can close the lid... */
4200 if (is_edp(intel_dp))
4201 status = edp_detect(intel_dp);
4202 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4203 status = ironlake_dp_detect(intel_dp);
4204 else
4205 status = g4x_dp_detect(intel_dp);
4206 if (status != connector_status_connected)
c8c8fb33 4207 goto out;
a9756bb5 4208
0d198328
AJ		 4209 intel_dp_probe_oui(intel_dp);
4210
0e32b39c
DA		 4211 ret = intel_dp_probe_mst(intel_dp);
4212 if (ret) {
4213 /* if we are in MST mode then this connector
4214 won't appear connected or have anything with EDID on it */
4215 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4216 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4217 status = connector_status_disconnected;
4218 goto out;
4219 }
4220
beb60608 4221 intel_dp_set_edid(intel_dp);
a9756bb5 4222
d63885da
PZ		 4223 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4224 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4225 status = connector_status_connected;
4226
4227out:
beb60608 4228 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4229 return status;
a4fc5ed6
KP		 4230}
4231
beb60608
CW		 4232static void
4233intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4234{
df0e9248 4235 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4236 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4237 enum intel_display_power_domain power_domain;
a4fc5ed6 4238
beb60608
CW		 4239 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4240 connector->base.id, connector->name);
4241 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4242
beb60608
CW		 4243 if (connector->status != connector_status_connected)
4244 return;
671dedd2 4245
beb60608
CW		 4246 power_domain = intel_dp_power_get(intel_dp);
4247
4248 intel_dp_set_edid(intel_dp);
4249
4250 intel_dp_power_put(intel_dp, power_domain);
4251
4252 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4253 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4254}
4255
4256static int intel_dp_get_modes(struct drm_connector *connector)
4257{
4258 struct intel_connector *intel_connector = to_intel_connector(connector);
4259 struct edid *edid;
4260
4261 edid = intel_connector->detect_edid;
4262 if (edid) {
4263 int ret = intel_connector_update_modes(connector, edid);
4264 if (ret)
4265 return ret;
4266 }
32f9d658 4267
f8779fda 4268 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4269 if (is_edp(intel_attached_dp(connector)) &&
4270 intel_connector->panel.fixed_mode) {
f8779fda 4271 struct drm_display_mode *mode;
beb60608
CW		 4272
4273 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4274 intel_connector->panel.fixed_mode);
f8779fda 4275 if (mode) {
32f9d658
ZW		 4276 drm_mode_probed_add(connector, mode);
4277 return 1;
4278 }
4279 }
beb60608 4280
32f9d658 4281 return 0;
a4fc5ed6
KP		 4282}
4283
1aad7ac0
CW		 4284static bool
4285intel_dp_detect_audio(struct drm_connector *connector)
4286{
1aad7ac0 4287 bool has_audio = false;
beb60608 4288 struct edid *edid;
1aad7ac0 4289
beb60608
CW		 4290 edid = to_intel_connector(connector)->detect_edid;
4291 if (edid)
1aad7ac0 4292 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4293
1aad7ac0
CW		 4294 return has_audio;
4295}
4296
f684960e
CW		 4297static int
4298intel_dp_set_property(struct drm_connector *connector,
4299 struct drm_property *property,
4300 uint64_t val)
4301{
e953fd7b 4302 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4303 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4304 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4305 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4306 int ret;
4307
662595df 4308 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4309 if (ret)
4310 return ret;
4311
3f43c48d 4312 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4313 int i = val;
4314 bool has_audio;
4315
4316 if (i == intel_dp->force_audio)
f684960e
CW		 4317 return 0;
4318
1aad7ac0 4319 intel_dp->force_audio = i;
f684960e 4320
c3e5f67b 4321 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4322 has_audio = intel_dp_detect_audio(connector);
4323 else
c3e5f67b 4324 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4325
4326 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4327 return 0;
4328
1aad7ac0 4329 intel_dp->has_audio = has_audio;
f684960e
CW		 4330 goto done;
4331 }
4332
e953fd7b 4333 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4334 bool old_auto = intel_dp->color_range_auto;
4335 uint32_t old_range = intel_dp->color_range;
4336
55bc60db
VS		 4337 switch (val) {
4338 case INTEL_BROADCAST_RGB_AUTO:
4339 intel_dp->color_range_auto = true;
4340 break;
4341 case INTEL_BROADCAST_RGB_FULL:
4342 intel_dp->color_range_auto = false;
4343 intel_dp->color_range = 0;
4344 break;
4345 case INTEL_BROADCAST_RGB_LIMITED:
4346 intel_dp->color_range_auto = false;
4347 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4348 break;
4349 default:
4350 return -EINVAL;
4351 }
ae4edb80
DV		 4352
4353 if (old_auto == intel_dp->color_range_auto &&
4354 old_range == intel_dp->color_range)
4355 return 0;
4356
e953fd7b
CW		 4357 goto done;
4358 }
4359
53b41837
YN		 4360 if (is_edp(intel_dp) &&
4361 property == connector->dev->mode_config.scaling_mode_property) {
4362 if (val == DRM_MODE_SCALE_NONE) {
4363 DRM_DEBUG_KMS("no scaling not supported\n");
4364 return -EINVAL;
4365 }
4366
4367 if (intel_connector->panel.fitting_mode == val) {
4368 /* the eDP scaling property is not changed */
4369 return 0;
4370 }
4371 intel_connector->panel.fitting_mode = val;
4372
4373 goto done;
4374 }
4375
f684960e
CW		 4376 return -EINVAL;
4377
4378done:
c0c36b94
CW		 4379 if (intel_encoder->base.crtc)
4380 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4381
4382 return 0;
4383}
4384
a4fc5ed6 4385static void
73845adf 4386intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4387{
1d508706 4388 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4389
10e972d3 4390 kfree(intel_connector->detect_edid);
beb60608 4391
9cd300e0
JN		 4392 if (!IS_ERR_OR_NULL(intel_connector->edid))
4393 kfree(intel_connector->edid);
4394
acd8db10
PZ		 4395 /* Can't call is_edp() since the encoder may have been destroyed
4396 * already. */
4397 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4398 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4399
a4fc5ed6 4400 drm_connector_cleanup(connector);
55f78c43 4401 kfree(connector);
a4fc5ed6
KP		 4402}
4403
00c09d70 4404void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4405{
da63a9f2
PZ		 4406 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4407 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4408
4f71d0cb 4409 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4410 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 4411 drm_encoder_cleanup(encoder);
bd943159
KP		 4412 if (is_edp(intel_dp)) {
4413 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4414 /*
4415 * vdd might still be enabled do to the delayed vdd off.
4416 * Make sure vdd is actually turned off here.
4417 */
773538e8 4418 pps_lock(intel_dp);
4be73780 4419 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4420 pps_unlock(intel_dp);
4421
01527b31
CT		 4422 if (intel_dp->edp_notifier.notifier_call) {
4423 unregister_reboot_notifier(&intel_dp->edp_notifier);
4424 intel_dp->edp_notifier.notifier_call = NULL;
4425 }
bd943159 4426 }
da63a9f2 4427 kfree(intel_dig_port);
24d05927
DV		 4428}
4429
07f9cd0b
ID		 4430static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4431{
4432 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4433
4434 if (!is_edp(intel_dp))
4435 return;
4436
951468f3
VS		 4437 /*
4438 * vdd might still be enabled do to the delayed vdd off.
4439 * Make sure vdd is actually turned off here.
4440 */
773538e8 4441 pps_lock(intel_dp);
07f9cd0b 4442 edp_panel_vdd_off_sync(intel_dp);
773538e8 4443 pps_unlock(intel_dp);
07f9cd0b
ID		 4444}
4445
6d93c0c4
ID		 4446static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4447{
4448 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4449}
4450
a4fc5ed6 4451static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4452 .dpms = intel_connector_dpms,
a4fc5ed6 4453 .detect = intel_dp_detect,
beb60608 4454 .force = intel_dp_force,
a4fc5ed6 4455 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4456 .set_property = intel_dp_set_property,
73845adf 4457 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4458};
4459
4460static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4461 .get_modes = intel_dp_get_modes,
4462 .mode_valid = intel_dp_mode_valid,
df0e9248 4463 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4464};
4465
a4fc5ed6 4466static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4467 .reset = intel_dp_encoder_reset,
24d05927 4468 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4469};
4470
0e32b39c 4471void
21d40d37 4472intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4473{
0e32b39c 4474 return;
c8110e52 4475}
6207937d 4476
13cf5504
DA		 4477bool
4478intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4479{
4480 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4481 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4482 struct drm_device *dev = intel_dig_port->base.base.dev;
4483 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33
ID		 4484 enum intel_display_power_domain power_domain;
4485 bool ret = true;
4486
0e32b39c
DA		 4487 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4488 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4489
26fbb774
VS		 4490 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4491 port_name(intel_dig_port->port),
0e32b39c 4492 long_hpd ? "long" : "short");
13cf5504 4493
1c767b33
ID		 4494 power_domain = intel_display_port_power_domain(intel_encoder);
4495 intel_display_power_get(dev_priv, power_domain);
4496
0e32b39c 4497 if (long_hpd) {
2a592bec
DA		 4498
4499 if (HAS_PCH_SPLIT(dev)) {
4500 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4501 goto mst_fail;
4502 } else {
4503 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4504 goto mst_fail;
4505 }
0e32b39c
DA		 4506
4507 if (!intel_dp_get_dpcd(intel_dp)) {
4508 goto mst_fail;
4509 }
4510
4511 intel_dp_probe_oui(intel_dp);
4512
4513 if (!intel_dp_probe_mst(intel_dp))
4514 goto mst_fail;
4515
4516 } else {
4517 if (intel_dp->is_mst) {
1c767b33 4518 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4519 goto mst_fail;
4520 }
4521
4522 if (!intel_dp->is_mst) {
4523 /*
4524 * we'll check the link status via the normal hot plug path later -
4525 * but for short hpds we should check it now
4526 */
5b215bcf 4527 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4528 intel_dp_check_link_status(intel_dp);
5b215bcf 4529 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4530 }
4531 }
1c767b33
ID		 4532 ret = false;
4533 goto put_power;
0e32b39c
DA		 4534mst_fail:
4535 /* if we were in MST mode, and device is not there get out of MST mode */
4536 if (intel_dp->is_mst) {
4537 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4538 intel_dp->is_mst = false;
4539 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4540 }
1c767b33
ID		 4541put_power:
4542 intel_display_power_put(dev_priv, power_domain);
4543
4544 return ret;
13cf5504
DA		 4545}
4546
e3421a18
ZW		 4547/* Return which DP Port should be selected for Transcoder DP control */
4548int
0206e353 4549intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4550{
4551 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4552 struct intel_encoder *intel_encoder;
4553 struct intel_dp *intel_dp;
e3421a18 4554
fa90ecef
PZ		 4555 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4556 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4557
fa90ecef
PZ		 4558 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4559 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4560 return intel_dp->output_reg;
e3421a18 4561 }
ea5b213a 4562
e3421a18
ZW		 4563 return -1;
4564}
4565
36e83a18 4566/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4567bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4568{
4569 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4570 union child_device_config *p_child;
36e83a18 4571 int i;
5d8a7752
VS		 4572 static const short port_mapping[] = {
4573 [PORT_B] = PORT_IDPB,
4574 [PORT_C] = PORT_IDPC,
4575 [PORT_D] = PORT_IDPD,
4576 };
36e83a18 4577
3b32a35b
VS		 4578 if (port == PORT_A)
4579 return true;
4580
41aa3448 4581 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4582 return false;
4583
41aa3448
RV		 4584 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4585 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4586
5d8a7752 4587 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4588 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4589 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4590 return true;
4591 }
4592 return false;
4593}
4594
0e32b39c 4595void
f684960e
CW		 4596intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4597{
53b41837
YN		 4598 struct intel_connector *intel_connector = to_intel_connector(connector);
4599
3f43c48d 4600 intel_attach_force_audio_property(connector);
e953fd7b 4601 intel_attach_broadcast_rgb_property(connector);
55bc60db 4602 intel_dp->color_range_auto = true;
53b41837
YN		 4603
4604 if (is_edp(intel_dp)) {
4605 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4606 drm_object_attach_property(
4607 &connector->base,
53b41837 4608 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4609 DRM_MODE_SCALE_ASPECT);
4610 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4611 }
f684960e
CW		 4612}
4613
dada1a9f
ID		 4614static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4615{
4616 intel_dp->last_power_cycle = jiffies;
4617 intel_dp->last_power_on = jiffies;
4618 intel_dp->last_backlight_off = jiffies;
4619}
4620
67a54566
DV		 4621static void
4622intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 4623 struct intel_dp *intel_dp,
4624 struct edp_power_seq *out)
67a54566
DV		 4625{
4626 struct drm_i915_private *dev_priv = dev->dev_private;
4627 struct edp_power_seq cur, vbt, spec, final;
4628 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4629 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 4630
e39b999a
VS		 4631 lockdep_assert_held(&dev_priv->pps_mutex);
4632
453c5420 4633 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4634 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4635 pp_on_reg = PCH_PP_ON_DELAYS;
4636 pp_off_reg = PCH_PP_OFF_DELAYS;
4637 pp_div_reg = PCH_PP_DIVISOR;
4638 } else {
bf13e81b
JN		 4639 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4640
4641 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4642 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4643 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4644 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4645 }
67a54566
DV		 4646
4647 /* Workaround: Need to write PP_CONTROL with the unlock key as
4648 * the very first thing. */
453c5420 4649 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4650 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4651
453c5420
JB		 4652 pp_on = I915_READ(pp_on_reg);
4653 pp_off = I915_READ(pp_off_reg);
4654 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4655
4656 /* Pull timing values out of registers */
4657 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4658 PANEL_POWER_UP_DELAY_SHIFT;
4659
4660 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4661 PANEL_LIGHT_ON_DELAY_SHIFT;
4662
4663 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4664 PANEL_LIGHT_OFF_DELAY_SHIFT;
4665
4666 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4667 PANEL_POWER_DOWN_DELAY_SHIFT;
4668
4669 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4670 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4671
4672 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4673 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4674
41aa3448 4675 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4676
4677 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4678 * our hw here, which are all in 100usec. */
4679 spec.t1_t3 = 210 * 10;
4680 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4681 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4682 spec.t10 = 500 * 10;
4683 /* This one is special and actually in units of 100ms, but zero
4684 * based in the hw (so we need to add 100 ms). But the sw vbt
4685 * table multiplies it with 1000 to make it in units of 100usec,
4686 * too. */
4687 spec.t11_t12 = (510 + 100) * 10;
4688
4689 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4690 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4691
4692 /* Use the max of the register settings and vbt. If both are
4693 * unset, fall back to the spec limits. */
4694#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4695 spec.field : \
4696 max(cur.field, vbt.field))
4697 assign_final(t1_t3);
4698 assign_final(t8);
4699 assign_final(t9);
4700 assign_final(t10);
4701 assign_final(t11_t12);
4702#undef assign_final
4703
4704#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4705 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4706 intel_dp->backlight_on_delay = get_delay(t8);
4707 intel_dp->backlight_off_delay = get_delay(t9);
4708 intel_dp->panel_power_down_delay = get_delay(t10);
4709 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4710#undef get_delay
4711
f30d26e4
JN		 4712 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4713 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4714 intel_dp->panel_power_cycle_delay);
4715
4716 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4717 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4718
4719 if (out)
4720 *out = final;
4721}
4722
4723static void
4724intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4725 struct intel_dp *intel_dp,
4726 struct edp_power_seq *seq)
4727{
4728 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4729 u32 pp_on, pp_off, pp_div, port_sel = 0;
4730 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4731 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 4732 enum port port = dp_to_dig_port(intel_dp)->port;
453c5420 4733
e39b999a 4734 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420
JB		 4735
4736 if (HAS_PCH_SPLIT(dev)) {
4737 pp_on_reg = PCH_PP_ON_DELAYS;
4738 pp_off_reg = PCH_PP_OFF_DELAYS;
4739 pp_div_reg = PCH_PP_DIVISOR;
4740 } else {
bf13e81b
JN		 4741 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4742
4743 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4744 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4745 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4746 }
4747
b2f19d1a
PZ		 4748 /*
4749 * And finally store the new values in the power sequencer. The
4750 * backlight delays are set to 1 because we do manual waits on them. For
4751 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4752 * we'll end up waiting for the backlight off delay twice: once when we
4753 * do the manual sleep, and once when we disable the panel and wait for
4754 * the PP_STATUS bit to become zero.
4755 */
f30d26e4 4756 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4757 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4758 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4759 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4760 /* Compute the divisor for the pp clock, simply match the Bspec
4761 * formula. */
453c5420 4762 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4763 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4764 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4765
4766 /* Haswell doesn't have any port selection bits for the panel
4767 * power sequencer any more. */
bc7d38a4 4768 if (IS_VALLEYVIEW(dev)) {
ad933b56 4769 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4770 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4771 if (port == PORT_A)
a24c144c 4772 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4773 else
a24c144c 4774 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4775 }
4776
453c5420
JB		 4777 pp_on |= port_sel;
4778
4779 I915_WRITE(pp_on_reg, pp_on);
4780 I915_WRITE(pp_off_reg, pp_off);
4781 I915_WRITE(pp_div_reg, pp_div);
67a54566 4782
67a54566 4783 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4784 I915_READ(pp_on_reg),
4785 I915_READ(pp_off_reg),
4786 I915_READ(pp_div_reg));
f684960e
CW		 4787}
4788
439d7ac0
PB		 4789void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4790{
4791 struct drm_i915_private *dev_priv = dev->dev_private;
4792 struct intel_encoder *encoder;
4793 struct intel_dp *intel_dp = NULL;
4794 struct intel_crtc_config *config = NULL;
4795 struct intel_crtc *intel_crtc = NULL;
4796 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4797 u32 reg, val;
4798 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4799
4800 if (refresh_rate <= 0) {
4801 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4802 return;
4803 }
4804
4805 if (intel_connector == NULL) {
4806 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4807 return;
4808 }
4809
1fcc9d1c
DV		 4810 /*
4811 * FIXME: This needs proper synchronization with psr state. But really
4812 * hard to tell without seeing the user of this function of this code.
4813 * Check locking and ordering once that lands.
4814 */
439d7ac0
PB		 4815 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4816 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4817 return;
4818 }
4819
4820 encoder = intel_attached_encoder(&intel_connector->base);
4821 intel_dp = enc_to_intel_dp(&encoder->base);
4822 intel_crtc = encoder->new_crtc;
4823
4824 if (!intel_crtc) {
4825 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4826 return;
4827 }
4828
4829 config = &intel_crtc->config;
4830
4831 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4832 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4833 return;
4834 }
4835
4836 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4837 index = DRRS_LOW_RR;
4838
4839 if (index == intel_dp->drrs_state.refresh_rate_type) {
4840 DRM_DEBUG_KMS(
4841 "DRRS requested for previously set RR...ignoring\n");
4842 return;
4843 }
4844
4845 if (!intel_crtc->active) {
4846 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4847 return;
4848 }
4849
4850 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4851 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4852 val = I915_READ(reg);
4853 if (index > DRRS_HIGH_RR) {
4854 val |= PIPECONF_EDP_RR_MODE_SWITCH;
f769cd24 4855 intel_dp_set_m_n(intel_crtc);
439d7ac0
PB		 4856 } else {
4857 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4858 }
4859 I915_WRITE(reg, val);
4860 }
4861
4862 /*
4863 * mutex taken to ensure that there is no race between differnt
4864 * drrs calls trying to update refresh rate. This scenario may occur
4865 * in future when idleness detection based DRRS in kernel and
4866 * possible calls from user space to set differnt RR are made.
4867 */
4868
4869 mutex_lock(&intel_dp->drrs_state.mutex);
4870
4871 intel_dp->drrs_state.refresh_rate_type = index;
4872
4873 mutex_unlock(&intel_dp->drrs_state.mutex);
4874
4875 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4876}
4877
4f9db5b5
PB		 4878static struct drm_display_mode *
4879intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4880 struct intel_connector *intel_connector,
4881 struct drm_display_mode *fixed_mode)
4882{
4883 struct drm_connector *connector = &intel_connector->base;
4884 struct intel_dp *intel_dp = &intel_dig_port->dp;
4885 struct drm_device *dev = intel_dig_port->base.base.dev;
4886 struct drm_i915_private *dev_priv = dev->dev_private;
4887 struct drm_display_mode *downclock_mode = NULL;
4888
4889 if (INTEL_INFO(dev)->gen <= 6) {
4890 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4891 return NULL;
4892 }
4893
4894 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 4895 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 4896 return NULL;
4897 }
4898
4899 downclock_mode = intel_find_panel_downclock
4900 (dev, fixed_mode, connector);
4901
4902 if (!downclock_mode) {
4079b8d1 4903 DRM_DEBUG_KMS("DRRS not supported\n");
4f9db5b5
PB		 4904 return NULL;
4905 }
4906
439d7ac0
PB		 4907 dev_priv->drrs.connector = intel_connector;
4908
4909 mutex_init(&intel_dp->drrs_state.mutex);
4910
4f9db5b5
PB		 4911 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4912
4913 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 4914 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 4915 return downclock_mode;
4916}
4917
aba86890
ID		 4918void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4919{
4920 struct drm_device *dev = intel_encoder->base.dev;
4921 struct drm_i915_private *dev_priv = dev->dev_private;
4922 struct intel_dp *intel_dp;
4923 enum intel_display_power_domain power_domain;
4924
4925 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4926 return;
4927
4928 intel_dp = enc_to_intel_dp(&intel_encoder->base);
773538e8
VS		 4929
4930 pps_lock(intel_dp);
4931
aba86890 4932 if (!edp_have_panel_vdd(intel_dp))
e39b999a 4933 goto out;
aba86890
ID		 4934 /*
4935 * The VDD bit needs a power domain reference, so if the bit is
4936 * already enabled when we boot or resume, grab this reference and
4937 * schedule a vdd off, so we don't hold on to the reference
4938 * indefinitely.
4939 */
4940 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4941 power_domain = intel_display_port_power_domain(intel_encoder);
4942 intel_display_power_get(dev_priv, power_domain);
4943
4944 edp_panel_vdd_schedule_off(intel_dp);
e39b999a 4945 out:
773538e8 4946 pps_unlock(intel_dp);
aba86890
ID		 4947}
4948
ed92f0b2 4949static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 4950 struct intel_connector *intel_connector,
4951 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 4952{
4953 struct drm_connector *connector = &intel_connector->base;
4954 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 4955 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4956 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 4957 struct drm_i915_private *dev_priv = dev->dev_private;
4958 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 4959 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 4960 bool has_dpcd;
4961 struct drm_display_mode *scan;
4962 struct edid *edid;
4963
4f9db5b5
PB		 4964 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4965
ed92f0b2
PZ		 4966 if (!is_edp(intel_dp))
4967 return true;
4968
aba86890 4969 intel_edp_panel_vdd_sanitize(intel_encoder);
63635217 4970
ed92f0b2 4971 /* Cache DPCD and EDID for edp. */
24f3e092 4972 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 4973 has_dpcd = intel_dp_get_dpcd(intel_dp);
1e0560e0 4974 intel_edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 4975
4976 if (has_dpcd) {
4977 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4978 dev_priv->no_aux_handshake =
4979 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4980 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4981 } else {
4982 /* if this fails, presume the device is a ghost */
4983 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 4984 return false;
4985 }
4986
4987 /* We now know it's not a ghost, init power sequence regs. */
773538e8 4988 pps_lock(intel_dp);
0095e6dc 4989 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
773538e8 4990 pps_unlock(intel_dp);
ed92f0b2 4991
060c8778 4992 mutex_lock(&dev->mode_config.mutex);
0b99836f 4993 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 4994 if (edid) {
4995 if (drm_add_edid_modes(connector, edid)) {
4996 drm_mode_connector_update_edid_property(connector,
4997 edid);
4998 drm_edid_to_eld(connector, edid);
4999 } else {
5000 kfree(edid);
5001 edid = ERR_PTR(-EINVAL);
5002 }
5003 } else {
5004 edid = ERR_PTR(-ENOENT);
5005 }
5006 intel_connector->edid = edid;
5007
5008 /* prefer fixed mode from EDID if available */
5009 list_for_each_entry(scan, &connector->probed_modes, head) {
5010 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5011 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 5012 downclock_mode = intel_dp_drrs_init(
5013 intel_dig_port,
5014 intel_connector, fixed_mode);
ed92f0b2
PZ		 5015 break;
5016 }
5017 }
5018
5019 /* fallback to VBT if available for eDP */
5020 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5021 fixed_mode = drm_mode_duplicate(dev,
5022 dev_priv->vbt.lfp_lvds_vbt_mode);
5023 if (fixed_mode)
5024 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5025 }
060c8778 5026 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5027
01527b31
CT		 5028 if (IS_VALLEYVIEW(dev)) {
5029 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5030 register_reboot_notifier(&intel_dp->edp_notifier);
5031 }
5032
4f9db5b5 5033 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 5034 intel_connector->panel.backlight_power = intel_edp_backlight_power;
ed92f0b2
PZ		 5035 intel_panel_setup_backlight(connector);
5036
5037 return true;
5038}
5039
16c25533 5040bool
f0fec3f2
PZ		 5041intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5042 struct intel_connector *intel_connector)
a4fc5ed6 5043{
f0fec3f2
PZ		 5044 struct drm_connector *connector = &intel_connector->base;
5045 struct intel_dp *intel_dp = &intel_dig_port->dp;
5046 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5047 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5048 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5049 enum port port = intel_dig_port->port;
0095e6dc 5050 struct edp_power_seq power_seq = { 0 };
0b99836f 5051 int type;
a4fc5ed6 5052
a4a5d2f8
VS		 5053 intel_dp->pps_pipe = INVALID_PIPE;
5054
ec5b01dd
DL		 5055 /* intel_dp vfuncs */
5056 if (IS_VALLEYVIEW(dev))
5057 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5058 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5059 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5060 else if (HAS_PCH_SPLIT(dev))
5061 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5062 else
5063 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5064
153b1100
DL		 5065 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
5066
0767935e
DV		 5067 /* Preserve the current hw state. */
5068 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5069 intel_dp->attached_connector = intel_connector;
3d3dc149 5070
3b32a35b 5071 if (intel_dp_is_edp(dev, port))
b329530c 5072 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5073 else
5074 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5075
f7d24902
ID		 5076 /*
5077 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5078 * for DP the encoder type can be set by the caller to
5079 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5080 */
5081 if (type == DRM_MODE_CONNECTOR_eDP)
5082 intel_encoder->type = INTEL_OUTPUT_EDP;
5083
e7281eab
ID		 5084 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5085 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5086 port_name(port));
5087
b329530c 5088 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5089 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5090
a4fc5ed6
KP		 5091 connector->interlace_allowed = true;
5092 connector->doublescan_allowed = 0;
5093
f0fec3f2 5094 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5095 edp_panel_vdd_work);
a4fc5ed6 5096
df0e9248 5097 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5098 drm_connector_register(connector);
a4fc5ed6 5099
affa9354 5100 if (HAS_DDI(dev))
bcbc889b
PZ		 5101 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5102 else
5103 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5104 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5105
0b99836f 5106 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5107 switch (port) {
5108 case PORT_A:
1d843f9d 5109 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5110 break;
5111 case PORT_B:
1d843f9d 5112 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 5113 break;
5114 case PORT_C:
1d843f9d 5115 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5116 break;
5117 case PORT_D:
1d843f9d 5118 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 5119 break;
5120 default:
ad1c0b19 5121 BUG();
5eb08b69
ZW		 5122 }
5123
dada1a9f 5124 if (is_edp(intel_dp)) {
773538e8 5125 pps_lock(intel_dp);
a4a5d2f8
VS		 5126 if (IS_VALLEYVIEW(dev)) {
5127 vlv_initial_power_sequencer_setup(intel_dp);
5128 } else {
5129 intel_dp_init_panel_power_timestamps(intel_dp);
5130 intel_dp_init_panel_power_sequencer(dev, intel_dp,
5131 &power_seq);
5132 }
773538e8 5133 pps_unlock(intel_dp);
dada1a9f 5134 }
0095e6dc 5135
9d1a1031 5136 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5137
0e32b39c
DA		 5138 /* init MST on ports that can support it */
5139 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5140 if (port == PORT_B || port == PORT_C || port == PORT_D) {
a4a5d2f8
VS		 5141 intel_dp_mst_encoder_init(intel_dig_port,
5142 intel_connector->base.base.id);
0e32b39c
DA		 5143 }
5144 }
5145
0095e6dc 5146 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4f71d0cb 5147 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5148 if (is_edp(intel_dp)) {
5149 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 5150 /*
5151 * vdd might still be enabled do to the delayed vdd off.
5152 * Make sure vdd is actually turned off here.
5153 */
773538e8 5154 pps_lock(intel_dp);
4be73780 5155 edp_panel_vdd_off_sync(intel_dp);
773538e8 5156 pps_unlock(intel_dp);
15b1d171 5157 }
34ea3d38 5158 drm_connector_unregister(connector);
b2f246a8 5159 drm_connector_cleanup(connector);
16c25533 5160 return false;
b2f246a8 5161 }
32f9d658 5162
f684960e
CW		 5163 intel_dp_add_properties(intel_dp, connector);
5164
a4fc5ed6
KP		 5165 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5166 * 0xd. Failure to do so will result in spurious interrupts being
5167 * generated on the port when a cable is not attached.
5168 */
5169 if (IS_G4X(dev) && !IS_GM45(dev)) {
5170 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5171 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5172 }
16c25533
PZ		 5173
5174 return true;
a4fc5ed6 5175}
f0fec3f2
PZ		 5176
5177void
5178intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5179{
13cf5504 5180 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5181 struct intel_digital_port *intel_dig_port;
5182 struct intel_encoder *intel_encoder;
5183 struct drm_encoder *encoder;
5184 struct intel_connector *intel_connector;
5185
b14c5679 5186 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5187 if (!intel_dig_port)
5188 return;
5189
b14c5679 5190 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 5191 if (!intel_connector) {
5192 kfree(intel_dig_port);
5193 return;
5194 }
5195
5196 intel_encoder = &intel_dig_port->base;
5197 encoder = &intel_encoder->base;
5198
5199 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5200 DRM_MODE_ENCODER_TMDS);
5201
5bfe2ac0 5202 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5203 intel_encoder->disable = intel_disable_dp;
00c09d70 5204 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5205 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5206 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5207 if (IS_CHERRYVIEW(dev)) {
9197c88b 5208 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5209 intel_encoder->pre_enable = chv_pre_enable_dp;
5210 intel_encoder->enable = vlv_enable_dp;
580d3811 5211 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5212 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5213 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5214 intel_encoder->pre_enable = vlv_pre_enable_dp;
5215 intel_encoder->enable = vlv_enable_dp;
49277c31 5216 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5217 } else {
ecff4f3b
JN		 5218 intel_encoder->pre_enable = g4x_pre_enable_dp;
5219 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5220 if (INTEL_INFO(dev)->gen >= 5)
5221 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5222 }
f0fec3f2 5223
174edf1f 5224 intel_dig_port->port = port;
f0fec3f2
PZ		 5225 intel_dig_port->dp.output_reg = output_reg;
5226
00c09d70 5227 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5228 if (IS_CHERRYVIEW(dev)) {
5229 if (port == PORT_D)
5230 intel_encoder->crtc_mask = 1 << 2;
5231 else
5232 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5233 } else {
5234 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5235 }
bc079e8b 5236 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 5237 intel_encoder->hot_plug = intel_dp_hot_plug;
5238
13cf5504
DA		 5239 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5240 dev_priv->hpd_irq_port[port] = intel_dig_port;
5241
15b1d171
PZ		 5242 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5243 drm_encoder_cleanup(encoder);
5244 kfree(intel_dig_port);
b2f246a8 5245 kfree(intel_connector);
15b1d171 5246 }
f0fec3f2 5247}
0e32b39c
DA		 5248
5249void intel_dp_mst_suspend(struct drm_device *dev)
5250{
5251 struct drm_i915_private *dev_priv = dev->dev_private;
5252 int i;
5253
5254 /* disable MST */
5255 for (i = 0; i < I915_MAX_PORTS; i++) {
5256 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5257 if (!intel_dig_port)
5258 continue;
5259
5260 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5261 if (!intel_dig_port->dp.can_mst)
5262 continue;
5263 if (intel_dig_port->dp.is_mst)
5264 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5265 }
5266 }
5267}
5268
5269void intel_dp_mst_resume(struct drm_device *dev)
5270{
5271 struct drm_i915_private *dev_priv = dev->dev_private;
5272 int i;
5273
5274 for (i = 0; i < I915_MAX_PORTS; i++) {
5275 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5276 if (!intel_dig_port)
5277 continue;
5278 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5279 int ret;
5280
5281 if (!intel_dig_port->dp.can_mst)
5282 continue;
5283
5284 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5285 if (ret != 0) {
5286 intel_dp_check_mst_status(&intel_dig_port->dp);
5287 }
5288 }
5289 }
5290}
Linux kernel - Deliverables
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