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drm/i915: Add support for DRRS to switch RR
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
65ce4bf5
CML		 60static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
58f6e632 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
cfcb0fc9
JB		 67/**
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
70 *
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
73 */
74static bool is_edp(struct intel_dp *intel_dp)
75{
da63a9f2
PZ		 76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
77
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 79}
80
68b4d824 81static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 82{
68b4d824
ID		 83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
84
85 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 86}
87
df0e9248
CW		 88static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
89{
fa90ecef 90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 91}
92
ea5b213a 93static void intel_dp_link_down(struct intel_dp *intel_dp);
adddaaf4 94static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 95static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 96
a4fc5ed6 97static int
ea5b213a 98intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 99{
7183dc29 100 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 101 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 102
103 switch (max_link_bw) {
104 case DP_LINK_BW_1_62:
105 case DP_LINK_BW_2_7:
106 break;
d4eead50 107 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
06ea66b6
TP		 108 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
109 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
110 max_link_bw = DP_LINK_BW_5_4;
111 else
112 max_link_bw = DP_LINK_BW_2_7;
d4eead50 113 break;
a4fc5ed6 114 default:
d4eead50
ID		 115 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
116 max_link_bw);
a4fc5ed6
KP		 117 max_link_bw = DP_LINK_BW_1_62;
118 break;
119 }
120 return max_link_bw;
121}
122
cd9dde44
AJ		 123/*
124 * The units on the numbers in the next two are... bizarre. Examples will
125 * make it clearer; this one parallels an example in the eDP spec.
126 *
127 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
128 *
129 * 270000 * 1 * 8 / 10 == 216000
130 *
131 * The actual data capacity of that configuration is 2.16Gbit/s, so the
132 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
133 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
134 * 119000. At 18bpp that's 2142000 kilobits per second.
135 *
136 * Thus the strange-looking division by 10 in intel_dp_link_required, to
137 * get the result in decakilobits instead of kilobits.
138 */
139
a4fc5ed6 140static int
c898261c 141intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 142{
cd9dde44 143 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 144}
145
fe27d53e
DA		 146static int
147intel_dp_max_data_rate(int max_link_clock, int max_lanes)
148{
149 return (max_link_clock * max_lanes * 8) / 10;
150}
151
c19de8eb 152static enum drm_mode_status
a4fc5ed6
KP		 153intel_dp_mode_valid(struct drm_connector *connector,
154 struct drm_display_mode *mode)
155{
df0e9248 156 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 157 struct intel_connector *intel_connector = to_intel_connector(connector);
158 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 159 int target_clock = mode->clock;
160 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 161
dd06f90e
JN		 162 if (is_edp(intel_dp) && fixed_mode) {
163 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 164 return MODE_PANEL;
165
dd06f90e 166 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 167 return MODE_PANEL;
03afc4a2
DV		 168
169 target_clock = fixed_mode->clock;
7de56f43
ZY		 170 }
171
36008365
DV		 172 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
173 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
174
175 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
176 mode_rate = intel_dp_link_required(target_clock, 18);
177
178 if (mode_rate > max_rate)
c4867936 179 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 180
181 if (mode->clock < 10000)
182 return MODE_CLOCK_LOW;
183
0af78a2b
DV		 184 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
185 return MODE_H_ILLEGAL;
186
a4fc5ed6
KP		 187 return MODE_OK;
188}
189
190static uint32_t
191pack_aux(uint8_t *src, int src_bytes)
192{
193 int i;
194 uint32_t v = 0;
195
196 if (src_bytes > 4)
197 src_bytes = 4;
198 for (i = 0; i < src_bytes; i++)
199 v |= ((uint32_t) src[i]) << ((3-i) * 8);
200 return v;
201}
202
203static void
204unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
205{
206 int i;
207 if (dst_bytes > 4)
208 dst_bytes = 4;
209 for (i = 0; i < dst_bytes; i++)
210 dst[i] = src >> ((3-i) * 8);
211}
212
fb0f8fbf
KP		 213/* hrawclock is 1/4 the FSB frequency */
214static int
215intel_hrawclk(struct drm_device *dev)
216{
217 struct drm_i915_private *dev_priv = dev->dev_private;
218 uint32_t clkcfg;
219
9473c8f4
VP		 220 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
221 if (IS_VALLEYVIEW(dev))
222 return 200;
223
fb0f8fbf
KP		 224 clkcfg = I915_READ(CLKCFG);
225 switch (clkcfg & CLKCFG_FSB_MASK) {
226 case CLKCFG_FSB_400:
227 return 100;
228 case CLKCFG_FSB_533:
229 return 133;
230 case CLKCFG_FSB_667:
231 return 166;
232 case CLKCFG_FSB_800:
233 return 200;
234 case CLKCFG_FSB_1067:
235 return 266;
236 case CLKCFG_FSB_1333:
237 return 333;
238 /* these two are just a guess; one of them might be right */
239 case CLKCFG_FSB_1600:
240 case CLKCFG_FSB_1600_ALT:
241 return 400;
242 default:
243 return 133;
244 }
245}
246
bf13e81b
JN		 247static void
248intel_dp_init_panel_power_sequencer(struct drm_device *dev,
249 struct intel_dp *intel_dp,
250 struct edp_power_seq *out);
251static void
252intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
253 struct intel_dp *intel_dp,
254 struct edp_power_seq *out);
255
256static enum pipe
257vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
258{
259 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
260 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
261 struct drm_device *dev = intel_dig_port->base.base.dev;
262 struct drm_i915_private *dev_priv = dev->dev_private;
263 enum port port = intel_dig_port->port;
264 enum pipe pipe;
265
266 /* modeset should have pipe */
267 if (crtc)
268 return to_intel_crtc(crtc)->pipe;
269
270 /* init time, try to find a pipe with this port selected */
271 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
272 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
273 PANEL_PORT_SELECT_MASK;
274 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
275 return pipe;
276 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
277 return pipe;
278 }
279
280 /* shrug */
281 return PIPE_A;
282}
283
284static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
285{
286 struct drm_device *dev = intel_dp_to_dev(intel_dp);
287
288 if (HAS_PCH_SPLIT(dev))
289 return PCH_PP_CONTROL;
290 else
291 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
292}
293
294static u32 _pp_stat_reg(struct intel_dp *intel_dp)
295{
296 struct drm_device *dev = intel_dp_to_dev(intel_dp);
297
298 if (HAS_PCH_SPLIT(dev))
299 return PCH_PP_STATUS;
300 else
301 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
302}
303
4be73780 304static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 305{
30add22d 306 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 307 struct drm_i915_private *dev_priv = dev->dev_private;
308
bf13e81b 309 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 310}
311
4be73780 312static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 313{
30add22d 314 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 315 struct drm_i915_private *dev_priv = dev->dev_private;
316
efbc20ab
PZ		 317 return !dev_priv->pm.suspended &&
318 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 319}
320
9b984dae
KP		 321static void
322intel_dp_check_edp(struct intel_dp *intel_dp)
323{
30add22d 324 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 325 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 326
9b984dae
KP		 327 if (!is_edp(intel_dp))
328 return;
453c5420 329
4be73780 330 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 331 WARN(1, "eDP powered off while attempting aux channel communication.\n");
332 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 333 I915_READ(_pp_stat_reg(intel_dp)),
334 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 335 }
336}
337
9ee32fea
DV		 338static uint32_t
339intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
340{
341 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
342 struct drm_device *dev = intel_dig_port->base.base.dev;
343 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 344 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 345 uint32_t status;
346 bool done;
347
ef04f00d 348#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 349 if (has_aux_irq)
b18ac466 350 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 351 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 352 else
353 done = wait_for_atomic(C, 10) == 0;
354 if (!done)
355 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
356 has_aux_irq);
357#undef C
358
359 return status;
360}
361
ec5b01dd 362static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 363{
174edf1f
PZ		 364 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
365 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 366
ec5b01dd
DL		 367 /*
368 * The clock divider is based off the hrawclk, and would like to run at
369 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 370 */
ec5b01dd
DL		 371 return index ? 0 : intel_hrawclk(dev) / 2;
372}
373
374static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
375{
376 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
377 struct drm_device *dev = intel_dig_port->base.base.dev;
378
379 if (index)
380 return 0;
381
382 if (intel_dig_port->port == PORT_A) {
383 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 384 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 385 else
b84a1cf8 386 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 387 } else {
388 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
389 }
390}
391
392static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
393{
394 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
395 struct drm_device *dev = intel_dig_port->base.base.dev;
396 struct drm_i915_private *dev_priv = dev->dev_private;
397
398 if (intel_dig_port->port == PORT_A) {
399 if (index)
400 return 0;
401 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 402 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
403 /* Workaround for non-ULT HSW */
bc86625a
CW		 404 switch (index) {
405 case 0: return 63;
406 case 1: return 72;
407 default: return 0;
408 }
ec5b01dd 409 } else {
bc86625a 410 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 411 }
b84a1cf8
RV		 412}
413
ec5b01dd
DL		 414static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
415{
416 return index ? 0 : 100;
417}
418
5ed12a19
DL		 419static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
420 bool has_aux_irq,
421 int send_bytes,
422 uint32_t aux_clock_divider)
423{
424 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
425 struct drm_device *dev = intel_dig_port->base.base.dev;
426 uint32_t precharge, timeout;
427
428 if (IS_GEN6(dev))
429 precharge = 3;
430 else
431 precharge = 5;
432
433 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
434 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
435 else
436 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
437
438 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 439 DP_AUX_CH_CTL_DONE |
5ed12a19 440 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 441 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 442 timeout |
788d4433 443 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 444 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
445 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 446 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 447}
448
b84a1cf8
RV		 449static int
450intel_dp_aux_ch(struct intel_dp *intel_dp,
451 uint8_t *send, int send_bytes,
452 uint8_t *recv, int recv_size)
453{
454 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
455 struct drm_device *dev = intel_dig_port->base.base.dev;
456 struct drm_i915_private *dev_priv = dev->dev_private;
457 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
458 uint32_t ch_data = ch_ctl + 4;
bc86625a 459 uint32_t aux_clock_divider;
b84a1cf8
RV		 460 int i, ret, recv_bytes;
461 uint32_t status;
5ed12a19 462 int try, clock = 0;
4e6b788c 463 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 464 bool vdd;
465
466 vdd = _edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 467
468 /* dp aux is extremely sensitive to irq latency, hence request the
469 * lowest possible wakeup latency and so prevent the cpu from going into
470 * deep sleep states.
471 */
472 pm_qos_update_request(&dev_priv->pm_qos, 0);
473
474 intel_dp_check_edp(intel_dp);
5eb08b69 475
c67a470b
PZ		 476 intel_aux_display_runtime_get(dev_priv);
477
11bee43e
JB		 478 /* Try to wait for any previous AUX channel activity */
479 for (try = 0; try < 3; try++) {
ef04f00d 480 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 481 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
482 break;
483 msleep(1);
484 }
485
486 if (try == 3) {
487 WARN(1, "dp_aux_ch not started status 0x%08x\n",
488 I915_READ(ch_ctl));
9ee32fea
DV		 489 ret = -EBUSY;
490 goto out;
4f7f7b7e
CW		 491 }
492
46a5ae9f
PZ		 493 /* Only 5 data registers! */
494 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
495 ret = -E2BIG;
496 goto out;
497 }
498
ec5b01dd 499 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 500 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
501 has_aux_irq,
502 send_bytes,
503 aux_clock_divider);
5ed12a19 504
bc86625a
CW		 505 /* Must try at least 3 times according to DP spec */
506 for (try = 0; try < 5; try++) {
507 /* Load the send data into the aux channel data registers */
508 for (i = 0; i < send_bytes; i += 4)
509 I915_WRITE(ch_data + i,
510 pack_aux(send + i, send_bytes - i));
511
512 /* Send the command and wait for it to complete */
5ed12a19 513 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 514
515 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
516
517 /* Clear done status and any errors */
518 I915_WRITE(ch_ctl,
519 status |
520 DP_AUX_CH_CTL_DONE |
521 DP_AUX_CH_CTL_TIME_OUT_ERROR |
522 DP_AUX_CH_CTL_RECEIVE_ERROR);
523
524 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
525 DP_AUX_CH_CTL_RECEIVE_ERROR))
526 continue;
527 if (status & DP_AUX_CH_CTL_DONE)
528 break;
529 }
4f7f7b7e 530 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 531 break;
532 }
533
a4fc5ed6 534 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 535 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 536 ret = -EBUSY;
537 goto out;
a4fc5ed6
KP		 538 }
539
540 /* Check for timeout or receive error.
541 * Timeouts occur when the sink is not connected
542 */
a5b3da54 543 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 544 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 545 ret = -EIO;
546 goto out;
a5b3da54 547 }
1ae8c0a5
KP		 548
549 /* Timeouts occur when the device isn't connected, so they're
550 * "normal" -- don't fill the kernel log with these */
a5b3da54 551 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 552 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 553 ret = -ETIMEDOUT;
554 goto out;
a4fc5ed6
KP		 555 }
556
557 /* Unload any bytes sent back from the other side */
558 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
559 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 560 if (recv_bytes > recv_size)
561 recv_bytes = recv_size;
0206e353 562
4f7f7b7e
CW		 563 for (i = 0; i < recv_bytes; i += 4)
564 unpack_aux(I915_READ(ch_data + i),
565 recv + i, recv_bytes - i);
a4fc5ed6 566
9ee32fea
DV		 567 ret = recv_bytes;
568out:
569 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 570 intel_aux_display_runtime_put(dev_priv);
9ee32fea 571
884f19e9
JN		 572 if (vdd)
573 edp_panel_vdd_off(intel_dp, false);
574
9ee32fea 575 return ret;
a4fc5ed6
KP		 576}
577
9d1a1031
JN		 578#define HEADER_SIZE 4
579static ssize_t
580intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 581{
9d1a1031
JN		 582 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
583 uint8_t txbuf[20], rxbuf[20];
584 size_t txsize, rxsize;
a4fc5ed6 585 int ret;
a4fc5ed6 586
9d1a1031
JN		 587 txbuf[0] = msg->request << 4;
588 txbuf[1] = msg->address >> 8;
589 txbuf[2] = msg->address & 0xff;
590 txbuf[3] = msg->size - 1;
46a5ae9f 591
9d1a1031
JN		 592 switch (msg->request & ~DP_AUX_I2C_MOT) {
593 case DP_AUX_NATIVE_WRITE:
594 case DP_AUX_I2C_WRITE:
595 txsize = HEADER_SIZE + msg->size;
596 rxsize = 1;
f51a44b9 597
9d1a1031
JN		 598 if (WARN_ON(txsize > 20))
599 return -E2BIG;
a4fc5ed6 600
9d1a1031 601 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 602
9d1a1031
JN		 603 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
604 if (ret > 0) {
605 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 606
9d1a1031
JN		 607 /* Return payload size. */
608 ret = msg->size;
609 }
610 break;
46a5ae9f 611
9d1a1031
JN		 612 case DP_AUX_NATIVE_READ:
613 case DP_AUX_I2C_READ:
614 txsize = HEADER_SIZE;
615 rxsize = msg->size + 1;
a4fc5ed6 616
9d1a1031
JN		 617 if (WARN_ON(rxsize > 20))
618 return -E2BIG;
a4fc5ed6 619
9d1a1031
JN		 620 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
621 if (ret > 0) {
622 msg->reply = rxbuf[0] >> 4;
623 /*
624 * Assume happy day, and copy the data. The caller is
625 * expected to check msg->reply before touching it.
626 *
627 * Return payload size.
628 */
629 ret--;
630 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 631 }
9d1a1031
JN		 632 break;
633
634 default:
635 ret = -EINVAL;
636 break;
a4fc5ed6 637 }
f51a44b9 638
9d1a1031 639 return ret;
a4fc5ed6
KP		 640}
641
9d1a1031
JN		 642static void
643intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
644{
645 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 646 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
647 enum port port = intel_dig_port->port;
0b99836f 648 const char *name = NULL;
ab2c0672
DA		 649 int ret;
650
33ad6626
JN		 651 switch (port) {
652 case PORT_A:
653 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 654 name = "DPDDC-A";
ab2c0672 655 break;
33ad6626
JN		 656 case PORT_B:
657 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 658 name = "DPDDC-B";
ab2c0672 659 break;
33ad6626
JN		 660 case PORT_C:
661 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 662 name = "DPDDC-C";
ab2c0672 663 break;
33ad6626
JN		 664 case PORT_D:
665 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 666 name = "DPDDC-D";
33ad6626
JN		 667 break;
668 default:
669 BUG();
ab2c0672
DA		 670 }
671
33ad6626
JN		 672 if (!HAS_DDI(dev))
673 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 674
0b99836f 675 intel_dp->aux.name = name;
9d1a1031
JN		 676 intel_dp->aux.dev = dev->dev;
677 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 678
0b99836f
JN		 679 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
680 connector->base.kdev->kobj.name);
8316f337 681
0b99836f
JN		 682 ret = drm_dp_aux_register_i2c_bus(&intel_dp->aux);
683 if (ret < 0) {
684 DRM_ERROR("drm_dp_aux_register_i2c_bus() for %s failed (%d)\n",
685 name, ret);
686 return;
ab2c0672 687 }
8a5e6aeb 688
0b99836f
JN		 689 ret = sysfs_create_link(&connector->base.kdev->kobj,
690 &intel_dp->aux.ddc.dev.kobj,
691 intel_dp->aux.ddc.dev.kobj.name);
692 if (ret < 0) {
693 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
694 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
ab2c0672 695 }
a4fc5ed6
KP		 696}
697
80f65de3
ID		 698static void
699intel_dp_connector_unregister(struct intel_connector *intel_connector)
700{
701 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
702
703 sysfs_remove_link(&intel_connector->base.kdev->kobj,
0b99836f 704 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 705 intel_connector_unregister(intel_connector);
706}
707
c6bb3538
DV		 708static void
709intel_dp_set_clock(struct intel_encoder *encoder,
710 struct intel_crtc_config *pipe_config, int link_bw)
711{
712 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 713 const struct dp_link_dpll *divisor = NULL;
714 int i, count = 0;
c6bb3538
DV		 715
716 if (IS_G4X(dev)) {
9dd4ffdf
CML		 717 divisor = gen4_dpll;
718 count = ARRAY_SIZE(gen4_dpll);
c6bb3538
DV		 719 } else if (IS_HASWELL(dev)) {
720 /* Haswell has special-purpose DP DDI clocks. */
721 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 722 divisor = pch_dpll;
723 count = ARRAY_SIZE(pch_dpll);
c6bb3538 724 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 725 divisor = vlv_dpll;
726 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 727 }
9dd4ffdf
CML		 728
729 if (divisor && count) {
730 for (i = 0; i < count; i++) {
731 if (link_bw == divisor[i].link_bw) {
732 pipe_config->dpll = divisor[i].dpll;
733 pipe_config->clock_set = true;
734 break;
735 }
736 }
c6bb3538
DV		 737 }
738}
739
439d7ac0
PB		 740static void
741intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
742{
743 struct drm_device *dev = crtc->base.dev;
744 struct drm_i915_private *dev_priv = dev->dev_private;
745 enum transcoder transcoder = crtc->config.cpu_transcoder;
746
747 I915_WRITE(PIPE_DATA_M2(transcoder),
748 TU_SIZE(m_n->tu) | m_n->gmch_m);
749 I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
750 I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
751 I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
752}
753
00c09d70 754bool
5bfe2ac0
DV		 755intel_dp_compute_config(struct intel_encoder *encoder,
756 struct intel_crtc_config *pipe_config)
a4fc5ed6 757{
5bfe2ac0 758 struct drm_device *dev = encoder->base.dev;
36008365 759 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 760 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 761 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 762 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 763 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 764 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 765 int lane_count, clock;
397fe157 766 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
06ea66b6
TP		 767 /* Conveniently, the link BW constants become indices with a shift...*/
768 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 769 int bpp, mode_rate;
06ea66b6 770 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 771 int link_avail, link_clock;
a4fc5ed6 772
bc7d38a4 773 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 774 pipe_config->has_pch_encoder = true;
775
03afc4a2 776 pipe_config->has_dp_encoder = true;
a4fc5ed6 777
dd06f90e
JN		 778 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
779 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
780 adjusted_mode);
2dd24552
JB		 781 if (!HAS_PCH_SPLIT(dev))
782 intel_gmch_panel_fitting(intel_crtc, pipe_config,
783 intel_connector->panel.fitting_mode);
784 else
b074cec8
JB		 785 intel_pch_panel_fitting(intel_crtc, pipe_config,
786 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 787 }
788
cb1793ce 789 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 790 return false;
791
083f9560
DV		 792 DRM_DEBUG_KMS("DP link computation with max lane count %i "
793 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 794 max_lane_count, bws[max_clock],
795 adjusted_mode->crtc_clock);
083f9560 796
36008365
DV		 797 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
798 * bpc in between. */
3e7ca985 799 bpp = pipe_config->pipe_bpp;
6da7f10d
JN		 800 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
801 dev_priv->vbt.edp_bpp < bpp) {
7984211e
ID		 802 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
803 dev_priv->vbt.edp_bpp);
6da7f10d 804 bpp = dev_priv->vbt.edp_bpp;
7984211e 805 }
657445fe 806
36008365 807 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 808 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
809 bpp);
36008365 810
38aecea0
DV		 811 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
812 for (clock = 0; clock <= max_clock; clock++) {
36008365
DV		 813 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
814 link_avail = intel_dp_max_data_rate(link_clock,
815 lane_count);
816
817 if (mode_rate <= link_avail) {
818 goto found;
819 }
820 }
821 }
822 }
c4867936 823
36008365 824 return false;
3685a8f3 825
36008365 826found:
55bc60db
VS		 827 if (intel_dp->color_range_auto) {
828 /*
829 * See:
830 * CEA-861-E - 5.1 Default Encoding Parameters
831 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
832 */
18316c8c 833 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 834 intel_dp->color_range = DP_COLOR_RANGE_16_235;
835 else
836 intel_dp->color_range = 0;
837 }
838
3685a8f3 839 if (intel_dp->color_range)
50f3b016 840 pipe_config->limited_color_range = true;
a4fc5ed6 841
36008365
DV		 842 intel_dp->link_bw = bws[clock];
843 intel_dp->lane_count = lane_count;
657445fe 844 pipe_config->pipe_bpp = bpp;
ff9a6750 845 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 846
36008365
DV		 847 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
848 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 849 pipe_config->port_clock, bpp);
36008365
DV		 850 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
851 mode_rate, link_avail);
a4fc5ed6 852
03afc4a2 853 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 854 adjusted_mode->crtc_clock,
855 pipe_config->port_clock,
03afc4a2 856 &pipe_config->dp_m_n);
9d1a455b 857
439d7ac0
PB		 858 if (intel_connector->panel.downclock_mode != NULL &&
859 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
860 intel_link_compute_m_n(bpp, lane_count,
861 intel_connector->panel.downclock_mode->clock,
862 pipe_config->port_clock,
863 &pipe_config->dp_m2_n2);
864 }
865
c6bb3538
DV		 866 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
867
03afc4a2 868 return true;
a4fc5ed6
KP		 869}
870
7c62a164 871static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 872{
7c62a164
DV		 873 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
874 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
875 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 876 struct drm_i915_private *dev_priv = dev->dev_private;
877 u32 dpa_ctl;
878
ff9a6750 879 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 880 dpa_ctl = I915_READ(DP_A);
881 dpa_ctl &= ~DP_PLL_FREQ_MASK;
882
ff9a6750 883 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 884 /* For a long time we've carried around a ILK-DevA w/a for the
885 * 160MHz clock. If we're really unlucky, it's still required.
886 */
887 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 888 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 889 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 890 } else {
891 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 892 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 893 }
1ce17038 894
ea9b6006
DV		 895 I915_WRITE(DP_A, dpa_ctl);
896
897 POSTING_READ(DP_A);
898 udelay(500);
899}
900
b934223d 901static void intel_dp_mode_set(struct intel_encoder *encoder)
a4fc5ed6 902{
b934223d 903 struct drm_device *dev = encoder->base.dev;
417e822d 904 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 905 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 906 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 907 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
908 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 909
417e822d 910 /*
1a2eb460 911 * There are four kinds of DP registers:
417e822d
KP		 912 *
913 * IBX PCH
1a2eb460
KP		 914 * SNB CPU
915 * IVB CPU
417e822d
KP		 916 * CPT PCH
917 *
918 * IBX PCH and CPU are the same for almost everything,
919 * except that the CPU DP PLL is configured in this
920 * register
921 *
922 * CPT PCH is quite different, having many bits moved
923 * to the TRANS_DP_CTL register instead. That
924 * configuration happens (oddly) in ironlake_pch_enable
925 */
9c9e7927 926
417e822d
KP		 927 /* Preserve the BIOS-computed detected bit. This is
928 * supposed to be read-only.
929 */
930 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 931
417e822d 932 /* Handle DP bits in common between all three register formats */
417e822d 933 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 934 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 935
e0dac65e
WF		 936 if (intel_dp->has_audio) {
937 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 938 pipe_name(crtc->pipe));
ea5b213a 939 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 940 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 941 }
247d89f6 942
417e822d 943 /* Split out the IBX/CPU vs CPT settings */
32f9d658 944
bc7d38a4 945 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 946 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
947 intel_dp->DP |= DP_SYNC_HS_HIGH;
948 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
949 intel_dp->DP |= DP_SYNC_VS_HIGH;
950 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
951
6aba5b6c 952 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 953 intel_dp->DP |= DP_ENHANCED_FRAMING;
954
7c62a164 955 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 956 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 957 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 958 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 959
960 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
961 intel_dp->DP |= DP_SYNC_HS_HIGH;
962 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
963 intel_dp->DP |= DP_SYNC_VS_HIGH;
964 intel_dp->DP |= DP_LINK_TRAIN_OFF;
965
6aba5b6c 966 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 967 intel_dp->DP |= DP_ENHANCED_FRAMING;
968
7c62a164 969 if (crtc->pipe == 1)
417e822d 970 intel_dp->DP |= DP_PIPEB_SELECT;
417e822d
KP		 971 } else {
972 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 973 }
ea9b6006 974
bc7d38a4 975 if (port == PORT_A && !IS_VALLEYVIEW(dev))
7c62a164 976 ironlake_set_pll_cpu_edp(intel_dp);
a4fc5ed6
KP		 977}
978
ffd6749d
PZ		 979#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
980#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 981
1a5ef5b7
PZ		 982#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
983#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 984
ffd6749d
PZ		 985#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
986#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 987
4be73780 988static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 989 u32 mask,
990 u32 value)
bd943159 991{
30add22d 992 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 993 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 994 u32 pp_stat_reg, pp_ctrl_reg;
995
bf13e81b
JN		 996 pp_stat_reg = _pp_stat_reg(intel_dp);
997 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 998
99ea7127 999 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1000 mask, value,
1001 I915_READ(pp_stat_reg),
1002 I915_READ(pp_ctrl_reg));
32ce697c 1003
453c5420 1004 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1005 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1006 I915_READ(pp_stat_reg),
1007 I915_READ(pp_ctrl_reg));
32ce697c 1008 }
54c136d4
CW		 1009
1010 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1011}
32ce697c 1012
4be73780 1013static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1014{
1015 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1016 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1017}
1018
4be73780 1019static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1020{
1021 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1022 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1023}
1024
4be73780 1025static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1026{
1027 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1028
1029 /* When we disable the VDD override bit last we have to do the manual
1030 * wait. */
1031 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1032 intel_dp->panel_power_cycle_delay);
1033
4be73780 1034 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1035}
1036
4be73780 1037static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1038{
1039 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1040 intel_dp->backlight_on_delay);
1041}
1042
4be73780 1043static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1044{
1045 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1046 intel_dp->backlight_off_delay);
1047}
99ea7127 1048
832dd3c1
KP		 1049/* Read the current pp_control value, unlocking the register if it
1050 * is locked
1051 */
1052
453c5420 1053static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1054{
453c5420
JB		 1055 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1056 struct drm_i915_private *dev_priv = dev->dev_private;
1057 u32 control;
832dd3c1 1058
bf13e81b 1059 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1060 control &= ~PANEL_UNLOCK_MASK;
1061 control |= PANEL_UNLOCK_REGS;
1062 return control;
bd943159
KP		 1063}
1064
adddaaf4 1065static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1066{
30add22d 1067 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1068 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1069 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1070 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1071 enum intel_display_power_domain power_domain;
5d613501 1072 u32 pp;
453c5420 1073 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1074 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1075
97af61f5 1076 if (!is_edp(intel_dp))
adddaaf4 1077 return false;
bd943159
KP		 1078
1079 intel_dp->want_panel_vdd = true;
99ea7127 1080
4be73780 1081 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1082 return need_to_disable;
b0665d57 1083
4e6e1a54
ID		 1084 power_domain = intel_display_port_power_domain(intel_encoder);
1085 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1086
b0665d57 1087 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1088
4be73780
DV		 1089 if (!edp_have_panel_power(intel_dp))
1090 wait_panel_power_cycle(intel_dp);
99ea7127 1091
453c5420 1092 pp = ironlake_get_pp_control(intel_dp);
5d613501 1093 pp |= EDP_FORCE_VDD;
ebf33b18 1094
bf13e81b
JN		 1095 pp_stat_reg = _pp_stat_reg(intel_dp);
1096 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1097
1098 I915_WRITE(pp_ctrl_reg, pp);
1099 POSTING_READ(pp_ctrl_reg);
1100 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1101 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1102 /*
1103 * If the panel wasn't on, delay before accessing aux channel
1104 */
4be73780 1105 if (!edp_have_panel_power(intel_dp)) {
bd943159 1106 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1107 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1108 }
adddaaf4
JN		 1109
1110 return need_to_disable;
1111}
1112
b80d6c78 1113void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4
JN		 1114{
1115 if (is_edp(intel_dp)) {
1116 bool vdd = _edp_panel_vdd_on(intel_dp);
1117
1118 WARN(!vdd, "eDP VDD already requested on\n");
1119 }
5d613501
JB		 1120}
1121
4be73780 1122static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1123{
30add22d 1124 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1125 struct drm_i915_private *dev_priv = dev->dev_private;
1126 u32 pp;
453c5420 1127 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1128
a0e99e68
DV		 1129 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1130
4be73780 1131 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
4e6e1a54
ID		 1132 struct intel_digital_port *intel_dig_port =
1133 dp_to_dig_port(intel_dp);
1134 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1135 enum intel_display_power_domain power_domain;
1136
b0665d57
PZ		 1137 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1138
453c5420 1139 pp = ironlake_get_pp_control(intel_dp);
bd943159 1140 pp &= ~EDP_FORCE_VDD;
bd943159 1141
9f08ef59
PZ		 1142 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1143 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1144
1145 I915_WRITE(pp_ctrl_reg, pp);
1146 POSTING_READ(pp_ctrl_reg);
99ea7127 1147
453c5420
JB		 1148 /* Make sure sequencer is idle before allowing subsequent activity */
1149 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1150 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c
PZ		 1151
1152 if ((pp & POWER_TARGET_ON) == 0)
dce56b3c 1153 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1154
4e6e1a54
ID		 1155 power_domain = intel_display_port_power_domain(intel_encoder);
1156 intel_display_power_put(dev_priv, power_domain);
bd943159
KP		 1157 }
1158}
5d613501 1159
4be73780 1160static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1161{
1162 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1163 struct intel_dp, panel_vdd_work);
30add22d 1164 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1165
627f7675 1166 mutex_lock(&dev->mode_config.mutex);
4be73780 1167 edp_panel_vdd_off_sync(intel_dp);
627f7675 1168 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1169}
1170
4be73780 1171static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1172{
97af61f5
KP		 1173 if (!is_edp(intel_dp))
1174 return;
5d613501 1175
bd943159 1176 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1177
bd943159
KP		 1178 intel_dp->want_panel_vdd = false;
1179
1180 if (sync) {
4be73780 1181 edp_panel_vdd_off_sync(intel_dp);
bd943159
KP		 1182 } else {
1183 /*
1184 * Queue the timer to fire a long
1185 * time from now (relative to the power down delay)
1186 * to keep the panel power up across a sequence of operations
1187 */
1188 schedule_delayed_work(&intel_dp->panel_vdd_work,
1189 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1190 }
5d613501
JB		 1191}
1192
4be73780 1193void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1194{
30add22d 1195 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1196 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1197 u32 pp;
453c5420 1198 u32 pp_ctrl_reg;
9934c132 1199
97af61f5 1200 if (!is_edp(intel_dp))
bd943159 1201 return;
99ea7127
KP		 1202
1203 DRM_DEBUG_KMS("Turn eDP power on\n");
1204
4be73780 1205 if (edp_have_panel_power(intel_dp)) {
99ea7127 1206 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1207 return;
99ea7127 1208 }
9934c132 1209
4be73780 1210 wait_panel_power_cycle(intel_dp);
37c6c9b0 1211
bf13e81b 1212 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1213 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1214 if (IS_GEN5(dev)) {
1215 /* ILK workaround: disable reset around power sequence */
1216 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1217 I915_WRITE(pp_ctrl_reg, pp);
1218 POSTING_READ(pp_ctrl_reg);
05ce1a49 1219 }
37c6c9b0 1220
1c0ae80a 1221 pp |= POWER_TARGET_ON;
99ea7127
KP		 1222 if (!IS_GEN5(dev))
1223 pp |= PANEL_POWER_RESET;
1224
453c5420
JB		 1225 I915_WRITE(pp_ctrl_reg, pp);
1226 POSTING_READ(pp_ctrl_reg);
9934c132 1227
4be73780 1228 wait_panel_on(intel_dp);
dce56b3c 1229 intel_dp->last_power_on = jiffies;
9934c132 1230
05ce1a49
KP		 1231 if (IS_GEN5(dev)) {
1232 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1233 I915_WRITE(pp_ctrl_reg, pp);
1234 POSTING_READ(pp_ctrl_reg);
05ce1a49 1235 }
9934c132
JB		 1236}
1237
4be73780 1238void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1239{
4e6e1a54
ID		 1240 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1241 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1242 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1243 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1244 enum intel_display_power_domain power_domain;
99ea7127 1245 u32 pp;
453c5420 1246 u32 pp_ctrl_reg;
9934c132 1247
97af61f5
KP		 1248 if (!is_edp(intel_dp))
1249 return;
37c6c9b0 1250
99ea7127 1251 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1252
4be73780 1253 edp_wait_backlight_off(intel_dp);
dce56b3c 1254
24f3e092
JN		 1255 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1256
453c5420 1257 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1258 /* We need to switch off panel power _and_ force vdd, for otherwise some
1259 * panels get very unhappy and cease to work. */
b3064154
PJ		 1260 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1261 EDP_BLC_ENABLE);
453c5420 1262
bf13e81b 1263 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1264
849e39f5
PZ		 1265 intel_dp->want_panel_vdd = false;
1266
453c5420
JB		 1267 I915_WRITE(pp_ctrl_reg, pp);
1268 POSTING_READ(pp_ctrl_reg);
9934c132 1269
dce56b3c 1270 intel_dp->last_power_cycle = jiffies;
4be73780 1271 wait_panel_off(intel_dp);
849e39f5
PZ		 1272
1273 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1274 power_domain = intel_display_port_power_domain(intel_encoder);
1275 intel_display_power_put(dev_priv, power_domain);
9934c132
JB		 1276}
1277
4be73780 1278void intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1279{
da63a9f2
PZ		 1280 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1281 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1282 struct drm_i915_private *dev_priv = dev->dev_private;
1283 u32 pp;
453c5420 1284 u32 pp_ctrl_reg;
32f9d658 1285
f01eca2e
KP		 1286 if (!is_edp(intel_dp))
1287 return;
1288
28c97730 1289 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1290 /*
1291 * If we enable the backlight right away following a panel power
1292 * on, we may see slight flicker as the panel syncs with the eDP
1293 * link. So delay a bit to make sure the image is solid before
1294 * allowing it to appear.
1295 */
4be73780 1296 wait_backlight_on(intel_dp);
453c5420 1297 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1298 pp |= EDP_BLC_ENABLE;
453c5420 1299
bf13e81b 1300 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1301
1302 I915_WRITE(pp_ctrl_reg, pp);
1303 POSTING_READ(pp_ctrl_reg);
035aa3de 1304
752aa88a 1305 intel_panel_enable_backlight(intel_dp->attached_connector);
32f9d658
ZW		 1306}
1307
4be73780 1308void intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1309{
30add22d 1310 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1311 struct drm_i915_private *dev_priv = dev->dev_private;
1312 u32 pp;
453c5420 1313 u32 pp_ctrl_reg;
32f9d658 1314
f01eca2e
KP		 1315 if (!is_edp(intel_dp))
1316 return;
1317
752aa88a 1318 intel_panel_disable_backlight(intel_dp->attached_connector);
035aa3de 1319
28c97730 1320 DRM_DEBUG_KMS("\n");
453c5420 1321 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1322 pp &= ~EDP_BLC_ENABLE;
453c5420 1323
bf13e81b 1324 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1325
1326 I915_WRITE(pp_ctrl_reg, pp);
1327 POSTING_READ(pp_ctrl_reg);
dce56b3c 1328 intel_dp->last_backlight_off = jiffies;
32f9d658 1329}
a4fc5ed6 1330
2bd2ad64 1331static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1332{
da63a9f2
PZ		 1333 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1334 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1335 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1336 struct drm_i915_private *dev_priv = dev->dev_private;
1337 u32 dpa_ctl;
1338
2bd2ad64
DV		 1339 assert_pipe_disabled(dev_priv,
1340 to_intel_crtc(crtc)->pipe);
1341
d240f20f
JB		 1342 DRM_DEBUG_KMS("\n");
1343 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1344 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1345 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1346
1347 /* We don't adjust intel_dp->DP while tearing down the link, to
1348 * facilitate link retraining (e.g. after hotplug). Hence clear all
1349 * enable bits here to ensure that we don't enable too much. */
1350 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1351 intel_dp->DP |= DP_PLL_ENABLE;
1352 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1353 POSTING_READ(DP_A);
1354 udelay(200);
d240f20f
JB		 1355}
1356
2bd2ad64 1357static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1358{
da63a9f2
PZ		 1359 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1360 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1361 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1362 struct drm_i915_private *dev_priv = dev->dev_private;
1363 u32 dpa_ctl;
1364
2bd2ad64
DV		 1365 assert_pipe_disabled(dev_priv,
1366 to_intel_crtc(crtc)->pipe);
1367
d240f20f 1368 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1369 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1370 "dp pll off, should be on\n");
1371 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1372
1373 /* We can't rely on the value tracked for the DP register in
1374 * intel_dp->DP because link_down must not change that (otherwise link
1375 * re-training will fail. */
298b0b39 1376 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1377 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1378 POSTING_READ(DP_A);
d240f20f
JB		 1379 udelay(200);
1380}
1381
c7ad3810 1382/* If the sink supports it, try to set the power state appropriately */
c19b0669 1383void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1384{
1385 int ret, i;
1386
1387 /* Should have a valid DPCD by this point */
1388 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1389 return;
1390
1391 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1392 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1393 DP_SET_POWER_D3);
c7ad3810
JB		 1394 if (ret != 1)
1395 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1396 } else {
1397 /*
1398 * When turning on, we need to retry for 1ms to give the sink
1399 * time to wake up.
1400 */
1401 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1402 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1403 DP_SET_POWER_D0);
c7ad3810
JB		 1404 if (ret == 1)
1405 break;
1406 msleep(1);
1407 }
1408 }
1409}
1410
19d8fe15
DV		 1411static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1412 enum pipe *pipe)
d240f20f 1413{
19d8fe15 1414 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1415 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1416 struct drm_device *dev = encoder->base.dev;
1417 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1418 enum intel_display_power_domain power_domain;
1419 u32 tmp;
1420
1421 power_domain = intel_display_port_power_domain(encoder);
1422 if (!intel_display_power_enabled(dev_priv, power_domain))
1423 return false;
1424
1425 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1426
1427 if (!(tmp & DP_PORT_EN))
1428 return false;
1429
bc7d38a4 1430 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1431 *pipe = PORT_TO_PIPE_CPT(tmp);
bc7d38a4 1432 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1433 *pipe = PORT_TO_PIPE(tmp);
1434 } else {
1435 u32 trans_sel;
1436 u32 trans_dp;
1437 int i;
1438
1439 switch (intel_dp->output_reg) {
1440 case PCH_DP_B:
1441 trans_sel = TRANS_DP_PORT_SEL_B;
1442 break;
1443 case PCH_DP_C:
1444 trans_sel = TRANS_DP_PORT_SEL_C;
1445 break;
1446 case PCH_DP_D:
1447 trans_sel = TRANS_DP_PORT_SEL_D;
1448 break;
1449 default:
1450 return true;
1451 }
1452
1453 for_each_pipe(i) {
1454 trans_dp = I915_READ(TRANS_DP_CTL(i));
1455 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1456 *pipe = i;
1457 return true;
1458 }
1459 }
19d8fe15 1460
4a0833ec
DV		 1461 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1462 intel_dp->output_reg);
1463 }
d240f20f 1464
19d8fe15
DV		 1465 return true;
1466}
d240f20f 1467
045ac3b5
JB		 1468static void intel_dp_get_config(struct intel_encoder *encoder,
1469 struct intel_crtc_config *pipe_config)
1470{
1471 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1472 u32 tmp, flags = 0;
63000ef6
XZ		 1473 struct drm_device *dev = encoder->base.dev;
1474 struct drm_i915_private *dev_priv = dev->dev_private;
1475 enum port port = dp_to_dig_port(intel_dp)->port;
1476 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1477 int dotclock;
045ac3b5 1478
63000ef6
XZ		 1479 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1480 tmp = I915_READ(intel_dp->output_reg);
1481 if (tmp & DP_SYNC_HS_HIGH)
1482 flags |= DRM_MODE_FLAG_PHSYNC;
1483 else
1484 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1485
63000ef6
XZ		 1486 if (tmp & DP_SYNC_VS_HIGH)
1487 flags |= DRM_MODE_FLAG_PVSYNC;
1488 else
1489 flags |= DRM_MODE_FLAG_NVSYNC;
1490 } else {
1491 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1492 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1493 flags |= DRM_MODE_FLAG_PHSYNC;
1494 else
1495 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1496
63000ef6
XZ		 1497 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1498 flags |= DRM_MODE_FLAG_PVSYNC;
1499 else
1500 flags |= DRM_MODE_FLAG_NVSYNC;
1501 }
045ac3b5
JB		 1502
1503 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1504
eb14cb74
VS		 1505 pipe_config->has_dp_encoder = true;
1506
1507 intel_dp_get_m_n(crtc, pipe_config);
1508
18442d08 1509 if (port == PORT_A) {
f1f644dc
JB		 1510 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1511 pipe_config->port_clock = 162000;
1512 else
1513 pipe_config->port_clock = 270000;
1514 }
18442d08
VS		 1515
1516 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1517 &pipe_config->dp_m_n);
1518
1519 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1520 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1521
241bfc38 1522 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1523
c6cd2ee2
JN		 1524 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1525 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1526 /*
1527 * This is a big fat ugly hack.
1528 *
1529 * Some machines in UEFI boot mode provide us a VBT that has 18
1530 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1531 * unknown we fail to light up. Yet the same BIOS boots up with
1532 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1533 * max, not what it tells us to use.
1534 *
1535 * Note: This will still be broken if the eDP panel is not lit
1536 * up by the BIOS, and thus we can't get the mode at module
1537 * load.
1538 */
1539 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1540 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1541 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1542 }
045ac3b5
JB		 1543}
1544
a031d709 1545static bool is_edp_psr(struct drm_device *dev)
2293bb5c 1546{
a031d709
RV		 1547 struct drm_i915_private *dev_priv = dev->dev_private;
1548
1549 return dev_priv->psr.sink_support;
2293bb5c
SK		 1550}
1551
2b28bb1b
RV		 1552static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1553{
1554 struct drm_i915_private *dev_priv = dev->dev_private;
1555
18b5992c 1556 if (!HAS_PSR(dev))
2b28bb1b
RV		 1557 return false;
1558
18b5992c 1559 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1560}
1561
1562static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1563 struct edp_vsc_psr *vsc_psr)
1564{
1565 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1566 struct drm_device *dev = dig_port->base.base.dev;
1567 struct drm_i915_private *dev_priv = dev->dev_private;
1568 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1569 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1570 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1571 uint32_t *data = (uint32_t *) vsc_psr;
1572 unsigned int i;
1573
1574 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1575 the video DIP being updated before program video DIP data buffer
1576 registers for DIP being updated. */
1577 I915_WRITE(ctl_reg, 0);
1578 POSTING_READ(ctl_reg);
1579
1580 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1581 if (i < sizeof(struct edp_vsc_psr))
1582 I915_WRITE(data_reg + i, *data++);
1583 else
1584 I915_WRITE(data_reg + i, 0);
1585 }
1586
1587 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1588 POSTING_READ(ctl_reg);
1589}
1590
1591static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1592{
1593 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1594 struct drm_i915_private *dev_priv = dev->dev_private;
1595 struct edp_vsc_psr psr_vsc;
1596
1597 if (intel_dp->psr_setup_done)
1598 return;
1599
1600 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1601 memset(&psr_vsc, 0, sizeof(psr_vsc));
1602 psr_vsc.sdp_header.HB0 = 0;
1603 psr_vsc.sdp_header.HB1 = 0x7;
1604 psr_vsc.sdp_header.HB2 = 0x2;
1605 psr_vsc.sdp_header.HB3 = 0x8;
1606 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1607
1608 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1609 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1610 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1611
1612 intel_dp->psr_setup_done = true;
1613}
1614
1615static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1616{
1617 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1618 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1619 uint32_t aux_clock_divider;
2b28bb1b
RV		 1620 int precharge = 0x3;
1621 int msg_size = 5; /* Header(4) + Message(1) */
1622
ec5b01dd
DL		 1623 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1624
2b28bb1b
RV		 1625 /* Enable PSR in sink */
1626 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
9d1a1031
JN		 1627 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1628 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 1629 else
9d1a1031
JN		 1630 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1631 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 1632
1633 /* Setup AUX registers */
18b5992c
BW		 1634 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1635 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1636 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1637 DP_AUX_CH_CTL_TIME_OUT_400us |
1638 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1639 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1640 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1641}
1642
1643static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1644{
1645 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1646 struct drm_i915_private *dev_priv = dev->dev_private;
1647 uint32_t max_sleep_time = 0x1f;
1648 uint32_t idle_frames = 1;
1649 uint32_t val = 0x0;
ed8546ac 1650 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
2b28bb1b
RV		 1651
1652 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1653 val |= EDP_PSR_LINK_STANDBY;
1654 val |= EDP_PSR_TP2_TP3_TIME_0us;
1655 val |= EDP_PSR_TP1_TIME_0us;
1656 val |= EDP_PSR_SKIP_AUX_EXIT;
1657 } else
1658 val |= EDP_PSR_LINK_DISABLE;
1659
18b5992c 1660 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 1661 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 1662 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1663 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1664 EDP_PSR_ENABLE);
1665}
1666
3f51e471
RV		 1667static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1668{
1669 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1670 struct drm_device *dev = dig_port->base.base.dev;
1671 struct drm_i915_private *dev_priv = dev->dev_private;
1672 struct drm_crtc *crtc = dig_port->base.base.crtc;
1673 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
f4510a27 1674 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->primary->fb)->obj;
3f51e471
RV		 1675 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1676
a031d709
RV		 1677 dev_priv->psr.source_ok = false;
1678
18b5992c 1679 if (!HAS_PSR(dev)) {
3f51e471 1680 DRM_DEBUG_KMS("PSR not supported on this platform\n");
3f51e471
RV		 1681 return false;
1682 }
1683
1684 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1685 (dig_port->port != PORT_A)) {
1686 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1687 return false;
1688 }
1689
d330a953 1690 if (!i915.enable_psr) {
105b7c11 1691 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1692 return false;
1693 }
1694
cd234b0b
CW		 1695 crtc = dig_port->base.base.crtc;
1696 if (crtc == NULL) {
1697 DRM_DEBUG_KMS("crtc not active for PSR\n");
cd234b0b
CW		 1698 return false;
1699 }
1700
1701 intel_crtc = to_intel_crtc(crtc);
20ddf665 1702 if (!intel_crtc_active(crtc)) {
3f51e471 1703 DRM_DEBUG_KMS("crtc not active for PSR\n");
3f51e471
RV		 1704 return false;
1705 }
1706
f4510a27 1707 obj = to_intel_framebuffer(crtc->primary->fb)->obj;
3f51e471
RV		 1708 if (obj->tiling_mode != I915_TILING_X ||
1709 obj->fence_reg == I915_FENCE_REG_NONE) {
1710 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
3f51e471
RV		 1711 return false;
1712 }
1713
1714 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1715 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
3f51e471
RV		 1716 return false;
1717 }
1718
1719 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1720 S3D_ENABLE) {
1721 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1722 return false;
1723 }
1724
ca73b4f0 1725 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1726 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1727 return false;
1728 }
1729
a031d709 1730 dev_priv->psr.source_ok = true;
3f51e471
RV		 1731 return true;
1732}
1733
3d739d92 1734static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1735{
1736 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1737
3f51e471
RV		 1738 if (!intel_edp_psr_match_conditions(intel_dp) ||
1739 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1740 return;
1741
1742 /* Setup PSR once */
1743 intel_edp_psr_setup(intel_dp);
1744
1745 /* Enable PSR on the panel */
1746 intel_edp_psr_enable_sink(intel_dp);
1747
1748 /* Enable PSR on the host */
1749 intel_edp_psr_enable_source(intel_dp);
1750}
1751
3d739d92
RV		 1752void intel_edp_psr_enable(struct intel_dp *intel_dp)
1753{
1754 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1755
1756 if (intel_edp_psr_match_conditions(intel_dp) &&
1757 !intel_edp_is_psr_enabled(dev))
1758 intel_edp_psr_do_enable(intel_dp);
1759}
1760
2b28bb1b
RV		 1761void intel_edp_psr_disable(struct intel_dp *intel_dp)
1762{
1763 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1764 struct drm_i915_private *dev_priv = dev->dev_private;
1765
1766 if (!intel_edp_is_psr_enabled(dev))
1767 return;
1768
18b5992c
BW		 1769 I915_WRITE(EDP_PSR_CTL(dev),
1770 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2b28bb1b
RV		 1771
1772 /* Wait till PSR is idle */
18b5992c 1773 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2b28bb1b
RV		 1774 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1775 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1776}
1777
3d739d92
RV		 1778void intel_edp_psr_update(struct drm_device *dev)
1779{
1780 struct intel_encoder *encoder;
1781 struct intel_dp *intel_dp = NULL;
1782
1783 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1784 if (encoder->type == INTEL_OUTPUT_EDP) {
1785 intel_dp = enc_to_intel_dp(&encoder->base);
1786
a031d709 1787 if (!is_edp_psr(dev))
3d739d92
RV		 1788 return;
1789
1790 if (!intel_edp_psr_match_conditions(intel_dp))
1791 intel_edp_psr_disable(intel_dp);
1792 else
1793 if (!intel_edp_is_psr_enabled(dev))
1794 intel_edp_psr_do_enable(intel_dp);
1795 }
1796}
1797
e8cb4558 1798static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1799{
e8cb4558 1800 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1801 enum port port = dp_to_dig_port(intel_dp)->port;
1802 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1803
1804 /* Make sure the panel is off before trying to change the mode. But also
1805 * ensure that we have vdd while we switch off the panel. */
24f3e092 1806 intel_edp_panel_vdd_on(intel_dp);
4be73780 1807 intel_edp_backlight_off(intel_dp);
fdbc3b1f 1808 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 1809 intel_edp_panel_off(intel_dp);
3739850b
DV		 1810
1811 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1812 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1813 intel_dp_link_down(intel_dp);
d240f20f
JB		 1814}
1815
49277c31 1816static void g4x_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1817{
2bd2ad64 1818 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1819 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 1820
49277c31
VS		 1821 if (port != PORT_A)
1822 return;
1823
1824 intel_dp_link_down(intel_dp);
1825 ironlake_edp_pll_off(intel_dp);
1826}
1827
1828static void vlv_post_disable_dp(struct intel_encoder *encoder)
1829{
1830 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1831
1832 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 1833}
1834
e8cb4558 1835static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1836{
e8cb4558
DV		 1837 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1838 struct drm_device *dev = encoder->base.dev;
1839 struct drm_i915_private *dev_priv = dev->dev_private;
1840 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1841
0c33d8d7
DV		 1842 if (WARN_ON(dp_reg & DP_PORT_EN))
1843 return;
5d613501 1844
24f3e092 1845 intel_edp_panel_vdd_on(intel_dp);
f01eca2e 1846 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1847 intel_dp_start_link_train(intel_dp);
4be73780
DV		 1848 intel_edp_panel_on(intel_dp);
1849 edp_panel_vdd_off(intel_dp, true);
33a34e4e 1850 intel_dp_complete_link_train(intel_dp);
3ab9c637 1851 intel_dp_stop_link_train(intel_dp);
ab1f90f9 1852}
89b667f8 1853
ecff4f3b
JN		 1854static void g4x_enable_dp(struct intel_encoder *encoder)
1855{
828f5c6e
JN		 1856 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1857
ecff4f3b 1858 intel_enable_dp(encoder);
4be73780 1859 intel_edp_backlight_on(intel_dp);
ab1f90f9 1860}
89b667f8 1861
ab1f90f9
JN		 1862static void vlv_enable_dp(struct intel_encoder *encoder)
1863{
828f5c6e
JN		 1864 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1865
4be73780 1866 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 1867}
1868
ecff4f3b 1869static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 1870{
1871 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1872 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1873
1874 if (dport->port == PORT_A)
1875 ironlake_edp_pll_on(intel_dp);
1876}
1877
1878static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1879{
2bd2ad64 1880 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1881 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1882 struct drm_device *dev = encoder->base.dev;
89b667f8 1883 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 1884 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 1885 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 1886 int pipe = intel_crtc->pipe;
bf13e81b 1887 struct edp_power_seq power_seq;
ab1f90f9 1888 u32 val;
a4fc5ed6 1889
ab1f90f9 1890 mutex_lock(&dev_priv->dpio_lock);
89b667f8 1891
ab3c759a 1892 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 1893 val = 0;
1894 if (pipe)
1895 val |= (1<<21);
1896 else
1897 val &= ~(1<<21);
1898 val |= 0x001000c4;
ab3c759a
CML		 1899 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1900 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1901 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 1902
ab1f90f9
JN		 1903 mutex_unlock(&dev_priv->dpio_lock);
1904
2cac613b
ID		 1905 if (is_edp(intel_dp)) {
1906 /* init power sequencer on this pipe and port */
1907 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1908 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1909 &power_seq);
1910 }
bf13e81b 1911
ab1f90f9
JN		 1912 intel_enable_dp(encoder);
1913
e4607fcf 1914 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 1915}
1916
ecff4f3b 1917static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 1918{
1919 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1920 struct drm_device *dev = encoder->base.dev;
1921 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 1922 struct intel_crtc *intel_crtc =
1923 to_intel_crtc(encoder->base.crtc);
e4607fcf 1924 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 1925 int pipe = intel_crtc->pipe;
89b667f8 1926
89b667f8 1927 /* Program Tx lane resets to default */
0980a60f 1928 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 1929 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 1930 DPIO_PCS_TX_LANE2_RESET |
1931 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 1932 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 1933 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1934 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1935 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1936 DPIO_PCS_CLK_SOFT_RESET);
1937
1938 /* Fix up inter-pair skew failure */
ab3c759a
CML		 1939 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1940 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1941 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 1942 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 1943}
1944
1945/*
df0c237d
JB		 1946 * Native read with retry for link status and receiver capability reads for
1947 * cases where the sink may still be asleep.
9d1a1031
JN		 1948 *
1949 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
1950 * supposed to retry 3 times per the spec.
a4fc5ed6 1951 */
9d1a1031
JN		 1952static ssize_t
1953intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
1954 void *buffer, size_t size)
a4fc5ed6 1955{
9d1a1031
JN		 1956 ssize_t ret;
1957 int i;
61da5fab 1958
61da5fab 1959 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1960 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
1961 if (ret == size)
1962 return ret;
61da5fab
JB		 1963 msleep(1);
1964 }
a4fc5ed6 1965
9d1a1031 1966 return ret;
a4fc5ed6
KP		 1967}
1968
1969/*
1970 * Fetch AUX CH registers 0x202 - 0x207 which contain
1971 * link status information
1972 */
1973static bool
93f62dad 1974intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1975{
9d1a1031
JN		 1976 return intel_dp_dpcd_read_wake(&intel_dp->aux,
1977 DP_LANE0_1_STATUS,
1978 link_status,
1979 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 1980}
1981
a4fc5ed6
KP		 1982/*
1983 * These are source-specific values; current Intel hardware supports
1984 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1985 */
a4fc5ed6
KP		 1986
1987static uint8_t
1a2eb460 1988intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1989{
30add22d 1990 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1991 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1992
8f93f4f1 1993 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
e2fa6fba 1994 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 1995 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 1996 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 1997 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 1998 return DP_TRAIN_VOLTAGE_SWING_1200;
1999 else
2000 return DP_TRAIN_VOLTAGE_SWING_800;
2001}
2002
2003static uint8_t
2004intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2005{
30add22d 2006 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2007 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2008
8f93f4f1
PZ		 2009 if (IS_BROADWELL(dev)) {
2010 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2011 case DP_TRAIN_VOLTAGE_SWING_400:
2012 case DP_TRAIN_VOLTAGE_SWING_600:
2013 return DP_TRAIN_PRE_EMPHASIS_6;
2014 case DP_TRAIN_VOLTAGE_SWING_800:
2015 return DP_TRAIN_PRE_EMPHASIS_3_5;
2016 case DP_TRAIN_VOLTAGE_SWING_1200:
2017 default:
2018 return DP_TRAIN_PRE_EMPHASIS_0;
2019 }
2020 } else if (IS_HASWELL(dev)) {
d6c0d722
PZ		 2021 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2022 case DP_TRAIN_VOLTAGE_SWING_400:
2023 return DP_TRAIN_PRE_EMPHASIS_9_5;
2024 case DP_TRAIN_VOLTAGE_SWING_600:
2025 return DP_TRAIN_PRE_EMPHASIS_6;
2026 case DP_TRAIN_VOLTAGE_SWING_800:
2027 return DP_TRAIN_PRE_EMPHASIS_3_5;
2028 case DP_TRAIN_VOLTAGE_SWING_1200:
2029 default:
2030 return DP_TRAIN_PRE_EMPHASIS_0;
2031 }
e2fa6fba
P		 2032 } else if (IS_VALLEYVIEW(dev)) {
2033 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2034 case DP_TRAIN_VOLTAGE_SWING_400:
2035 return DP_TRAIN_PRE_EMPHASIS_9_5;
2036 case DP_TRAIN_VOLTAGE_SWING_600:
2037 return DP_TRAIN_PRE_EMPHASIS_6;
2038 case DP_TRAIN_VOLTAGE_SWING_800:
2039 return DP_TRAIN_PRE_EMPHASIS_3_5;
2040 case DP_TRAIN_VOLTAGE_SWING_1200:
2041 default:
2042 return DP_TRAIN_PRE_EMPHASIS_0;
2043 }
bc7d38a4 2044 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2045 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2046 case DP_TRAIN_VOLTAGE_SWING_400:
2047 return DP_TRAIN_PRE_EMPHASIS_6;
2048 case DP_TRAIN_VOLTAGE_SWING_600:
2049 case DP_TRAIN_VOLTAGE_SWING_800:
2050 return DP_TRAIN_PRE_EMPHASIS_3_5;
2051 default:
2052 return DP_TRAIN_PRE_EMPHASIS_0;
2053 }
2054 } else {
2055 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2056 case DP_TRAIN_VOLTAGE_SWING_400:
2057 return DP_TRAIN_PRE_EMPHASIS_6;
2058 case DP_TRAIN_VOLTAGE_SWING_600:
2059 return DP_TRAIN_PRE_EMPHASIS_6;
2060 case DP_TRAIN_VOLTAGE_SWING_800:
2061 return DP_TRAIN_PRE_EMPHASIS_3_5;
2062 case DP_TRAIN_VOLTAGE_SWING_1200:
2063 default:
2064 return DP_TRAIN_PRE_EMPHASIS_0;
2065 }
a4fc5ed6
KP		 2066 }
2067}
2068
e2fa6fba
P		 2069static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2070{
2071 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2072 struct drm_i915_private *dev_priv = dev->dev_private;
2073 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2074 struct intel_crtc *intel_crtc =
2075 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2076 unsigned long demph_reg_value, preemph_reg_value,
2077 uniqtranscale_reg_value;
2078 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2079 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2080 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2081
2082 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2083 case DP_TRAIN_PRE_EMPHASIS_0:
2084 preemph_reg_value = 0x0004000;
2085 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2086 case DP_TRAIN_VOLTAGE_SWING_400:
2087 demph_reg_value = 0x2B405555;
2088 uniqtranscale_reg_value = 0x552AB83A;
2089 break;
2090 case DP_TRAIN_VOLTAGE_SWING_600:
2091 demph_reg_value = 0x2B404040;
2092 uniqtranscale_reg_value = 0x5548B83A;
2093 break;
2094 case DP_TRAIN_VOLTAGE_SWING_800:
2095 demph_reg_value = 0x2B245555;
2096 uniqtranscale_reg_value = 0x5560B83A;
2097 break;
2098 case DP_TRAIN_VOLTAGE_SWING_1200:
2099 demph_reg_value = 0x2B405555;
2100 uniqtranscale_reg_value = 0x5598DA3A;
2101 break;
2102 default:
2103 return 0;
2104 }
2105 break;
2106 case DP_TRAIN_PRE_EMPHASIS_3_5:
2107 preemph_reg_value = 0x0002000;
2108 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2109 case DP_TRAIN_VOLTAGE_SWING_400:
2110 demph_reg_value = 0x2B404040;
2111 uniqtranscale_reg_value = 0x5552B83A;
2112 break;
2113 case DP_TRAIN_VOLTAGE_SWING_600:
2114 demph_reg_value = 0x2B404848;
2115 uniqtranscale_reg_value = 0x5580B83A;
2116 break;
2117 case DP_TRAIN_VOLTAGE_SWING_800:
2118 demph_reg_value = 0x2B404040;
2119 uniqtranscale_reg_value = 0x55ADDA3A;
2120 break;
2121 default:
2122 return 0;
2123 }
2124 break;
2125 case DP_TRAIN_PRE_EMPHASIS_6:
2126 preemph_reg_value = 0x0000000;
2127 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2128 case DP_TRAIN_VOLTAGE_SWING_400:
2129 demph_reg_value = 0x2B305555;
2130 uniqtranscale_reg_value = 0x5570B83A;
2131 break;
2132 case DP_TRAIN_VOLTAGE_SWING_600:
2133 demph_reg_value = 0x2B2B4040;
2134 uniqtranscale_reg_value = 0x55ADDA3A;
2135 break;
2136 default:
2137 return 0;
2138 }
2139 break;
2140 case DP_TRAIN_PRE_EMPHASIS_9_5:
2141 preemph_reg_value = 0x0006000;
2142 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2143 case DP_TRAIN_VOLTAGE_SWING_400:
2144 demph_reg_value = 0x1B405555;
2145 uniqtranscale_reg_value = 0x55ADDA3A;
2146 break;
2147 default:
2148 return 0;
2149 }
2150 break;
2151 default:
2152 return 0;
2153 }
2154
0980a60f 2155 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2156 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2157 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2158 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2159 uniqtranscale_reg_value);
ab3c759a
CML		 2160 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2161 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2162 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2163 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2164 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2165
2166 return 0;
2167}
2168
a4fc5ed6 2169static void
0301b3ac
JN		 2170intel_get_adjust_train(struct intel_dp *intel_dp,
2171 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2172{
2173 uint8_t v = 0;
2174 uint8_t p = 0;
2175 int lane;
1a2eb460
KP		 2176 uint8_t voltage_max;
2177 uint8_t preemph_max;
a4fc5ed6 2178
33a34e4e 2179 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2180 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2181 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2182
2183 if (this_v > v)
2184 v = this_v;
2185 if (this_p > p)
2186 p = this_p;
2187 }
2188
1a2eb460 2189 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2190 if (v >= voltage_max)
2191 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2192
1a2eb460
KP		 2193 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2194 if (p >= preemph_max)
2195 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2196
2197 for (lane = 0; lane < 4; lane++)
33a34e4e 2198 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2199}
2200
2201static uint32_t
f0a3424e 2202intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2203{
3cf2efb1 2204 uint32_t signal_levels = 0;
a4fc5ed6 2205
3cf2efb1 2206 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2207 case DP_TRAIN_VOLTAGE_SWING_400:
2208 default:
2209 signal_levels |= DP_VOLTAGE_0_4;
2210 break;
2211 case DP_TRAIN_VOLTAGE_SWING_600:
2212 signal_levels |= DP_VOLTAGE_0_6;
2213 break;
2214 case DP_TRAIN_VOLTAGE_SWING_800:
2215 signal_levels |= DP_VOLTAGE_0_8;
2216 break;
2217 case DP_TRAIN_VOLTAGE_SWING_1200:
2218 signal_levels |= DP_VOLTAGE_1_2;
2219 break;
2220 }
3cf2efb1 2221 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2222 case DP_TRAIN_PRE_EMPHASIS_0:
2223 default:
2224 signal_levels |= DP_PRE_EMPHASIS_0;
2225 break;
2226 case DP_TRAIN_PRE_EMPHASIS_3_5:
2227 signal_levels |= DP_PRE_EMPHASIS_3_5;
2228 break;
2229 case DP_TRAIN_PRE_EMPHASIS_6:
2230 signal_levels |= DP_PRE_EMPHASIS_6;
2231 break;
2232 case DP_TRAIN_PRE_EMPHASIS_9_5:
2233 signal_levels |= DP_PRE_EMPHASIS_9_5;
2234 break;
2235 }
2236 return signal_levels;
2237}
2238
e3421a18
ZW		 2239/* Gen6's DP voltage swing and pre-emphasis control */
2240static uint32_t
2241intel_gen6_edp_signal_levels(uint8_t train_set)
2242{
3c5a62b5
YL		 2243 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2244 DP_TRAIN_PRE_EMPHASIS_MASK);
2245 switch (signal_levels) {
e3421a18 2246 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2247 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2248 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2249 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2250 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2251 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2252 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2253 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2254 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2255 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2256 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2257 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2258 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2259 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2260 default:
3c5a62b5
YL		 2261 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2262 "0x%x\n", signal_levels);
2263 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2264 }
2265}
2266
1a2eb460
KP		 2267/* Gen7's DP voltage swing and pre-emphasis control */
2268static uint32_t
2269intel_gen7_edp_signal_levels(uint8_t train_set)
2270{
2271 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2272 DP_TRAIN_PRE_EMPHASIS_MASK);
2273 switch (signal_levels) {
2274 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2275 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2276 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2277 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2278 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2279 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2280
2281 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2282 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2283 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2284 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2285
2286 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2287 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2288 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2289 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2290
2291 default:
2292 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2293 "0x%x\n", signal_levels);
2294 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2295 }
2296}
2297
d6c0d722
PZ		 2298/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2299static uint32_t
f0a3424e 2300intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2301{
d6c0d722
PZ		 2302 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2303 DP_TRAIN_PRE_EMPHASIS_MASK);
2304 switch (signal_levels) {
2305 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2306 return DDI_BUF_EMP_400MV_0DB_HSW;
2307 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2308 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2309 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2310 return DDI_BUF_EMP_400MV_6DB_HSW;
2311 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2312 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2313
d6c0d722
PZ		 2314 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2315 return DDI_BUF_EMP_600MV_0DB_HSW;
2316 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2317 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2318 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2319 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2320
d6c0d722
PZ		 2321 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2322 return DDI_BUF_EMP_800MV_0DB_HSW;
2323 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2324 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2325 default:
2326 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2327 "0x%x\n", signal_levels);
2328 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2329 }
a4fc5ed6
KP		 2330}
2331
8f93f4f1
PZ		 2332static uint32_t
2333intel_bdw_signal_levels(uint8_t train_set)
2334{
2335 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2336 DP_TRAIN_PRE_EMPHASIS_MASK);
2337 switch (signal_levels) {
2338 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2339 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2340 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2341 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2342 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2343 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2344
2345 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2346 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2347 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2348 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2349 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2350 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2351
2352 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2353 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2354 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2355 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2356
2357 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2358 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2359
2360 default:
2361 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2362 "0x%x\n", signal_levels);
2363 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2364 }
2365}
2366
f0a3424e
PZ		 2367/* Properly updates "DP" with the correct signal levels. */
2368static void
2369intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2370{
2371 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2372 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2373 struct drm_device *dev = intel_dig_port->base.base.dev;
2374 uint32_t signal_levels, mask;
2375 uint8_t train_set = intel_dp->train_set[0];
2376
8f93f4f1
PZ		 2377 if (IS_BROADWELL(dev)) {
2378 signal_levels = intel_bdw_signal_levels(train_set);
2379 mask = DDI_BUF_EMP_MASK;
2380 } else if (IS_HASWELL(dev)) {
f0a3424e
PZ		 2381 signal_levels = intel_hsw_signal_levels(train_set);
2382 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 2383 } else if (IS_VALLEYVIEW(dev)) {
2384 signal_levels = intel_vlv_signal_levels(intel_dp);
2385 mask = 0;
bc7d38a4 2386 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2387 signal_levels = intel_gen7_edp_signal_levels(train_set);
2388 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2389 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2390 signal_levels = intel_gen6_edp_signal_levels(train_set);
2391 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2392 } else {
2393 signal_levels = intel_gen4_signal_levels(train_set);
2394 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2395 }
2396
2397 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2398
2399 *DP = (*DP & ~mask) | signal_levels;
2400}
2401
a4fc5ed6 2402static bool
ea5b213a 2403intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2404 uint32_t *DP,
58e10eb9 2405 uint8_t dp_train_pat)
a4fc5ed6 2406{
174edf1f
PZ		 2407 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2408 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2409 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2410 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2411 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2412 int ret, len;
a4fc5ed6 2413
22b8bf17 2414 if (HAS_DDI(dev)) {
3ab9c637 2415 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2416
2417 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2418 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2419 else
2420 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2421
2422 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2423 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2424 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2425 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2426
2427 break;
2428 case DP_TRAINING_PATTERN_1:
2429 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2430 break;
2431 case DP_TRAINING_PATTERN_2:
2432 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2433 break;
2434 case DP_TRAINING_PATTERN_3:
2435 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2436 break;
2437 }
174edf1f 2438 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2439
bc7d38a4 2440 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2441 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2442
2443 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2444 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2445 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2446 break;
2447 case DP_TRAINING_PATTERN_1:
70aff66c 2448 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2449 break;
2450 case DP_TRAINING_PATTERN_2:
70aff66c 2451 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2452 break;
2453 case DP_TRAINING_PATTERN_3:
2454 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2455 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2456 break;
2457 }
2458
2459 } else {
70aff66c 2460 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2461
2462 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2463 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2464 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2465 break;
2466 case DP_TRAINING_PATTERN_1:
70aff66c 2467 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2468 break;
2469 case DP_TRAINING_PATTERN_2:
70aff66c 2470 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2471 break;
2472 case DP_TRAINING_PATTERN_3:
2473 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2474 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2475 break;
2476 }
2477 }
2478
70aff66c 2479 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 2480 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2481
2cdfe6c8
JN		 2482 buf[0] = dp_train_pat;
2483 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 2484 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 2485 /* don't write DP_TRAINING_LANEx_SET on disable */
2486 len = 1;
2487 } else {
2488 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2489 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2490 len = intel_dp->lane_count + 1;
47ea7542 2491 }
a4fc5ed6 2492
9d1a1031
JN		 2493 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
2494 buf, len);
2cdfe6c8
JN		 2495
2496 return ret == len;
a4fc5ed6
KP		 2497}
2498
70aff66c
JN		 2499static bool
2500intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2501 uint8_t dp_train_pat)
2502{
953d22e8 2503 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 2504 intel_dp_set_signal_levels(intel_dp, DP);
2505 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2506}
2507
2508static bool
2509intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 2510 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 2511{
2512 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2513 struct drm_device *dev = intel_dig_port->base.base.dev;
2514 struct drm_i915_private *dev_priv = dev->dev_private;
2515 int ret;
2516
2517 intel_get_adjust_train(intel_dp, link_status);
2518 intel_dp_set_signal_levels(intel_dp, DP);
2519
2520 I915_WRITE(intel_dp->output_reg, *DP);
2521 POSTING_READ(intel_dp->output_reg);
2522
9d1a1031
JN		 2523 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
2524 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 2525
2526 return ret == intel_dp->lane_count;
2527}
2528
3ab9c637
ID		 2529static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2530{
2531 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2532 struct drm_device *dev = intel_dig_port->base.base.dev;
2533 struct drm_i915_private *dev_priv = dev->dev_private;
2534 enum port port = intel_dig_port->port;
2535 uint32_t val;
2536
2537 if (!HAS_DDI(dev))
2538 return;
2539
2540 val = I915_READ(DP_TP_CTL(port));
2541 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2542 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2543 I915_WRITE(DP_TP_CTL(port), val);
2544
2545 /*
2546 * On PORT_A we can have only eDP in SST mode. There the only reason
2547 * we need to set idle transmission mode is to work around a HW issue
2548 * where we enable the pipe while not in idle link-training mode.
2549 * In this case there is requirement to wait for a minimum number of
2550 * idle patterns to be sent.
2551 */
2552 if (port == PORT_A)
2553 return;
2554
2555 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2556 1))
2557 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2558}
2559
33a34e4e 2560/* Enable corresponding port and start training pattern 1 */
c19b0669 2561void
33a34e4e 2562intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2563{
da63a9f2 2564 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2565 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2566 int i;
2567 uint8_t voltage;
cdb0e95b 2568 int voltage_tries, loop_tries;
ea5b213a 2569 uint32_t DP = intel_dp->DP;
6aba5b6c 2570 uint8_t link_config[2];
a4fc5ed6 2571
affa9354 2572 if (HAS_DDI(dev))
c19b0669
PZ		 2573 intel_ddi_prepare_link_retrain(encoder);
2574
3cf2efb1 2575 /* Write the link configuration data */
6aba5b6c
JN		 2576 link_config[0] = intel_dp->link_bw;
2577 link_config[1] = intel_dp->lane_count;
2578 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2579 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 2580 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 2581
2582 link_config[0] = 0;
2583 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 2584 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 2585
2586 DP |= DP_PORT_EN;
1a2eb460 2587
70aff66c
JN		 2588 /* clock recovery */
2589 if (!intel_dp_reset_link_train(intel_dp, &DP,
2590 DP_TRAINING_PATTERN_1 |
2591 DP_LINK_SCRAMBLING_DISABLE)) {
2592 DRM_ERROR("failed to enable link training\n");
2593 return;
2594 }
2595
a4fc5ed6 2596 voltage = 0xff;
cdb0e95b
KP		 2597 voltage_tries = 0;
2598 loop_tries = 0;
a4fc5ed6 2599 for (;;) {
70aff66c 2600 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 2601
a7c9655f 2602 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2603 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2604 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2605 break;
93f62dad 2606 }
a4fc5ed6 2607
01916270 2608 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2609 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2610 break;
2611 }
2612
2613 /* Check to see if we've tried the max voltage */
2614 for (i = 0; i < intel_dp->lane_count; i++)
2615 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2616 break;
3b4f819d 2617 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2618 ++loop_tries;
2619 if (loop_tries == 5) {
3def84b3 2620 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 2621 break;
2622 }
70aff66c
JN		 2623 intel_dp_reset_link_train(intel_dp, &DP,
2624 DP_TRAINING_PATTERN_1 |
2625 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 2626 voltage_tries = 0;
2627 continue;
2628 }
a4fc5ed6 2629
3cf2efb1 2630 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2631 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2632 ++voltage_tries;
b06fbda3 2633 if (voltage_tries == 5) {
3def84b3 2634 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 2635 break;
2636 }
2637 } else
2638 voltage_tries = 0;
2639 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2640
70aff66c
JN		 2641 /* Update training set as requested by target */
2642 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2643 DRM_ERROR("failed to update link training\n");
2644 break;
2645 }
a4fc5ed6
KP		 2646 }
2647
33a34e4e
JB		 2648 intel_dp->DP = DP;
2649}
2650
c19b0669 2651void
33a34e4e
JB		 2652intel_dp_complete_link_train(struct intel_dp *intel_dp)
2653{
33a34e4e 2654 bool channel_eq = false;
37f80975 2655 int tries, cr_tries;
33a34e4e 2656 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 2657 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2658
2659 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2660 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2661 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 2662
a4fc5ed6 2663 /* channel equalization */
70aff66c 2664 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2665 training_pattern |
70aff66c
JN		 2666 DP_LINK_SCRAMBLING_DISABLE)) {
2667 DRM_ERROR("failed to start channel equalization\n");
2668 return;
2669 }
2670
a4fc5ed6 2671 tries = 0;
37f80975 2672 cr_tries = 0;
a4fc5ed6
KP		 2673 channel_eq = false;
2674 for (;;) {
70aff66c 2675 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2676
37f80975
JB		 2677 if (cr_tries > 5) {
2678 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 2679 break;
2680 }
2681
a7c9655f 2682 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 2683 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2684 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2685 break;
70aff66c 2686 }
a4fc5ed6 2687
37f80975 2688 /* Make sure clock is still ok */
01916270 2689 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 2690 intel_dp_start_link_train(intel_dp);
70aff66c 2691 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2692 training_pattern |
70aff66c 2693 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2694 cr_tries++;
2695 continue;
2696 }
2697
1ffdff13 2698 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2699 channel_eq = true;
2700 break;
2701 }
a4fc5ed6 2702
37f80975
JB		 2703 /* Try 5 times, then try clock recovery if that fails */
2704 if (tries > 5) {
2705 intel_dp_link_down(intel_dp);
2706 intel_dp_start_link_train(intel_dp);
70aff66c 2707 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2708 training_pattern |
70aff66c 2709 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2710 tries = 0;
2711 cr_tries++;
2712 continue;
2713 }
a4fc5ed6 2714
70aff66c
JN		 2715 /* Update training set as requested by target */
2716 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2717 DRM_ERROR("failed to update link training\n");
2718 break;
2719 }
3cf2efb1 2720 ++tries;
869184a6 2721 }
3cf2efb1 2722
3ab9c637
ID		 2723 intel_dp_set_idle_link_train(intel_dp);
2724
2725 intel_dp->DP = DP;
2726
d6c0d722 2727 if (channel_eq)
07f42258 2728 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2729
3ab9c637
ID		 2730}
2731
2732void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2733{
70aff66c 2734 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 2735 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2736}
2737
2738static void
ea5b213a 2739intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2740{
da63a9f2 2741 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2742 enum port port = intel_dig_port->port;
da63a9f2 2743 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2744 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2745 struct intel_crtc *intel_crtc =
2746 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2747 uint32_t DP = intel_dp->DP;
a4fc5ed6 2748
c19b0669
PZ		 2749 /*
2750 * DDI code has a strict mode set sequence and we should try to respect
2751 * it, otherwise we might hang the machine in many different ways. So we
2752 * really should be disabling the port only on a complete crtc_disable
2753 * sequence. This function is just called under two conditions on DDI
2754 * code:
2755 * - Link train failed while doing crtc_enable, and on this case we
2756 * really should respect the mode set sequence and wait for a
2757 * crtc_disable.
2758 * - Someone turned the monitor off and intel_dp_check_link_status
2759 * called us. We don't need to disable the whole port on this case, so
2760 * when someone turns the monitor on again,
2761 * intel_ddi_prepare_link_retrain will take care of redoing the link
2762 * train.
2763 */
affa9354 2764 if (HAS_DDI(dev))
c19b0669
PZ		 2765 return;
2766
0c33d8d7 2767 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2768 return;
2769
28c97730 2770 DRM_DEBUG_KMS("\n");
32f9d658 2771
bc7d38a4 2772 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 2773 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2774 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2775 } else {
2776 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2777 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2778 }
fe255d00 2779 POSTING_READ(intel_dp->output_reg);
5eb08b69 2780
ab527efc
DV		 2781 /* We don't really know why we're doing this */
2782 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2783
493a7081 2784 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2785 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2786 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2787
5bddd17f
EA		 2788 /* Hardware workaround: leaving our transcoder select
2789 * set to transcoder B while it's off will prevent the
2790 * corresponding HDMI output on transcoder A.
2791 *
2792 * Combine this with another hardware workaround:
2793 * transcoder select bit can only be cleared while the
2794 * port is enabled.
2795 */
2796 DP &= ~DP_PIPEB_SELECT;
2797 I915_WRITE(intel_dp->output_reg, DP);
2798
2799 /* Changes to enable or select take place the vblank
2800 * after being written.
2801 */
ff50afe9
DV		 2802 if (WARN_ON(crtc == NULL)) {
2803 /* We should never try to disable a port without a crtc
2804 * attached. For paranoia keep the code around for a
2805 * bit. */
31acbcc4
CW		 2806 POSTING_READ(intel_dp->output_reg);
2807 msleep(50);
2808 } else
ab527efc 2809 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2810 }
2811
832afda6 2812 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2813 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2814 POSTING_READ(intel_dp->output_reg);
f01eca2e 2815 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2816}
2817
26d61aad
KP		 2818static bool
2819intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2820{
a031d709
RV		 2821 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2822 struct drm_device *dev = dig_port->base.base.dev;
2823 struct drm_i915_private *dev_priv = dev->dev_private;
2824
577c7a50
DL		 2825 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2826
9d1a1031
JN		 2827 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
2828 sizeof(intel_dp->dpcd)) < 0)
edb39244 2829 return false; /* aux transfer failed */
92fd8fd1 2830
577c7a50
DL		 2831 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2832 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2833 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2834
edb39244
AJ		 2835 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2836 return false; /* DPCD not present */
2837
2293bb5c
SK		 2838 /* Check if the panel supports PSR */
2839 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 2840 if (is_edp(intel_dp)) {
9d1a1031
JN		 2841 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
2842 intel_dp->psr_dpcd,
2843 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 2844 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2845 dev_priv->psr.sink_support = true;
50003939 2846 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 2847 }
50003939
JN		 2848 }
2849
06ea66b6
TP		 2850 /* Training Pattern 3 support */
2851 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
2852 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
2853 intel_dp->use_tps3 = true;
2854 DRM_DEBUG_KMS("Displayport TPS3 supported");
2855 } else
2856 intel_dp->use_tps3 = false;
2857
edb39244
AJ		 2858 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2859 DP_DWN_STRM_PORT_PRESENT))
2860 return true; /* native DP sink */
2861
2862 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2863 return true; /* no per-port downstream info */
2864
9d1a1031
JN		 2865 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
2866 intel_dp->downstream_ports,
2867 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 2868 return false; /* downstream port status fetch failed */
2869
2870 return true;
92fd8fd1
KP		 2871}
2872
0d198328
AJ		 2873static void
2874intel_dp_probe_oui(struct intel_dp *intel_dp)
2875{
2876 u8 buf[3];
2877
2878 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2879 return;
2880
24f3e092 2881 intel_edp_panel_vdd_on(intel_dp);
351cfc34 2882
9d1a1031 2883 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 2884 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2885 buf[0], buf[1], buf[2]);
2886
9d1a1031 2887 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 2888 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2889 buf[0], buf[1], buf[2]);
351cfc34 2890
4be73780 2891 edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2892}
2893
d2e216d0
RV		 2894int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
2895{
2896 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2897 struct drm_device *dev = intel_dig_port->base.base.dev;
2898 struct intel_crtc *intel_crtc =
2899 to_intel_crtc(intel_dig_port->base.base.crtc);
2900 u8 buf[1];
2901
9d1a1031 2902 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 2903 return -EAGAIN;
2904
2905 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
2906 return -ENOTTY;
2907
9d1a1031
JN		 2908 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
2909 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 2910 return -EAGAIN;
2911
2912 /* Wait 2 vblanks to be sure we will have the correct CRC value */
2913 intel_wait_for_vblank(dev, intel_crtc->pipe);
2914 intel_wait_for_vblank(dev, intel_crtc->pipe);
2915
9d1a1031 2916 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 2917 return -EAGAIN;
2918
9d1a1031 2919 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 2920 return 0;
2921}
2922
a60f0e38
JB		 2923static bool
2924intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2925{
9d1a1031
JN		 2926 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2927 DP_DEVICE_SERVICE_IRQ_VECTOR,
2928 sink_irq_vector, 1) == 1;
a60f0e38
JB		 2929}
2930
2931static void
2932intel_dp_handle_test_request(struct intel_dp *intel_dp)
2933{
2934 /* NAK by default */
9d1a1031 2935 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2936}
2937
a4fc5ed6
KP		 2938/*
2939 * According to DP spec
2940 * 5.1.2:
2941 * 1. Read DPCD
2942 * 2. Configure link according to Receiver Capabilities
2943 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2944 * 4. Check link status on receipt of hot-plug interrupt
2945 */
2946
00c09d70 2947void
ea5b213a 2948intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2949{
da63a9f2 2950 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2951 u8 sink_irq_vector;
93f62dad 2952 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2953
da63a9f2 2954 if (!intel_encoder->connectors_active)
d2b996ac 2955 return;
59cd09e1 2956
da63a9f2 2957 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2958 return;
2959
92fd8fd1 2960 /* Try to read receiver status if the link appears to be up */
93f62dad 2961 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 2962 return;
2963 }
2964
92fd8fd1 2965 /* Now read the DPCD to see if it's actually running */
26d61aad 2966 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2967 return;
2968 }
2969
a60f0e38
JB		 2970 /* Try to read the source of the interrupt */
2971 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2972 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2973 /* Clear interrupt source */
9d1a1031
JN		 2974 drm_dp_dpcd_writeb(&intel_dp->aux,
2975 DP_DEVICE_SERVICE_IRQ_VECTOR,
2976 sink_irq_vector);
a60f0e38
JB		 2977
2978 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2979 intel_dp_handle_test_request(intel_dp);
2980 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2981 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2982 }
2983
1ffdff13 2984 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2985 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2986 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2987 intel_dp_start_link_train(intel_dp);
2988 intel_dp_complete_link_train(intel_dp);
3ab9c637 2989 intel_dp_stop_link_train(intel_dp);
33a34e4e 2990 }
a4fc5ed6 2991}
a4fc5ed6 2992
caf9ab24 2993/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2994static enum drm_connector_status
26d61aad 2995intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2996{
caf9ab24 2997 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 2998 uint8_t type;
2999
3000 if (!intel_dp_get_dpcd(intel_dp))
3001 return connector_status_disconnected;
3002
3003 /* if there's no downstream port, we're done */
3004 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3005 return connector_status_connected;
caf9ab24
AJ		 3006
3007 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3008 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3009 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3010 uint8_t reg;
9d1a1031
JN		 3011
3012 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3013 &reg, 1) < 0)
caf9ab24 3014 return connector_status_unknown;
9d1a1031 3015
23235177
AJ		 3016 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3017 : connector_status_disconnected;
caf9ab24
AJ		 3018 }
3019
3020 /* If no HPD, poke DDC gently */
0b99836f 3021 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3022 return connector_status_connected;
caf9ab24
AJ		 3023
3024 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3025 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3026 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3027 if (type == DP_DS_PORT_TYPE_VGA ||
3028 type == DP_DS_PORT_TYPE_NON_EDID)
3029 return connector_status_unknown;
3030 } else {
3031 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3032 DP_DWN_STRM_PORT_TYPE_MASK;
3033 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3034 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3035 return connector_status_unknown;
3036 }
caf9ab24
AJ		 3037
3038 /* Anything else is out of spec, warn and ignore */
3039 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3040 return connector_status_disconnected;
71ba9000
AJ		 3041}
3042
5eb08b69 3043static enum drm_connector_status
a9756bb5 3044ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3045{
30add22d 3046 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3047 struct drm_i915_private *dev_priv = dev->dev_private;
3048 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 3049 enum drm_connector_status status;
3050
fe16d949
CW		 3051 /* Can't disconnect eDP, but you can close the lid... */
3052 if (is_edp(intel_dp)) {
30add22d 3053 status = intel_panel_detect(dev);
fe16d949
CW		 3054 if (status == connector_status_unknown)
3055 status = connector_status_connected;
3056 return status;
3057 }
01cb9ea6 3058
1b469639
DL		 3059 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3060 return connector_status_disconnected;
3061
26d61aad 3062 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3063}
3064
a4fc5ed6 3065static enum drm_connector_status
a9756bb5 3066g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3067{
30add22d 3068 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3069 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3070 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3071 uint32_t bit;
5eb08b69 3072
35aad75f
JB		 3073 /* Can't disconnect eDP, but you can close the lid... */
3074 if (is_edp(intel_dp)) {
3075 enum drm_connector_status status;
3076
3077 status = intel_panel_detect(dev);
3078 if (status == connector_status_unknown)
3079 status = connector_status_connected;
3080 return status;
3081 }
3082
232a6ee9
TP		 3083 if (IS_VALLEYVIEW(dev)) {
3084 switch (intel_dig_port->port) {
3085 case PORT_B:
3086 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3087 break;
3088 case PORT_C:
3089 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3090 break;
3091 case PORT_D:
3092 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3093 break;
3094 default:
3095 return connector_status_unknown;
3096 }
3097 } else {
3098 switch (intel_dig_port->port) {
3099 case PORT_B:
3100 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3101 break;
3102 case PORT_C:
3103 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3104 break;
3105 case PORT_D:
3106 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3107 break;
3108 default:
3109 return connector_status_unknown;
3110 }
a4fc5ed6
KP		 3111 }
3112
10f76a38 3113 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3114 return connector_status_disconnected;
3115
26d61aad 3116 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3117}
3118
8c241fef
KP		 3119static struct edid *
3120intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3121{
9cd300e0 3122 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3123
9cd300e0
JN		 3124 /* use cached edid if we have one */
3125 if (intel_connector->edid) {
9cd300e0
JN		 3126 /* invalid edid */
3127 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3128 return NULL;
3129
55e9edeb 3130 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3131 }
8c241fef 3132
9cd300e0 3133 return drm_get_edid(connector, adapter);
8c241fef
KP		 3134}
3135
3136static int
3137intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3138{
9cd300e0 3139 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3140
9cd300e0
JN		 3141 /* use cached edid if we have one */
3142 if (intel_connector->edid) {
3143 /* invalid edid */
3144 if (IS_ERR(intel_connector->edid))
3145 return 0;
3146
3147 return intel_connector_update_modes(connector,
3148 intel_connector->edid);
d6f24d0f
JB		 3149 }
3150
9cd300e0 3151 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3152}
3153
a9756bb5
ZW		 3154static enum drm_connector_status
3155intel_dp_detect(struct drm_connector *connector, bool force)
3156{
3157 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3158 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3159 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3160 struct drm_device *dev = connector->dev;
c8c8fb33 3161 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 3162 enum drm_connector_status status;
671dedd2 3163 enum intel_display_power_domain power_domain;
a9756bb5
ZW		 3164 struct edid *edid = NULL;
3165
c8c8fb33
PZ		 3166 intel_runtime_pm_get(dev_priv);
3167
671dedd2
ID		 3168 power_domain = intel_display_port_power_domain(intel_encoder);
3169 intel_display_power_get(dev_priv, power_domain);
3170
164c8598
CW		 3171 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3172 connector->base.id, drm_get_connector_name(connector));
3173
a9756bb5
ZW		 3174 intel_dp->has_audio = false;
3175
3176 if (HAS_PCH_SPLIT(dev))
3177 status = ironlake_dp_detect(intel_dp);
3178 else
3179 status = g4x_dp_detect(intel_dp);
1b9be9d0 3180
a9756bb5 3181 if (status != connector_status_connected)
c8c8fb33 3182 goto out;
a9756bb5 3183
0d198328
AJ		 3184 intel_dp_probe_oui(intel_dp);
3185
c3e5f67b
DV		 3186 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3187 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3188 } else {
0b99836f 3189 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
f684960e
CW		 3190 if (edid) {
3191 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3192 kfree(edid);
3193 }
a9756bb5
ZW		 3194 }
3195
d63885da
PZ		 3196 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3197 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3198 status = connector_status_connected;
3199
3200out:
671dedd2
ID		 3201 intel_display_power_put(dev_priv, power_domain);
3202
c8c8fb33 3203 intel_runtime_pm_put(dev_priv);
671dedd2 3204
c8c8fb33 3205 return status;
a4fc5ed6
KP		 3206}
3207
3208static int intel_dp_get_modes(struct drm_connector *connector)
3209{
df0e9248 3210 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3211 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3212 struct intel_encoder *intel_encoder = &intel_dig_port->base;
dd06f90e 3213 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3214 struct drm_device *dev = connector->dev;
671dedd2
ID		 3215 struct drm_i915_private *dev_priv = dev->dev_private;
3216 enum intel_display_power_domain power_domain;
32f9d658 3217 int ret;
a4fc5ed6
KP		 3218
3219 /* We should parse the EDID data and find out if it has an audio sink
3220 */
3221
671dedd2
ID		 3222 power_domain = intel_display_port_power_domain(intel_encoder);
3223 intel_display_power_get(dev_priv, power_domain);
3224
0b99836f 3225 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
671dedd2 3226 intel_display_power_put(dev_priv, power_domain);
f8779fda 3227 if (ret)
32f9d658
ZW		 3228 return ret;
3229
f8779fda 3230 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3231 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3232 struct drm_display_mode *mode;
dd06f90e
JN		 3233 mode = drm_mode_duplicate(dev,
3234 intel_connector->panel.fixed_mode);
f8779fda 3235 if (mode) {
32f9d658
ZW		 3236 drm_mode_probed_add(connector, mode);
3237 return 1;
3238 }
3239 }
3240 return 0;
a4fc5ed6
KP		 3241}
3242
1aad7ac0
CW		 3243static bool
3244intel_dp_detect_audio(struct drm_connector *connector)
3245{
3246 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3247 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3248 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3249 struct drm_device *dev = connector->dev;
3250 struct drm_i915_private *dev_priv = dev->dev_private;
3251 enum intel_display_power_domain power_domain;
1aad7ac0
CW		 3252 struct edid *edid;
3253 bool has_audio = false;
3254
671dedd2
ID		 3255 power_domain = intel_display_port_power_domain(intel_encoder);
3256 intel_display_power_get(dev_priv, power_domain);
3257
0b99836f 3258 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
1aad7ac0
CW		 3259 if (edid) {
3260 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3261 kfree(edid);
3262 }
3263
671dedd2
ID		 3264 intel_display_power_put(dev_priv, power_domain);
3265
1aad7ac0
CW		 3266 return has_audio;
3267}
3268
f684960e
CW		 3269static int
3270intel_dp_set_property(struct drm_connector *connector,
3271 struct drm_property *property,
3272 uint64_t val)
3273{
e953fd7b 3274 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3275 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3276 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3277 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3278 int ret;
3279
662595df 3280 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3281 if (ret)
3282 return ret;
3283
3f43c48d 3284 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3285 int i = val;
3286 bool has_audio;
3287
3288 if (i == intel_dp->force_audio)
f684960e
CW		 3289 return 0;
3290
1aad7ac0 3291 intel_dp->force_audio = i;
f684960e 3292
c3e5f67b 3293 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3294 has_audio = intel_dp_detect_audio(connector);
3295 else
c3e5f67b 3296 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3297
3298 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3299 return 0;
3300
1aad7ac0 3301 intel_dp->has_audio = has_audio;
f684960e
CW		 3302 goto done;
3303 }
3304
e953fd7b 3305 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3306 bool old_auto = intel_dp->color_range_auto;
3307 uint32_t old_range = intel_dp->color_range;
3308
55bc60db
VS		 3309 switch (val) {
3310 case INTEL_BROADCAST_RGB_AUTO:
3311 intel_dp->color_range_auto = true;
3312 break;
3313 case INTEL_BROADCAST_RGB_FULL:
3314 intel_dp->color_range_auto = false;
3315 intel_dp->color_range = 0;
3316 break;
3317 case INTEL_BROADCAST_RGB_LIMITED:
3318 intel_dp->color_range_auto = false;
3319 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3320 break;
3321 default:
3322 return -EINVAL;
3323 }
ae4edb80
DV		 3324
3325 if (old_auto == intel_dp->color_range_auto &&
3326 old_range == intel_dp->color_range)
3327 return 0;
3328
e953fd7b
CW		 3329 goto done;
3330 }
3331
53b41837
YN		 3332 if (is_edp(intel_dp) &&
3333 property == connector->dev->mode_config.scaling_mode_property) {
3334 if (val == DRM_MODE_SCALE_NONE) {
3335 DRM_DEBUG_KMS("no scaling not supported\n");
3336 return -EINVAL;
3337 }
3338
3339 if (intel_connector->panel.fitting_mode == val) {
3340 /* the eDP scaling property is not changed */
3341 return 0;
3342 }
3343 intel_connector->panel.fitting_mode = val;
3344
3345 goto done;
3346 }
3347
f684960e
CW		 3348 return -EINVAL;
3349
3350done:
c0c36b94
CW		 3351 if (intel_encoder->base.crtc)
3352 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3353
3354 return 0;
3355}
3356
a4fc5ed6 3357static void
73845adf 3358intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3359{
1d508706 3360 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3361
9cd300e0
JN		 3362 if (!IS_ERR_OR_NULL(intel_connector->edid))
3363 kfree(intel_connector->edid);
3364
acd8db10
PZ		 3365 /* Can't call is_edp() since the encoder may have been destroyed
3366 * already. */
3367 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3368 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3369
a4fc5ed6 3370 drm_connector_cleanup(connector);
55f78c43 3371 kfree(connector);
a4fc5ed6
KP		 3372}
3373
00c09d70 3374void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3375{
da63a9f2
PZ		 3376 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3377 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3378 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927 3379
0b99836f 3380 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
24d05927 3381 drm_encoder_cleanup(encoder);
bd943159
KP		 3382 if (is_edp(intel_dp)) {
3383 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 3384 mutex_lock(&dev->mode_config.mutex);
4be73780 3385 edp_panel_vdd_off_sync(intel_dp);
bd173813 3386 mutex_unlock(&dev->mode_config.mutex);
bd943159 3387 }
da63a9f2 3388 kfree(intel_dig_port);
24d05927
DV		 3389}
3390
a4fc5ed6 3391static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3392 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3393 .detect = intel_dp_detect,
3394 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3395 .set_property = intel_dp_set_property,
73845adf 3396 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3397};
3398
3399static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3400 .get_modes = intel_dp_get_modes,
3401 .mode_valid = intel_dp_mode_valid,
df0e9248 3402 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3403};
3404
a4fc5ed6 3405static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3406 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3407};
3408
995b6762 3409static void
21d40d37 3410intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3411{
fa90ecef 3412 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3413
885a5014 3414 intel_dp_check_link_status(intel_dp);
c8110e52 3415}
6207937d 3416
e3421a18
ZW		 3417/* Return which DP Port should be selected for Transcoder DP control */
3418int
0206e353 3419intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3420{
3421 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3422 struct intel_encoder *intel_encoder;
3423 struct intel_dp *intel_dp;
e3421a18 3424
fa90ecef
PZ		 3425 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3426 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3427
fa90ecef
PZ		 3428 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3429 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3430 return intel_dp->output_reg;
e3421a18 3431 }
ea5b213a 3432
e3421a18
ZW		 3433 return -1;
3434}
3435
36e83a18 3436/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 3437bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 3438{
3439 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 3440 union child_device_config *p_child;
36e83a18 3441 int i;
5d8a7752
VS		 3442 static const short port_mapping[] = {
3443 [PORT_B] = PORT_IDPB,
3444 [PORT_C] = PORT_IDPC,
3445 [PORT_D] = PORT_IDPD,
3446 };
36e83a18 3447
3b32a35b
VS		 3448 if (port == PORT_A)
3449 return true;
3450
41aa3448 3451 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3452 return false;
3453
41aa3448
RV		 3454 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3455 p_child = dev_priv->vbt.child_dev + i;
36e83a18 3456
5d8a7752 3457 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 3458 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3459 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 3460 return true;
3461 }
3462 return false;
3463}
3464
f684960e
CW		 3465static void
3466intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3467{
53b41837
YN		 3468 struct intel_connector *intel_connector = to_intel_connector(connector);
3469
3f43c48d 3470 intel_attach_force_audio_property(connector);
e953fd7b 3471 intel_attach_broadcast_rgb_property(connector);
55bc60db 3472 intel_dp->color_range_auto = true;
53b41837
YN		 3473
3474 if (is_edp(intel_dp)) {
3475 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3476 drm_object_attach_property(
3477 &connector->base,
53b41837 3478 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3479 DRM_MODE_SCALE_ASPECT);
3480 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3481 }
f684960e
CW		 3482}
3483
dada1a9f
ID		 3484static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3485{
3486 intel_dp->last_power_cycle = jiffies;
3487 intel_dp->last_power_on = jiffies;
3488 intel_dp->last_backlight_off = jiffies;
3489}
3490
67a54566
DV		 3491static void
3492intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3493 struct intel_dp *intel_dp,
3494 struct edp_power_seq *out)
67a54566
DV		 3495{
3496 struct drm_i915_private *dev_priv = dev->dev_private;
3497 struct edp_power_seq cur, vbt, spec, final;
3498 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 3499 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 3500
3501 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 3502 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 3503 pp_on_reg = PCH_PP_ON_DELAYS;
3504 pp_off_reg = PCH_PP_OFF_DELAYS;
3505 pp_div_reg = PCH_PP_DIVISOR;
3506 } else {
bf13e81b
JN		 3507 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3508
3509 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3510 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3511 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3512 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 3513 }
67a54566
DV		 3514
3515 /* Workaround: Need to write PP_CONTROL with the unlock key as
3516 * the very first thing. */
453c5420 3517 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 3518 I915_WRITE(pp_ctrl_reg, pp);
67a54566 3519
453c5420
JB		 3520 pp_on = I915_READ(pp_on_reg);
3521 pp_off = I915_READ(pp_off_reg);
3522 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3523
3524 /* Pull timing values out of registers */
3525 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3526 PANEL_POWER_UP_DELAY_SHIFT;
3527
3528 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3529 PANEL_LIGHT_ON_DELAY_SHIFT;
3530
3531 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3532 PANEL_LIGHT_OFF_DELAY_SHIFT;
3533
3534 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3535 PANEL_POWER_DOWN_DELAY_SHIFT;
3536
3537 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3538 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3539
3540 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3541 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3542
41aa3448 3543 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3544
3545 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3546 * our hw here, which are all in 100usec. */
3547 spec.t1_t3 = 210 * 10;
3548 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3549 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3550 spec.t10 = 500 * 10;
3551 /* This one is special and actually in units of 100ms, but zero
3552 * based in the hw (so we need to add 100 ms). But the sw vbt
3553 * table multiplies it with 1000 to make it in units of 100usec,
3554 * too. */
3555 spec.t11_t12 = (510 + 100) * 10;
3556
3557 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3558 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3559
3560 /* Use the max of the register settings and vbt. If both are
3561 * unset, fall back to the spec limits. */
3562#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3563 spec.field : \
3564 max(cur.field, vbt.field))
3565 assign_final(t1_t3);
3566 assign_final(t8);
3567 assign_final(t9);
3568 assign_final(t10);
3569 assign_final(t11_t12);
3570#undef assign_final
3571
3572#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3573 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3574 intel_dp->backlight_on_delay = get_delay(t8);
3575 intel_dp->backlight_off_delay = get_delay(t9);
3576 intel_dp->panel_power_down_delay = get_delay(t10);
3577 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3578#undef get_delay
3579
f30d26e4
JN		 3580 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3581 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3582 intel_dp->panel_power_cycle_delay);
3583
3584 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3585 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3586
3587 if (out)
3588 *out = final;
3589}
3590
3591static void
3592intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3593 struct intel_dp *intel_dp,
3594 struct edp_power_seq *seq)
3595{
3596 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3597 u32 pp_on, pp_off, pp_div, port_sel = 0;
3598 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3599 int pp_on_reg, pp_off_reg, pp_div_reg;
3600
3601 if (HAS_PCH_SPLIT(dev)) {
3602 pp_on_reg = PCH_PP_ON_DELAYS;
3603 pp_off_reg = PCH_PP_OFF_DELAYS;
3604 pp_div_reg = PCH_PP_DIVISOR;
3605 } else {
bf13e81b
JN		 3606 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3607
3608 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3609 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3610 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 3611 }
3612
b2f19d1a
PZ		 3613 /*
3614 * And finally store the new values in the power sequencer. The
3615 * backlight delays are set to 1 because we do manual waits on them. For
3616 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3617 * we'll end up waiting for the backlight off delay twice: once when we
3618 * do the manual sleep, and once when we disable the panel and wait for
3619 * the PP_STATUS bit to become zero.
3620 */
f30d26e4 3621 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 3622 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3623 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 3624 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 3625 /* Compute the divisor for the pp clock, simply match the Bspec
3626 * formula. */
453c5420 3627 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 3628 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 3629 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3630
3631 /* Haswell doesn't have any port selection bits for the panel
3632 * power sequencer any more. */
bc7d38a4 3633 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 3634 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3635 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3636 else
3637 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 3638 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3639 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 3640 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 3641 else
a24c144c 3642 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 3643 }
3644
453c5420
JB		 3645 pp_on |= port_sel;
3646
3647 I915_WRITE(pp_on_reg, pp_on);
3648 I915_WRITE(pp_off_reg, pp_off);
3649 I915_WRITE(pp_div_reg, pp_div);
67a54566 3650
67a54566 3651 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 3652 I915_READ(pp_on_reg),
3653 I915_READ(pp_off_reg),
3654 I915_READ(pp_div_reg));
f684960e
CW		 3655}
3656
439d7ac0
PB		 3657void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
3658{
3659 struct drm_i915_private *dev_priv = dev->dev_private;
3660 struct intel_encoder *encoder;
3661 struct intel_dp *intel_dp = NULL;
3662 struct intel_crtc_config *config = NULL;
3663 struct intel_crtc *intel_crtc = NULL;
3664 struct intel_connector *intel_connector = dev_priv->drrs.connector;
3665 u32 reg, val;
3666 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
3667
3668 if (refresh_rate <= 0) {
3669 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
3670 return;
3671 }
3672
3673 if (intel_connector == NULL) {
3674 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
3675 return;
3676 }
3677
3678 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
3679 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
3680 return;
3681 }
3682
3683 encoder = intel_attached_encoder(&intel_connector->base);
3684 intel_dp = enc_to_intel_dp(&encoder->base);
3685 intel_crtc = encoder->new_crtc;
3686
3687 if (!intel_crtc) {
3688 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
3689 return;
3690 }
3691
3692 config = &intel_crtc->config;
3693
3694 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
3695 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
3696 return;
3697 }
3698
3699 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
3700 index = DRRS_LOW_RR;
3701
3702 if (index == intel_dp->drrs_state.refresh_rate_type) {
3703 DRM_DEBUG_KMS(
3704 "DRRS requested for previously set RR...ignoring\n");
3705 return;
3706 }
3707
3708 if (!intel_crtc->active) {
3709 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
3710 return;
3711 }
3712
3713 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
3714 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
3715 val = I915_READ(reg);
3716 if (index > DRRS_HIGH_RR) {
3717 val |= PIPECONF_EDP_RR_MODE_SWITCH;
3718 intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
3719 } else {
3720 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
3721 }
3722 I915_WRITE(reg, val);
3723 }
3724
3725 /*
3726 * mutex taken to ensure that there is no race between differnt
3727 * drrs calls trying to update refresh rate. This scenario may occur
3728 * in future when idleness detection based DRRS in kernel and
3729 * possible calls from user space to set differnt RR are made.
3730 */
3731
3732 mutex_lock(&intel_dp->drrs_state.mutex);
3733
3734 intel_dp->drrs_state.refresh_rate_type = index;
3735
3736 mutex_unlock(&intel_dp->drrs_state.mutex);
3737
3738 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
3739}
3740
4f9db5b5
PB		 3741static struct drm_display_mode *
3742intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
3743 struct intel_connector *intel_connector,
3744 struct drm_display_mode *fixed_mode)
3745{
3746 struct drm_connector *connector = &intel_connector->base;
3747 struct intel_dp *intel_dp = &intel_dig_port->dp;
3748 struct drm_device *dev = intel_dig_port->base.base.dev;
3749 struct drm_i915_private *dev_priv = dev->dev_private;
3750 struct drm_display_mode *downclock_mode = NULL;
3751
3752 if (INTEL_INFO(dev)->gen <= 6) {
3753 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
3754 return NULL;
3755 }
3756
3757 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
3758 DRM_INFO("VBT doesn't support DRRS\n");
3759 return NULL;
3760 }
3761
3762 downclock_mode = intel_find_panel_downclock
3763 (dev, fixed_mode, connector);
3764
3765 if (!downclock_mode) {
3766 DRM_INFO("DRRS not supported\n");
3767 return NULL;
3768 }
3769
439d7ac0
PB		 3770 dev_priv->drrs.connector = intel_connector;
3771
3772 mutex_init(&intel_dp->drrs_state.mutex);
3773
4f9db5b5
PB		 3774 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
3775
3776 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
3777 DRM_INFO("seamless DRRS supported for eDP panel.\n");
3778 return downclock_mode;
3779}
3780
ed92f0b2 3781static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 3782 struct intel_connector *intel_connector,
3783 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 3784{
3785 struct drm_connector *connector = &intel_connector->base;
3786 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3787 struct drm_device *dev = intel_dig_port->base.base.dev;
3788 struct drm_i915_private *dev_priv = dev->dev_private;
3789 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 3790 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 3791 bool has_dpcd;
3792 struct drm_display_mode *scan;
3793 struct edid *edid;
3794
4f9db5b5
PB		 3795 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
3796
ed92f0b2
PZ		 3797 if (!is_edp(intel_dp))
3798 return true;
3799
ed92f0b2 3800 /* Cache DPCD and EDID for edp. */
24f3e092 3801 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 3802 has_dpcd = intel_dp_get_dpcd(intel_dp);
4be73780 3803 edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 3804
3805 if (has_dpcd) {
3806 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3807 dev_priv->no_aux_handshake =
3808 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3809 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3810 } else {
3811 /* if this fails, presume the device is a ghost */
3812 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 3813 return false;
3814 }
3815
3816 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 3817 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 3818
4da98541 3819 mutex_lock(&dev->mode_config.mutex);
0b99836f 3820 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 3821 if (edid) {
3822 if (drm_add_edid_modes(connector, edid)) {
3823 drm_mode_connector_update_edid_property(connector,
3824 edid);
3825 drm_edid_to_eld(connector, edid);
3826 } else {
3827 kfree(edid);
3828 edid = ERR_PTR(-EINVAL);
3829 }
3830 } else {
3831 edid = ERR_PTR(-ENOENT);
3832 }
3833 intel_connector->edid = edid;
3834
3835 /* prefer fixed mode from EDID if available */
3836 list_for_each_entry(scan, &connector->probed_modes, head) {
3837 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3838 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 3839 downclock_mode = intel_dp_drrs_init(
3840 intel_dig_port,
3841 intel_connector, fixed_mode);
ed92f0b2
PZ		 3842 break;
3843 }
3844 }
3845
3846 /* fallback to VBT if available for eDP */
3847 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3848 fixed_mode = drm_mode_duplicate(dev,
3849 dev_priv->vbt.lfp_lvds_vbt_mode);
3850 if (fixed_mode)
3851 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3852 }
4da98541 3853 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 3854
4f9db5b5 3855 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
ed92f0b2
PZ		 3856 intel_panel_setup_backlight(connector);
3857
3858 return true;
3859}
3860
16c25533 3861bool
f0fec3f2
PZ		 3862intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3863 struct intel_connector *intel_connector)
a4fc5ed6 3864{
f0fec3f2
PZ		 3865 struct drm_connector *connector = &intel_connector->base;
3866 struct intel_dp *intel_dp = &intel_dig_port->dp;
3867 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3868 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 3869 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3870 enum port port = intel_dig_port->port;
0095e6dc 3871 struct edp_power_seq power_seq = { 0 };
0b99836f 3872 int type;
a4fc5ed6 3873
ec5b01dd
DL		 3874 /* intel_dp vfuncs */
3875 if (IS_VALLEYVIEW(dev))
3876 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
3877 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3878 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
3879 else if (HAS_PCH_SPLIT(dev))
3880 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
3881 else
3882 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
3883
153b1100
DL		 3884 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
3885
0767935e
DV		 3886 /* Preserve the current hw state. */
3887 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 3888 intel_dp->attached_connector = intel_connector;
3d3dc149 3889
3b32a35b 3890 if (intel_dp_is_edp(dev, port))
b329530c 3891 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 3892 else
3893 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 3894
f7d24902
ID		 3895 /*
3896 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3897 * for DP the encoder type can be set by the caller to
3898 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3899 */
3900 if (type == DRM_MODE_CONNECTOR_eDP)
3901 intel_encoder->type = INTEL_OUTPUT_EDP;
3902
e7281eab
ID		 3903 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3904 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3905 port_name(port));
3906
b329530c 3907 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3908 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3909
a4fc5ed6
KP		 3910 connector->interlace_allowed = true;
3911 connector->doublescan_allowed = 0;
3912
f0fec3f2 3913 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 3914 edp_panel_vdd_work);
a4fc5ed6 3915
df0e9248 3916 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3917 drm_sysfs_connector_add(connector);
3918
affa9354 3919 if (HAS_DDI(dev))
bcbc889b
PZ		 3920 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3921 else
3922 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 3923 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 3924
0b99836f 3925 /* Set up the hotplug pin. */
ab9d7c30
PZ		 3926 switch (port) {
3927 case PORT_A:
1d843f9d 3928 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3929 break;
3930 case PORT_B:
1d843f9d 3931 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3932 break;
3933 case PORT_C:
1d843f9d 3934 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3935 break;
3936 case PORT_D:
1d843f9d 3937 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3938 break;
3939 default:
ad1c0b19 3940 BUG();
5eb08b69
ZW		 3941 }
3942
dada1a9f
ID		 3943 if (is_edp(intel_dp)) {
3944 intel_dp_init_panel_power_timestamps(intel_dp);
0095e6dc 3945 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
dada1a9f 3946 }
0095e6dc 3947
9d1a1031 3948 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 3949
2b28bb1b
RV		 3950 intel_dp->psr_setup_done = false;
3951
0095e6dc 3952 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
0b99836f 3953 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
15b1d171
PZ		 3954 if (is_edp(intel_dp)) {
3955 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3956 mutex_lock(&dev->mode_config.mutex);
4be73780 3957 edp_panel_vdd_off_sync(intel_dp);
15b1d171
PZ		 3958 mutex_unlock(&dev->mode_config.mutex);
3959 }
b2f246a8
PZ		 3960 drm_sysfs_connector_remove(connector);
3961 drm_connector_cleanup(connector);
16c25533 3962 return false;
b2f246a8 3963 }
32f9d658 3964
f684960e
CW		 3965 intel_dp_add_properties(intel_dp, connector);
3966
a4fc5ed6
KP		 3967 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3968 * 0xd. Failure to do so will result in spurious interrupts being
3969 * generated on the port when a cable is not attached.
3970 */
3971 if (IS_G4X(dev) && !IS_GM45(dev)) {
3972 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3973 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3974 }
16c25533
PZ		 3975
3976 return true;
a4fc5ed6 3977}
f0fec3f2
PZ		 3978
3979void
3980intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3981{
3982 struct intel_digital_port *intel_dig_port;
3983 struct intel_encoder *intel_encoder;
3984 struct drm_encoder *encoder;
3985 struct intel_connector *intel_connector;
3986
b14c5679 3987 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 3988 if (!intel_dig_port)
3989 return;
3990
b14c5679 3991 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 3992 if (!intel_connector) {
3993 kfree(intel_dig_port);
3994 return;
3995 }
3996
3997 intel_encoder = &intel_dig_port->base;
3998 encoder = &intel_encoder->base;
3999
4000 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4001 DRM_MODE_ENCODER_TMDS);
4002
5bfe2ac0 4003 intel_encoder->compute_config = intel_dp_compute_config;
b934223d 4004 intel_encoder->mode_set = intel_dp_mode_set;
00c09d70 4005 intel_encoder->disable = intel_disable_dp;
00c09d70 4006 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 4007 intel_encoder->get_config = intel_dp_get_config;
ab1f90f9 4008 if (IS_VALLEYVIEW(dev)) {
ecff4f3b 4009 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 4010 intel_encoder->pre_enable = vlv_pre_enable_dp;
4011 intel_encoder->enable = vlv_enable_dp;
49277c31 4012 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 4013 } else {
ecff4f3b
JN		 4014 intel_encoder->pre_enable = g4x_pre_enable_dp;
4015 intel_encoder->enable = g4x_enable_dp;
49277c31 4016 intel_encoder->post_disable = g4x_post_disable_dp;
ab1f90f9 4017 }
f0fec3f2 4018
174edf1f 4019 intel_dig_port->port = port;
f0fec3f2
PZ		 4020 intel_dig_port->dp.output_reg = output_reg;
4021
00c09d70 4022 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2 4023 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 4024 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 4025 intel_encoder->hot_plug = intel_dp_hot_plug;
4026
15b1d171
PZ		 4027 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4028 drm_encoder_cleanup(encoder);
4029 kfree(intel_dig_port);
b2f246a8 4030 kfree(intel_connector);
15b1d171 4031 }
f0fec3f2 4032}
Linux kernel - Deliverables
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