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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
2d1a8a48 | 30 | #include <linux/export.h> |
760285e7 DH |
31 | #include <drm/drmP.h> |
32 | #include <drm/drm_crtc.h> | |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/drm_edid.h> | |
a4fc5ed6 | 35 | #include "intel_drv.h" |
760285e7 | 36 | #include <drm/i915_drm.h> |
a4fc5ed6 | 37 | #include "i915_drv.h" |
a4fc5ed6 | 38 | |
a4fc5ed6 KP |
39 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
40 | ||
9dd4ffdf CML |
41 | struct dp_link_dpll { |
42 | int link_bw; | |
43 | struct dpll dpll; | |
44 | }; | |
45 | ||
46 | static const struct dp_link_dpll gen4_dpll[] = { | |
47 | { DP_LINK_BW_1_62, | |
48 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, | |
49 | { DP_LINK_BW_2_7, | |
50 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } | |
51 | }; | |
52 | ||
53 | static const struct dp_link_dpll pch_dpll[] = { | |
54 | { DP_LINK_BW_1_62, | |
55 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, | |
56 | { DP_LINK_BW_2_7, | |
57 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } | |
58 | }; | |
59 | ||
65ce4bf5 CML |
60 | static const struct dp_link_dpll vlv_dpll[] = { |
61 | { DP_LINK_BW_1_62, | |
58f6e632 | 62 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
65ce4bf5 CML |
63 | { DP_LINK_BW_2_7, |
64 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } | |
65 | }; | |
66 | ||
ef9348c8 CML |
67 | /* |
68 | * CHV supports eDP 1.4 that have more link rates. | |
69 | * Below only provides the fixed rate but exclude variable rate. | |
70 | */ | |
71 | static const struct dp_link_dpll chv_dpll[] = { | |
72 | /* | |
73 | * CHV requires to program fractional division for m2. | |
74 | * m2 is stored in fixed point format using formula below | |
75 | * (m2_int << 22) | m2_fraction | |
76 | */ | |
77 | { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */ | |
78 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, | |
79 | { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */ | |
80 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, | |
81 | { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */ | |
82 | { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } | |
83 | }; | |
84 | ||
cfcb0fc9 JB |
85 | /** |
86 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) | |
87 | * @intel_dp: DP struct | |
88 | * | |
89 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
90 | * will return true, and false otherwise. | |
91 | */ | |
92 | static bool is_edp(struct intel_dp *intel_dp) | |
93 | { | |
da63a9f2 PZ |
94 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
95 | ||
96 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; | |
cfcb0fc9 JB |
97 | } |
98 | ||
68b4d824 | 99 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
cfcb0fc9 | 100 | { |
68b4d824 ID |
101 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
102 | ||
103 | return intel_dig_port->base.base.dev; | |
cfcb0fc9 JB |
104 | } |
105 | ||
df0e9248 CW |
106 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
107 | { | |
fa90ecef | 108 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
109 | } |
110 | ||
ea5b213a | 111 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
adddaaf4 | 112 | static bool _edp_panel_vdd_on(struct intel_dp *intel_dp); |
4be73780 | 113 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
a4fc5ed6 | 114 | |
a4fc5ed6 | 115 | static int |
ea5b213a | 116 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
a4fc5ed6 | 117 | { |
7183dc29 | 118 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
06ea66b6 | 119 | struct drm_device *dev = intel_dp->attached_connector->base.dev; |
a4fc5ed6 KP |
120 | |
121 | switch (max_link_bw) { | |
122 | case DP_LINK_BW_1_62: | |
123 | case DP_LINK_BW_2_7: | |
124 | break; | |
d4eead50 | 125 | case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ |
06ea66b6 TP |
126 | if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) && |
127 | intel_dp->dpcd[DP_DPCD_REV] >= 0x12) | |
128 | max_link_bw = DP_LINK_BW_5_4; | |
129 | else | |
130 | max_link_bw = DP_LINK_BW_2_7; | |
d4eead50 | 131 | break; |
a4fc5ed6 | 132 | default: |
d4eead50 ID |
133 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", |
134 | max_link_bw); | |
a4fc5ed6 KP |
135 | max_link_bw = DP_LINK_BW_1_62; |
136 | break; | |
137 | } | |
138 | return max_link_bw; | |
139 | } | |
140 | ||
cd9dde44 AJ |
141 | /* |
142 | * The units on the numbers in the next two are... bizarre. Examples will | |
143 | * make it clearer; this one parallels an example in the eDP spec. | |
144 | * | |
145 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: | |
146 | * | |
147 | * 270000 * 1 * 8 / 10 == 216000 | |
148 | * | |
149 | * The actual data capacity of that configuration is 2.16Gbit/s, so the | |
150 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - | |
151 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be | |
152 | * 119000. At 18bpp that's 2142000 kilobits per second. | |
153 | * | |
154 | * Thus the strange-looking division by 10 in intel_dp_link_required, to | |
155 | * get the result in decakilobits instead of kilobits. | |
156 | */ | |
157 | ||
a4fc5ed6 | 158 | static int |
c898261c | 159 | intel_dp_link_required(int pixel_clock, int bpp) |
a4fc5ed6 | 160 | { |
cd9dde44 | 161 | return (pixel_clock * bpp + 9) / 10; |
a4fc5ed6 KP |
162 | } |
163 | ||
fe27d53e DA |
164 | static int |
165 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) | |
166 | { | |
167 | return (max_link_clock * max_lanes * 8) / 10; | |
168 | } | |
169 | ||
c19de8eb | 170 | static enum drm_mode_status |
a4fc5ed6 KP |
171 | intel_dp_mode_valid(struct drm_connector *connector, |
172 | struct drm_display_mode *mode) | |
173 | { | |
df0e9248 | 174 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
dd06f90e JN |
175 | struct intel_connector *intel_connector = to_intel_connector(connector); |
176 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
36008365 DV |
177 | int target_clock = mode->clock; |
178 | int max_rate, mode_rate, max_lanes, max_link_clock; | |
a4fc5ed6 | 179 | |
dd06f90e JN |
180 | if (is_edp(intel_dp) && fixed_mode) { |
181 | if (mode->hdisplay > fixed_mode->hdisplay) | |
7de56f43 ZY |
182 | return MODE_PANEL; |
183 | ||
dd06f90e | 184 | if (mode->vdisplay > fixed_mode->vdisplay) |
7de56f43 | 185 | return MODE_PANEL; |
03afc4a2 DV |
186 | |
187 | target_clock = fixed_mode->clock; | |
7de56f43 ZY |
188 | } |
189 | ||
36008365 DV |
190 | max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); |
191 | max_lanes = drm_dp_max_lane_count(intel_dp->dpcd); | |
192 | ||
193 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); | |
194 | mode_rate = intel_dp_link_required(target_clock, 18); | |
195 | ||
196 | if (mode_rate > max_rate) | |
c4867936 | 197 | return MODE_CLOCK_HIGH; |
a4fc5ed6 KP |
198 | |
199 | if (mode->clock < 10000) | |
200 | return MODE_CLOCK_LOW; | |
201 | ||
0af78a2b DV |
202 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
203 | return MODE_H_ILLEGAL; | |
204 | ||
a4fc5ed6 KP |
205 | return MODE_OK; |
206 | } | |
207 | ||
208 | static uint32_t | |
209 | pack_aux(uint8_t *src, int src_bytes) | |
210 | { | |
211 | int i; | |
212 | uint32_t v = 0; | |
213 | ||
214 | if (src_bytes > 4) | |
215 | src_bytes = 4; | |
216 | for (i = 0; i < src_bytes; i++) | |
217 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
218 | return v; | |
219 | } | |
220 | ||
221 | static void | |
222 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) | |
223 | { | |
224 | int i; | |
225 | if (dst_bytes > 4) | |
226 | dst_bytes = 4; | |
227 | for (i = 0; i < dst_bytes; i++) | |
228 | dst[i] = src >> ((3-i) * 8); | |
229 | } | |
230 | ||
fb0f8fbf KP |
231 | /* hrawclock is 1/4 the FSB frequency */ |
232 | static int | |
233 | intel_hrawclk(struct drm_device *dev) | |
234 | { | |
235 | struct drm_i915_private *dev_priv = dev->dev_private; | |
236 | uint32_t clkcfg; | |
237 | ||
9473c8f4 VP |
238 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ |
239 | if (IS_VALLEYVIEW(dev)) | |
240 | return 200; | |
241 | ||
fb0f8fbf KP |
242 | clkcfg = I915_READ(CLKCFG); |
243 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
244 | case CLKCFG_FSB_400: | |
245 | return 100; | |
246 | case CLKCFG_FSB_533: | |
247 | return 133; | |
248 | case CLKCFG_FSB_667: | |
249 | return 166; | |
250 | case CLKCFG_FSB_800: | |
251 | return 200; | |
252 | case CLKCFG_FSB_1067: | |
253 | return 266; | |
254 | case CLKCFG_FSB_1333: | |
255 | return 333; | |
256 | /* these two are just a guess; one of them might be right */ | |
257 | case CLKCFG_FSB_1600: | |
258 | case CLKCFG_FSB_1600_ALT: | |
259 | return 400; | |
260 | default: | |
261 | return 133; | |
262 | } | |
263 | } | |
264 | ||
bf13e81b JN |
265 | static void |
266 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
267 | struct intel_dp *intel_dp, | |
268 | struct edp_power_seq *out); | |
269 | static void | |
270 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
271 | struct intel_dp *intel_dp, | |
272 | struct edp_power_seq *out); | |
273 | ||
274 | static enum pipe | |
275 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) | |
276 | { | |
277 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
278 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; | |
279 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
280 | struct drm_i915_private *dev_priv = dev->dev_private; | |
281 | enum port port = intel_dig_port->port; | |
282 | enum pipe pipe; | |
283 | ||
284 | /* modeset should have pipe */ | |
285 | if (crtc) | |
286 | return to_intel_crtc(crtc)->pipe; | |
287 | ||
288 | /* init time, try to find a pipe with this port selected */ | |
289 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { | |
290 | u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & | |
291 | PANEL_PORT_SELECT_MASK; | |
292 | if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B) | |
293 | return pipe; | |
294 | if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C) | |
295 | return pipe; | |
296 | } | |
297 | ||
298 | /* shrug */ | |
299 | return PIPE_A; | |
300 | } | |
301 | ||
302 | static u32 _pp_ctrl_reg(struct intel_dp *intel_dp) | |
303 | { | |
304 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
305 | ||
306 | if (HAS_PCH_SPLIT(dev)) | |
307 | return PCH_PP_CONTROL; | |
308 | else | |
309 | return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); | |
310 | } | |
311 | ||
312 | static u32 _pp_stat_reg(struct intel_dp *intel_dp) | |
313 | { | |
314 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
315 | ||
316 | if (HAS_PCH_SPLIT(dev)) | |
317 | return PCH_PP_STATUS; | |
318 | else | |
319 | return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); | |
320 | } | |
321 | ||
4be73780 | 322 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
ebf33b18 | 323 | { |
30add22d | 324 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
ebf33b18 KP |
325 | struct drm_i915_private *dev_priv = dev->dev_private; |
326 | ||
bf13e81b | 327 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
ebf33b18 KP |
328 | } |
329 | ||
4be73780 | 330 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
ebf33b18 | 331 | { |
30add22d | 332 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
ebf33b18 | 333 | struct drm_i915_private *dev_priv = dev->dev_private; |
bb4932c4 ID |
334 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
335 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
336 | enum intel_display_power_domain power_domain; | |
ebf33b18 | 337 | |
bb4932c4 ID |
338 | power_domain = intel_display_port_power_domain(intel_encoder); |
339 | return intel_display_power_enabled(dev_priv, power_domain) && | |
efbc20ab | 340 | (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0; |
ebf33b18 KP |
341 | } |
342 | ||
9b984dae KP |
343 | static void |
344 | intel_dp_check_edp(struct intel_dp *intel_dp) | |
345 | { | |
30add22d | 346 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
9b984dae | 347 | struct drm_i915_private *dev_priv = dev->dev_private; |
ebf33b18 | 348 | |
9b984dae KP |
349 | if (!is_edp(intel_dp)) |
350 | return; | |
453c5420 | 351 | |
4be73780 | 352 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
9b984dae KP |
353 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
354 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", | |
bf13e81b JN |
355 | I915_READ(_pp_stat_reg(intel_dp)), |
356 | I915_READ(_pp_ctrl_reg(intel_dp))); | |
9b984dae KP |
357 | } |
358 | } | |
359 | ||
9ee32fea DV |
360 | static uint32_t |
361 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) | |
362 | { | |
363 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
364 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
365 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9ed35ab1 | 366 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
9ee32fea DV |
367 | uint32_t status; |
368 | bool done; | |
369 | ||
ef04f00d | 370 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
9ee32fea | 371 | if (has_aux_irq) |
b18ac466 | 372 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
3598706b | 373 | msecs_to_jiffies_timeout(10)); |
9ee32fea DV |
374 | else |
375 | done = wait_for_atomic(C, 10) == 0; | |
376 | if (!done) | |
377 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", | |
378 | has_aux_irq); | |
379 | #undef C | |
380 | ||
381 | return status; | |
382 | } | |
383 | ||
ec5b01dd | 384 | static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
a4fc5ed6 | 385 | { |
174edf1f PZ |
386 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
387 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
9ee32fea | 388 | |
ec5b01dd DL |
389 | /* |
390 | * The clock divider is based off the hrawclk, and would like to run at | |
391 | * 2MHz. So, take the hrawclk value and divide by 2 and use that | |
a4fc5ed6 | 392 | */ |
ec5b01dd DL |
393 | return index ? 0 : intel_hrawclk(dev) / 2; |
394 | } | |
395 | ||
396 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
397 | { | |
398 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
399 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
400 | ||
401 | if (index) | |
402 | return 0; | |
403 | ||
404 | if (intel_dig_port->port == PORT_A) { | |
405 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
b84a1cf8 | 406 | return 200; /* SNB & IVB eDP input clock at 400Mhz */ |
e3421a18 | 407 | else |
b84a1cf8 | 408 | return 225; /* eDP input clock at 450Mhz */ |
ec5b01dd DL |
409 | } else { |
410 | return DIV_ROUND_UP(intel_pch_rawclk(dev), 2); | |
411 | } | |
412 | } | |
413 | ||
414 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
415 | { | |
416 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
417 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
418 | struct drm_i915_private *dev_priv = dev->dev_private; | |
419 | ||
420 | if (intel_dig_port->port == PORT_A) { | |
421 | if (index) | |
422 | return 0; | |
423 | return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000); | |
2c55c336 JN |
424 | } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
425 | /* Workaround for non-ULT HSW */ | |
bc86625a CW |
426 | switch (index) { |
427 | case 0: return 63; | |
428 | case 1: return 72; | |
429 | default: return 0; | |
430 | } | |
ec5b01dd | 431 | } else { |
bc86625a | 432 | return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
2c55c336 | 433 | } |
b84a1cf8 RV |
434 | } |
435 | ||
ec5b01dd DL |
436 | static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
437 | { | |
438 | return index ? 0 : 100; | |
439 | } | |
440 | ||
5ed12a19 DL |
441 | static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp, |
442 | bool has_aux_irq, | |
443 | int send_bytes, | |
444 | uint32_t aux_clock_divider) | |
445 | { | |
446 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
447 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
448 | uint32_t precharge, timeout; | |
449 | ||
450 | if (IS_GEN6(dev)) | |
451 | precharge = 3; | |
452 | else | |
453 | precharge = 5; | |
454 | ||
455 | if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL) | |
456 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; | |
457 | else | |
458 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; | |
459 | ||
460 | return DP_AUX_CH_CTL_SEND_BUSY | | |
788d4433 | 461 | DP_AUX_CH_CTL_DONE | |
5ed12a19 | 462 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
788d4433 | 463 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
5ed12a19 | 464 | timeout | |
788d4433 | 465 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
5ed12a19 DL |
466 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
467 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
788d4433 | 468 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
5ed12a19 DL |
469 | } |
470 | ||
b84a1cf8 RV |
471 | static int |
472 | intel_dp_aux_ch(struct intel_dp *intel_dp, | |
473 | uint8_t *send, int send_bytes, | |
474 | uint8_t *recv, int recv_size) | |
475 | { | |
476 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
477 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
478 | struct drm_i915_private *dev_priv = dev->dev_private; | |
479 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; | |
480 | uint32_t ch_data = ch_ctl + 4; | |
bc86625a | 481 | uint32_t aux_clock_divider; |
b84a1cf8 RV |
482 | int i, ret, recv_bytes; |
483 | uint32_t status; | |
5ed12a19 | 484 | int try, clock = 0; |
4e6b788c | 485 | bool has_aux_irq = HAS_AUX_IRQ(dev); |
884f19e9 JN |
486 | bool vdd; |
487 | ||
488 | vdd = _edp_panel_vdd_on(intel_dp); | |
b84a1cf8 RV |
489 | |
490 | /* dp aux is extremely sensitive to irq latency, hence request the | |
491 | * lowest possible wakeup latency and so prevent the cpu from going into | |
492 | * deep sleep states. | |
493 | */ | |
494 | pm_qos_update_request(&dev_priv->pm_qos, 0); | |
495 | ||
496 | intel_dp_check_edp(intel_dp); | |
5eb08b69 | 497 | |
c67a470b PZ |
498 | intel_aux_display_runtime_get(dev_priv); |
499 | ||
11bee43e JB |
500 | /* Try to wait for any previous AUX channel activity */ |
501 | for (try = 0; try < 3; try++) { | |
ef04f00d | 502 | status = I915_READ_NOTRACE(ch_ctl); |
11bee43e JB |
503 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
504 | break; | |
505 | msleep(1); | |
506 | } | |
507 | ||
508 | if (try == 3) { | |
509 | WARN(1, "dp_aux_ch not started status 0x%08x\n", | |
510 | I915_READ(ch_ctl)); | |
9ee32fea DV |
511 | ret = -EBUSY; |
512 | goto out; | |
4f7f7b7e CW |
513 | } |
514 | ||
46a5ae9f PZ |
515 | /* Only 5 data registers! */ |
516 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { | |
517 | ret = -E2BIG; | |
518 | goto out; | |
519 | } | |
520 | ||
ec5b01dd | 521 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
153b1100 DL |
522 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
523 | has_aux_irq, | |
524 | send_bytes, | |
525 | aux_clock_divider); | |
5ed12a19 | 526 | |
bc86625a CW |
527 | /* Must try at least 3 times according to DP spec */ |
528 | for (try = 0; try < 5; try++) { | |
529 | /* Load the send data into the aux channel data registers */ | |
530 | for (i = 0; i < send_bytes; i += 4) | |
531 | I915_WRITE(ch_data + i, | |
532 | pack_aux(send + i, send_bytes - i)); | |
533 | ||
534 | /* Send the command and wait for it to complete */ | |
5ed12a19 | 535 | I915_WRITE(ch_ctl, send_ctl); |
bc86625a CW |
536 | |
537 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); | |
538 | ||
539 | /* Clear done status and any errors */ | |
540 | I915_WRITE(ch_ctl, | |
541 | status | | |
542 | DP_AUX_CH_CTL_DONE | | |
543 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
544 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
545 | ||
546 | if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
547 | DP_AUX_CH_CTL_RECEIVE_ERROR)) | |
548 | continue; | |
549 | if (status & DP_AUX_CH_CTL_DONE) | |
550 | break; | |
551 | } | |
4f7f7b7e | 552 | if (status & DP_AUX_CH_CTL_DONE) |
a4fc5ed6 KP |
553 | break; |
554 | } | |
555 | ||
a4fc5ed6 | 556 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 557 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
9ee32fea DV |
558 | ret = -EBUSY; |
559 | goto out; | |
a4fc5ed6 KP |
560 | } |
561 | ||
562 | /* Check for timeout or receive error. | |
563 | * Timeouts occur when the sink is not connected | |
564 | */ | |
a5b3da54 | 565 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 566 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
9ee32fea DV |
567 | ret = -EIO; |
568 | goto out; | |
a5b3da54 | 569 | } |
1ae8c0a5 KP |
570 | |
571 | /* Timeouts occur when the device isn't connected, so they're | |
572 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 573 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
28c97730 | 574 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
9ee32fea DV |
575 | ret = -ETIMEDOUT; |
576 | goto out; | |
a4fc5ed6 KP |
577 | } |
578 | ||
579 | /* Unload any bytes sent back from the other side */ | |
580 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
581 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
a4fc5ed6 KP |
582 | if (recv_bytes > recv_size) |
583 | recv_bytes = recv_size; | |
0206e353 | 584 | |
4f7f7b7e CW |
585 | for (i = 0; i < recv_bytes; i += 4) |
586 | unpack_aux(I915_READ(ch_data + i), | |
587 | recv + i, recv_bytes - i); | |
a4fc5ed6 | 588 | |
9ee32fea DV |
589 | ret = recv_bytes; |
590 | out: | |
591 | pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); | |
c67a470b | 592 | intel_aux_display_runtime_put(dev_priv); |
9ee32fea | 593 | |
884f19e9 JN |
594 | if (vdd) |
595 | edp_panel_vdd_off(intel_dp, false); | |
596 | ||
9ee32fea | 597 | return ret; |
a4fc5ed6 KP |
598 | } |
599 | ||
a6c8aff0 JN |
600 | #define BARE_ADDRESS_SIZE 3 |
601 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) | |
9d1a1031 JN |
602 | static ssize_t |
603 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) | |
a4fc5ed6 | 604 | { |
9d1a1031 JN |
605 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
606 | uint8_t txbuf[20], rxbuf[20]; | |
607 | size_t txsize, rxsize; | |
a4fc5ed6 | 608 | int ret; |
a4fc5ed6 | 609 | |
9d1a1031 JN |
610 | txbuf[0] = msg->request << 4; |
611 | txbuf[1] = msg->address >> 8; | |
612 | txbuf[2] = msg->address & 0xff; | |
613 | txbuf[3] = msg->size - 1; | |
46a5ae9f | 614 | |
9d1a1031 JN |
615 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
616 | case DP_AUX_NATIVE_WRITE: | |
617 | case DP_AUX_I2C_WRITE: | |
a6c8aff0 | 618 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
9d1a1031 | 619 | rxsize = 1; |
f51a44b9 | 620 | |
9d1a1031 JN |
621 | if (WARN_ON(txsize > 20)) |
622 | return -E2BIG; | |
a4fc5ed6 | 623 | |
9d1a1031 | 624 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); |
a4fc5ed6 | 625 | |
9d1a1031 JN |
626 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
627 | if (ret > 0) { | |
628 | msg->reply = rxbuf[0] >> 4; | |
a4fc5ed6 | 629 | |
9d1a1031 JN |
630 | /* Return payload size. */ |
631 | ret = msg->size; | |
632 | } | |
633 | break; | |
46a5ae9f | 634 | |
9d1a1031 JN |
635 | case DP_AUX_NATIVE_READ: |
636 | case DP_AUX_I2C_READ: | |
a6c8aff0 | 637 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
9d1a1031 | 638 | rxsize = msg->size + 1; |
a4fc5ed6 | 639 | |
9d1a1031 JN |
640 | if (WARN_ON(rxsize > 20)) |
641 | return -E2BIG; | |
a4fc5ed6 | 642 | |
9d1a1031 JN |
643 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
644 | if (ret > 0) { | |
645 | msg->reply = rxbuf[0] >> 4; | |
646 | /* | |
647 | * Assume happy day, and copy the data. The caller is | |
648 | * expected to check msg->reply before touching it. | |
649 | * | |
650 | * Return payload size. | |
651 | */ | |
652 | ret--; | |
653 | memcpy(msg->buffer, rxbuf + 1, ret); | |
a4fc5ed6 | 654 | } |
9d1a1031 JN |
655 | break; |
656 | ||
657 | default: | |
658 | ret = -EINVAL; | |
659 | break; | |
a4fc5ed6 | 660 | } |
f51a44b9 | 661 | |
9d1a1031 | 662 | return ret; |
a4fc5ed6 KP |
663 | } |
664 | ||
9d1a1031 JN |
665 | static void |
666 | intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) | |
667 | { | |
668 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
33ad6626 JN |
669 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
670 | enum port port = intel_dig_port->port; | |
0b99836f | 671 | const char *name = NULL; |
ab2c0672 DA |
672 | int ret; |
673 | ||
33ad6626 JN |
674 | switch (port) { |
675 | case PORT_A: | |
676 | intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; | |
0b99836f | 677 | name = "DPDDC-A"; |
ab2c0672 | 678 | break; |
33ad6626 JN |
679 | case PORT_B: |
680 | intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; | |
0b99836f | 681 | name = "DPDDC-B"; |
ab2c0672 | 682 | break; |
33ad6626 JN |
683 | case PORT_C: |
684 | intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; | |
0b99836f | 685 | name = "DPDDC-C"; |
ab2c0672 | 686 | break; |
33ad6626 JN |
687 | case PORT_D: |
688 | intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; | |
0b99836f | 689 | name = "DPDDC-D"; |
33ad6626 JN |
690 | break; |
691 | default: | |
692 | BUG(); | |
ab2c0672 DA |
693 | } |
694 | ||
33ad6626 JN |
695 | if (!HAS_DDI(dev)) |
696 | intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; | |
8316f337 | 697 | |
0b99836f | 698 | intel_dp->aux.name = name; |
9d1a1031 JN |
699 | intel_dp->aux.dev = dev->dev; |
700 | intel_dp->aux.transfer = intel_dp_aux_transfer; | |
8316f337 | 701 | |
0b99836f JN |
702 | DRM_DEBUG_KMS("registering %s bus for %s\n", name, |
703 | connector->base.kdev->kobj.name); | |
8316f337 | 704 | |
0b99836f JN |
705 | ret = drm_dp_aux_register_i2c_bus(&intel_dp->aux); |
706 | if (ret < 0) { | |
707 | DRM_ERROR("drm_dp_aux_register_i2c_bus() for %s failed (%d)\n", | |
708 | name, ret); | |
709 | return; | |
ab2c0672 | 710 | } |
8a5e6aeb | 711 | |
0b99836f JN |
712 | ret = sysfs_create_link(&connector->base.kdev->kobj, |
713 | &intel_dp->aux.ddc.dev.kobj, | |
714 | intel_dp->aux.ddc.dev.kobj.name); | |
715 | if (ret < 0) { | |
716 | DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret); | |
717 | drm_dp_aux_unregister_i2c_bus(&intel_dp->aux); | |
ab2c0672 | 718 | } |
a4fc5ed6 KP |
719 | } |
720 | ||
80f65de3 ID |
721 | static void |
722 | intel_dp_connector_unregister(struct intel_connector *intel_connector) | |
723 | { | |
724 | struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base); | |
725 | ||
726 | sysfs_remove_link(&intel_connector->base.kdev->kobj, | |
0b99836f | 727 | intel_dp->aux.ddc.dev.kobj.name); |
80f65de3 ID |
728 | intel_connector_unregister(intel_connector); |
729 | } | |
730 | ||
c6bb3538 DV |
731 | static void |
732 | intel_dp_set_clock(struct intel_encoder *encoder, | |
733 | struct intel_crtc_config *pipe_config, int link_bw) | |
734 | { | |
735 | struct drm_device *dev = encoder->base.dev; | |
9dd4ffdf CML |
736 | const struct dp_link_dpll *divisor = NULL; |
737 | int i, count = 0; | |
c6bb3538 DV |
738 | |
739 | if (IS_G4X(dev)) { | |
9dd4ffdf CML |
740 | divisor = gen4_dpll; |
741 | count = ARRAY_SIZE(gen4_dpll); | |
c6bb3538 DV |
742 | } else if (IS_HASWELL(dev)) { |
743 | /* Haswell has special-purpose DP DDI clocks. */ | |
744 | } else if (HAS_PCH_SPLIT(dev)) { | |
9dd4ffdf CML |
745 | divisor = pch_dpll; |
746 | count = ARRAY_SIZE(pch_dpll); | |
ef9348c8 CML |
747 | } else if (IS_CHERRYVIEW(dev)) { |
748 | divisor = chv_dpll; | |
749 | count = ARRAY_SIZE(chv_dpll); | |
c6bb3538 | 750 | } else if (IS_VALLEYVIEW(dev)) { |
65ce4bf5 CML |
751 | divisor = vlv_dpll; |
752 | count = ARRAY_SIZE(vlv_dpll); | |
c6bb3538 | 753 | } |
9dd4ffdf CML |
754 | |
755 | if (divisor && count) { | |
756 | for (i = 0; i < count; i++) { | |
757 | if (link_bw == divisor[i].link_bw) { | |
758 | pipe_config->dpll = divisor[i].dpll; | |
759 | pipe_config->clock_set = true; | |
760 | break; | |
761 | } | |
762 | } | |
c6bb3538 DV |
763 | } |
764 | } | |
765 | ||
439d7ac0 PB |
766 | static void |
767 | intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n) | |
768 | { | |
769 | struct drm_device *dev = crtc->base.dev; | |
770 | struct drm_i915_private *dev_priv = dev->dev_private; | |
771 | enum transcoder transcoder = crtc->config.cpu_transcoder; | |
772 | ||
773 | I915_WRITE(PIPE_DATA_M2(transcoder), | |
774 | TU_SIZE(m_n->tu) | m_n->gmch_m); | |
775 | I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n); | |
776 | I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m); | |
777 | I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n); | |
778 | } | |
779 | ||
00c09d70 | 780 | bool |
5bfe2ac0 DV |
781 | intel_dp_compute_config(struct intel_encoder *encoder, |
782 | struct intel_crtc_config *pipe_config) | |
a4fc5ed6 | 783 | { |
5bfe2ac0 | 784 | struct drm_device *dev = encoder->base.dev; |
36008365 | 785 | struct drm_i915_private *dev_priv = dev->dev_private; |
5bfe2ac0 | 786 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
5bfe2ac0 | 787 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 788 | enum port port = dp_to_dig_port(intel_dp)->port; |
2dd24552 | 789 | struct intel_crtc *intel_crtc = encoder->new_crtc; |
dd06f90e | 790 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
a4fc5ed6 | 791 | int lane_count, clock; |
397fe157 | 792 | int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); |
06ea66b6 TP |
793 | /* Conveniently, the link BW constants become indices with a shift...*/ |
794 | int max_clock = intel_dp_max_link_bw(intel_dp) >> 3; | |
083f9560 | 795 | int bpp, mode_rate; |
06ea66b6 | 796 | static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 }; |
ff9a6750 | 797 | int link_avail, link_clock; |
a4fc5ed6 | 798 | |
bc7d38a4 | 799 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) |
5bfe2ac0 DV |
800 | pipe_config->has_pch_encoder = true; |
801 | ||
03afc4a2 | 802 | pipe_config->has_dp_encoder = true; |
9ed109a7 | 803 | pipe_config->has_audio = intel_dp->has_audio; |
a4fc5ed6 | 804 | |
dd06f90e JN |
805 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
806 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, | |
807 | adjusted_mode); | |
2dd24552 JB |
808 | if (!HAS_PCH_SPLIT(dev)) |
809 | intel_gmch_panel_fitting(intel_crtc, pipe_config, | |
810 | intel_connector->panel.fitting_mode); | |
811 | else | |
b074cec8 JB |
812 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
813 | intel_connector->panel.fitting_mode); | |
0d3a1bee ZY |
814 | } |
815 | ||
cb1793ce | 816 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
0af78a2b DV |
817 | return false; |
818 | ||
083f9560 DV |
819 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
820 | "max bw %02x pixel clock %iKHz\n", | |
241bfc38 DL |
821 | max_lane_count, bws[max_clock], |
822 | adjusted_mode->crtc_clock); | |
083f9560 | 823 | |
36008365 DV |
824 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
825 | * bpc in between. */ | |
3e7ca985 | 826 | bpp = pipe_config->pipe_bpp; |
6da7f10d JN |
827 | if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && |
828 | dev_priv->vbt.edp_bpp < bpp) { | |
7984211e ID |
829 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
830 | dev_priv->vbt.edp_bpp); | |
6da7f10d | 831 | bpp = dev_priv->vbt.edp_bpp; |
7984211e | 832 | } |
657445fe | 833 | |
36008365 | 834 | for (; bpp >= 6*3; bpp -= 2*3) { |
241bfc38 DL |
835 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
836 | bpp); | |
36008365 | 837 | |
38aecea0 DV |
838 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { |
839 | for (clock = 0; clock <= max_clock; clock++) { | |
36008365 DV |
840 | link_clock = drm_dp_bw_code_to_link_rate(bws[clock]); |
841 | link_avail = intel_dp_max_data_rate(link_clock, | |
842 | lane_count); | |
843 | ||
844 | if (mode_rate <= link_avail) { | |
845 | goto found; | |
846 | } | |
847 | } | |
848 | } | |
849 | } | |
c4867936 | 850 | |
36008365 | 851 | return false; |
3685a8f3 | 852 | |
36008365 | 853 | found: |
55bc60db VS |
854 | if (intel_dp->color_range_auto) { |
855 | /* | |
856 | * See: | |
857 | * CEA-861-E - 5.1 Default Encoding Parameters | |
858 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry | |
859 | */ | |
18316c8c | 860 | if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1) |
55bc60db VS |
861 | intel_dp->color_range = DP_COLOR_RANGE_16_235; |
862 | else | |
863 | intel_dp->color_range = 0; | |
864 | } | |
865 | ||
3685a8f3 | 866 | if (intel_dp->color_range) |
50f3b016 | 867 | pipe_config->limited_color_range = true; |
a4fc5ed6 | 868 | |
36008365 DV |
869 | intel_dp->link_bw = bws[clock]; |
870 | intel_dp->lane_count = lane_count; | |
657445fe | 871 | pipe_config->pipe_bpp = bpp; |
ff9a6750 | 872 | pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); |
a4fc5ed6 | 873 | |
36008365 DV |
874 | DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", |
875 | intel_dp->link_bw, intel_dp->lane_count, | |
ff9a6750 | 876 | pipe_config->port_clock, bpp); |
36008365 DV |
877 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
878 | mode_rate, link_avail); | |
a4fc5ed6 | 879 | |
03afc4a2 | 880 | intel_link_compute_m_n(bpp, lane_count, |
241bfc38 DL |
881 | adjusted_mode->crtc_clock, |
882 | pipe_config->port_clock, | |
03afc4a2 | 883 | &pipe_config->dp_m_n); |
9d1a455b | 884 | |
439d7ac0 PB |
885 | if (intel_connector->panel.downclock_mode != NULL && |
886 | intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) { | |
887 | intel_link_compute_m_n(bpp, lane_count, | |
888 | intel_connector->panel.downclock_mode->clock, | |
889 | pipe_config->port_clock, | |
890 | &pipe_config->dp_m2_n2); | |
891 | } | |
892 | ||
c6bb3538 DV |
893 | intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); |
894 | ||
03afc4a2 | 895 | return true; |
a4fc5ed6 KP |
896 | } |
897 | ||
7c62a164 | 898 | static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp) |
ea9b6006 | 899 | { |
7c62a164 DV |
900 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
901 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); | |
902 | struct drm_device *dev = crtc->base.dev; | |
ea9b6006 DV |
903 | struct drm_i915_private *dev_priv = dev->dev_private; |
904 | u32 dpa_ctl; | |
905 | ||
ff9a6750 | 906 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock); |
ea9b6006 DV |
907 | dpa_ctl = I915_READ(DP_A); |
908 | dpa_ctl &= ~DP_PLL_FREQ_MASK; | |
909 | ||
ff9a6750 | 910 | if (crtc->config.port_clock == 162000) { |
1ce17038 DV |
911 | /* For a long time we've carried around a ILK-DevA w/a for the |
912 | * 160MHz clock. If we're really unlucky, it's still required. | |
913 | */ | |
914 | DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); | |
ea9b6006 | 915 | dpa_ctl |= DP_PLL_FREQ_160MHZ; |
7c62a164 | 916 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
ea9b6006 DV |
917 | } else { |
918 | dpa_ctl |= DP_PLL_FREQ_270MHZ; | |
7c62a164 | 919 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
ea9b6006 | 920 | } |
1ce17038 | 921 | |
ea9b6006 DV |
922 | I915_WRITE(DP_A, dpa_ctl); |
923 | ||
924 | POSTING_READ(DP_A); | |
925 | udelay(500); | |
926 | } | |
927 | ||
8ac33ed3 | 928 | static void intel_dp_prepare(struct intel_encoder *encoder) |
a4fc5ed6 | 929 | { |
b934223d | 930 | struct drm_device *dev = encoder->base.dev; |
417e822d | 931 | struct drm_i915_private *dev_priv = dev->dev_private; |
b934223d | 932 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 933 | enum port port = dp_to_dig_port(intel_dp)->port; |
b934223d DV |
934 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
935 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; | |
a4fc5ed6 | 936 | |
417e822d | 937 | /* |
1a2eb460 | 938 | * There are four kinds of DP registers: |
417e822d KP |
939 | * |
940 | * IBX PCH | |
1a2eb460 KP |
941 | * SNB CPU |
942 | * IVB CPU | |
417e822d KP |
943 | * CPT PCH |
944 | * | |
945 | * IBX PCH and CPU are the same for almost everything, | |
946 | * except that the CPU DP PLL is configured in this | |
947 | * register | |
948 | * | |
949 | * CPT PCH is quite different, having many bits moved | |
950 | * to the TRANS_DP_CTL register instead. That | |
951 | * configuration happens (oddly) in ironlake_pch_enable | |
952 | */ | |
9c9e7927 | 953 | |
417e822d KP |
954 | /* Preserve the BIOS-computed detected bit. This is |
955 | * supposed to be read-only. | |
956 | */ | |
957 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
a4fc5ed6 | 958 | |
417e822d | 959 | /* Handle DP bits in common between all three register formats */ |
417e822d | 960 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
17aa6be9 | 961 | intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); |
a4fc5ed6 | 962 | |
9ed109a7 | 963 | if (crtc->config.has_audio) { |
e0dac65e | 964 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
7c62a164 | 965 | pipe_name(crtc->pipe)); |
ea5b213a | 966 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
b934223d | 967 | intel_write_eld(&encoder->base, adjusted_mode); |
e0dac65e | 968 | } |
247d89f6 | 969 | |
417e822d | 970 | /* Split out the IBX/CPU vs CPT settings */ |
32f9d658 | 971 | |
bc7d38a4 | 972 | if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
1a2eb460 KP |
973 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
974 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
975 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
976 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
977 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
978 | ||
6aba5b6c | 979 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1a2eb460 KP |
980 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
981 | ||
7c62a164 | 982 | intel_dp->DP |= crtc->pipe << 29; |
bc7d38a4 | 983 | } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { |
b2634017 | 984 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) |
3685a8f3 | 985 | intel_dp->DP |= intel_dp->color_range; |
417e822d KP |
986 | |
987 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
988 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
989 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
990 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
991 | intel_dp->DP |= DP_LINK_TRAIN_OFF; | |
992 | ||
6aba5b6c | 993 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
417e822d KP |
994 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
995 | ||
44f37d1f CML |
996 | if (!IS_CHERRYVIEW(dev)) { |
997 | if (crtc->pipe == 1) | |
998 | intel_dp->DP |= DP_PIPEB_SELECT; | |
999 | } else { | |
1000 | intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); | |
1001 | } | |
417e822d KP |
1002 | } else { |
1003 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
32f9d658 | 1004 | } |
a4fc5ed6 KP |
1005 | } |
1006 | ||
ffd6749d PZ |
1007 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
1008 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) | |
99ea7127 | 1009 | |
1a5ef5b7 PZ |
1010 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
1011 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) | |
99ea7127 | 1012 | |
ffd6749d PZ |
1013 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
1014 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) | |
99ea7127 | 1015 | |
4be73780 | 1016 | static void wait_panel_status(struct intel_dp *intel_dp, |
99ea7127 KP |
1017 | u32 mask, |
1018 | u32 value) | |
bd943159 | 1019 | { |
30add22d | 1020 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
99ea7127 | 1021 | struct drm_i915_private *dev_priv = dev->dev_private; |
453c5420 JB |
1022 | u32 pp_stat_reg, pp_ctrl_reg; |
1023 | ||
bf13e81b JN |
1024 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1025 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
32ce697c | 1026 | |
99ea7127 | 1027 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
453c5420 JB |
1028 | mask, value, |
1029 | I915_READ(pp_stat_reg), | |
1030 | I915_READ(pp_ctrl_reg)); | |
32ce697c | 1031 | |
453c5420 | 1032 | if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { |
99ea7127 | 1033 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
453c5420 JB |
1034 | I915_READ(pp_stat_reg), |
1035 | I915_READ(pp_ctrl_reg)); | |
32ce697c | 1036 | } |
54c136d4 CW |
1037 | |
1038 | DRM_DEBUG_KMS("Wait complete\n"); | |
99ea7127 | 1039 | } |
32ce697c | 1040 | |
4be73780 | 1041 | static void wait_panel_on(struct intel_dp *intel_dp) |
99ea7127 KP |
1042 | { |
1043 | DRM_DEBUG_KMS("Wait for panel power on\n"); | |
4be73780 | 1044 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
bd943159 KP |
1045 | } |
1046 | ||
4be73780 | 1047 | static void wait_panel_off(struct intel_dp *intel_dp) |
99ea7127 KP |
1048 | { |
1049 | DRM_DEBUG_KMS("Wait for panel power off time\n"); | |
4be73780 | 1050 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
99ea7127 KP |
1051 | } |
1052 | ||
4be73780 | 1053 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
99ea7127 KP |
1054 | { |
1055 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); | |
dce56b3c PZ |
1056 | |
1057 | /* When we disable the VDD override bit last we have to do the manual | |
1058 | * wait. */ | |
1059 | wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle, | |
1060 | intel_dp->panel_power_cycle_delay); | |
1061 | ||
4be73780 | 1062 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
99ea7127 KP |
1063 | } |
1064 | ||
4be73780 | 1065 | static void wait_backlight_on(struct intel_dp *intel_dp) |
dce56b3c PZ |
1066 | { |
1067 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, | |
1068 | intel_dp->backlight_on_delay); | |
1069 | } | |
1070 | ||
4be73780 | 1071 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
dce56b3c PZ |
1072 | { |
1073 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, | |
1074 | intel_dp->backlight_off_delay); | |
1075 | } | |
99ea7127 | 1076 | |
832dd3c1 KP |
1077 | /* Read the current pp_control value, unlocking the register if it |
1078 | * is locked | |
1079 | */ | |
1080 | ||
453c5420 | 1081 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
832dd3c1 | 1082 | { |
453c5420 JB |
1083 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1084 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1085 | u32 control; | |
832dd3c1 | 1086 | |
bf13e81b | 1087 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
832dd3c1 KP |
1088 | control &= ~PANEL_UNLOCK_MASK; |
1089 | control |= PANEL_UNLOCK_REGS; | |
1090 | return control; | |
bd943159 KP |
1091 | } |
1092 | ||
adddaaf4 | 1093 | static bool _edp_panel_vdd_on(struct intel_dp *intel_dp) |
5d613501 | 1094 | { |
30add22d | 1095 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
4e6e1a54 ID |
1096 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1097 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
5d613501 | 1098 | struct drm_i915_private *dev_priv = dev->dev_private; |
4e6e1a54 | 1099 | enum intel_display_power_domain power_domain; |
5d613501 | 1100 | u32 pp; |
453c5420 | 1101 | u32 pp_stat_reg, pp_ctrl_reg; |
adddaaf4 | 1102 | bool need_to_disable = !intel_dp->want_panel_vdd; |
5d613501 | 1103 | |
97af61f5 | 1104 | if (!is_edp(intel_dp)) |
adddaaf4 | 1105 | return false; |
bd943159 KP |
1106 | |
1107 | intel_dp->want_panel_vdd = true; | |
99ea7127 | 1108 | |
4be73780 | 1109 | if (edp_have_panel_vdd(intel_dp)) |
adddaaf4 | 1110 | return need_to_disable; |
b0665d57 | 1111 | |
4e6e1a54 ID |
1112 | power_domain = intel_display_port_power_domain(intel_encoder); |
1113 | intel_display_power_get(dev_priv, power_domain); | |
e9cb81a2 | 1114 | |
b0665d57 | 1115 | DRM_DEBUG_KMS("Turning eDP VDD on\n"); |
bd943159 | 1116 | |
4be73780 DV |
1117 | if (!edp_have_panel_power(intel_dp)) |
1118 | wait_panel_power_cycle(intel_dp); | |
99ea7127 | 1119 | |
453c5420 | 1120 | pp = ironlake_get_pp_control(intel_dp); |
5d613501 | 1121 | pp |= EDP_FORCE_VDD; |
ebf33b18 | 1122 | |
bf13e81b JN |
1123 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1124 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
453c5420 JB |
1125 | |
1126 | I915_WRITE(pp_ctrl_reg, pp); | |
1127 | POSTING_READ(pp_ctrl_reg); | |
1128 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
1129 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
ebf33b18 KP |
1130 | /* |
1131 | * If the panel wasn't on, delay before accessing aux channel | |
1132 | */ | |
4be73780 | 1133 | if (!edp_have_panel_power(intel_dp)) { |
bd943159 | 1134 | DRM_DEBUG_KMS("eDP was not running\n"); |
f01eca2e | 1135 | msleep(intel_dp->panel_power_up_delay); |
f01eca2e | 1136 | } |
adddaaf4 JN |
1137 | |
1138 | return need_to_disable; | |
1139 | } | |
1140 | ||
b80d6c78 | 1141 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
adddaaf4 JN |
1142 | { |
1143 | if (is_edp(intel_dp)) { | |
1144 | bool vdd = _edp_panel_vdd_on(intel_dp); | |
1145 | ||
1146 | WARN(!vdd, "eDP VDD already requested on\n"); | |
1147 | } | |
5d613501 JB |
1148 | } |
1149 | ||
4be73780 | 1150 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
5d613501 | 1151 | { |
30add22d | 1152 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
5d613501 JB |
1153 | struct drm_i915_private *dev_priv = dev->dev_private; |
1154 | u32 pp; | |
453c5420 | 1155 | u32 pp_stat_reg, pp_ctrl_reg; |
5d613501 | 1156 | |
a0e99e68 DV |
1157 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); |
1158 | ||
4be73780 | 1159 | if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) { |
4e6e1a54 ID |
1160 | struct intel_digital_port *intel_dig_port = |
1161 | dp_to_dig_port(intel_dp); | |
1162 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
1163 | enum intel_display_power_domain power_domain; | |
1164 | ||
b0665d57 PZ |
1165 | DRM_DEBUG_KMS("Turning eDP VDD off\n"); |
1166 | ||
453c5420 | 1167 | pp = ironlake_get_pp_control(intel_dp); |
bd943159 | 1168 | pp &= ~EDP_FORCE_VDD; |
bd943159 | 1169 | |
9f08ef59 PZ |
1170 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1171 | pp_stat_reg = _pp_stat_reg(intel_dp); | |
453c5420 JB |
1172 | |
1173 | I915_WRITE(pp_ctrl_reg, pp); | |
1174 | POSTING_READ(pp_ctrl_reg); | |
99ea7127 | 1175 | |
453c5420 JB |
1176 | /* Make sure sequencer is idle before allowing subsequent activity */ |
1177 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
1178 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
90791a5c PZ |
1179 | |
1180 | if ((pp & POWER_TARGET_ON) == 0) | |
dce56b3c | 1181 | intel_dp->last_power_cycle = jiffies; |
e9cb81a2 | 1182 | |
4e6e1a54 ID |
1183 | power_domain = intel_display_port_power_domain(intel_encoder); |
1184 | intel_display_power_put(dev_priv, power_domain); | |
bd943159 KP |
1185 | } |
1186 | } | |
5d613501 | 1187 | |
4be73780 | 1188 | static void edp_panel_vdd_work(struct work_struct *__work) |
bd943159 KP |
1189 | { |
1190 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), | |
1191 | struct intel_dp, panel_vdd_work); | |
30add22d | 1192 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
bd943159 | 1193 | |
627f7675 | 1194 | mutex_lock(&dev->mode_config.mutex); |
4be73780 | 1195 | edp_panel_vdd_off_sync(intel_dp); |
627f7675 | 1196 | mutex_unlock(&dev->mode_config.mutex); |
bd943159 KP |
1197 | } |
1198 | ||
4be73780 | 1199 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
bd943159 | 1200 | { |
97af61f5 KP |
1201 | if (!is_edp(intel_dp)) |
1202 | return; | |
5d613501 | 1203 | |
bd943159 | 1204 | WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); |
f2e8b18a | 1205 | |
bd943159 KP |
1206 | intel_dp->want_panel_vdd = false; |
1207 | ||
1208 | if (sync) { | |
4be73780 | 1209 | edp_panel_vdd_off_sync(intel_dp); |
bd943159 KP |
1210 | } else { |
1211 | /* | |
1212 | * Queue the timer to fire a long | |
1213 | * time from now (relative to the power down delay) | |
1214 | * to keep the panel power up across a sequence of operations | |
1215 | */ | |
1216 | schedule_delayed_work(&intel_dp->panel_vdd_work, | |
1217 | msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); | |
1218 | } | |
5d613501 JB |
1219 | } |
1220 | ||
4be73780 | 1221 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
9934c132 | 1222 | { |
30add22d | 1223 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
9934c132 | 1224 | struct drm_i915_private *dev_priv = dev->dev_private; |
99ea7127 | 1225 | u32 pp; |
453c5420 | 1226 | u32 pp_ctrl_reg; |
9934c132 | 1227 | |
97af61f5 | 1228 | if (!is_edp(intel_dp)) |
bd943159 | 1229 | return; |
99ea7127 KP |
1230 | |
1231 | DRM_DEBUG_KMS("Turn eDP power on\n"); | |
1232 | ||
4be73780 | 1233 | if (edp_have_panel_power(intel_dp)) { |
99ea7127 | 1234 | DRM_DEBUG_KMS("eDP power already on\n"); |
7d639f35 | 1235 | return; |
99ea7127 | 1236 | } |
9934c132 | 1237 | |
4be73780 | 1238 | wait_panel_power_cycle(intel_dp); |
37c6c9b0 | 1239 | |
bf13e81b | 1240 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 1241 | pp = ironlake_get_pp_control(intel_dp); |
05ce1a49 KP |
1242 | if (IS_GEN5(dev)) { |
1243 | /* ILK workaround: disable reset around power sequence */ | |
1244 | pp &= ~PANEL_POWER_RESET; | |
bf13e81b JN |
1245 | I915_WRITE(pp_ctrl_reg, pp); |
1246 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 1247 | } |
37c6c9b0 | 1248 | |
1c0ae80a | 1249 | pp |= POWER_TARGET_ON; |
99ea7127 KP |
1250 | if (!IS_GEN5(dev)) |
1251 | pp |= PANEL_POWER_RESET; | |
1252 | ||
453c5420 JB |
1253 | I915_WRITE(pp_ctrl_reg, pp); |
1254 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 1255 | |
4be73780 | 1256 | wait_panel_on(intel_dp); |
dce56b3c | 1257 | intel_dp->last_power_on = jiffies; |
9934c132 | 1258 | |
05ce1a49 KP |
1259 | if (IS_GEN5(dev)) { |
1260 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ | |
bf13e81b JN |
1261 | I915_WRITE(pp_ctrl_reg, pp); |
1262 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 1263 | } |
9934c132 JB |
1264 | } |
1265 | ||
4be73780 | 1266 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
9934c132 | 1267 | { |
4e6e1a54 ID |
1268 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1269 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
30add22d | 1270 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
9934c132 | 1271 | struct drm_i915_private *dev_priv = dev->dev_private; |
4e6e1a54 | 1272 | enum intel_display_power_domain power_domain; |
99ea7127 | 1273 | u32 pp; |
453c5420 | 1274 | u32 pp_ctrl_reg; |
9934c132 | 1275 | |
97af61f5 KP |
1276 | if (!is_edp(intel_dp)) |
1277 | return; | |
37c6c9b0 | 1278 | |
99ea7127 | 1279 | DRM_DEBUG_KMS("Turn eDP power off\n"); |
37c6c9b0 | 1280 | |
4be73780 | 1281 | edp_wait_backlight_off(intel_dp); |
dce56b3c | 1282 | |
24f3e092 JN |
1283 | WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n"); |
1284 | ||
453c5420 | 1285 | pp = ironlake_get_pp_control(intel_dp); |
35a38556 DV |
1286 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
1287 | * panels get very unhappy and cease to work. */ | |
b3064154 PJ |
1288 | pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
1289 | EDP_BLC_ENABLE); | |
453c5420 | 1290 | |
bf13e81b | 1291 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 1292 | |
849e39f5 PZ |
1293 | intel_dp->want_panel_vdd = false; |
1294 | ||
453c5420 JB |
1295 | I915_WRITE(pp_ctrl_reg, pp); |
1296 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 1297 | |
dce56b3c | 1298 | intel_dp->last_power_cycle = jiffies; |
4be73780 | 1299 | wait_panel_off(intel_dp); |
849e39f5 PZ |
1300 | |
1301 | /* We got a reference when we enabled the VDD. */ | |
4e6e1a54 ID |
1302 | power_domain = intel_display_port_power_domain(intel_encoder); |
1303 | intel_display_power_put(dev_priv, power_domain); | |
9934c132 JB |
1304 | } |
1305 | ||
4be73780 | 1306 | void intel_edp_backlight_on(struct intel_dp *intel_dp) |
32f9d658 | 1307 | { |
da63a9f2 PZ |
1308 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1309 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
32f9d658 ZW |
1310 | struct drm_i915_private *dev_priv = dev->dev_private; |
1311 | u32 pp; | |
453c5420 | 1312 | u32 pp_ctrl_reg; |
32f9d658 | 1313 | |
f01eca2e KP |
1314 | if (!is_edp(intel_dp)) |
1315 | return; | |
1316 | ||
28c97730 | 1317 | DRM_DEBUG_KMS("\n"); |
01cb9ea6 JB |
1318 | /* |
1319 | * If we enable the backlight right away following a panel power | |
1320 | * on, we may see slight flicker as the panel syncs with the eDP | |
1321 | * link. So delay a bit to make sure the image is solid before | |
1322 | * allowing it to appear. | |
1323 | */ | |
4be73780 | 1324 | wait_backlight_on(intel_dp); |
453c5420 | 1325 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 1326 | pp |= EDP_BLC_ENABLE; |
453c5420 | 1327 | |
bf13e81b | 1328 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
1329 | |
1330 | I915_WRITE(pp_ctrl_reg, pp); | |
1331 | POSTING_READ(pp_ctrl_reg); | |
035aa3de | 1332 | |
752aa88a | 1333 | intel_panel_enable_backlight(intel_dp->attached_connector); |
32f9d658 ZW |
1334 | } |
1335 | ||
4be73780 | 1336 | void intel_edp_backlight_off(struct intel_dp *intel_dp) |
32f9d658 | 1337 | { |
30add22d | 1338 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
32f9d658 ZW |
1339 | struct drm_i915_private *dev_priv = dev->dev_private; |
1340 | u32 pp; | |
453c5420 | 1341 | u32 pp_ctrl_reg; |
32f9d658 | 1342 | |
f01eca2e KP |
1343 | if (!is_edp(intel_dp)) |
1344 | return; | |
1345 | ||
752aa88a | 1346 | intel_panel_disable_backlight(intel_dp->attached_connector); |
035aa3de | 1347 | |
28c97730 | 1348 | DRM_DEBUG_KMS("\n"); |
453c5420 | 1349 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 1350 | pp &= ~EDP_BLC_ENABLE; |
453c5420 | 1351 | |
bf13e81b | 1352 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
1353 | |
1354 | I915_WRITE(pp_ctrl_reg, pp); | |
1355 | POSTING_READ(pp_ctrl_reg); | |
dce56b3c | 1356 | intel_dp->last_backlight_off = jiffies; |
32f9d658 | 1357 | } |
a4fc5ed6 | 1358 | |
2bd2ad64 | 1359 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp) |
d240f20f | 1360 | { |
da63a9f2 PZ |
1361 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1362 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; | |
1363 | struct drm_device *dev = crtc->dev; | |
d240f20f JB |
1364 | struct drm_i915_private *dev_priv = dev->dev_private; |
1365 | u32 dpa_ctl; | |
1366 | ||
2bd2ad64 DV |
1367 | assert_pipe_disabled(dev_priv, |
1368 | to_intel_crtc(crtc)->pipe); | |
1369 | ||
d240f20f JB |
1370 | DRM_DEBUG_KMS("\n"); |
1371 | dpa_ctl = I915_READ(DP_A); | |
0767935e DV |
1372 | WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); |
1373 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); | |
1374 | ||
1375 | /* We don't adjust intel_dp->DP while tearing down the link, to | |
1376 | * facilitate link retraining (e.g. after hotplug). Hence clear all | |
1377 | * enable bits here to ensure that we don't enable too much. */ | |
1378 | intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); | |
1379 | intel_dp->DP |= DP_PLL_ENABLE; | |
1380 | I915_WRITE(DP_A, intel_dp->DP); | |
298b0b39 JB |
1381 | POSTING_READ(DP_A); |
1382 | udelay(200); | |
d240f20f JB |
1383 | } |
1384 | ||
2bd2ad64 | 1385 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
d240f20f | 1386 | { |
da63a9f2 PZ |
1387 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1388 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; | |
1389 | struct drm_device *dev = crtc->dev; | |
d240f20f JB |
1390 | struct drm_i915_private *dev_priv = dev->dev_private; |
1391 | u32 dpa_ctl; | |
1392 | ||
2bd2ad64 DV |
1393 | assert_pipe_disabled(dev_priv, |
1394 | to_intel_crtc(crtc)->pipe); | |
1395 | ||
d240f20f | 1396 | dpa_ctl = I915_READ(DP_A); |
0767935e DV |
1397 | WARN((dpa_ctl & DP_PLL_ENABLE) == 0, |
1398 | "dp pll off, should be on\n"); | |
1399 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); | |
1400 | ||
1401 | /* We can't rely on the value tracked for the DP register in | |
1402 | * intel_dp->DP because link_down must not change that (otherwise link | |
1403 | * re-training will fail. */ | |
298b0b39 | 1404 | dpa_ctl &= ~DP_PLL_ENABLE; |
d240f20f | 1405 | I915_WRITE(DP_A, dpa_ctl); |
1af5fa1b | 1406 | POSTING_READ(DP_A); |
d240f20f JB |
1407 | udelay(200); |
1408 | } | |
1409 | ||
c7ad3810 | 1410 | /* If the sink supports it, try to set the power state appropriately */ |
c19b0669 | 1411 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
c7ad3810 JB |
1412 | { |
1413 | int ret, i; | |
1414 | ||
1415 | /* Should have a valid DPCD by this point */ | |
1416 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
1417 | return; | |
1418 | ||
1419 | if (mode != DRM_MODE_DPMS_ON) { | |
9d1a1031 JN |
1420 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
1421 | DP_SET_POWER_D3); | |
c7ad3810 JB |
1422 | if (ret != 1) |
1423 | DRM_DEBUG_DRIVER("failed to write sink power state\n"); | |
1424 | } else { | |
1425 | /* | |
1426 | * When turning on, we need to retry for 1ms to give the sink | |
1427 | * time to wake up. | |
1428 | */ | |
1429 | for (i = 0; i < 3; i++) { | |
9d1a1031 JN |
1430 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
1431 | DP_SET_POWER_D0); | |
c7ad3810 JB |
1432 | if (ret == 1) |
1433 | break; | |
1434 | msleep(1); | |
1435 | } | |
1436 | } | |
1437 | } | |
1438 | ||
19d8fe15 DV |
1439 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
1440 | enum pipe *pipe) | |
d240f20f | 1441 | { |
19d8fe15 | 1442 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1443 | enum port port = dp_to_dig_port(intel_dp)->port; |
19d8fe15 DV |
1444 | struct drm_device *dev = encoder->base.dev; |
1445 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d129bea ID |
1446 | enum intel_display_power_domain power_domain; |
1447 | u32 tmp; | |
1448 | ||
1449 | power_domain = intel_display_port_power_domain(encoder); | |
1450 | if (!intel_display_power_enabled(dev_priv, power_domain)) | |
1451 | return false; | |
1452 | ||
1453 | tmp = I915_READ(intel_dp->output_reg); | |
19d8fe15 DV |
1454 | |
1455 | if (!(tmp & DP_PORT_EN)) | |
1456 | return false; | |
1457 | ||
bc7d38a4 | 1458 | if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
19d8fe15 | 1459 | *pipe = PORT_TO_PIPE_CPT(tmp); |
71485e0a VS |
1460 | } else if (IS_CHERRYVIEW(dev)) { |
1461 | *pipe = DP_PORT_TO_PIPE_CHV(tmp); | |
bc7d38a4 | 1462 | } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { |
19d8fe15 DV |
1463 | *pipe = PORT_TO_PIPE(tmp); |
1464 | } else { | |
1465 | u32 trans_sel; | |
1466 | u32 trans_dp; | |
1467 | int i; | |
1468 | ||
1469 | switch (intel_dp->output_reg) { | |
1470 | case PCH_DP_B: | |
1471 | trans_sel = TRANS_DP_PORT_SEL_B; | |
1472 | break; | |
1473 | case PCH_DP_C: | |
1474 | trans_sel = TRANS_DP_PORT_SEL_C; | |
1475 | break; | |
1476 | case PCH_DP_D: | |
1477 | trans_sel = TRANS_DP_PORT_SEL_D; | |
1478 | break; | |
1479 | default: | |
1480 | return true; | |
1481 | } | |
1482 | ||
1483 | for_each_pipe(i) { | |
1484 | trans_dp = I915_READ(TRANS_DP_CTL(i)); | |
1485 | if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { | |
1486 | *pipe = i; | |
1487 | return true; | |
1488 | } | |
1489 | } | |
19d8fe15 | 1490 | |
4a0833ec DV |
1491 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
1492 | intel_dp->output_reg); | |
1493 | } | |
d240f20f | 1494 | |
19d8fe15 DV |
1495 | return true; |
1496 | } | |
d240f20f | 1497 | |
045ac3b5 JB |
1498 | static void intel_dp_get_config(struct intel_encoder *encoder, |
1499 | struct intel_crtc_config *pipe_config) | |
1500 | { | |
1501 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
045ac3b5 | 1502 | u32 tmp, flags = 0; |
63000ef6 XZ |
1503 | struct drm_device *dev = encoder->base.dev; |
1504 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1505 | enum port port = dp_to_dig_port(intel_dp)->port; | |
1506 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
18442d08 | 1507 | int dotclock; |
045ac3b5 | 1508 | |
9ed109a7 DV |
1509 | tmp = I915_READ(intel_dp->output_reg); |
1510 | if (tmp & DP_AUDIO_OUTPUT_ENABLE) | |
1511 | pipe_config->has_audio = true; | |
1512 | ||
63000ef6 | 1513 | if ((port == PORT_A) || !HAS_PCH_CPT(dev)) { |
63000ef6 XZ |
1514 | if (tmp & DP_SYNC_HS_HIGH) |
1515 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1516 | else | |
1517 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 1518 | |
63000ef6 XZ |
1519 | if (tmp & DP_SYNC_VS_HIGH) |
1520 | flags |= DRM_MODE_FLAG_PVSYNC; | |
1521 | else | |
1522 | flags |= DRM_MODE_FLAG_NVSYNC; | |
1523 | } else { | |
1524 | tmp = I915_READ(TRANS_DP_CTL(crtc->pipe)); | |
1525 | if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH) | |
1526 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1527 | else | |
1528 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 1529 | |
63000ef6 XZ |
1530 | if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
1531 | flags |= DRM_MODE_FLAG_PVSYNC; | |
1532 | else | |
1533 | flags |= DRM_MODE_FLAG_NVSYNC; | |
1534 | } | |
045ac3b5 JB |
1535 | |
1536 | pipe_config->adjusted_mode.flags |= flags; | |
f1f644dc | 1537 | |
eb14cb74 VS |
1538 | pipe_config->has_dp_encoder = true; |
1539 | ||
1540 | intel_dp_get_m_n(crtc, pipe_config); | |
1541 | ||
18442d08 | 1542 | if (port == PORT_A) { |
f1f644dc JB |
1543 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) |
1544 | pipe_config->port_clock = 162000; | |
1545 | else | |
1546 | pipe_config->port_clock = 270000; | |
1547 | } | |
18442d08 VS |
1548 | |
1549 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, | |
1550 | &pipe_config->dp_m_n); | |
1551 | ||
1552 | if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) | |
1553 | ironlake_check_encoder_dotclock(pipe_config, dotclock); | |
1554 | ||
241bfc38 | 1555 | pipe_config->adjusted_mode.crtc_clock = dotclock; |
7f16e5c1 | 1556 | |
c6cd2ee2 JN |
1557 | if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && |
1558 | pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { | |
1559 | /* | |
1560 | * This is a big fat ugly hack. | |
1561 | * | |
1562 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
1563 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
1564 | * unknown we fail to light up. Yet the same BIOS boots up with | |
1565 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
1566 | * max, not what it tells us to use. | |
1567 | * | |
1568 | * Note: This will still be broken if the eDP panel is not lit | |
1569 | * up by the BIOS, and thus we can't get the mode at module | |
1570 | * load. | |
1571 | */ | |
1572 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
1573 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); | |
1574 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; | |
1575 | } | |
045ac3b5 JB |
1576 | } |
1577 | ||
a031d709 | 1578 | static bool is_edp_psr(struct drm_device *dev) |
2293bb5c | 1579 | { |
a031d709 RV |
1580 | struct drm_i915_private *dev_priv = dev->dev_private; |
1581 | ||
1582 | return dev_priv->psr.sink_support; | |
2293bb5c SK |
1583 | } |
1584 | ||
2b28bb1b RV |
1585 | static bool intel_edp_is_psr_enabled(struct drm_device *dev) |
1586 | { | |
1587 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1588 | ||
18b5992c | 1589 | if (!HAS_PSR(dev)) |
2b28bb1b RV |
1590 | return false; |
1591 | ||
18b5992c | 1592 | return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; |
2b28bb1b RV |
1593 | } |
1594 | ||
1595 | static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp, | |
1596 | struct edp_vsc_psr *vsc_psr) | |
1597 | { | |
1598 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
1599 | struct drm_device *dev = dig_port->base.base.dev; | |
1600 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1601 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); | |
1602 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder); | |
1603 | u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder); | |
1604 | uint32_t *data = (uint32_t *) vsc_psr; | |
1605 | unsigned int i; | |
1606 | ||
1607 | /* As per BSPec (Pipe Video Data Island Packet), we need to disable | |
1608 | the video DIP being updated before program video DIP data buffer | |
1609 | registers for DIP being updated. */ | |
1610 | I915_WRITE(ctl_reg, 0); | |
1611 | POSTING_READ(ctl_reg); | |
1612 | ||
1613 | for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) { | |
1614 | if (i < sizeof(struct edp_vsc_psr)) | |
1615 | I915_WRITE(data_reg + i, *data++); | |
1616 | else | |
1617 | I915_WRITE(data_reg + i, 0); | |
1618 | } | |
1619 | ||
1620 | I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); | |
1621 | POSTING_READ(ctl_reg); | |
1622 | } | |
1623 | ||
1624 | static void intel_edp_psr_setup(struct intel_dp *intel_dp) | |
1625 | { | |
1626 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1627 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1628 | struct edp_vsc_psr psr_vsc; | |
1629 | ||
1630 | if (intel_dp->psr_setup_done) | |
1631 | return; | |
1632 | ||
1633 | /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ | |
1634 | memset(&psr_vsc, 0, sizeof(psr_vsc)); | |
1635 | psr_vsc.sdp_header.HB0 = 0; | |
1636 | psr_vsc.sdp_header.HB1 = 0x7; | |
1637 | psr_vsc.sdp_header.HB2 = 0x2; | |
1638 | psr_vsc.sdp_header.HB3 = 0x8; | |
1639 | intel_edp_psr_write_vsc(intel_dp, &psr_vsc); | |
1640 | ||
1641 | /* Avoid continuous PSR exit by masking memup and hpd */ | |
18b5992c | 1642 | I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP | |
0cc4b699 | 1643 | EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP); |
2b28bb1b RV |
1644 | |
1645 | intel_dp->psr_setup_done = true; | |
1646 | } | |
1647 | ||
1648 | static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp) | |
1649 | { | |
1650 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1651 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ec5b01dd | 1652 | uint32_t aux_clock_divider; |
2b28bb1b RV |
1653 | int precharge = 0x3; |
1654 | int msg_size = 5; /* Header(4) + Message(1) */ | |
1655 | ||
ec5b01dd DL |
1656 | aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); |
1657 | ||
2b28bb1b RV |
1658 | /* Enable PSR in sink */ |
1659 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) | |
9d1a1031 JN |
1660 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, |
1661 | DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE); | |
2b28bb1b | 1662 | else |
9d1a1031 JN |
1663 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, |
1664 | DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); | |
2b28bb1b RV |
1665 | |
1666 | /* Setup AUX registers */ | |
18b5992c BW |
1667 | I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND); |
1668 | I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION); | |
1669 | I915_WRITE(EDP_PSR_AUX_CTL(dev), | |
2b28bb1b RV |
1670 | DP_AUX_CH_CTL_TIME_OUT_400us | |
1671 | (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
1672 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
1673 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); | |
1674 | } | |
1675 | ||
1676 | static void intel_edp_psr_enable_source(struct intel_dp *intel_dp) | |
1677 | { | |
1678 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1679 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1680 | uint32_t max_sleep_time = 0x1f; | |
1681 | uint32_t idle_frames = 1; | |
1682 | uint32_t val = 0x0; | |
ed8546ac | 1683 | const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; |
2b28bb1b RV |
1684 | |
1685 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) { | |
1686 | val |= EDP_PSR_LINK_STANDBY; | |
1687 | val |= EDP_PSR_TP2_TP3_TIME_0us; | |
1688 | val |= EDP_PSR_TP1_TIME_0us; | |
1689 | val |= EDP_PSR_SKIP_AUX_EXIT; | |
1690 | } else | |
1691 | val |= EDP_PSR_LINK_DISABLE; | |
1692 | ||
18b5992c | 1693 | I915_WRITE(EDP_PSR_CTL(dev), val | |
24bd9bf5 | 1694 | (IS_BROADWELL(dev) ? 0 : link_entry_time) | |
2b28bb1b RV |
1695 | max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | |
1696 | idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | | |
1697 | EDP_PSR_ENABLE); | |
1698 | } | |
1699 | ||
3f51e471 RV |
1700 | static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp) |
1701 | { | |
1702 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
1703 | struct drm_device *dev = dig_port->base.base.dev; | |
1704 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1705 | struct drm_crtc *crtc = dig_port->base.base.crtc; | |
1706 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
f4510a27 | 1707 | struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->primary->fb)->obj; |
3f51e471 RV |
1708 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
1709 | ||
a031d709 RV |
1710 | dev_priv->psr.source_ok = false; |
1711 | ||
18b5992c | 1712 | if (!HAS_PSR(dev)) { |
3f51e471 | 1713 | DRM_DEBUG_KMS("PSR not supported on this platform\n"); |
3f51e471 RV |
1714 | return false; |
1715 | } | |
1716 | ||
1717 | if ((intel_encoder->type != INTEL_OUTPUT_EDP) || | |
1718 | (dig_port->port != PORT_A)) { | |
1719 | DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n"); | |
3f51e471 RV |
1720 | return false; |
1721 | } | |
1722 | ||
d330a953 | 1723 | if (!i915.enable_psr) { |
105b7c11 | 1724 | DRM_DEBUG_KMS("PSR disable by flag\n"); |
105b7c11 RV |
1725 | return false; |
1726 | } | |
1727 | ||
cd234b0b CW |
1728 | crtc = dig_port->base.base.crtc; |
1729 | if (crtc == NULL) { | |
1730 | DRM_DEBUG_KMS("crtc not active for PSR\n"); | |
cd234b0b CW |
1731 | return false; |
1732 | } | |
1733 | ||
1734 | intel_crtc = to_intel_crtc(crtc); | |
20ddf665 | 1735 | if (!intel_crtc_active(crtc)) { |
3f51e471 | 1736 | DRM_DEBUG_KMS("crtc not active for PSR\n"); |
3f51e471 RV |
1737 | return false; |
1738 | } | |
1739 | ||
f4510a27 | 1740 | obj = to_intel_framebuffer(crtc->primary->fb)->obj; |
3f51e471 RV |
1741 | if (obj->tiling_mode != I915_TILING_X || |
1742 | obj->fence_reg == I915_FENCE_REG_NONE) { | |
1743 | DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n"); | |
3f51e471 RV |
1744 | return false; |
1745 | } | |
1746 | ||
1747 | if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) { | |
1748 | DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n"); | |
3f51e471 RV |
1749 | return false; |
1750 | } | |
1751 | ||
1752 | if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) & | |
1753 | S3D_ENABLE) { | |
1754 | DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); | |
3f51e471 RV |
1755 | return false; |
1756 | } | |
1757 | ||
ca73b4f0 | 1758 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
3f51e471 | 1759 | DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); |
3f51e471 RV |
1760 | return false; |
1761 | } | |
1762 | ||
a031d709 | 1763 | dev_priv->psr.source_ok = true; |
3f51e471 RV |
1764 | return true; |
1765 | } | |
1766 | ||
3d739d92 | 1767 | static void intel_edp_psr_do_enable(struct intel_dp *intel_dp) |
2b28bb1b RV |
1768 | { |
1769 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1770 | ||
3f51e471 RV |
1771 | if (!intel_edp_psr_match_conditions(intel_dp) || |
1772 | intel_edp_is_psr_enabled(dev)) | |
2b28bb1b RV |
1773 | return; |
1774 | ||
1775 | /* Setup PSR once */ | |
1776 | intel_edp_psr_setup(intel_dp); | |
1777 | ||
1778 | /* Enable PSR on the panel */ | |
1779 | intel_edp_psr_enable_sink(intel_dp); | |
1780 | ||
1781 | /* Enable PSR on the host */ | |
1782 | intel_edp_psr_enable_source(intel_dp); | |
1783 | } | |
1784 | ||
3d739d92 RV |
1785 | void intel_edp_psr_enable(struct intel_dp *intel_dp) |
1786 | { | |
1787 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1788 | ||
1789 | if (intel_edp_psr_match_conditions(intel_dp) && | |
1790 | !intel_edp_is_psr_enabled(dev)) | |
1791 | intel_edp_psr_do_enable(intel_dp); | |
1792 | } | |
1793 | ||
2b28bb1b RV |
1794 | void intel_edp_psr_disable(struct intel_dp *intel_dp) |
1795 | { | |
1796 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1797 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1798 | ||
1799 | if (!intel_edp_is_psr_enabled(dev)) | |
1800 | return; | |
1801 | ||
18b5992c BW |
1802 | I915_WRITE(EDP_PSR_CTL(dev), |
1803 | I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); | |
2b28bb1b RV |
1804 | |
1805 | /* Wait till PSR is idle */ | |
18b5992c | 1806 | if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & |
2b28bb1b RV |
1807 | EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10)) |
1808 | DRM_ERROR("Timed out waiting for PSR Idle State\n"); | |
1809 | } | |
1810 | ||
3d739d92 RV |
1811 | void intel_edp_psr_update(struct drm_device *dev) |
1812 | { | |
1813 | struct intel_encoder *encoder; | |
1814 | struct intel_dp *intel_dp = NULL; | |
1815 | ||
1816 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) | |
1817 | if (encoder->type == INTEL_OUTPUT_EDP) { | |
1818 | intel_dp = enc_to_intel_dp(&encoder->base); | |
1819 | ||
a031d709 | 1820 | if (!is_edp_psr(dev)) |
3d739d92 RV |
1821 | return; |
1822 | ||
1823 | if (!intel_edp_psr_match_conditions(intel_dp)) | |
1824 | intel_edp_psr_disable(intel_dp); | |
1825 | else | |
1826 | if (!intel_edp_is_psr_enabled(dev)) | |
1827 | intel_edp_psr_do_enable(intel_dp); | |
1828 | } | |
1829 | } | |
1830 | ||
e8cb4558 | 1831 | static void intel_disable_dp(struct intel_encoder *encoder) |
d240f20f | 1832 | { |
e8cb4558 | 1833 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
982a3866 ID |
1834 | enum port port = dp_to_dig_port(intel_dp)->port; |
1835 | struct drm_device *dev = encoder->base.dev; | |
6cb49835 DV |
1836 | |
1837 | /* Make sure the panel is off before trying to change the mode. But also | |
1838 | * ensure that we have vdd while we switch off the panel. */ | |
24f3e092 | 1839 | intel_edp_panel_vdd_on(intel_dp); |
4be73780 | 1840 | intel_edp_backlight_off(intel_dp); |
fdbc3b1f | 1841 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
4be73780 | 1842 | intel_edp_panel_off(intel_dp); |
3739850b DV |
1843 | |
1844 | /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ | |
982a3866 | 1845 | if (!(port == PORT_A || IS_VALLEYVIEW(dev))) |
3739850b | 1846 | intel_dp_link_down(intel_dp); |
d240f20f JB |
1847 | } |
1848 | ||
49277c31 | 1849 | static void g4x_post_disable_dp(struct intel_encoder *encoder) |
d240f20f | 1850 | { |
2bd2ad64 | 1851 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
982a3866 | 1852 | enum port port = dp_to_dig_port(intel_dp)->port; |
2bd2ad64 | 1853 | |
49277c31 VS |
1854 | if (port != PORT_A) |
1855 | return; | |
1856 | ||
1857 | intel_dp_link_down(intel_dp); | |
1858 | ironlake_edp_pll_off(intel_dp); | |
1859 | } | |
1860 | ||
1861 | static void vlv_post_disable_dp(struct intel_encoder *encoder) | |
1862 | { | |
1863 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
1864 | ||
1865 | intel_dp_link_down(intel_dp); | |
2bd2ad64 DV |
1866 | } |
1867 | ||
580d3811 VS |
1868 | static void chv_post_disable_dp(struct intel_encoder *encoder) |
1869 | { | |
1870 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
1871 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
1872 | struct drm_device *dev = encoder->base.dev; | |
1873 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1874 | struct intel_crtc *intel_crtc = | |
1875 | to_intel_crtc(encoder->base.crtc); | |
1876 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
1877 | enum pipe pipe = intel_crtc->pipe; | |
1878 | u32 val; | |
1879 | ||
1880 | intel_dp_link_down(intel_dp); | |
1881 | ||
1882 | mutex_lock(&dev_priv->dpio_lock); | |
1883 | ||
1884 | /* Propagate soft reset to data lane reset */ | |
97fd4d5c | 1885 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
d2152b25 | 1886 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
97fd4d5c | 1887 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
d2152b25 | 1888 | |
97fd4d5c VS |
1889 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); |
1890 | val |= CHV_PCS_REQ_SOFTRESET_EN; | |
1891 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); | |
1892 | ||
1893 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); | |
1894 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
1895 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); | |
1896 | ||
1897 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); | |
580d3811 | 1898 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
97fd4d5c | 1899 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
580d3811 VS |
1900 | |
1901 | mutex_unlock(&dev_priv->dpio_lock); | |
1902 | } | |
1903 | ||
e8cb4558 | 1904 | static void intel_enable_dp(struct intel_encoder *encoder) |
d240f20f | 1905 | { |
e8cb4558 DV |
1906 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1907 | struct drm_device *dev = encoder->base.dev; | |
1908 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1909 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); | |
5d613501 | 1910 | |
0c33d8d7 DV |
1911 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
1912 | return; | |
5d613501 | 1913 | |
24f3e092 | 1914 | intel_edp_panel_vdd_on(intel_dp); |
f01eca2e | 1915 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
33a34e4e | 1916 | intel_dp_start_link_train(intel_dp); |
4be73780 DV |
1917 | intel_edp_panel_on(intel_dp); |
1918 | edp_panel_vdd_off(intel_dp, true); | |
33a34e4e | 1919 | intel_dp_complete_link_train(intel_dp); |
3ab9c637 | 1920 | intel_dp_stop_link_train(intel_dp); |
ab1f90f9 | 1921 | } |
89b667f8 | 1922 | |
ecff4f3b JN |
1923 | static void g4x_enable_dp(struct intel_encoder *encoder) |
1924 | { | |
828f5c6e JN |
1925 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1926 | ||
ecff4f3b | 1927 | intel_enable_dp(encoder); |
4be73780 | 1928 | intel_edp_backlight_on(intel_dp); |
ab1f90f9 | 1929 | } |
89b667f8 | 1930 | |
ab1f90f9 JN |
1931 | static void vlv_enable_dp(struct intel_encoder *encoder) |
1932 | { | |
828f5c6e JN |
1933 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1934 | ||
4be73780 | 1935 | intel_edp_backlight_on(intel_dp); |
d240f20f JB |
1936 | } |
1937 | ||
ecff4f3b | 1938 | static void g4x_pre_enable_dp(struct intel_encoder *encoder) |
ab1f90f9 JN |
1939 | { |
1940 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
1941 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
1942 | ||
8ac33ed3 DV |
1943 | intel_dp_prepare(encoder); |
1944 | ||
d41f1efb DV |
1945 | /* Only ilk+ has port A */ |
1946 | if (dport->port == PORT_A) { | |
1947 | ironlake_set_pll_cpu_edp(intel_dp); | |
ab1f90f9 | 1948 | ironlake_edp_pll_on(intel_dp); |
d41f1efb | 1949 | } |
ab1f90f9 JN |
1950 | } |
1951 | ||
1952 | static void vlv_pre_enable_dp(struct intel_encoder *encoder) | |
a4fc5ed6 | 1953 | { |
2bd2ad64 | 1954 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1955 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
b2634017 | 1956 | struct drm_device *dev = encoder->base.dev; |
89b667f8 | 1957 | struct drm_i915_private *dev_priv = dev->dev_private; |
ab1f90f9 | 1958 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
e4607fcf | 1959 | enum dpio_channel port = vlv_dport_to_channel(dport); |
ab1f90f9 | 1960 | int pipe = intel_crtc->pipe; |
bf13e81b | 1961 | struct edp_power_seq power_seq; |
ab1f90f9 | 1962 | u32 val; |
a4fc5ed6 | 1963 | |
ab1f90f9 | 1964 | mutex_lock(&dev_priv->dpio_lock); |
89b667f8 | 1965 | |
ab3c759a | 1966 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
ab1f90f9 JN |
1967 | val = 0; |
1968 | if (pipe) | |
1969 | val |= (1<<21); | |
1970 | else | |
1971 | val &= ~(1<<21); | |
1972 | val |= 0x001000c4; | |
ab3c759a CML |
1973 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
1974 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); | |
1975 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); | |
89b667f8 | 1976 | |
ab1f90f9 JN |
1977 | mutex_unlock(&dev_priv->dpio_lock); |
1978 | ||
2cac613b ID |
1979 | if (is_edp(intel_dp)) { |
1980 | /* init power sequencer on this pipe and port */ | |
1981 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); | |
1982 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, | |
1983 | &power_seq); | |
1984 | } | |
bf13e81b | 1985 | |
ab1f90f9 JN |
1986 | intel_enable_dp(encoder); |
1987 | ||
e4607fcf | 1988 | vlv_wait_port_ready(dev_priv, dport); |
89b667f8 JB |
1989 | } |
1990 | ||
ecff4f3b | 1991 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) |
89b667f8 JB |
1992 | { |
1993 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1994 | struct drm_device *dev = encoder->base.dev; | |
1995 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5e69f97f CML |
1996 | struct intel_crtc *intel_crtc = |
1997 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 1998 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 1999 | int pipe = intel_crtc->pipe; |
89b667f8 | 2000 | |
8ac33ed3 DV |
2001 | intel_dp_prepare(encoder); |
2002 | ||
89b667f8 | 2003 | /* Program Tx lane resets to default */ |
0980a60f | 2004 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 2005 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
89b667f8 JB |
2006 | DPIO_PCS_TX_LANE2_RESET | |
2007 | DPIO_PCS_TX_LANE1_RESET); | |
ab3c759a | 2008 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
89b667f8 JB |
2009 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
2010 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | | |
2011 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | | |
2012 | DPIO_PCS_CLK_SOFT_RESET); | |
2013 | ||
2014 | /* Fix up inter-pair skew failure */ | |
ab3c759a CML |
2015 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
2016 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); | |
2017 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); | |
0980a60f | 2018 | mutex_unlock(&dev_priv->dpio_lock); |
a4fc5ed6 KP |
2019 | } |
2020 | ||
e4a1d846 CML |
2021 | static void chv_pre_enable_dp(struct intel_encoder *encoder) |
2022 | { | |
2023 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
2024 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
2025 | struct drm_device *dev = encoder->base.dev; | |
2026 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2027 | struct edp_power_seq power_seq; | |
2028 | struct intel_crtc *intel_crtc = | |
2029 | to_intel_crtc(encoder->base.crtc); | |
2030 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
2031 | int pipe = intel_crtc->pipe; | |
2032 | int data, i; | |
949c1d43 | 2033 | u32 val; |
e4a1d846 | 2034 | |
e4a1d846 | 2035 | mutex_lock(&dev_priv->dpio_lock); |
949c1d43 VS |
2036 | |
2037 | /* Deassert soft data lane reset*/ | |
97fd4d5c | 2038 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
d2152b25 | 2039 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
97fd4d5c VS |
2040 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
2041 | ||
2042 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); | |
2043 | val |= CHV_PCS_REQ_SOFTRESET_EN; | |
2044 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); | |
2045 | ||
2046 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); | |
2047 | val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
2048 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); | |
d2152b25 | 2049 | |
97fd4d5c | 2050 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); |
949c1d43 | 2051 | val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
97fd4d5c | 2052 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
949c1d43 VS |
2053 | |
2054 | /* Program Tx lane latency optimal setting*/ | |
e4a1d846 CML |
2055 | for (i = 0; i < 4; i++) { |
2056 | /* Set the latency optimal bit */ | |
2057 | data = (i == 1) ? 0x0 : 0x6; | |
2058 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i), | |
2059 | data << DPIO_FRC_LATENCY_SHFIT); | |
2060 | ||
2061 | /* Set the upar bit */ | |
2062 | data = (i == 1) ? 0x0 : 0x1; | |
2063 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), | |
2064 | data << DPIO_UPAR_SHIFT); | |
2065 | } | |
2066 | ||
2067 | /* Data lane stagger programming */ | |
2068 | /* FIXME: Fix up value only after power analysis */ | |
2069 | ||
2070 | mutex_unlock(&dev_priv->dpio_lock); | |
2071 | ||
2072 | if (is_edp(intel_dp)) { | |
2073 | /* init power sequencer on this pipe and port */ | |
2074 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); | |
2075 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, | |
2076 | &power_seq); | |
2077 | } | |
2078 | ||
2079 | intel_enable_dp(encoder); | |
2080 | ||
2081 | vlv_wait_port_ready(dev_priv, dport); | |
2082 | } | |
2083 | ||
a4fc5ed6 | 2084 | /* |
df0c237d JB |
2085 | * Native read with retry for link status and receiver capability reads for |
2086 | * cases where the sink may still be asleep. | |
9d1a1031 JN |
2087 | * |
2088 | * Sinks are *supposed* to come up within 1ms from an off state, but we're also | |
2089 | * supposed to retry 3 times per the spec. | |
a4fc5ed6 | 2090 | */ |
9d1a1031 JN |
2091 | static ssize_t |
2092 | intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset, | |
2093 | void *buffer, size_t size) | |
a4fc5ed6 | 2094 | { |
9d1a1031 JN |
2095 | ssize_t ret; |
2096 | int i; | |
61da5fab | 2097 | |
61da5fab | 2098 | for (i = 0; i < 3; i++) { |
9d1a1031 JN |
2099 | ret = drm_dp_dpcd_read(aux, offset, buffer, size); |
2100 | if (ret == size) | |
2101 | return ret; | |
61da5fab JB |
2102 | msleep(1); |
2103 | } | |
a4fc5ed6 | 2104 | |
9d1a1031 | 2105 | return ret; |
a4fc5ed6 KP |
2106 | } |
2107 | ||
2108 | /* | |
2109 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
2110 | * link status information | |
2111 | */ | |
2112 | static bool | |
93f62dad | 2113 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 | 2114 | { |
9d1a1031 JN |
2115 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
2116 | DP_LANE0_1_STATUS, | |
2117 | link_status, | |
2118 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; | |
a4fc5ed6 KP |
2119 | } |
2120 | ||
a4fc5ed6 KP |
2121 | /* |
2122 | * These are source-specific values; current Intel hardware supports | |
2123 | * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB | |
2124 | */ | |
a4fc5ed6 KP |
2125 | |
2126 | static uint8_t | |
1a2eb460 | 2127 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
a4fc5ed6 | 2128 | { |
30add22d | 2129 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
bc7d38a4 | 2130 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 2131 | |
8f93f4f1 | 2132 | if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev)) |
e2fa6fba | 2133 | return DP_TRAIN_VOLTAGE_SWING_1200; |
bc7d38a4 | 2134 | else if (IS_GEN7(dev) && port == PORT_A) |
1a2eb460 | 2135 | return DP_TRAIN_VOLTAGE_SWING_800; |
bc7d38a4 | 2136 | else if (HAS_PCH_CPT(dev) && port != PORT_A) |
1a2eb460 KP |
2137 | return DP_TRAIN_VOLTAGE_SWING_1200; |
2138 | else | |
2139 | return DP_TRAIN_VOLTAGE_SWING_800; | |
2140 | } | |
2141 | ||
2142 | static uint8_t | |
2143 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) | |
2144 | { | |
30add22d | 2145 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
bc7d38a4 | 2146 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 2147 | |
8f93f4f1 PZ |
2148 | if (IS_BROADWELL(dev)) { |
2149 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2150 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2151 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2152 | return DP_TRAIN_PRE_EMPHASIS_6; | |
2153 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2154 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
2155 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
2156 | default: | |
2157 | return DP_TRAIN_PRE_EMPHASIS_0; | |
2158 | } | |
2159 | } else if (IS_HASWELL(dev)) { | |
d6c0d722 PZ |
2160 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2161 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2162 | return DP_TRAIN_PRE_EMPHASIS_9_5; | |
2163 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2164 | return DP_TRAIN_PRE_EMPHASIS_6; | |
2165 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2166 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
2167 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
2168 | default: | |
2169 | return DP_TRAIN_PRE_EMPHASIS_0; | |
2170 | } | |
e2fa6fba P |
2171 | } else if (IS_VALLEYVIEW(dev)) { |
2172 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2173 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2174 | return DP_TRAIN_PRE_EMPHASIS_9_5; | |
2175 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2176 | return DP_TRAIN_PRE_EMPHASIS_6; | |
2177 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2178 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
2179 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
2180 | default: | |
2181 | return DP_TRAIN_PRE_EMPHASIS_0; | |
2182 | } | |
bc7d38a4 | 2183 | } else if (IS_GEN7(dev) && port == PORT_A) { |
1a2eb460 KP |
2184 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2185 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2186 | return DP_TRAIN_PRE_EMPHASIS_6; | |
2187 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2188 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2189 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
2190 | default: | |
2191 | return DP_TRAIN_PRE_EMPHASIS_0; | |
2192 | } | |
2193 | } else { | |
2194 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2195 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2196 | return DP_TRAIN_PRE_EMPHASIS_6; | |
2197 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2198 | return DP_TRAIN_PRE_EMPHASIS_6; | |
2199 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2200 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
2201 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
2202 | default: | |
2203 | return DP_TRAIN_PRE_EMPHASIS_0; | |
2204 | } | |
a4fc5ed6 KP |
2205 | } |
2206 | } | |
2207 | ||
e2fa6fba P |
2208 | static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) |
2209 | { | |
2210 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
2211 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2212 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
5e69f97f CML |
2213 | struct intel_crtc *intel_crtc = |
2214 | to_intel_crtc(dport->base.base.crtc); | |
e2fa6fba P |
2215 | unsigned long demph_reg_value, preemph_reg_value, |
2216 | uniqtranscale_reg_value; | |
2217 | uint8_t train_set = intel_dp->train_set[0]; | |
e4607fcf | 2218 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 2219 | int pipe = intel_crtc->pipe; |
e2fa6fba P |
2220 | |
2221 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
2222 | case DP_TRAIN_PRE_EMPHASIS_0: | |
2223 | preemph_reg_value = 0x0004000; | |
2224 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2225 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2226 | demph_reg_value = 0x2B405555; | |
2227 | uniqtranscale_reg_value = 0x552AB83A; | |
2228 | break; | |
2229 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2230 | demph_reg_value = 0x2B404040; | |
2231 | uniqtranscale_reg_value = 0x5548B83A; | |
2232 | break; | |
2233 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2234 | demph_reg_value = 0x2B245555; | |
2235 | uniqtranscale_reg_value = 0x5560B83A; | |
2236 | break; | |
2237 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
2238 | demph_reg_value = 0x2B405555; | |
2239 | uniqtranscale_reg_value = 0x5598DA3A; | |
2240 | break; | |
2241 | default: | |
2242 | return 0; | |
2243 | } | |
2244 | break; | |
2245 | case DP_TRAIN_PRE_EMPHASIS_3_5: | |
2246 | preemph_reg_value = 0x0002000; | |
2247 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2248 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2249 | demph_reg_value = 0x2B404040; | |
2250 | uniqtranscale_reg_value = 0x5552B83A; | |
2251 | break; | |
2252 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2253 | demph_reg_value = 0x2B404848; | |
2254 | uniqtranscale_reg_value = 0x5580B83A; | |
2255 | break; | |
2256 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2257 | demph_reg_value = 0x2B404040; | |
2258 | uniqtranscale_reg_value = 0x55ADDA3A; | |
2259 | break; | |
2260 | default: | |
2261 | return 0; | |
2262 | } | |
2263 | break; | |
2264 | case DP_TRAIN_PRE_EMPHASIS_6: | |
2265 | preemph_reg_value = 0x0000000; | |
2266 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2267 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2268 | demph_reg_value = 0x2B305555; | |
2269 | uniqtranscale_reg_value = 0x5570B83A; | |
2270 | break; | |
2271 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2272 | demph_reg_value = 0x2B2B4040; | |
2273 | uniqtranscale_reg_value = 0x55ADDA3A; | |
2274 | break; | |
2275 | default: | |
2276 | return 0; | |
2277 | } | |
2278 | break; | |
2279 | case DP_TRAIN_PRE_EMPHASIS_9_5: | |
2280 | preemph_reg_value = 0x0006000; | |
2281 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2282 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2283 | demph_reg_value = 0x1B405555; | |
2284 | uniqtranscale_reg_value = 0x55ADDA3A; | |
2285 | break; | |
2286 | default: | |
2287 | return 0; | |
2288 | } | |
2289 | break; | |
2290 | default: | |
2291 | return 0; | |
2292 | } | |
2293 | ||
0980a60f | 2294 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a CML |
2295 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); |
2296 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); | |
2297 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), | |
e2fa6fba | 2298 | uniqtranscale_reg_value); |
ab3c759a CML |
2299 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); |
2300 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); | |
2301 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); | |
2302 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); | |
0980a60f | 2303 | mutex_unlock(&dev_priv->dpio_lock); |
e2fa6fba P |
2304 | |
2305 | return 0; | |
2306 | } | |
2307 | ||
e4a1d846 CML |
2308 | static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp) |
2309 | { | |
2310 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
2311 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2312 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
2313 | struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc); | |
f72df8db | 2314 | u32 deemph_reg_value, margin_reg_value, val; |
e4a1d846 CML |
2315 | uint8_t train_set = intel_dp->train_set[0]; |
2316 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
f72df8db VS |
2317 | enum pipe pipe = intel_crtc->pipe; |
2318 | int i; | |
e4a1d846 CML |
2319 | |
2320 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
2321 | case DP_TRAIN_PRE_EMPHASIS_0: | |
2322 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2323 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2324 | deemph_reg_value = 128; | |
2325 | margin_reg_value = 52; | |
2326 | break; | |
2327 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2328 | deemph_reg_value = 128; | |
2329 | margin_reg_value = 77; | |
2330 | break; | |
2331 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2332 | deemph_reg_value = 128; | |
2333 | margin_reg_value = 102; | |
2334 | break; | |
2335 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
2336 | deemph_reg_value = 128; | |
2337 | margin_reg_value = 154; | |
2338 | /* FIXME extra to set for 1200 */ | |
2339 | break; | |
2340 | default: | |
2341 | return 0; | |
2342 | } | |
2343 | break; | |
2344 | case DP_TRAIN_PRE_EMPHASIS_3_5: | |
2345 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2346 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2347 | deemph_reg_value = 85; | |
2348 | margin_reg_value = 78; | |
2349 | break; | |
2350 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2351 | deemph_reg_value = 85; | |
2352 | margin_reg_value = 116; | |
2353 | break; | |
2354 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2355 | deemph_reg_value = 85; | |
2356 | margin_reg_value = 154; | |
2357 | break; | |
2358 | default: | |
2359 | return 0; | |
2360 | } | |
2361 | break; | |
2362 | case DP_TRAIN_PRE_EMPHASIS_6: | |
2363 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2364 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2365 | deemph_reg_value = 64; | |
2366 | margin_reg_value = 104; | |
2367 | break; | |
2368 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2369 | deemph_reg_value = 64; | |
2370 | margin_reg_value = 154; | |
2371 | break; | |
2372 | default: | |
2373 | return 0; | |
2374 | } | |
2375 | break; | |
2376 | case DP_TRAIN_PRE_EMPHASIS_9_5: | |
2377 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2378 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2379 | deemph_reg_value = 43; | |
2380 | margin_reg_value = 154; | |
2381 | break; | |
2382 | default: | |
2383 | return 0; | |
2384 | } | |
2385 | break; | |
2386 | default: | |
2387 | return 0; | |
2388 | } | |
2389 | ||
2390 | mutex_lock(&dev_priv->dpio_lock); | |
2391 | ||
2392 | /* Clear calc init */ | |
1966e59e VS |
2393 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
2394 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); | |
2395 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); | |
2396 | ||
2397 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); | |
2398 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); | |
2399 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); | |
e4a1d846 CML |
2400 | |
2401 | /* Program swing deemph */ | |
f72df8db VS |
2402 | for (i = 0; i < 4; i++) { |
2403 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); | |
2404 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; | |
2405 | val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; | |
2406 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); | |
2407 | } | |
e4a1d846 CML |
2408 | |
2409 | /* Program swing margin */ | |
f72df8db VS |
2410 | for (i = 0; i < 4; i++) { |
2411 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); | |
2412 | val &= ~DPIO_SWING_MARGIN_MASK; | |
2413 | val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT; | |
2414 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); | |
2415 | } | |
e4a1d846 CML |
2416 | |
2417 | /* Disable unique transition scale */ | |
f72df8db VS |
2418 | for (i = 0; i < 4; i++) { |
2419 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); | |
2420 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; | |
2421 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); | |
2422 | } | |
e4a1d846 CML |
2423 | |
2424 | if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK) | |
2425 | == DP_TRAIN_PRE_EMPHASIS_0) && | |
2426 | ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK) | |
2427 | == DP_TRAIN_VOLTAGE_SWING_1200)) { | |
2428 | ||
2429 | /* | |
2430 | * The document said it needs to set bit 27 for ch0 and bit 26 | |
2431 | * for ch1. Might be a typo in the doc. | |
2432 | * For now, for this unique transition scale selection, set bit | |
2433 | * 27 for ch0 and ch1. | |
2434 | */ | |
f72df8db VS |
2435 | for (i = 0; i < 4; i++) { |
2436 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); | |
2437 | val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; | |
2438 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); | |
2439 | } | |
e4a1d846 | 2440 | |
f72df8db VS |
2441 | for (i = 0; i < 4; i++) { |
2442 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); | |
2443 | val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); | |
2444 | val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT); | |
2445 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); | |
2446 | } | |
e4a1d846 CML |
2447 | } |
2448 | ||
2449 | /* Start swing calculation */ | |
1966e59e VS |
2450 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
2451 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; | |
2452 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); | |
2453 | ||
2454 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); | |
2455 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; | |
2456 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); | |
e4a1d846 CML |
2457 | |
2458 | /* LRC Bypass */ | |
2459 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); | |
2460 | val |= DPIO_LRC_BYPASS; | |
2461 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); | |
2462 | ||
2463 | mutex_unlock(&dev_priv->dpio_lock); | |
2464 | ||
2465 | return 0; | |
2466 | } | |
2467 | ||
a4fc5ed6 | 2468 | static void |
0301b3ac JN |
2469 | intel_get_adjust_train(struct intel_dp *intel_dp, |
2470 | const uint8_t link_status[DP_LINK_STATUS_SIZE]) | |
a4fc5ed6 KP |
2471 | { |
2472 | uint8_t v = 0; | |
2473 | uint8_t p = 0; | |
2474 | int lane; | |
1a2eb460 KP |
2475 | uint8_t voltage_max; |
2476 | uint8_t preemph_max; | |
a4fc5ed6 | 2477 | |
33a34e4e | 2478 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
0f037bde DV |
2479 | uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); |
2480 | uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); | |
a4fc5ed6 KP |
2481 | |
2482 | if (this_v > v) | |
2483 | v = this_v; | |
2484 | if (this_p > p) | |
2485 | p = this_p; | |
2486 | } | |
2487 | ||
1a2eb460 | 2488 | voltage_max = intel_dp_voltage_max(intel_dp); |
417e822d KP |
2489 | if (v >= voltage_max) |
2490 | v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; | |
a4fc5ed6 | 2491 | |
1a2eb460 KP |
2492 | preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); |
2493 | if (p >= preemph_max) | |
2494 | p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; | |
a4fc5ed6 KP |
2495 | |
2496 | for (lane = 0; lane < 4; lane++) | |
33a34e4e | 2497 | intel_dp->train_set[lane] = v | p; |
a4fc5ed6 KP |
2498 | } |
2499 | ||
2500 | static uint32_t | |
f0a3424e | 2501 | intel_gen4_signal_levels(uint8_t train_set) |
a4fc5ed6 | 2502 | { |
3cf2efb1 | 2503 | uint32_t signal_levels = 0; |
a4fc5ed6 | 2504 | |
3cf2efb1 | 2505 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
a4fc5ed6 KP |
2506 | case DP_TRAIN_VOLTAGE_SWING_400: |
2507 | default: | |
2508 | signal_levels |= DP_VOLTAGE_0_4; | |
2509 | break; | |
2510 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2511 | signal_levels |= DP_VOLTAGE_0_6; | |
2512 | break; | |
2513 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2514 | signal_levels |= DP_VOLTAGE_0_8; | |
2515 | break; | |
2516 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
2517 | signal_levels |= DP_VOLTAGE_1_2; | |
2518 | break; | |
2519 | } | |
3cf2efb1 | 2520 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
a4fc5ed6 KP |
2521 | case DP_TRAIN_PRE_EMPHASIS_0: |
2522 | default: | |
2523 | signal_levels |= DP_PRE_EMPHASIS_0; | |
2524 | break; | |
2525 | case DP_TRAIN_PRE_EMPHASIS_3_5: | |
2526 | signal_levels |= DP_PRE_EMPHASIS_3_5; | |
2527 | break; | |
2528 | case DP_TRAIN_PRE_EMPHASIS_6: | |
2529 | signal_levels |= DP_PRE_EMPHASIS_6; | |
2530 | break; | |
2531 | case DP_TRAIN_PRE_EMPHASIS_9_5: | |
2532 | signal_levels |= DP_PRE_EMPHASIS_9_5; | |
2533 | break; | |
2534 | } | |
2535 | return signal_levels; | |
2536 | } | |
2537 | ||
e3421a18 ZW |
2538 | /* Gen6's DP voltage swing and pre-emphasis control */ |
2539 | static uint32_t | |
2540 | intel_gen6_edp_signal_levels(uint8_t train_set) | |
2541 | { | |
3c5a62b5 YL |
2542 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
2543 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
2544 | switch (signal_levels) { | |
e3421a18 | 2545 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
2546 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
2547 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
2548 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2549 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; | |
e3421a18 | 2550 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
3c5a62b5 YL |
2551 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
2552 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; | |
e3421a18 | 2553 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
3c5a62b5 YL |
2554 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
2555 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; | |
e3421a18 | 2556 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
2557 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: |
2558 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; | |
e3421a18 | 2559 | default: |
3c5a62b5 YL |
2560 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
2561 | "0x%x\n", signal_levels); | |
2562 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
e3421a18 ZW |
2563 | } |
2564 | } | |
2565 | ||
1a2eb460 KP |
2566 | /* Gen7's DP voltage swing and pre-emphasis control */ |
2567 | static uint32_t | |
2568 | intel_gen7_edp_signal_levels(uint8_t train_set) | |
2569 | { | |
2570 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | | |
2571 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
2572 | switch (signal_levels) { | |
2573 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: | |
2574 | return EDP_LINK_TRAIN_400MV_0DB_IVB; | |
2575 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2576 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; | |
2577 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: | |
2578 | return EDP_LINK_TRAIN_400MV_6DB_IVB; | |
2579 | ||
2580 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: | |
2581 | return EDP_LINK_TRAIN_600MV_0DB_IVB; | |
2582 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2583 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; | |
2584 | ||
2585 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: | |
2586 | return EDP_LINK_TRAIN_800MV_0DB_IVB; | |
2587 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2588 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; | |
2589 | ||
2590 | default: | |
2591 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
2592 | "0x%x\n", signal_levels); | |
2593 | return EDP_LINK_TRAIN_500MV_0DB_IVB; | |
2594 | } | |
2595 | } | |
2596 | ||
d6c0d722 PZ |
2597 | /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ |
2598 | static uint32_t | |
f0a3424e | 2599 | intel_hsw_signal_levels(uint8_t train_set) |
a4fc5ed6 | 2600 | { |
d6c0d722 PZ |
2601 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
2602 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
2603 | switch (signal_levels) { | |
2604 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: | |
2605 | return DDI_BUF_EMP_400MV_0DB_HSW; | |
2606 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2607 | return DDI_BUF_EMP_400MV_3_5DB_HSW; | |
2608 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: | |
2609 | return DDI_BUF_EMP_400MV_6DB_HSW; | |
2610 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5: | |
2611 | return DDI_BUF_EMP_400MV_9_5DB_HSW; | |
a4fc5ed6 | 2612 | |
d6c0d722 PZ |
2613 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
2614 | return DDI_BUF_EMP_600MV_0DB_HSW; | |
2615 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2616 | return DDI_BUF_EMP_600MV_3_5DB_HSW; | |
2617 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: | |
2618 | return DDI_BUF_EMP_600MV_6DB_HSW; | |
a4fc5ed6 | 2619 | |
d6c0d722 PZ |
2620 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
2621 | return DDI_BUF_EMP_800MV_0DB_HSW; | |
2622 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2623 | return DDI_BUF_EMP_800MV_3_5DB_HSW; | |
2624 | default: | |
2625 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
2626 | "0x%x\n", signal_levels); | |
2627 | return DDI_BUF_EMP_400MV_0DB_HSW; | |
a4fc5ed6 | 2628 | } |
a4fc5ed6 KP |
2629 | } |
2630 | ||
8f93f4f1 PZ |
2631 | static uint32_t |
2632 | intel_bdw_signal_levels(uint8_t train_set) | |
2633 | { | |
2634 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | | |
2635 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
2636 | switch (signal_levels) { | |
2637 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: | |
2638 | return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */ | |
2639 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2640 | return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */ | |
2641 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: | |
2642 | return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */ | |
2643 | ||
2644 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: | |
2645 | return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */ | |
2646 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2647 | return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */ | |
2648 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: | |
2649 | return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */ | |
2650 | ||
2651 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: | |
2652 | return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */ | |
2653 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2654 | return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */ | |
2655 | ||
2656 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: | |
2657 | return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */ | |
2658 | ||
2659 | default: | |
2660 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
2661 | "0x%x\n", signal_levels); | |
2662 | return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */ | |
2663 | } | |
2664 | } | |
2665 | ||
f0a3424e PZ |
2666 | /* Properly updates "DP" with the correct signal levels. */ |
2667 | static void | |
2668 | intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) | |
2669 | { | |
2670 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
bc7d38a4 | 2671 | enum port port = intel_dig_port->port; |
f0a3424e PZ |
2672 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2673 | uint32_t signal_levels, mask; | |
2674 | uint8_t train_set = intel_dp->train_set[0]; | |
2675 | ||
8f93f4f1 PZ |
2676 | if (IS_BROADWELL(dev)) { |
2677 | signal_levels = intel_bdw_signal_levels(train_set); | |
2678 | mask = DDI_BUF_EMP_MASK; | |
2679 | } else if (IS_HASWELL(dev)) { | |
f0a3424e PZ |
2680 | signal_levels = intel_hsw_signal_levels(train_set); |
2681 | mask = DDI_BUF_EMP_MASK; | |
e4a1d846 CML |
2682 | } else if (IS_CHERRYVIEW(dev)) { |
2683 | signal_levels = intel_chv_signal_levels(intel_dp); | |
2684 | mask = 0; | |
e2fa6fba P |
2685 | } else if (IS_VALLEYVIEW(dev)) { |
2686 | signal_levels = intel_vlv_signal_levels(intel_dp); | |
2687 | mask = 0; | |
bc7d38a4 | 2688 | } else if (IS_GEN7(dev) && port == PORT_A) { |
f0a3424e PZ |
2689 | signal_levels = intel_gen7_edp_signal_levels(train_set); |
2690 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; | |
bc7d38a4 | 2691 | } else if (IS_GEN6(dev) && port == PORT_A) { |
f0a3424e PZ |
2692 | signal_levels = intel_gen6_edp_signal_levels(train_set); |
2693 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; | |
2694 | } else { | |
2695 | signal_levels = intel_gen4_signal_levels(train_set); | |
2696 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; | |
2697 | } | |
2698 | ||
2699 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); | |
2700 | ||
2701 | *DP = (*DP & ~mask) | signal_levels; | |
2702 | } | |
2703 | ||
a4fc5ed6 | 2704 | static bool |
ea5b213a | 2705 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
70aff66c | 2706 | uint32_t *DP, |
58e10eb9 | 2707 | uint8_t dp_train_pat) |
a4fc5ed6 | 2708 | { |
174edf1f PZ |
2709 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2710 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
a4fc5ed6 | 2711 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 2712 | enum port port = intel_dig_port->port; |
2cdfe6c8 JN |
2713 | uint8_t buf[sizeof(intel_dp->train_set) + 1]; |
2714 | int ret, len; | |
a4fc5ed6 | 2715 | |
22b8bf17 | 2716 | if (HAS_DDI(dev)) { |
3ab9c637 | 2717 | uint32_t temp = I915_READ(DP_TP_CTL(port)); |
d6c0d722 PZ |
2718 | |
2719 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) | |
2720 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; | |
2721 | else | |
2722 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; | |
2723 | ||
2724 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
2725 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2726 | case DP_TRAINING_PATTERN_DISABLE: | |
d6c0d722 PZ |
2727 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; |
2728 | ||
2729 | break; | |
2730 | case DP_TRAINING_PATTERN_1: | |
2731 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
2732 | break; | |
2733 | case DP_TRAINING_PATTERN_2: | |
2734 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; | |
2735 | break; | |
2736 | case DP_TRAINING_PATTERN_3: | |
2737 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; | |
2738 | break; | |
2739 | } | |
174edf1f | 2740 | I915_WRITE(DP_TP_CTL(port), temp); |
d6c0d722 | 2741 | |
bc7d38a4 | 2742 | } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { |
70aff66c | 2743 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
47ea7542 PZ |
2744 | |
2745 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2746 | case DP_TRAINING_PATTERN_DISABLE: | |
70aff66c | 2747 | *DP |= DP_LINK_TRAIN_OFF_CPT; |
47ea7542 PZ |
2748 | break; |
2749 | case DP_TRAINING_PATTERN_1: | |
70aff66c | 2750 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; |
47ea7542 PZ |
2751 | break; |
2752 | case DP_TRAINING_PATTERN_2: | |
70aff66c | 2753 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
47ea7542 PZ |
2754 | break; |
2755 | case DP_TRAINING_PATTERN_3: | |
2756 | DRM_ERROR("DP training pattern 3 not supported\n"); | |
70aff66c | 2757 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
47ea7542 PZ |
2758 | break; |
2759 | } | |
2760 | ||
2761 | } else { | |
70aff66c | 2762 | *DP &= ~DP_LINK_TRAIN_MASK; |
47ea7542 PZ |
2763 | |
2764 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2765 | case DP_TRAINING_PATTERN_DISABLE: | |
70aff66c | 2766 | *DP |= DP_LINK_TRAIN_OFF; |
47ea7542 PZ |
2767 | break; |
2768 | case DP_TRAINING_PATTERN_1: | |
70aff66c | 2769 | *DP |= DP_LINK_TRAIN_PAT_1; |
47ea7542 PZ |
2770 | break; |
2771 | case DP_TRAINING_PATTERN_2: | |
70aff66c | 2772 | *DP |= DP_LINK_TRAIN_PAT_2; |
47ea7542 PZ |
2773 | break; |
2774 | case DP_TRAINING_PATTERN_3: | |
2775 | DRM_ERROR("DP training pattern 3 not supported\n"); | |
70aff66c | 2776 | *DP |= DP_LINK_TRAIN_PAT_2; |
47ea7542 PZ |
2777 | break; |
2778 | } | |
2779 | } | |
2780 | ||
70aff66c | 2781 | I915_WRITE(intel_dp->output_reg, *DP); |
ea5b213a | 2782 | POSTING_READ(intel_dp->output_reg); |
a4fc5ed6 | 2783 | |
2cdfe6c8 JN |
2784 | buf[0] = dp_train_pat; |
2785 | if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == | |
47ea7542 | 2786 | DP_TRAINING_PATTERN_DISABLE) { |
2cdfe6c8 JN |
2787 | /* don't write DP_TRAINING_LANEx_SET on disable */ |
2788 | len = 1; | |
2789 | } else { | |
2790 | /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ | |
2791 | memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); | |
2792 | len = intel_dp->lane_count + 1; | |
47ea7542 | 2793 | } |
a4fc5ed6 | 2794 | |
9d1a1031 JN |
2795 | ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET, |
2796 | buf, len); | |
2cdfe6c8 JN |
2797 | |
2798 | return ret == len; | |
a4fc5ed6 KP |
2799 | } |
2800 | ||
70aff66c JN |
2801 | static bool |
2802 | intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP, | |
2803 | uint8_t dp_train_pat) | |
2804 | { | |
953d22e8 | 2805 | memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); |
70aff66c JN |
2806 | intel_dp_set_signal_levels(intel_dp, DP); |
2807 | return intel_dp_set_link_train(intel_dp, DP, dp_train_pat); | |
2808 | } | |
2809 | ||
2810 | static bool | |
2811 | intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP, | |
0301b3ac | 2812 | const uint8_t link_status[DP_LINK_STATUS_SIZE]) |
70aff66c JN |
2813 | { |
2814 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2815 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
2816 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2817 | int ret; | |
2818 | ||
2819 | intel_get_adjust_train(intel_dp, link_status); | |
2820 | intel_dp_set_signal_levels(intel_dp, DP); | |
2821 | ||
2822 | I915_WRITE(intel_dp->output_reg, *DP); | |
2823 | POSTING_READ(intel_dp->output_reg); | |
2824 | ||
9d1a1031 JN |
2825 | ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, |
2826 | intel_dp->train_set, intel_dp->lane_count); | |
70aff66c JN |
2827 | |
2828 | return ret == intel_dp->lane_count; | |
2829 | } | |
2830 | ||
3ab9c637 ID |
2831 | static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
2832 | { | |
2833 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2834 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
2835 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2836 | enum port port = intel_dig_port->port; | |
2837 | uint32_t val; | |
2838 | ||
2839 | if (!HAS_DDI(dev)) | |
2840 | return; | |
2841 | ||
2842 | val = I915_READ(DP_TP_CTL(port)); | |
2843 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
2844 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; | |
2845 | I915_WRITE(DP_TP_CTL(port), val); | |
2846 | ||
2847 | /* | |
2848 | * On PORT_A we can have only eDP in SST mode. There the only reason | |
2849 | * we need to set idle transmission mode is to work around a HW issue | |
2850 | * where we enable the pipe while not in idle link-training mode. | |
2851 | * In this case there is requirement to wait for a minimum number of | |
2852 | * idle patterns to be sent. | |
2853 | */ | |
2854 | if (port == PORT_A) | |
2855 | return; | |
2856 | ||
2857 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), | |
2858 | 1)) | |
2859 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); | |
2860 | } | |
2861 | ||
33a34e4e | 2862 | /* Enable corresponding port and start training pattern 1 */ |
c19b0669 | 2863 | void |
33a34e4e | 2864 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
a4fc5ed6 | 2865 | { |
da63a9f2 | 2866 | struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; |
c19b0669 | 2867 | struct drm_device *dev = encoder->dev; |
a4fc5ed6 KP |
2868 | int i; |
2869 | uint8_t voltage; | |
cdb0e95b | 2870 | int voltage_tries, loop_tries; |
ea5b213a | 2871 | uint32_t DP = intel_dp->DP; |
6aba5b6c | 2872 | uint8_t link_config[2]; |
a4fc5ed6 | 2873 | |
affa9354 | 2874 | if (HAS_DDI(dev)) |
c19b0669 PZ |
2875 | intel_ddi_prepare_link_retrain(encoder); |
2876 | ||
3cf2efb1 | 2877 | /* Write the link configuration data */ |
6aba5b6c JN |
2878 | link_config[0] = intel_dp->link_bw; |
2879 | link_config[1] = intel_dp->lane_count; | |
2880 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) | |
2881 | link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; | |
9d1a1031 | 2882 | drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); |
6aba5b6c JN |
2883 | |
2884 | link_config[0] = 0; | |
2885 | link_config[1] = DP_SET_ANSI_8B10B; | |
9d1a1031 | 2886 | drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); |
a4fc5ed6 KP |
2887 | |
2888 | DP |= DP_PORT_EN; | |
1a2eb460 | 2889 | |
70aff66c JN |
2890 | /* clock recovery */ |
2891 | if (!intel_dp_reset_link_train(intel_dp, &DP, | |
2892 | DP_TRAINING_PATTERN_1 | | |
2893 | DP_LINK_SCRAMBLING_DISABLE)) { | |
2894 | DRM_ERROR("failed to enable link training\n"); | |
2895 | return; | |
2896 | } | |
2897 | ||
a4fc5ed6 | 2898 | voltage = 0xff; |
cdb0e95b KP |
2899 | voltage_tries = 0; |
2900 | loop_tries = 0; | |
a4fc5ed6 | 2901 | for (;;) { |
70aff66c | 2902 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
a4fc5ed6 | 2903 | |
a7c9655f | 2904 | drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); |
93f62dad KP |
2905 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
2906 | DRM_ERROR("failed to get link status\n"); | |
a4fc5ed6 | 2907 | break; |
93f62dad | 2908 | } |
a4fc5ed6 | 2909 | |
01916270 | 2910 | if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
93f62dad | 2911 | DRM_DEBUG_KMS("clock recovery OK\n"); |
3cf2efb1 CW |
2912 | break; |
2913 | } | |
2914 | ||
2915 | /* Check to see if we've tried the max voltage */ | |
2916 | for (i = 0; i < intel_dp->lane_count; i++) | |
2917 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) | |
a4fc5ed6 | 2918 | break; |
3b4f819d | 2919 | if (i == intel_dp->lane_count) { |
b06fbda3 DV |
2920 | ++loop_tries; |
2921 | if (loop_tries == 5) { | |
3def84b3 | 2922 | DRM_ERROR("too many full retries, give up\n"); |
cdb0e95b KP |
2923 | break; |
2924 | } | |
70aff66c JN |
2925 | intel_dp_reset_link_train(intel_dp, &DP, |
2926 | DP_TRAINING_PATTERN_1 | | |
2927 | DP_LINK_SCRAMBLING_DISABLE); | |
cdb0e95b KP |
2928 | voltage_tries = 0; |
2929 | continue; | |
2930 | } | |
a4fc5ed6 | 2931 | |
3cf2efb1 | 2932 | /* Check to see if we've tried the same voltage 5 times */ |
b06fbda3 | 2933 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
24773670 | 2934 | ++voltage_tries; |
b06fbda3 | 2935 | if (voltage_tries == 5) { |
3def84b3 | 2936 | DRM_ERROR("too many voltage retries, give up\n"); |
b06fbda3 DV |
2937 | break; |
2938 | } | |
2939 | } else | |
2940 | voltage_tries = 0; | |
2941 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; | |
a4fc5ed6 | 2942 | |
70aff66c JN |
2943 | /* Update training set as requested by target */ |
2944 | if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { | |
2945 | DRM_ERROR("failed to update link training\n"); | |
2946 | break; | |
2947 | } | |
a4fc5ed6 KP |
2948 | } |
2949 | ||
33a34e4e JB |
2950 | intel_dp->DP = DP; |
2951 | } | |
2952 | ||
c19b0669 | 2953 | void |
33a34e4e JB |
2954 | intel_dp_complete_link_train(struct intel_dp *intel_dp) |
2955 | { | |
33a34e4e | 2956 | bool channel_eq = false; |
37f80975 | 2957 | int tries, cr_tries; |
33a34e4e | 2958 | uint32_t DP = intel_dp->DP; |
06ea66b6 TP |
2959 | uint32_t training_pattern = DP_TRAINING_PATTERN_2; |
2960 | ||
2961 | /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/ | |
2962 | if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) | |
2963 | training_pattern = DP_TRAINING_PATTERN_3; | |
33a34e4e | 2964 | |
a4fc5ed6 | 2965 | /* channel equalization */ |
70aff66c | 2966 | if (!intel_dp_set_link_train(intel_dp, &DP, |
06ea66b6 | 2967 | training_pattern | |
70aff66c JN |
2968 | DP_LINK_SCRAMBLING_DISABLE)) { |
2969 | DRM_ERROR("failed to start channel equalization\n"); | |
2970 | return; | |
2971 | } | |
2972 | ||
a4fc5ed6 | 2973 | tries = 0; |
37f80975 | 2974 | cr_tries = 0; |
a4fc5ed6 KP |
2975 | channel_eq = false; |
2976 | for (;;) { | |
70aff66c | 2977 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
e3421a18 | 2978 | |
37f80975 JB |
2979 | if (cr_tries > 5) { |
2980 | DRM_ERROR("failed to train DP, aborting\n"); | |
37f80975 JB |
2981 | break; |
2982 | } | |
2983 | ||
a7c9655f | 2984 | drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); |
70aff66c JN |
2985 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
2986 | DRM_ERROR("failed to get link status\n"); | |
a4fc5ed6 | 2987 | break; |
70aff66c | 2988 | } |
a4fc5ed6 | 2989 | |
37f80975 | 2990 | /* Make sure clock is still ok */ |
01916270 | 2991 | if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
37f80975 | 2992 | intel_dp_start_link_train(intel_dp); |
70aff66c | 2993 | intel_dp_set_link_train(intel_dp, &DP, |
06ea66b6 | 2994 | training_pattern | |
70aff66c | 2995 | DP_LINK_SCRAMBLING_DISABLE); |
37f80975 JB |
2996 | cr_tries++; |
2997 | continue; | |
2998 | } | |
2999 | ||
1ffdff13 | 3000 | if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
3cf2efb1 CW |
3001 | channel_eq = true; |
3002 | break; | |
3003 | } | |
a4fc5ed6 | 3004 | |
37f80975 JB |
3005 | /* Try 5 times, then try clock recovery if that fails */ |
3006 | if (tries > 5) { | |
3007 | intel_dp_link_down(intel_dp); | |
3008 | intel_dp_start_link_train(intel_dp); | |
70aff66c | 3009 | intel_dp_set_link_train(intel_dp, &DP, |
06ea66b6 | 3010 | training_pattern | |
70aff66c | 3011 | DP_LINK_SCRAMBLING_DISABLE); |
37f80975 JB |
3012 | tries = 0; |
3013 | cr_tries++; | |
3014 | continue; | |
3015 | } | |
a4fc5ed6 | 3016 | |
70aff66c JN |
3017 | /* Update training set as requested by target */ |
3018 | if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { | |
3019 | DRM_ERROR("failed to update link training\n"); | |
3020 | break; | |
3021 | } | |
3cf2efb1 | 3022 | ++tries; |
869184a6 | 3023 | } |
3cf2efb1 | 3024 | |
3ab9c637 ID |
3025 | intel_dp_set_idle_link_train(intel_dp); |
3026 | ||
3027 | intel_dp->DP = DP; | |
3028 | ||
d6c0d722 | 3029 | if (channel_eq) |
07f42258 | 3030 | DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); |
d6c0d722 | 3031 | |
3ab9c637 ID |
3032 | } |
3033 | ||
3034 | void intel_dp_stop_link_train(struct intel_dp *intel_dp) | |
3035 | { | |
70aff66c | 3036 | intel_dp_set_link_train(intel_dp, &intel_dp->DP, |
3ab9c637 | 3037 | DP_TRAINING_PATTERN_DISABLE); |
a4fc5ed6 KP |
3038 | } |
3039 | ||
3040 | static void | |
ea5b213a | 3041 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 3042 | { |
da63a9f2 | 3043 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
bc7d38a4 | 3044 | enum port port = intel_dig_port->port; |
da63a9f2 | 3045 | struct drm_device *dev = intel_dig_port->base.base.dev; |
a4fc5ed6 | 3046 | struct drm_i915_private *dev_priv = dev->dev_private; |
ab527efc DV |
3047 | struct intel_crtc *intel_crtc = |
3048 | to_intel_crtc(intel_dig_port->base.base.crtc); | |
ea5b213a | 3049 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 3050 | |
bc76e320 | 3051 | if (WARN_ON(HAS_DDI(dev))) |
c19b0669 PZ |
3052 | return; |
3053 | ||
0c33d8d7 | 3054 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
1b39d6f3 CW |
3055 | return; |
3056 | ||
28c97730 | 3057 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 3058 | |
bc7d38a4 | 3059 | if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { |
e3421a18 | 3060 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
ea5b213a | 3061 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
e3421a18 ZW |
3062 | } else { |
3063 | DP &= ~DP_LINK_TRAIN_MASK; | |
ea5b213a | 3064 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
e3421a18 | 3065 | } |
fe255d00 | 3066 | POSTING_READ(intel_dp->output_reg); |
5eb08b69 | 3067 | |
493a7081 | 3068 | if (HAS_PCH_IBX(dev) && |
1b39d6f3 | 3069 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { |
da63a9f2 | 3070 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
31acbcc4 | 3071 | |
5bddd17f EA |
3072 | /* Hardware workaround: leaving our transcoder select |
3073 | * set to transcoder B while it's off will prevent the | |
3074 | * corresponding HDMI output on transcoder A. | |
3075 | * | |
3076 | * Combine this with another hardware workaround: | |
3077 | * transcoder select bit can only be cleared while the | |
3078 | * port is enabled. | |
3079 | */ | |
3080 | DP &= ~DP_PIPEB_SELECT; | |
3081 | I915_WRITE(intel_dp->output_reg, DP); | |
3082 | ||
3083 | /* Changes to enable or select take place the vblank | |
3084 | * after being written. | |
3085 | */ | |
ff50afe9 DV |
3086 | if (WARN_ON(crtc == NULL)) { |
3087 | /* We should never try to disable a port without a crtc | |
3088 | * attached. For paranoia keep the code around for a | |
3089 | * bit. */ | |
31acbcc4 CW |
3090 | POSTING_READ(intel_dp->output_reg); |
3091 | msleep(50); | |
3092 | } else | |
ab527efc | 3093 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
5bddd17f EA |
3094 | } |
3095 | ||
832afda6 | 3096 | DP &= ~DP_AUDIO_OUTPUT_ENABLE; |
ea5b213a CW |
3097 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
3098 | POSTING_READ(intel_dp->output_reg); | |
f01eca2e | 3099 | msleep(intel_dp->panel_power_down_delay); |
a4fc5ed6 KP |
3100 | } |
3101 | ||
26d61aad KP |
3102 | static bool |
3103 | intel_dp_get_dpcd(struct intel_dp *intel_dp) | |
92fd8fd1 | 3104 | { |
a031d709 RV |
3105 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
3106 | struct drm_device *dev = dig_port->base.base.dev; | |
3107 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3108 | ||
577c7a50 DL |
3109 | char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; |
3110 | ||
9d1a1031 JN |
3111 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, |
3112 | sizeof(intel_dp->dpcd)) < 0) | |
edb39244 | 3113 | return false; /* aux transfer failed */ |
92fd8fd1 | 3114 | |
577c7a50 DL |
3115 | hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd), |
3116 | 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false); | |
3117 | DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump); | |
3118 | ||
edb39244 AJ |
3119 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) |
3120 | return false; /* DPCD not present */ | |
3121 | ||
2293bb5c SK |
3122 | /* Check if the panel supports PSR */ |
3123 | memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); | |
50003939 | 3124 | if (is_edp(intel_dp)) { |
9d1a1031 JN |
3125 | intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT, |
3126 | intel_dp->psr_dpcd, | |
3127 | sizeof(intel_dp->psr_dpcd)); | |
a031d709 RV |
3128 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { |
3129 | dev_priv->psr.sink_support = true; | |
50003939 | 3130 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); |
a031d709 | 3131 | } |
50003939 JN |
3132 | } |
3133 | ||
06ea66b6 TP |
3134 | /* Training Pattern 3 support */ |
3135 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 && | |
3136 | intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) { | |
3137 | intel_dp->use_tps3 = true; | |
3138 | DRM_DEBUG_KMS("Displayport TPS3 supported"); | |
3139 | } else | |
3140 | intel_dp->use_tps3 = false; | |
3141 | ||
edb39244 AJ |
3142 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
3143 | DP_DWN_STRM_PORT_PRESENT)) | |
3144 | return true; /* native DP sink */ | |
3145 | ||
3146 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) | |
3147 | return true; /* no per-port downstream info */ | |
3148 | ||
9d1a1031 JN |
3149 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
3150 | intel_dp->downstream_ports, | |
3151 | DP_MAX_DOWNSTREAM_PORTS) < 0) | |
edb39244 AJ |
3152 | return false; /* downstream port status fetch failed */ |
3153 | ||
3154 | return true; | |
92fd8fd1 KP |
3155 | } |
3156 | ||
0d198328 AJ |
3157 | static void |
3158 | intel_dp_probe_oui(struct intel_dp *intel_dp) | |
3159 | { | |
3160 | u8 buf[3]; | |
3161 | ||
3162 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) | |
3163 | return; | |
3164 | ||
24f3e092 | 3165 | intel_edp_panel_vdd_on(intel_dp); |
351cfc34 | 3166 | |
9d1a1031 | 3167 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) |
0d198328 AJ |
3168 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
3169 | buf[0], buf[1], buf[2]); | |
3170 | ||
9d1a1031 | 3171 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) |
0d198328 AJ |
3172 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
3173 | buf[0], buf[1], buf[2]); | |
351cfc34 | 3174 | |
4be73780 | 3175 | edp_panel_vdd_off(intel_dp, false); |
0d198328 AJ |
3176 | } |
3177 | ||
d2e216d0 RV |
3178 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) |
3179 | { | |
3180 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
3181 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
3182 | struct intel_crtc *intel_crtc = | |
3183 | to_intel_crtc(intel_dig_port->base.base.crtc); | |
3184 | u8 buf[1]; | |
3185 | ||
9d1a1031 | 3186 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0) |
d2e216d0 RV |
3187 | return -EAGAIN; |
3188 | ||
3189 | if (!(buf[0] & DP_TEST_CRC_SUPPORTED)) | |
3190 | return -ENOTTY; | |
3191 | ||
9d1a1031 JN |
3192 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
3193 | DP_TEST_SINK_START) < 0) | |
d2e216d0 RV |
3194 | return -EAGAIN; |
3195 | ||
3196 | /* Wait 2 vblanks to be sure we will have the correct CRC value */ | |
3197 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
3198 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
3199 | ||
9d1a1031 | 3200 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) |
d2e216d0 RV |
3201 | return -EAGAIN; |
3202 | ||
9d1a1031 | 3203 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0); |
d2e216d0 RV |
3204 | return 0; |
3205 | } | |
3206 | ||
a60f0e38 JB |
3207 | static bool |
3208 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
3209 | { | |
9d1a1031 JN |
3210 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
3211 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
3212 | sink_irq_vector, 1) == 1; | |
a60f0e38 JB |
3213 | } |
3214 | ||
3215 | static void | |
3216 | intel_dp_handle_test_request(struct intel_dp *intel_dp) | |
3217 | { | |
3218 | /* NAK by default */ | |
9d1a1031 | 3219 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK); |
a60f0e38 JB |
3220 | } |
3221 | ||
a4fc5ed6 KP |
3222 | /* |
3223 | * According to DP spec | |
3224 | * 5.1.2: | |
3225 | * 1. Read DPCD | |
3226 | * 2. Configure link according to Receiver Capabilities | |
3227 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
3228 | * 4. Check link status on receipt of hot-plug interrupt | |
3229 | */ | |
3230 | ||
00c09d70 | 3231 | void |
ea5b213a | 3232 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
a4fc5ed6 | 3233 | { |
da63a9f2 | 3234 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
a60f0e38 | 3235 | u8 sink_irq_vector; |
93f62dad | 3236 | u8 link_status[DP_LINK_STATUS_SIZE]; |
a60f0e38 | 3237 | |
da63a9f2 | 3238 | if (!intel_encoder->connectors_active) |
d2b996ac | 3239 | return; |
59cd09e1 | 3240 | |
da63a9f2 | 3241 | if (WARN_ON(!intel_encoder->base.crtc)) |
a4fc5ed6 KP |
3242 | return; |
3243 | ||
92fd8fd1 | 3244 | /* Try to read receiver status if the link appears to be up */ |
93f62dad | 3245 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
a4fc5ed6 KP |
3246 | return; |
3247 | } | |
3248 | ||
92fd8fd1 | 3249 | /* Now read the DPCD to see if it's actually running */ |
26d61aad | 3250 | if (!intel_dp_get_dpcd(intel_dp)) { |
59cd09e1 JB |
3251 | return; |
3252 | } | |
3253 | ||
a60f0e38 JB |
3254 | /* Try to read the source of the interrupt */ |
3255 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
3256 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { | |
3257 | /* Clear interrupt source */ | |
9d1a1031 JN |
3258 | drm_dp_dpcd_writeb(&intel_dp->aux, |
3259 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
3260 | sink_irq_vector); | |
a60f0e38 JB |
3261 | |
3262 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
3263 | intel_dp_handle_test_request(intel_dp); | |
3264 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) | |
3265 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
3266 | } | |
3267 | ||
1ffdff13 | 3268 | if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
92fd8fd1 | 3269 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
da63a9f2 | 3270 | drm_get_encoder_name(&intel_encoder->base)); |
33a34e4e JB |
3271 | intel_dp_start_link_train(intel_dp); |
3272 | intel_dp_complete_link_train(intel_dp); | |
3ab9c637 | 3273 | intel_dp_stop_link_train(intel_dp); |
33a34e4e | 3274 | } |
a4fc5ed6 | 3275 | } |
a4fc5ed6 | 3276 | |
caf9ab24 | 3277 | /* XXX this is probably wrong for multiple downstream ports */ |
71ba9000 | 3278 | static enum drm_connector_status |
26d61aad | 3279 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
71ba9000 | 3280 | { |
caf9ab24 | 3281 | uint8_t *dpcd = intel_dp->dpcd; |
caf9ab24 AJ |
3282 | uint8_t type; |
3283 | ||
3284 | if (!intel_dp_get_dpcd(intel_dp)) | |
3285 | return connector_status_disconnected; | |
3286 | ||
3287 | /* if there's no downstream port, we're done */ | |
3288 | if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) | |
26d61aad | 3289 | return connector_status_connected; |
caf9ab24 AJ |
3290 | |
3291 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ | |
c9ff160b JN |
3292 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
3293 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { | |
23235177 | 3294 | uint8_t reg; |
9d1a1031 JN |
3295 | |
3296 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT, | |
3297 | ®, 1) < 0) | |
caf9ab24 | 3298 | return connector_status_unknown; |
9d1a1031 | 3299 | |
23235177 AJ |
3300 | return DP_GET_SINK_COUNT(reg) ? connector_status_connected |
3301 | : connector_status_disconnected; | |
caf9ab24 AJ |
3302 | } |
3303 | ||
3304 | /* If no HPD, poke DDC gently */ | |
0b99836f | 3305 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
26d61aad | 3306 | return connector_status_connected; |
caf9ab24 AJ |
3307 | |
3308 | /* Well we tried, say unknown for unreliable port types */ | |
c9ff160b JN |
3309 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
3310 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; | |
3311 | if (type == DP_DS_PORT_TYPE_VGA || | |
3312 | type == DP_DS_PORT_TYPE_NON_EDID) | |
3313 | return connector_status_unknown; | |
3314 | } else { | |
3315 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & | |
3316 | DP_DWN_STRM_PORT_TYPE_MASK; | |
3317 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || | |
3318 | type == DP_DWN_STRM_PORT_TYPE_OTHER) | |
3319 | return connector_status_unknown; | |
3320 | } | |
caf9ab24 AJ |
3321 | |
3322 | /* Anything else is out of spec, warn and ignore */ | |
3323 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); | |
26d61aad | 3324 | return connector_status_disconnected; |
71ba9000 AJ |
3325 | } |
3326 | ||
5eb08b69 | 3327 | static enum drm_connector_status |
a9756bb5 | 3328 | ironlake_dp_detect(struct intel_dp *intel_dp) |
5eb08b69 | 3329 | { |
30add22d | 3330 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1b469639 DL |
3331 | struct drm_i915_private *dev_priv = dev->dev_private; |
3332 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
5eb08b69 ZW |
3333 | enum drm_connector_status status; |
3334 | ||
fe16d949 CW |
3335 | /* Can't disconnect eDP, but you can close the lid... */ |
3336 | if (is_edp(intel_dp)) { | |
30add22d | 3337 | status = intel_panel_detect(dev); |
fe16d949 CW |
3338 | if (status == connector_status_unknown) |
3339 | status = connector_status_connected; | |
3340 | return status; | |
3341 | } | |
01cb9ea6 | 3342 | |
1b469639 DL |
3343 | if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) |
3344 | return connector_status_disconnected; | |
3345 | ||
26d61aad | 3346 | return intel_dp_detect_dpcd(intel_dp); |
5eb08b69 ZW |
3347 | } |
3348 | ||
a4fc5ed6 | 3349 | static enum drm_connector_status |
a9756bb5 | 3350 | g4x_dp_detect(struct intel_dp *intel_dp) |
a4fc5ed6 | 3351 | { |
30add22d | 3352 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
a4fc5ed6 | 3353 | struct drm_i915_private *dev_priv = dev->dev_private; |
34f2be46 | 3354 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
10f76a38 | 3355 | uint32_t bit; |
5eb08b69 | 3356 | |
35aad75f JB |
3357 | /* Can't disconnect eDP, but you can close the lid... */ |
3358 | if (is_edp(intel_dp)) { | |
3359 | enum drm_connector_status status; | |
3360 | ||
3361 | status = intel_panel_detect(dev); | |
3362 | if (status == connector_status_unknown) | |
3363 | status = connector_status_connected; | |
3364 | return status; | |
3365 | } | |
3366 | ||
232a6ee9 TP |
3367 | if (IS_VALLEYVIEW(dev)) { |
3368 | switch (intel_dig_port->port) { | |
3369 | case PORT_B: | |
3370 | bit = PORTB_HOTPLUG_LIVE_STATUS_VLV; | |
3371 | break; | |
3372 | case PORT_C: | |
3373 | bit = PORTC_HOTPLUG_LIVE_STATUS_VLV; | |
3374 | break; | |
3375 | case PORT_D: | |
3376 | bit = PORTD_HOTPLUG_LIVE_STATUS_VLV; | |
3377 | break; | |
3378 | default: | |
3379 | return connector_status_unknown; | |
3380 | } | |
3381 | } else { | |
3382 | switch (intel_dig_port->port) { | |
3383 | case PORT_B: | |
3384 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; | |
3385 | break; | |
3386 | case PORT_C: | |
3387 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; | |
3388 | break; | |
3389 | case PORT_D: | |
3390 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; | |
3391 | break; | |
3392 | default: | |
3393 | return connector_status_unknown; | |
3394 | } | |
a4fc5ed6 KP |
3395 | } |
3396 | ||
10f76a38 | 3397 | if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) |
a4fc5ed6 KP |
3398 | return connector_status_disconnected; |
3399 | ||
26d61aad | 3400 | return intel_dp_detect_dpcd(intel_dp); |
a9756bb5 ZW |
3401 | } |
3402 | ||
8c241fef KP |
3403 | static struct edid * |
3404 | intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) | |
3405 | { | |
9cd300e0 | 3406 | struct intel_connector *intel_connector = to_intel_connector(connector); |
d6f24d0f | 3407 | |
9cd300e0 JN |
3408 | /* use cached edid if we have one */ |
3409 | if (intel_connector->edid) { | |
9cd300e0 JN |
3410 | /* invalid edid */ |
3411 | if (IS_ERR(intel_connector->edid)) | |
d6f24d0f JB |
3412 | return NULL; |
3413 | ||
55e9edeb | 3414 | return drm_edid_duplicate(intel_connector->edid); |
d6f24d0f | 3415 | } |
8c241fef | 3416 | |
9cd300e0 | 3417 | return drm_get_edid(connector, adapter); |
8c241fef KP |
3418 | } |
3419 | ||
3420 | static int | |
3421 | intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) | |
3422 | { | |
9cd300e0 | 3423 | struct intel_connector *intel_connector = to_intel_connector(connector); |
8c241fef | 3424 | |
9cd300e0 JN |
3425 | /* use cached edid if we have one */ |
3426 | if (intel_connector->edid) { | |
3427 | /* invalid edid */ | |
3428 | if (IS_ERR(intel_connector->edid)) | |
3429 | return 0; | |
3430 | ||
3431 | return intel_connector_update_modes(connector, | |
3432 | intel_connector->edid); | |
d6f24d0f JB |
3433 | } |
3434 | ||
9cd300e0 | 3435 | return intel_ddc_get_modes(connector, adapter); |
8c241fef KP |
3436 | } |
3437 | ||
a9756bb5 ZW |
3438 | static enum drm_connector_status |
3439 | intel_dp_detect(struct drm_connector *connector, bool force) | |
3440 | { | |
3441 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
d63885da PZ |
3442 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3443 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
fa90ecef | 3444 | struct drm_device *dev = connector->dev; |
c8c8fb33 | 3445 | struct drm_i915_private *dev_priv = dev->dev_private; |
a9756bb5 | 3446 | enum drm_connector_status status; |
671dedd2 | 3447 | enum intel_display_power_domain power_domain; |
a9756bb5 ZW |
3448 | struct edid *edid = NULL; |
3449 | ||
c8c8fb33 PZ |
3450 | intel_runtime_pm_get(dev_priv); |
3451 | ||
671dedd2 ID |
3452 | power_domain = intel_display_port_power_domain(intel_encoder); |
3453 | intel_display_power_get(dev_priv, power_domain); | |
3454 | ||
164c8598 CW |
3455 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
3456 | connector->base.id, drm_get_connector_name(connector)); | |
3457 | ||
a9756bb5 ZW |
3458 | intel_dp->has_audio = false; |
3459 | ||
3460 | if (HAS_PCH_SPLIT(dev)) | |
3461 | status = ironlake_dp_detect(intel_dp); | |
3462 | else | |
3463 | status = g4x_dp_detect(intel_dp); | |
1b9be9d0 | 3464 | |
a9756bb5 | 3465 | if (status != connector_status_connected) |
c8c8fb33 | 3466 | goto out; |
a9756bb5 | 3467 | |
0d198328 AJ |
3468 | intel_dp_probe_oui(intel_dp); |
3469 | ||
c3e5f67b DV |
3470 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { |
3471 | intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); | |
f684960e | 3472 | } else { |
0b99836f | 3473 | edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc); |
f684960e CW |
3474 | if (edid) { |
3475 | intel_dp->has_audio = drm_detect_monitor_audio(edid); | |
f684960e CW |
3476 | kfree(edid); |
3477 | } | |
a9756bb5 ZW |
3478 | } |
3479 | ||
d63885da PZ |
3480 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
3481 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
c8c8fb33 PZ |
3482 | status = connector_status_connected; |
3483 | ||
3484 | out: | |
671dedd2 ID |
3485 | intel_display_power_put(dev_priv, power_domain); |
3486 | ||
c8c8fb33 | 3487 | intel_runtime_pm_put(dev_priv); |
671dedd2 | 3488 | |
c8c8fb33 | 3489 | return status; |
a4fc5ed6 KP |
3490 | } |
3491 | ||
3492 | static int intel_dp_get_modes(struct drm_connector *connector) | |
3493 | { | |
df0e9248 | 3494 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
671dedd2 ID |
3495 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3496 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
dd06f90e | 3497 | struct intel_connector *intel_connector = to_intel_connector(connector); |
fa90ecef | 3498 | struct drm_device *dev = connector->dev; |
671dedd2 ID |
3499 | struct drm_i915_private *dev_priv = dev->dev_private; |
3500 | enum intel_display_power_domain power_domain; | |
32f9d658 | 3501 | int ret; |
a4fc5ed6 KP |
3502 | |
3503 | /* We should parse the EDID data and find out if it has an audio sink | |
3504 | */ | |
3505 | ||
671dedd2 ID |
3506 | power_domain = intel_display_port_power_domain(intel_encoder); |
3507 | intel_display_power_get(dev_priv, power_domain); | |
3508 | ||
0b99836f | 3509 | ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc); |
671dedd2 | 3510 | intel_display_power_put(dev_priv, power_domain); |
f8779fda | 3511 | if (ret) |
32f9d658 ZW |
3512 | return ret; |
3513 | ||
f8779fda | 3514 | /* if eDP has no EDID, fall back to fixed mode */ |
dd06f90e | 3515 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
f8779fda | 3516 | struct drm_display_mode *mode; |
dd06f90e JN |
3517 | mode = drm_mode_duplicate(dev, |
3518 | intel_connector->panel.fixed_mode); | |
f8779fda | 3519 | if (mode) { |
32f9d658 ZW |
3520 | drm_mode_probed_add(connector, mode); |
3521 | return 1; | |
3522 | } | |
3523 | } | |
3524 | return 0; | |
a4fc5ed6 KP |
3525 | } |
3526 | ||
1aad7ac0 CW |
3527 | static bool |
3528 | intel_dp_detect_audio(struct drm_connector *connector) | |
3529 | { | |
3530 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
671dedd2 ID |
3531 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3532 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
3533 | struct drm_device *dev = connector->dev; | |
3534 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3535 | enum intel_display_power_domain power_domain; | |
1aad7ac0 CW |
3536 | struct edid *edid; |
3537 | bool has_audio = false; | |
3538 | ||
671dedd2 ID |
3539 | power_domain = intel_display_port_power_domain(intel_encoder); |
3540 | intel_display_power_get(dev_priv, power_domain); | |
3541 | ||
0b99836f | 3542 | edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc); |
1aad7ac0 CW |
3543 | if (edid) { |
3544 | has_audio = drm_detect_monitor_audio(edid); | |
1aad7ac0 CW |
3545 | kfree(edid); |
3546 | } | |
3547 | ||
671dedd2 ID |
3548 | intel_display_power_put(dev_priv, power_domain); |
3549 | ||
1aad7ac0 CW |
3550 | return has_audio; |
3551 | } | |
3552 | ||
f684960e CW |
3553 | static int |
3554 | intel_dp_set_property(struct drm_connector *connector, | |
3555 | struct drm_property *property, | |
3556 | uint64_t val) | |
3557 | { | |
e953fd7b | 3558 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
53b41837 | 3559 | struct intel_connector *intel_connector = to_intel_connector(connector); |
da63a9f2 PZ |
3560 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
3561 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
f684960e CW |
3562 | int ret; |
3563 | ||
662595df | 3564 | ret = drm_object_property_set_value(&connector->base, property, val); |
f684960e CW |
3565 | if (ret) |
3566 | return ret; | |
3567 | ||
3f43c48d | 3568 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
3569 | int i = val; |
3570 | bool has_audio; | |
3571 | ||
3572 | if (i == intel_dp->force_audio) | |
f684960e CW |
3573 | return 0; |
3574 | ||
1aad7ac0 | 3575 | intel_dp->force_audio = i; |
f684960e | 3576 | |
c3e5f67b | 3577 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
3578 | has_audio = intel_dp_detect_audio(connector); |
3579 | else | |
c3e5f67b | 3580 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 CW |
3581 | |
3582 | if (has_audio == intel_dp->has_audio) | |
f684960e CW |
3583 | return 0; |
3584 | ||
1aad7ac0 | 3585 | intel_dp->has_audio = has_audio; |
f684960e CW |
3586 | goto done; |
3587 | } | |
3588 | ||
e953fd7b | 3589 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 DV |
3590 | bool old_auto = intel_dp->color_range_auto; |
3591 | uint32_t old_range = intel_dp->color_range; | |
3592 | ||
55bc60db VS |
3593 | switch (val) { |
3594 | case INTEL_BROADCAST_RGB_AUTO: | |
3595 | intel_dp->color_range_auto = true; | |
3596 | break; | |
3597 | case INTEL_BROADCAST_RGB_FULL: | |
3598 | intel_dp->color_range_auto = false; | |
3599 | intel_dp->color_range = 0; | |
3600 | break; | |
3601 | case INTEL_BROADCAST_RGB_LIMITED: | |
3602 | intel_dp->color_range_auto = false; | |
3603 | intel_dp->color_range = DP_COLOR_RANGE_16_235; | |
3604 | break; | |
3605 | default: | |
3606 | return -EINVAL; | |
3607 | } | |
ae4edb80 DV |
3608 | |
3609 | if (old_auto == intel_dp->color_range_auto && | |
3610 | old_range == intel_dp->color_range) | |
3611 | return 0; | |
3612 | ||
e953fd7b CW |
3613 | goto done; |
3614 | } | |
3615 | ||
53b41837 YN |
3616 | if (is_edp(intel_dp) && |
3617 | property == connector->dev->mode_config.scaling_mode_property) { | |
3618 | if (val == DRM_MODE_SCALE_NONE) { | |
3619 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
3620 | return -EINVAL; | |
3621 | } | |
3622 | ||
3623 | if (intel_connector->panel.fitting_mode == val) { | |
3624 | /* the eDP scaling property is not changed */ | |
3625 | return 0; | |
3626 | } | |
3627 | intel_connector->panel.fitting_mode = val; | |
3628 | ||
3629 | goto done; | |
3630 | } | |
3631 | ||
f684960e CW |
3632 | return -EINVAL; |
3633 | ||
3634 | done: | |
c0c36b94 CW |
3635 | if (intel_encoder->base.crtc) |
3636 | intel_crtc_restore_mode(intel_encoder->base.crtc); | |
f684960e CW |
3637 | |
3638 | return 0; | |
3639 | } | |
3640 | ||
a4fc5ed6 | 3641 | static void |
73845adf | 3642 | intel_dp_connector_destroy(struct drm_connector *connector) |
a4fc5ed6 | 3643 | { |
1d508706 | 3644 | struct intel_connector *intel_connector = to_intel_connector(connector); |
aaa6fd2a | 3645 | |
9cd300e0 JN |
3646 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
3647 | kfree(intel_connector->edid); | |
3648 | ||
acd8db10 PZ |
3649 | /* Can't call is_edp() since the encoder may have been destroyed |
3650 | * already. */ | |
3651 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
1d508706 | 3652 | intel_panel_fini(&intel_connector->panel); |
aaa6fd2a | 3653 | |
a4fc5ed6 | 3654 | drm_connector_cleanup(connector); |
55f78c43 | 3655 | kfree(connector); |
a4fc5ed6 KP |
3656 | } |
3657 | ||
00c09d70 | 3658 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
24d05927 | 3659 | { |
da63a9f2 PZ |
3660 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
3661 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
bd173813 | 3662 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
24d05927 | 3663 | |
0b99836f | 3664 | drm_dp_aux_unregister_i2c_bus(&intel_dp->aux); |
24d05927 | 3665 | drm_encoder_cleanup(encoder); |
bd943159 KP |
3666 | if (is_edp(intel_dp)) { |
3667 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
bd173813 | 3668 | mutex_lock(&dev->mode_config.mutex); |
4be73780 | 3669 | edp_panel_vdd_off_sync(intel_dp); |
bd173813 | 3670 | mutex_unlock(&dev->mode_config.mutex); |
bd943159 | 3671 | } |
da63a9f2 | 3672 | kfree(intel_dig_port); |
24d05927 DV |
3673 | } |
3674 | ||
a4fc5ed6 | 3675 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
2bd2ad64 | 3676 | .dpms = intel_connector_dpms, |
a4fc5ed6 KP |
3677 | .detect = intel_dp_detect, |
3678 | .fill_modes = drm_helper_probe_single_connector_modes, | |
f684960e | 3679 | .set_property = intel_dp_set_property, |
73845adf | 3680 | .destroy = intel_dp_connector_destroy, |
a4fc5ed6 KP |
3681 | }; |
3682 | ||
3683 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
3684 | .get_modes = intel_dp_get_modes, | |
3685 | .mode_valid = intel_dp_mode_valid, | |
df0e9248 | 3686 | .best_encoder = intel_best_encoder, |
a4fc5ed6 KP |
3687 | }; |
3688 | ||
a4fc5ed6 | 3689 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
24d05927 | 3690 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
3691 | }; |
3692 | ||
995b6762 | 3693 | static void |
21d40d37 | 3694 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
c8110e52 | 3695 | { |
fa90ecef | 3696 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
c8110e52 | 3697 | |
885a5014 | 3698 | intel_dp_check_link_status(intel_dp); |
c8110e52 | 3699 | } |
6207937d | 3700 | |
e3421a18 ZW |
3701 | /* Return which DP Port should be selected for Transcoder DP control */ |
3702 | int | |
0206e353 | 3703 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
e3421a18 ZW |
3704 | { |
3705 | struct drm_device *dev = crtc->dev; | |
fa90ecef PZ |
3706 | struct intel_encoder *intel_encoder; |
3707 | struct intel_dp *intel_dp; | |
e3421a18 | 3708 | |
fa90ecef PZ |
3709 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
3710 | intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
e3421a18 | 3711 | |
fa90ecef PZ |
3712 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
3713 | intel_encoder->type == INTEL_OUTPUT_EDP) | |
ea5b213a | 3714 | return intel_dp->output_reg; |
e3421a18 | 3715 | } |
ea5b213a | 3716 | |
e3421a18 ZW |
3717 | return -1; |
3718 | } | |
3719 | ||
36e83a18 | 3720 | /* check the VBT to see whether the eDP is on DP-D port */ |
5d8a7752 | 3721 | bool intel_dp_is_edp(struct drm_device *dev, enum port port) |
36e83a18 ZY |
3722 | { |
3723 | struct drm_i915_private *dev_priv = dev->dev_private; | |
768f69c9 | 3724 | union child_device_config *p_child; |
36e83a18 | 3725 | int i; |
5d8a7752 VS |
3726 | static const short port_mapping[] = { |
3727 | [PORT_B] = PORT_IDPB, | |
3728 | [PORT_C] = PORT_IDPC, | |
3729 | [PORT_D] = PORT_IDPD, | |
3730 | }; | |
36e83a18 | 3731 | |
3b32a35b VS |
3732 | if (port == PORT_A) |
3733 | return true; | |
3734 | ||
41aa3448 | 3735 | if (!dev_priv->vbt.child_dev_num) |
36e83a18 ZY |
3736 | return false; |
3737 | ||
41aa3448 RV |
3738 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
3739 | p_child = dev_priv->vbt.child_dev + i; | |
36e83a18 | 3740 | |
5d8a7752 | 3741 | if (p_child->common.dvo_port == port_mapping[port] && |
f02586df VS |
3742 | (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == |
3743 | (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) | |
36e83a18 ZY |
3744 | return true; |
3745 | } | |
3746 | return false; | |
3747 | } | |
3748 | ||
f684960e CW |
3749 | static void |
3750 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) | |
3751 | { | |
53b41837 YN |
3752 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3753 | ||
3f43c48d | 3754 | intel_attach_force_audio_property(connector); |
e953fd7b | 3755 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 3756 | intel_dp->color_range_auto = true; |
53b41837 YN |
3757 | |
3758 | if (is_edp(intel_dp)) { | |
3759 | drm_mode_create_scaling_mode_property(connector->dev); | |
6de6d846 RC |
3760 | drm_object_attach_property( |
3761 | &connector->base, | |
53b41837 | 3762 | connector->dev->mode_config.scaling_mode_property, |
8e740cd1 YN |
3763 | DRM_MODE_SCALE_ASPECT); |
3764 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; | |
53b41837 | 3765 | } |
f684960e CW |
3766 | } |
3767 | ||
dada1a9f ID |
3768 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
3769 | { | |
3770 | intel_dp->last_power_cycle = jiffies; | |
3771 | intel_dp->last_power_on = jiffies; | |
3772 | intel_dp->last_backlight_off = jiffies; | |
3773 | } | |
3774 | ||
67a54566 DV |
3775 | static void |
3776 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
f30d26e4 JN |
3777 | struct intel_dp *intel_dp, |
3778 | struct edp_power_seq *out) | |
67a54566 DV |
3779 | { |
3780 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3781 | struct edp_power_seq cur, vbt, spec, final; | |
3782 | u32 pp_on, pp_off, pp_div, pp; | |
bf13e81b | 3783 | int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; |
453c5420 JB |
3784 | |
3785 | if (HAS_PCH_SPLIT(dev)) { | |
bf13e81b | 3786 | pp_ctrl_reg = PCH_PP_CONTROL; |
453c5420 JB |
3787 | pp_on_reg = PCH_PP_ON_DELAYS; |
3788 | pp_off_reg = PCH_PP_OFF_DELAYS; | |
3789 | pp_div_reg = PCH_PP_DIVISOR; | |
3790 | } else { | |
bf13e81b JN |
3791 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
3792 | ||
3793 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); | |
3794 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); | |
3795 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); | |
3796 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); | |
453c5420 | 3797 | } |
67a54566 DV |
3798 | |
3799 | /* Workaround: Need to write PP_CONTROL with the unlock key as | |
3800 | * the very first thing. */ | |
453c5420 | 3801 | pp = ironlake_get_pp_control(intel_dp); |
bf13e81b | 3802 | I915_WRITE(pp_ctrl_reg, pp); |
67a54566 | 3803 | |
453c5420 JB |
3804 | pp_on = I915_READ(pp_on_reg); |
3805 | pp_off = I915_READ(pp_off_reg); | |
3806 | pp_div = I915_READ(pp_div_reg); | |
67a54566 DV |
3807 | |
3808 | /* Pull timing values out of registers */ | |
3809 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> | |
3810 | PANEL_POWER_UP_DELAY_SHIFT; | |
3811 | ||
3812 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> | |
3813 | PANEL_LIGHT_ON_DELAY_SHIFT; | |
3814 | ||
3815 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> | |
3816 | PANEL_LIGHT_OFF_DELAY_SHIFT; | |
3817 | ||
3818 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> | |
3819 | PANEL_POWER_DOWN_DELAY_SHIFT; | |
3820 | ||
3821 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> | |
3822 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; | |
3823 | ||
3824 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
3825 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); | |
3826 | ||
41aa3448 | 3827 | vbt = dev_priv->vbt.edp_pps; |
67a54566 DV |
3828 | |
3829 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of | |
3830 | * our hw here, which are all in 100usec. */ | |
3831 | spec.t1_t3 = 210 * 10; | |
3832 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ | |
3833 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ | |
3834 | spec.t10 = 500 * 10; | |
3835 | /* This one is special and actually in units of 100ms, but zero | |
3836 | * based in the hw (so we need to add 100 ms). But the sw vbt | |
3837 | * table multiplies it with 1000 to make it in units of 100usec, | |
3838 | * too. */ | |
3839 | spec.t11_t12 = (510 + 100) * 10; | |
3840 | ||
3841 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
3842 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); | |
3843 | ||
3844 | /* Use the max of the register settings and vbt. If both are | |
3845 | * unset, fall back to the spec limits. */ | |
3846 | #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \ | |
3847 | spec.field : \ | |
3848 | max(cur.field, vbt.field)) | |
3849 | assign_final(t1_t3); | |
3850 | assign_final(t8); | |
3851 | assign_final(t9); | |
3852 | assign_final(t10); | |
3853 | assign_final(t11_t12); | |
3854 | #undef assign_final | |
3855 | ||
3856 | #define get_delay(field) (DIV_ROUND_UP(final.field, 10)) | |
3857 | intel_dp->panel_power_up_delay = get_delay(t1_t3); | |
3858 | intel_dp->backlight_on_delay = get_delay(t8); | |
3859 | intel_dp->backlight_off_delay = get_delay(t9); | |
3860 | intel_dp->panel_power_down_delay = get_delay(t10); | |
3861 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); | |
3862 | #undef get_delay | |
3863 | ||
f30d26e4 JN |
3864 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
3865 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, | |
3866 | intel_dp->panel_power_cycle_delay); | |
3867 | ||
3868 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", | |
3869 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); | |
3870 | ||
3871 | if (out) | |
3872 | *out = final; | |
3873 | } | |
3874 | ||
3875 | static void | |
3876 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
3877 | struct intel_dp *intel_dp, | |
3878 | struct edp_power_seq *seq) | |
3879 | { | |
3880 | struct drm_i915_private *dev_priv = dev->dev_private; | |
453c5420 JB |
3881 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
3882 | int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); | |
3883 | int pp_on_reg, pp_off_reg, pp_div_reg; | |
3884 | ||
3885 | if (HAS_PCH_SPLIT(dev)) { | |
3886 | pp_on_reg = PCH_PP_ON_DELAYS; | |
3887 | pp_off_reg = PCH_PP_OFF_DELAYS; | |
3888 | pp_div_reg = PCH_PP_DIVISOR; | |
3889 | } else { | |
bf13e81b JN |
3890 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
3891 | ||
3892 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); | |
3893 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); | |
3894 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); | |
453c5420 JB |
3895 | } |
3896 | ||
b2f19d1a PZ |
3897 | /* |
3898 | * And finally store the new values in the power sequencer. The | |
3899 | * backlight delays are set to 1 because we do manual waits on them. For | |
3900 | * T8, even BSpec recommends doing it. For T9, if we don't do this, | |
3901 | * we'll end up waiting for the backlight off delay twice: once when we | |
3902 | * do the manual sleep, and once when we disable the panel and wait for | |
3903 | * the PP_STATUS bit to become zero. | |
3904 | */ | |
f30d26e4 | 3905 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
b2f19d1a PZ |
3906 | (1 << PANEL_LIGHT_ON_DELAY_SHIFT); |
3907 | pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) | | |
f30d26e4 | 3908 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
67a54566 DV |
3909 | /* Compute the divisor for the pp clock, simply match the Bspec |
3910 | * formula. */ | |
453c5420 | 3911 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; |
f30d26e4 | 3912 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) |
67a54566 DV |
3913 | << PANEL_POWER_CYCLE_DELAY_SHIFT); |
3914 | ||
3915 | /* Haswell doesn't have any port selection bits for the panel | |
3916 | * power sequencer any more. */ | |
bc7d38a4 | 3917 | if (IS_VALLEYVIEW(dev)) { |
bf13e81b JN |
3918 | if (dp_to_dig_port(intel_dp)->port == PORT_B) |
3919 | port_sel = PANEL_PORT_SELECT_DPB_VLV; | |
3920 | else | |
3921 | port_sel = PANEL_PORT_SELECT_DPC_VLV; | |
bc7d38a4 ID |
3922 | } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
3923 | if (dp_to_dig_port(intel_dp)->port == PORT_A) | |
a24c144c | 3924 | port_sel = PANEL_PORT_SELECT_DPA; |
67a54566 | 3925 | else |
a24c144c | 3926 | port_sel = PANEL_PORT_SELECT_DPD; |
67a54566 DV |
3927 | } |
3928 | ||
453c5420 JB |
3929 | pp_on |= port_sel; |
3930 | ||
3931 | I915_WRITE(pp_on_reg, pp_on); | |
3932 | I915_WRITE(pp_off_reg, pp_off); | |
3933 | I915_WRITE(pp_div_reg, pp_div); | |
67a54566 | 3934 | |
67a54566 | 3935 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
453c5420 JB |
3936 | I915_READ(pp_on_reg), |
3937 | I915_READ(pp_off_reg), | |
3938 | I915_READ(pp_div_reg)); | |
f684960e CW |
3939 | } |
3940 | ||
439d7ac0 PB |
3941 | void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) |
3942 | { | |
3943 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3944 | struct intel_encoder *encoder; | |
3945 | struct intel_dp *intel_dp = NULL; | |
3946 | struct intel_crtc_config *config = NULL; | |
3947 | struct intel_crtc *intel_crtc = NULL; | |
3948 | struct intel_connector *intel_connector = dev_priv->drrs.connector; | |
3949 | u32 reg, val; | |
3950 | enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR; | |
3951 | ||
3952 | if (refresh_rate <= 0) { | |
3953 | DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); | |
3954 | return; | |
3955 | } | |
3956 | ||
3957 | if (intel_connector == NULL) { | |
3958 | DRM_DEBUG_KMS("DRRS supported for eDP only.\n"); | |
3959 | return; | |
3960 | } | |
3961 | ||
3962 | if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) { | |
3963 | DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n"); | |
3964 | return; | |
3965 | } | |
3966 | ||
3967 | encoder = intel_attached_encoder(&intel_connector->base); | |
3968 | intel_dp = enc_to_intel_dp(&encoder->base); | |
3969 | intel_crtc = encoder->new_crtc; | |
3970 | ||
3971 | if (!intel_crtc) { | |
3972 | DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); | |
3973 | return; | |
3974 | } | |
3975 | ||
3976 | config = &intel_crtc->config; | |
3977 | ||
3978 | if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) { | |
3979 | DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); | |
3980 | return; | |
3981 | } | |
3982 | ||
3983 | if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate) | |
3984 | index = DRRS_LOW_RR; | |
3985 | ||
3986 | if (index == intel_dp->drrs_state.refresh_rate_type) { | |
3987 | DRM_DEBUG_KMS( | |
3988 | "DRRS requested for previously set RR...ignoring\n"); | |
3989 | return; | |
3990 | } | |
3991 | ||
3992 | if (!intel_crtc->active) { | |
3993 | DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); | |
3994 | return; | |
3995 | } | |
3996 | ||
3997 | if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) { | |
3998 | reg = PIPECONF(intel_crtc->config.cpu_transcoder); | |
3999 | val = I915_READ(reg); | |
4000 | if (index > DRRS_HIGH_RR) { | |
4001 | val |= PIPECONF_EDP_RR_MODE_SWITCH; | |
4002 | intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2); | |
4003 | } else { | |
4004 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; | |
4005 | } | |
4006 | I915_WRITE(reg, val); | |
4007 | } | |
4008 | ||
4009 | /* | |
4010 | * mutex taken to ensure that there is no race between differnt | |
4011 | * drrs calls trying to update refresh rate. This scenario may occur | |
4012 | * in future when idleness detection based DRRS in kernel and | |
4013 | * possible calls from user space to set differnt RR are made. | |
4014 | */ | |
4015 | ||
4016 | mutex_lock(&intel_dp->drrs_state.mutex); | |
4017 | ||
4018 | intel_dp->drrs_state.refresh_rate_type = index; | |
4019 | ||
4020 | mutex_unlock(&intel_dp->drrs_state.mutex); | |
4021 | ||
4022 | DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); | |
4023 | } | |
4024 | ||
4f9db5b5 PB |
4025 | static struct drm_display_mode * |
4026 | intel_dp_drrs_init(struct intel_digital_port *intel_dig_port, | |
4027 | struct intel_connector *intel_connector, | |
4028 | struct drm_display_mode *fixed_mode) | |
4029 | { | |
4030 | struct drm_connector *connector = &intel_connector->base; | |
4031 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
4032 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
4033 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4034 | struct drm_display_mode *downclock_mode = NULL; | |
4035 | ||
4036 | if (INTEL_INFO(dev)->gen <= 6) { | |
4037 | DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); | |
4038 | return NULL; | |
4039 | } | |
4040 | ||
4041 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { | |
4042 | DRM_INFO("VBT doesn't support DRRS\n"); | |
4043 | return NULL; | |
4044 | } | |
4045 | ||
4046 | downclock_mode = intel_find_panel_downclock | |
4047 | (dev, fixed_mode, connector); | |
4048 | ||
4049 | if (!downclock_mode) { | |
4050 | DRM_INFO("DRRS not supported\n"); | |
4051 | return NULL; | |
4052 | } | |
4053 | ||
439d7ac0 PB |
4054 | dev_priv->drrs.connector = intel_connector; |
4055 | ||
4056 | mutex_init(&intel_dp->drrs_state.mutex); | |
4057 | ||
4f9db5b5 PB |
4058 | intel_dp->drrs_state.type = dev_priv->vbt.drrs_type; |
4059 | ||
4060 | intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR; | |
4061 | DRM_INFO("seamless DRRS supported for eDP panel.\n"); | |
4062 | return downclock_mode; | |
4063 | } | |
4064 | ||
ed92f0b2 | 4065 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
0095e6dc PZ |
4066 | struct intel_connector *intel_connector, |
4067 | struct edp_power_seq *power_seq) | |
ed92f0b2 PZ |
4068 | { |
4069 | struct drm_connector *connector = &intel_connector->base; | |
4070 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
63635217 PZ |
4071 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4072 | struct drm_device *dev = intel_encoder->base.dev; | |
ed92f0b2 PZ |
4073 | struct drm_i915_private *dev_priv = dev->dev_private; |
4074 | struct drm_display_mode *fixed_mode = NULL; | |
4f9db5b5 | 4075 | struct drm_display_mode *downclock_mode = NULL; |
ed92f0b2 PZ |
4076 | bool has_dpcd; |
4077 | struct drm_display_mode *scan; | |
4078 | struct edid *edid; | |
4079 | ||
4f9db5b5 PB |
4080 | intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED; |
4081 | ||
ed92f0b2 PZ |
4082 | if (!is_edp(intel_dp)) |
4083 | return true; | |
4084 | ||
63635217 PZ |
4085 | /* The VDD bit needs a power domain reference, so if the bit is already |
4086 | * enabled when we boot, grab this reference. */ | |
4087 | if (edp_have_panel_vdd(intel_dp)) { | |
4088 | enum intel_display_power_domain power_domain; | |
4089 | power_domain = intel_display_port_power_domain(intel_encoder); | |
4090 | intel_display_power_get(dev_priv, power_domain); | |
4091 | } | |
4092 | ||
ed92f0b2 | 4093 | /* Cache DPCD and EDID for edp. */ |
24f3e092 | 4094 | intel_edp_panel_vdd_on(intel_dp); |
ed92f0b2 | 4095 | has_dpcd = intel_dp_get_dpcd(intel_dp); |
4be73780 | 4096 | edp_panel_vdd_off(intel_dp, false); |
ed92f0b2 PZ |
4097 | |
4098 | if (has_dpcd) { | |
4099 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) | |
4100 | dev_priv->no_aux_handshake = | |
4101 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & | |
4102 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; | |
4103 | } else { | |
4104 | /* if this fails, presume the device is a ghost */ | |
4105 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); | |
ed92f0b2 PZ |
4106 | return false; |
4107 | } | |
4108 | ||
4109 | /* We now know it's not a ghost, init power sequence regs. */ | |
0095e6dc | 4110 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq); |
ed92f0b2 | 4111 | |
060c8778 | 4112 | mutex_lock(&dev->mode_config.mutex); |
0b99836f | 4113 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
ed92f0b2 PZ |
4114 | if (edid) { |
4115 | if (drm_add_edid_modes(connector, edid)) { | |
4116 | drm_mode_connector_update_edid_property(connector, | |
4117 | edid); | |
4118 | drm_edid_to_eld(connector, edid); | |
4119 | } else { | |
4120 | kfree(edid); | |
4121 | edid = ERR_PTR(-EINVAL); | |
4122 | } | |
4123 | } else { | |
4124 | edid = ERR_PTR(-ENOENT); | |
4125 | } | |
4126 | intel_connector->edid = edid; | |
4127 | ||
4128 | /* prefer fixed mode from EDID if available */ | |
4129 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
4130 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { | |
4131 | fixed_mode = drm_mode_duplicate(dev, scan); | |
4f9db5b5 PB |
4132 | downclock_mode = intel_dp_drrs_init( |
4133 | intel_dig_port, | |
4134 | intel_connector, fixed_mode); | |
ed92f0b2 PZ |
4135 | break; |
4136 | } | |
4137 | } | |
4138 | ||
4139 | /* fallback to VBT if available for eDP */ | |
4140 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { | |
4141 | fixed_mode = drm_mode_duplicate(dev, | |
4142 | dev_priv->vbt.lfp_lvds_vbt_mode); | |
4143 | if (fixed_mode) | |
4144 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
4145 | } | |
060c8778 | 4146 | mutex_unlock(&dev->mode_config.mutex); |
ed92f0b2 | 4147 | |
4f9db5b5 | 4148 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
ed92f0b2 PZ |
4149 | intel_panel_setup_backlight(connector); |
4150 | ||
4151 | return true; | |
4152 | } | |
4153 | ||
16c25533 | 4154 | bool |
f0fec3f2 PZ |
4155 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
4156 | struct intel_connector *intel_connector) | |
a4fc5ed6 | 4157 | { |
f0fec3f2 PZ |
4158 | struct drm_connector *connector = &intel_connector->base; |
4159 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
4160 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
4161 | struct drm_device *dev = intel_encoder->base.dev; | |
a4fc5ed6 | 4162 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 4163 | enum port port = intel_dig_port->port; |
0095e6dc | 4164 | struct edp_power_seq power_seq = { 0 }; |
0b99836f | 4165 | int type; |
a4fc5ed6 | 4166 | |
ec5b01dd DL |
4167 | /* intel_dp vfuncs */ |
4168 | if (IS_VALLEYVIEW(dev)) | |
4169 | intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider; | |
4170 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
4171 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; | |
4172 | else if (HAS_PCH_SPLIT(dev)) | |
4173 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; | |
4174 | else | |
4175 | intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider; | |
4176 | ||
153b1100 DL |
4177 | intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl; |
4178 | ||
0767935e DV |
4179 | /* Preserve the current hw state. */ |
4180 | intel_dp->DP = I915_READ(intel_dp->output_reg); | |
dd06f90e | 4181 | intel_dp->attached_connector = intel_connector; |
3d3dc149 | 4182 | |
3b32a35b | 4183 | if (intel_dp_is_edp(dev, port)) |
b329530c | 4184 | type = DRM_MODE_CONNECTOR_eDP; |
3b32a35b VS |
4185 | else |
4186 | type = DRM_MODE_CONNECTOR_DisplayPort; | |
b329530c | 4187 | |
f7d24902 ID |
4188 | /* |
4189 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but | |
4190 | * for DP the encoder type can be set by the caller to | |
4191 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. | |
4192 | */ | |
4193 | if (type == DRM_MODE_CONNECTOR_eDP) | |
4194 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
4195 | ||
e7281eab ID |
4196 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
4197 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", | |
4198 | port_name(port)); | |
4199 | ||
b329530c | 4200 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
4201 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
4202 | ||
a4fc5ed6 KP |
4203 | connector->interlace_allowed = true; |
4204 | connector->doublescan_allowed = 0; | |
4205 | ||
f0fec3f2 | 4206 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
4be73780 | 4207 | edp_panel_vdd_work); |
a4fc5ed6 | 4208 | |
df0e9248 | 4209 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
a4fc5ed6 KP |
4210 | drm_sysfs_connector_add(connector); |
4211 | ||
affa9354 | 4212 | if (HAS_DDI(dev)) |
bcbc889b PZ |
4213 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
4214 | else | |
4215 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
80f65de3 | 4216 | intel_connector->unregister = intel_dp_connector_unregister; |
bcbc889b | 4217 | |
0b99836f | 4218 | /* Set up the hotplug pin. */ |
ab9d7c30 PZ |
4219 | switch (port) { |
4220 | case PORT_A: | |
1d843f9d | 4221 | intel_encoder->hpd_pin = HPD_PORT_A; |
ab9d7c30 PZ |
4222 | break; |
4223 | case PORT_B: | |
1d843f9d | 4224 | intel_encoder->hpd_pin = HPD_PORT_B; |
ab9d7c30 PZ |
4225 | break; |
4226 | case PORT_C: | |
1d843f9d | 4227 | intel_encoder->hpd_pin = HPD_PORT_C; |
ab9d7c30 PZ |
4228 | break; |
4229 | case PORT_D: | |
1d843f9d | 4230 | intel_encoder->hpd_pin = HPD_PORT_D; |
ab9d7c30 PZ |
4231 | break; |
4232 | default: | |
ad1c0b19 | 4233 | BUG(); |
5eb08b69 ZW |
4234 | } |
4235 | ||
dada1a9f ID |
4236 | if (is_edp(intel_dp)) { |
4237 | intel_dp_init_panel_power_timestamps(intel_dp); | |
0095e6dc | 4238 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
dada1a9f | 4239 | } |
0095e6dc | 4240 | |
9d1a1031 | 4241 | intel_dp_aux_init(intel_dp, intel_connector); |
c1f05264 | 4242 | |
2b28bb1b RV |
4243 | intel_dp->psr_setup_done = false; |
4244 | ||
0095e6dc | 4245 | if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) { |
0b99836f | 4246 | drm_dp_aux_unregister_i2c_bus(&intel_dp->aux); |
15b1d171 PZ |
4247 | if (is_edp(intel_dp)) { |
4248 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
4249 | mutex_lock(&dev->mode_config.mutex); | |
4be73780 | 4250 | edp_panel_vdd_off_sync(intel_dp); |
15b1d171 PZ |
4251 | mutex_unlock(&dev->mode_config.mutex); |
4252 | } | |
b2f246a8 PZ |
4253 | drm_sysfs_connector_remove(connector); |
4254 | drm_connector_cleanup(connector); | |
16c25533 | 4255 | return false; |
b2f246a8 | 4256 | } |
32f9d658 | 4257 | |
f684960e CW |
4258 | intel_dp_add_properties(intel_dp, connector); |
4259 | ||
a4fc5ed6 KP |
4260 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
4261 | * 0xd. Failure to do so will result in spurious interrupts being | |
4262 | * generated on the port when a cable is not attached. | |
4263 | */ | |
4264 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
4265 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
4266 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
4267 | } | |
16c25533 PZ |
4268 | |
4269 | return true; | |
a4fc5ed6 | 4270 | } |
f0fec3f2 PZ |
4271 | |
4272 | void | |
4273 | intel_dp_init(struct drm_device *dev, int output_reg, enum port port) | |
4274 | { | |
4275 | struct intel_digital_port *intel_dig_port; | |
4276 | struct intel_encoder *intel_encoder; | |
4277 | struct drm_encoder *encoder; | |
4278 | struct intel_connector *intel_connector; | |
4279 | ||
b14c5679 | 4280 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
f0fec3f2 PZ |
4281 | if (!intel_dig_port) |
4282 | return; | |
4283 | ||
b14c5679 | 4284 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
f0fec3f2 PZ |
4285 | if (!intel_connector) { |
4286 | kfree(intel_dig_port); | |
4287 | return; | |
4288 | } | |
4289 | ||
4290 | intel_encoder = &intel_dig_port->base; | |
4291 | encoder = &intel_encoder->base; | |
4292 | ||
4293 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, | |
4294 | DRM_MODE_ENCODER_TMDS); | |
4295 | ||
5bfe2ac0 | 4296 | intel_encoder->compute_config = intel_dp_compute_config; |
00c09d70 | 4297 | intel_encoder->disable = intel_disable_dp; |
00c09d70 | 4298 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
045ac3b5 | 4299 | intel_encoder->get_config = intel_dp_get_config; |
e4a1d846 CML |
4300 | if (IS_CHERRYVIEW(dev)) { |
4301 | intel_encoder->pre_enable = chv_pre_enable_dp; | |
4302 | intel_encoder->enable = vlv_enable_dp; | |
580d3811 | 4303 | intel_encoder->post_disable = chv_post_disable_dp; |
e4a1d846 | 4304 | } else if (IS_VALLEYVIEW(dev)) { |
ecff4f3b | 4305 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
ab1f90f9 JN |
4306 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
4307 | intel_encoder->enable = vlv_enable_dp; | |
49277c31 | 4308 | intel_encoder->post_disable = vlv_post_disable_dp; |
ab1f90f9 | 4309 | } else { |
ecff4f3b JN |
4310 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
4311 | intel_encoder->enable = g4x_enable_dp; | |
49277c31 | 4312 | intel_encoder->post_disable = g4x_post_disable_dp; |
ab1f90f9 | 4313 | } |
f0fec3f2 | 4314 | |
174edf1f | 4315 | intel_dig_port->port = port; |
f0fec3f2 PZ |
4316 | intel_dig_port->dp.output_reg = output_reg; |
4317 | ||
00c09d70 | 4318 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
882ec384 VS |
4319 | if (IS_CHERRYVIEW(dev)) { |
4320 | if (port == PORT_D) | |
4321 | intel_encoder->crtc_mask = 1 << 2; | |
4322 | else | |
4323 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
4324 | } else { | |
4325 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
4326 | } | |
bc079e8b | 4327 | intel_encoder->cloneable = 0; |
f0fec3f2 PZ |
4328 | intel_encoder->hot_plug = intel_dp_hot_plug; |
4329 | ||
15b1d171 PZ |
4330 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) { |
4331 | drm_encoder_cleanup(encoder); | |
4332 | kfree(intel_dig_port); | |
b2f246a8 | 4333 | kfree(intel_connector); |
15b1d171 | 4334 | } |
f0fec3f2 | 4335 | } |