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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
a4fc5ed6 KP |
30 | #include "drmP.h" |
31 | #include "drm.h" | |
32 | #include "drm_crtc.h" | |
33 | #include "drm_crtc_helper.h" | |
34 | #include "intel_drv.h" | |
35 | #include "i915_drm.h" | |
36 | #include "i915_drv.h" | |
ab2c0672 | 37 | #include "drm_dp_helper.h" |
a4fc5ed6 | 38 | |
ae266c98 | 39 | |
a4fc5ed6 KP |
40 | #define DP_LINK_STATUS_SIZE 6 |
41 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) | |
42 | ||
43 | #define DP_LINK_CONFIGURATION_SIZE 9 | |
44 | ||
ea5b213a CW |
45 | #define IS_eDP(i) ((i)->base.type == INTEL_OUTPUT_EDP) |
46 | #define IS_PCH_eDP(i) ((i)->is_pch_edp) | |
32f9d658 | 47 | |
ea5b213a CW |
48 | struct intel_dp { |
49 | struct intel_encoder base; | |
a4fc5ed6 KP |
50 | uint32_t output_reg; |
51 | uint32_t DP; | |
52 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; | |
a4fc5ed6 | 53 | bool has_audio; |
c8110e52 | 54 | int dpms_mode; |
a4fc5ed6 KP |
55 | uint8_t link_bw; |
56 | uint8_t lane_count; | |
57 | uint8_t dpcd[4]; | |
a4fc5ed6 KP |
58 | struct i2c_adapter adapter; |
59 | struct i2c_algo_dp_aux_data algo; | |
f0917379 | 60 | bool is_pch_edp; |
a4fc5ed6 KP |
61 | }; |
62 | ||
ea5b213a CW |
63 | static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
64 | { | |
65 | return container_of(enc_to_intel_encoder(encoder), struct intel_dp, base); | |
66 | } | |
a4fc5ed6 | 67 | |
ea5b213a CW |
68 | static void intel_dp_link_train(struct intel_dp *intel_dp); |
69 | static void intel_dp_link_down(struct intel_dp *intel_dp); | |
a4fc5ed6 | 70 | |
32f9d658 | 71 | void |
21d40d37 | 72 | intel_edp_link_config (struct intel_encoder *intel_encoder, |
ea5b213a | 73 | int *lane_num, int *link_bw) |
32f9d658 | 74 | { |
ea5b213a | 75 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
32f9d658 | 76 | |
ea5b213a CW |
77 | *lane_num = intel_dp->lane_count; |
78 | if (intel_dp->link_bw == DP_LINK_BW_1_62) | |
32f9d658 | 79 | *link_bw = 162000; |
ea5b213a | 80 | else if (intel_dp->link_bw == DP_LINK_BW_2_7) |
32f9d658 ZW |
81 | *link_bw = 270000; |
82 | } | |
83 | ||
a4fc5ed6 | 84 | static int |
ea5b213a | 85 | intel_dp_max_lane_count(struct intel_dp *intel_dp) |
a4fc5ed6 | 86 | { |
a4fc5ed6 KP |
87 | int max_lane_count = 4; |
88 | ||
ea5b213a CW |
89 | if (intel_dp->dpcd[0] >= 0x11) { |
90 | max_lane_count = intel_dp->dpcd[2] & 0x1f; | |
a4fc5ed6 KP |
91 | switch (max_lane_count) { |
92 | case 1: case 2: case 4: | |
93 | break; | |
94 | default: | |
95 | max_lane_count = 4; | |
96 | } | |
97 | } | |
98 | return max_lane_count; | |
99 | } | |
100 | ||
101 | static int | |
ea5b213a | 102 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
a4fc5ed6 | 103 | { |
ea5b213a | 104 | int max_link_bw = intel_dp->dpcd[1]; |
a4fc5ed6 KP |
105 | |
106 | switch (max_link_bw) { | |
107 | case DP_LINK_BW_1_62: | |
108 | case DP_LINK_BW_2_7: | |
109 | break; | |
110 | default: | |
111 | max_link_bw = DP_LINK_BW_1_62; | |
112 | break; | |
113 | } | |
114 | return max_link_bw; | |
115 | } | |
116 | ||
117 | static int | |
118 | intel_dp_link_clock(uint8_t link_bw) | |
119 | { | |
120 | if (link_bw == DP_LINK_BW_2_7) | |
121 | return 270000; | |
122 | else | |
123 | return 162000; | |
124 | } | |
125 | ||
126 | /* I think this is a fiction */ | |
127 | static int | |
ea5b213a | 128 | intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock) |
a4fc5ed6 | 129 | { |
885a5fb5 ZW |
130 | struct drm_i915_private *dev_priv = dev->dev_private; |
131 | ||
ea5b213a | 132 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) |
885a5fb5 ZW |
133 | return (pixel_clock * dev_priv->edp_bpp) / 8; |
134 | else | |
135 | return pixel_clock * 3; | |
a4fc5ed6 KP |
136 | } |
137 | ||
fe27d53e DA |
138 | static int |
139 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) | |
140 | { | |
141 | return (max_link_clock * max_lanes * 8) / 10; | |
142 | } | |
143 | ||
a4fc5ed6 KP |
144 | static int |
145 | intel_dp_mode_valid(struct drm_connector *connector, | |
146 | struct drm_display_mode *mode) | |
147 | { | |
55f78c43 | 148 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
ea5b213a | 149 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
7de56f43 ZY |
150 | struct drm_device *dev = connector->dev; |
151 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a CW |
152 | int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); |
153 | int max_lanes = intel_dp_max_lane_count(intel_dp); | |
a4fc5ed6 | 154 | |
ea5b213a | 155 | if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) && |
7de56f43 ZY |
156 | dev_priv->panel_fixed_mode) { |
157 | if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay) | |
158 | return MODE_PANEL; | |
159 | ||
160 | if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay) | |
161 | return MODE_PANEL; | |
162 | } | |
163 | ||
fe27d53e DA |
164 | /* only refuse the mode on non eDP since we have seen some wierd eDP panels |
165 | which are outside spec tolerances but somehow work by magic */ | |
ea5b213a CW |
166 | if (!IS_eDP(intel_dp) && |
167 | (intel_dp_link_required(connector->dev, intel_dp, mode->clock) | |
fe27d53e | 168 | > intel_dp_max_data_rate(max_link_clock, max_lanes))) |
a4fc5ed6 KP |
169 | return MODE_CLOCK_HIGH; |
170 | ||
171 | if (mode->clock < 10000) | |
172 | return MODE_CLOCK_LOW; | |
173 | ||
174 | return MODE_OK; | |
175 | } | |
176 | ||
177 | static uint32_t | |
178 | pack_aux(uint8_t *src, int src_bytes) | |
179 | { | |
180 | int i; | |
181 | uint32_t v = 0; | |
182 | ||
183 | if (src_bytes > 4) | |
184 | src_bytes = 4; | |
185 | for (i = 0; i < src_bytes; i++) | |
186 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
187 | return v; | |
188 | } | |
189 | ||
190 | static void | |
191 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) | |
192 | { | |
193 | int i; | |
194 | if (dst_bytes > 4) | |
195 | dst_bytes = 4; | |
196 | for (i = 0; i < dst_bytes; i++) | |
197 | dst[i] = src >> ((3-i) * 8); | |
198 | } | |
199 | ||
fb0f8fbf KP |
200 | /* hrawclock is 1/4 the FSB frequency */ |
201 | static int | |
202 | intel_hrawclk(struct drm_device *dev) | |
203 | { | |
204 | struct drm_i915_private *dev_priv = dev->dev_private; | |
205 | uint32_t clkcfg; | |
206 | ||
207 | clkcfg = I915_READ(CLKCFG); | |
208 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
209 | case CLKCFG_FSB_400: | |
210 | return 100; | |
211 | case CLKCFG_FSB_533: | |
212 | return 133; | |
213 | case CLKCFG_FSB_667: | |
214 | return 166; | |
215 | case CLKCFG_FSB_800: | |
216 | return 200; | |
217 | case CLKCFG_FSB_1067: | |
218 | return 266; | |
219 | case CLKCFG_FSB_1333: | |
220 | return 333; | |
221 | /* these two are just a guess; one of them might be right */ | |
222 | case CLKCFG_FSB_1600: | |
223 | case CLKCFG_FSB_1600_ALT: | |
224 | return 400; | |
225 | default: | |
226 | return 133; | |
227 | } | |
228 | } | |
229 | ||
a4fc5ed6 | 230 | static int |
ea5b213a | 231 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
232 | uint8_t *send, int send_bytes, |
233 | uint8_t *recv, int recv_size) | |
234 | { | |
ea5b213a CW |
235 | uint32_t output_reg = intel_dp->output_reg; |
236 | struct drm_device *dev = intel_dp->base.enc.dev; | |
a4fc5ed6 KP |
237 | struct drm_i915_private *dev_priv = dev->dev_private; |
238 | uint32_t ch_ctl = output_reg + 0x10; | |
239 | uint32_t ch_data = ch_ctl + 4; | |
240 | int i; | |
241 | int recv_bytes; | |
a4fc5ed6 | 242 | uint32_t status; |
fb0f8fbf | 243 | uint32_t aux_clock_divider; |
e3421a18 | 244 | int try, precharge; |
a4fc5ed6 KP |
245 | |
246 | /* The clock divider is based off the hrawclk, | |
fb0f8fbf KP |
247 | * and would like to run at 2MHz. So, take the |
248 | * hrawclk value and divide by 2 and use that | |
a4fc5ed6 | 249 | */ |
ea5b213a | 250 | if (IS_eDP(intel_dp)) { |
e3421a18 ZW |
251 | if (IS_GEN6(dev)) |
252 | aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */ | |
253 | else | |
254 | aux_clock_divider = 225; /* eDP input clock at 450Mhz */ | |
255 | } else if (HAS_PCH_SPLIT(dev)) | |
f2b115e6 | 256 | aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */ |
5eb08b69 ZW |
257 | else |
258 | aux_clock_divider = intel_hrawclk(dev) / 2; | |
259 | ||
e3421a18 ZW |
260 | if (IS_GEN6(dev)) |
261 | precharge = 3; | |
262 | else | |
263 | precharge = 5; | |
264 | ||
4f7f7b7e CW |
265 | if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) { |
266 | DRM_ERROR("dp_aux_ch not started status 0x%08x\n", | |
267 | I915_READ(ch_ctl)); | |
268 | return -EBUSY; | |
269 | } | |
270 | ||
fb0f8fbf KP |
271 | /* Must try at least 3 times according to DP spec */ |
272 | for (try = 0; try < 5; try++) { | |
273 | /* Load the send data into the aux channel data registers */ | |
4f7f7b7e CW |
274 | for (i = 0; i < send_bytes; i += 4) |
275 | I915_WRITE(ch_data + i, | |
276 | pack_aux(send + i, send_bytes - i)); | |
fb0f8fbf KP |
277 | |
278 | /* Send the command and wait for it to complete */ | |
4f7f7b7e CW |
279 | I915_WRITE(ch_ctl, |
280 | DP_AUX_CH_CTL_SEND_BUSY | | |
281 | DP_AUX_CH_CTL_TIME_OUT_400us | | |
282 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
283 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
284 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | | |
285 | DP_AUX_CH_CTL_DONE | | |
286 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
287 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
fb0f8fbf | 288 | for (;;) { |
fb0f8fbf KP |
289 | status = I915_READ(ch_ctl); |
290 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) | |
291 | break; | |
4f7f7b7e | 292 | udelay(100); |
fb0f8fbf KP |
293 | } |
294 | ||
295 | /* Clear done status and any errors */ | |
4f7f7b7e CW |
296 | I915_WRITE(ch_ctl, |
297 | status | | |
298 | DP_AUX_CH_CTL_DONE | | |
299 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
300 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
301 | if (status & DP_AUX_CH_CTL_DONE) | |
a4fc5ed6 KP |
302 | break; |
303 | } | |
304 | ||
a4fc5ed6 | 305 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 306 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
a5b3da54 | 307 | return -EBUSY; |
a4fc5ed6 KP |
308 | } |
309 | ||
310 | /* Check for timeout or receive error. | |
311 | * Timeouts occur when the sink is not connected | |
312 | */ | |
a5b3da54 | 313 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 314 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
a5b3da54 KP |
315 | return -EIO; |
316 | } | |
1ae8c0a5 KP |
317 | |
318 | /* Timeouts occur when the device isn't connected, so they're | |
319 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 320 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
28c97730 | 321 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
a5b3da54 | 322 | return -ETIMEDOUT; |
a4fc5ed6 KP |
323 | } |
324 | ||
325 | /* Unload any bytes sent back from the other side */ | |
326 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
327 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
a4fc5ed6 KP |
328 | if (recv_bytes > recv_size) |
329 | recv_bytes = recv_size; | |
330 | ||
4f7f7b7e CW |
331 | for (i = 0; i < recv_bytes; i += 4) |
332 | unpack_aux(I915_READ(ch_data + i), | |
333 | recv + i, recv_bytes - i); | |
a4fc5ed6 KP |
334 | |
335 | return recv_bytes; | |
336 | } | |
337 | ||
338 | /* Write data to the aux channel in native mode */ | |
339 | static int | |
ea5b213a | 340 | intel_dp_aux_native_write(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
341 | uint16_t address, uint8_t *send, int send_bytes) |
342 | { | |
343 | int ret; | |
344 | uint8_t msg[20]; | |
345 | int msg_bytes; | |
346 | uint8_t ack; | |
347 | ||
348 | if (send_bytes > 16) | |
349 | return -1; | |
350 | msg[0] = AUX_NATIVE_WRITE << 4; | |
351 | msg[1] = address >> 8; | |
eebc863e | 352 | msg[2] = address & 0xff; |
a4fc5ed6 KP |
353 | msg[3] = send_bytes - 1; |
354 | memcpy(&msg[4], send, send_bytes); | |
355 | msg_bytes = send_bytes + 4; | |
356 | for (;;) { | |
ea5b213a | 357 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); |
a4fc5ed6 KP |
358 | if (ret < 0) |
359 | return ret; | |
360 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) | |
361 | break; | |
362 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
363 | udelay(100); | |
364 | else | |
a5b3da54 | 365 | return -EIO; |
a4fc5ed6 KP |
366 | } |
367 | return send_bytes; | |
368 | } | |
369 | ||
370 | /* Write a single byte to the aux channel in native mode */ | |
371 | static int | |
ea5b213a | 372 | intel_dp_aux_native_write_1(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
373 | uint16_t address, uint8_t byte) |
374 | { | |
ea5b213a | 375 | return intel_dp_aux_native_write(intel_dp, address, &byte, 1); |
a4fc5ed6 KP |
376 | } |
377 | ||
378 | /* read bytes from a native aux channel */ | |
379 | static int | |
ea5b213a | 380 | intel_dp_aux_native_read(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
381 | uint16_t address, uint8_t *recv, int recv_bytes) |
382 | { | |
383 | uint8_t msg[4]; | |
384 | int msg_bytes; | |
385 | uint8_t reply[20]; | |
386 | int reply_bytes; | |
387 | uint8_t ack; | |
388 | int ret; | |
389 | ||
390 | msg[0] = AUX_NATIVE_READ << 4; | |
391 | msg[1] = address >> 8; | |
392 | msg[2] = address & 0xff; | |
393 | msg[3] = recv_bytes - 1; | |
394 | ||
395 | msg_bytes = 4; | |
396 | reply_bytes = recv_bytes + 1; | |
397 | ||
398 | for (;;) { | |
ea5b213a | 399 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, |
a4fc5ed6 | 400 | reply, reply_bytes); |
a5b3da54 KP |
401 | if (ret == 0) |
402 | return -EPROTO; | |
403 | if (ret < 0) | |
a4fc5ed6 KP |
404 | return ret; |
405 | ack = reply[0]; | |
406 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { | |
407 | memcpy(recv, reply + 1, ret - 1); | |
408 | return ret - 1; | |
409 | } | |
410 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
411 | udelay(100); | |
412 | else | |
a5b3da54 | 413 | return -EIO; |
a4fc5ed6 KP |
414 | } |
415 | } | |
416 | ||
417 | static int | |
ab2c0672 DA |
418 | intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
419 | uint8_t write_byte, uint8_t *read_byte) | |
a4fc5ed6 | 420 | { |
ab2c0672 | 421 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
ea5b213a CW |
422 | struct intel_dp *intel_dp = container_of(adapter, |
423 | struct intel_dp, | |
424 | adapter); | |
ab2c0672 DA |
425 | uint16_t address = algo_data->address; |
426 | uint8_t msg[5]; | |
427 | uint8_t reply[2]; | |
428 | int msg_bytes; | |
429 | int reply_bytes; | |
430 | int ret; | |
431 | ||
432 | /* Set up the command byte */ | |
433 | if (mode & MODE_I2C_READ) | |
434 | msg[0] = AUX_I2C_READ << 4; | |
435 | else | |
436 | msg[0] = AUX_I2C_WRITE << 4; | |
437 | ||
438 | if (!(mode & MODE_I2C_STOP)) | |
439 | msg[0] |= AUX_I2C_MOT << 4; | |
a4fc5ed6 | 440 | |
ab2c0672 DA |
441 | msg[1] = address >> 8; |
442 | msg[2] = address; | |
443 | ||
444 | switch (mode) { | |
445 | case MODE_I2C_WRITE: | |
446 | msg[3] = 0; | |
447 | msg[4] = write_byte; | |
448 | msg_bytes = 5; | |
449 | reply_bytes = 1; | |
450 | break; | |
451 | case MODE_I2C_READ: | |
452 | msg[3] = 0; | |
453 | msg_bytes = 4; | |
454 | reply_bytes = 2; | |
455 | break; | |
456 | default: | |
457 | msg_bytes = 3; | |
458 | reply_bytes = 1; | |
459 | break; | |
460 | } | |
461 | ||
462 | for (;;) { | |
ea5b213a | 463 | ret = intel_dp_aux_ch(intel_dp, |
ab2c0672 DA |
464 | msg, msg_bytes, |
465 | reply, reply_bytes); | |
466 | if (ret < 0) { | |
3ff99164 | 467 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
ab2c0672 DA |
468 | return ret; |
469 | } | |
470 | switch (reply[0] & AUX_I2C_REPLY_MASK) { | |
471 | case AUX_I2C_REPLY_ACK: | |
472 | if (mode == MODE_I2C_READ) { | |
473 | *read_byte = reply[1]; | |
474 | } | |
475 | return reply_bytes - 1; | |
476 | case AUX_I2C_REPLY_NACK: | |
3ff99164 | 477 | DRM_DEBUG_KMS("aux_ch nack\n"); |
ab2c0672 DA |
478 | return -EREMOTEIO; |
479 | case AUX_I2C_REPLY_DEFER: | |
3ff99164 | 480 | DRM_DEBUG_KMS("aux_ch defer\n"); |
ab2c0672 DA |
481 | udelay(100); |
482 | break; | |
483 | default: | |
484 | DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]); | |
485 | return -EREMOTEIO; | |
486 | } | |
487 | } | |
a4fc5ed6 KP |
488 | } |
489 | ||
490 | static int | |
ea5b213a | 491 | intel_dp_i2c_init(struct intel_dp *intel_dp, |
55f78c43 | 492 | struct intel_connector *intel_connector, const char *name) |
a4fc5ed6 | 493 | { |
d54e9d28 | 494 | DRM_DEBUG_KMS("i2c_init %s\n", name); |
ea5b213a CW |
495 | intel_dp->algo.running = false; |
496 | intel_dp->algo.address = 0; | |
497 | intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; | |
498 | ||
499 | memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter)); | |
500 | intel_dp->adapter.owner = THIS_MODULE; | |
501 | intel_dp->adapter.class = I2C_CLASS_DDC; | |
502 | strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); | |
503 | intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; | |
504 | intel_dp->adapter.algo_data = &intel_dp->algo; | |
505 | intel_dp->adapter.dev.parent = &intel_connector->base.kdev; | |
506 | ||
507 | return i2c_dp_aux_add_bus(&intel_dp->adapter); | |
a4fc5ed6 KP |
508 | } |
509 | ||
510 | static bool | |
511 | intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
512 | struct drm_display_mode *adjusted_mode) | |
513 | { | |
0d3a1bee ZY |
514 | struct drm_device *dev = encoder->dev; |
515 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a | 516 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
a4fc5ed6 | 517 | int lane_count, clock; |
ea5b213a CW |
518 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
519 | int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; | |
a4fc5ed6 KP |
520 | static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
521 | ||
ea5b213a | 522 | if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) && |
0d3a1bee | 523 | dev_priv->panel_fixed_mode) { |
1d8e1c75 CW |
524 | intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode); |
525 | intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN, | |
526 | mode, adjusted_mode); | |
0d3a1bee ZY |
527 | /* |
528 | * the mode->clock is used to calculate the Data&Link M/N | |
529 | * of the pipe. For the eDP the fixed clock should be used. | |
530 | */ | |
531 | mode->clock = dev_priv->panel_fixed_mode->clock; | |
532 | } | |
533 | ||
a4fc5ed6 KP |
534 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { |
535 | for (clock = 0; clock <= max_clock; clock++) { | |
fe27d53e | 536 | int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); |
a4fc5ed6 | 537 | |
ea5b213a | 538 | if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock) |
885a5fb5 | 539 | <= link_avail) { |
ea5b213a CW |
540 | intel_dp->link_bw = bws[clock]; |
541 | intel_dp->lane_count = lane_count; | |
542 | adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); | |
28c97730 ZY |
543 | DRM_DEBUG_KMS("Display port link bw %02x lane " |
544 | "count %d clock %d\n", | |
ea5b213a | 545 | intel_dp->link_bw, intel_dp->lane_count, |
a4fc5ed6 KP |
546 | adjusted_mode->clock); |
547 | return true; | |
548 | } | |
549 | } | |
550 | } | |
fe27d53e | 551 | |
ea5b213a | 552 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) { |
fe27d53e | 553 | /* okay we failed just pick the highest */ |
ea5b213a CW |
554 | intel_dp->lane_count = max_lane_count; |
555 | intel_dp->link_bw = bws[max_clock]; | |
556 | adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); | |
fe27d53e DA |
557 | DRM_DEBUG_KMS("Force picking display port link bw %02x lane " |
558 | "count %d clock %d\n", | |
ea5b213a | 559 | intel_dp->link_bw, intel_dp->lane_count, |
fe27d53e | 560 | adjusted_mode->clock); |
1d8e1c75 | 561 | |
fe27d53e DA |
562 | return true; |
563 | } | |
1d8e1c75 | 564 | |
a4fc5ed6 KP |
565 | return false; |
566 | } | |
567 | ||
568 | struct intel_dp_m_n { | |
569 | uint32_t tu; | |
570 | uint32_t gmch_m; | |
571 | uint32_t gmch_n; | |
572 | uint32_t link_m; | |
573 | uint32_t link_n; | |
574 | }; | |
575 | ||
576 | static void | |
577 | intel_reduce_ratio(uint32_t *num, uint32_t *den) | |
578 | { | |
579 | while (*num > 0xffffff || *den > 0xffffff) { | |
580 | *num >>= 1; | |
581 | *den >>= 1; | |
582 | } | |
583 | } | |
584 | ||
585 | static void | |
36e83a18 | 586 | intel_dp_compute_m_n(int bpp, |
a4fc5ed6 KP |
587 | int nlanes, |
588 | int pixel_clock, | |
589 | int link_clock, | |
590 | struct intel_dp_m_n *m_n) | |
591 | { | |
592 | m_n->tu = 64; | |
36e83a18 | 593 | m_n->gmch_m = (pixel_clock * bpp) >> 3; |
a4fc5ed6 KP |
594 | m_n->gmch_n = link_clock * nlanes; |
595 | intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); | |
596 | m_n->link_m = pixel_clock; | |
597 | m_n->link_n = link_clock; | |
598 | intel_reduce_ratio(&m_n->link_m, &m_n->link_n); | |
599 | } | |
600 | ||
36e83a18 ZY |
601 | bool intel_pch_has_edp(struct drm_crtc *crtc) |
602 | { | |
603 | struct drm_device *dev = crtc->dev; | |
604 | struct drm_mode_config *mode_config = &dev->mode_config; | |
605 | struct drm_encoder *encoder; | |
606 | ||
607 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { | |
ea5b213a | 608 | struct intel_dp *intel_dp; |
36e83a18 | 609 | |
ea5b213a | 610 | if (encoder->crtc != crtc) |
36e83a18 ZY |
611 | continue; |
612 | ||
ea5b213a CW |
613 | intel_dp = enc_to_intel_dp(encoder); |
614 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) | |
615 | return intel_dp->is_pch_edp; | |
36e83a18 ZY |
616 | } |
617 | return false; | |
618 | } | |
619 | ||
a4fc5ed6 KP |
620 | void |
621 | intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, | |
622 | struct drm_display_mode *adjusted_mode) | |
623 | { | |
624 | struct drm_device *dev = crtc->dev; | |
625 | struct drm_mode_config *mode_config = &dev->mode_config; | |
55f78c43 | 626 | struct drm_encoder *encoder; |
a4fc5ed6 KP |
627 | struct drm_i915_private *dev_priv = dev->dev_private; |
628 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
36e83a18 | 629 | int lane_count = 4, bpp = 24; |
a4fc5ed6 KP |
630 | struct intel_dp_m_n m_n; |
631 | ||
632 | /* | |
21d40d37 | 633 | * Find the lane count in the intel_encoder private |
a4fc5ed6 | 634 | */ |
55f78c43 | 635 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { |
ea5b213a | 636 | struct intel_dp *intel_dp; |
a4fc5ed6 | 637 | |
d8201ab6 | 638 | if (encoder->crtc != crtc) |
a4fc5ed6 KP |
639 | continue; |
640 | ||
ea5b213a CW |
641 | intel_dp = enc_to_intel_dp(encoder); |
642 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) { | |
643 | lane_count = intel_dp->lane_count; | |
644 | if (IS_PCH_eDP(intel_dp)) | |
36e83a18 | 645 | bpp = dev_priv->edp_bpp; |
a4fc5ed6 KP |
646 | break; |
647 | } | |
648 | } | |
649 | ||
650 | /* | |
651 | * Compute the GMCH and Link ratios. The '3' here is | |
652 | * the number of bytes_per_pixel post-LUT, which we always | |
653 | * set up for 8-bits of R/G/B, or 3 bytes total. | |
654 | */ | |
36e83a18 | 655 | intel_dp_compute_m_n(bpp, lane_count, |
a4fc5ed6 KP |
656 | mode->clock, adjusted_mode->clock, &m_n); |
657 | ||
c619eed4 | 658 | if (HAS_PCH_SPLIT(dev)) { |
5eb08b69 ZW |
659 | if (intel_crtc->pipe == 0) { |
660 | I915_WRITE(TRANSA_DATA_M1, | |
661 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
662 | m_n.gmch_m); | |
663 | I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n); | |
664 | I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m); | |
665 | I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n); | |
666 | } else { | |
667 | I915_WRITE(TRANSB_DATA_M1, | |
668 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
669 | m_n.gmch_m); | |
670 | I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n); | |
671 | I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m); | |
672 | I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n); | |
673 | } | |
a4fc5ed6 | 674 | } else { |
5eb08b69 ZW |
675 | if (intel_crtc->pipe == 0) { |
676 | I915_WRITE(PIPEA_GMCH_DATA_M, | |
677 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
678 | m_n.gmch_m); | |
679 | I915_WRITE(PIPEA_GMCH_DATA_N, | |
680 | m_n.gmch_n); | |
681 | I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m); | |
682 | I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n); | |
683 | } else { | |
684 | I915_WRITE(PIPEB_GMCH_DATA_M, | |
685 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
686 | m_n.gmch_m); | |
687 | I915_WRITE(PIPEB_GMCH_DATA_N, | |
688 | m_n.gmch_n); | |
689 | I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m); | |
690 | I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n); | |
691 | } | |
a4fc5ed6 KP |
692 | } |
693 | } | |
694 | ||
695 | static void | |
696 | intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
697 | struct drm_display_mode *adjusted_mode) | |
698 | { | |
e3421a18 | 699 | struct drm_device *dev = encoder->dev; |
ea5b213a CW |
700 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
701 | struct drm_crtc *crtc = intel_dp->base.enc.crtc; | |
a4fc5ed6 KP |
702 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
703 | ||
ea5b213a | 704 | intel_dp->DP = (DP_VOLTAGE_0_4 | |
9c9e7927 AJ |
705 | DP_PRE_EMPHASIS_0); |
706 | ||
707 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
ea5b213a | 708 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
9c9e7927 | 709 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
ea5b213a | 710 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
a4fc5ed6 | 711 | |
ea5b213a CW |
712 | if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) |
713 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
e3421a18 | 714 | else |
ea5b213a | 715 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
a4fc5ed6 | 716 | |
ea5b213a | 717 | switch (intel_dp->lane_count) { |
a4fc5ed6 | 718 | case 1: |
ea5b213a | 719 | intel_dp->DP |= DP_PORT_WIDTH_1; |
a4fc5ed6 KP |
720 | break; |
721 | case 2: | |
ea5b213a | 722 | intel_dp->DP |= DP_PORT_WIDTH_2; |
a4fc5ed6 KP |
723 | break; |
724 | case 4: | |
ea5b213a | 725 | intel_dp->DP |= DP_PORT_WIDTH_4; |
a4fc5ed6 KP |
726 | break; |
727 | } | |
ea5b213a CW |
728 | if (intel_dp->has_audio) |
729 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; | |
a4fc5ed6 | 730 | |
ea5b213a CW |
731 | memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); |
732 | intel_dp->link_configuration[0] = intel_dp->link_bw; | |
733 | intel_dp->link_configuration[1] = intel_dp->lane_count; | |
a4fc5ed6 KP |
734 | |
735 | /* | |
9962c925 | 736 | * Check for DPCD version > 1.1 and enhanced framing support |
a4fc5ed6 | 737 | */ |
ea5b213a CW |
738 | if (intel_dp->dpcd[0] >= 0x11 && (intel_dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)) { |
739 | intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; | |
740 | intel_dp->DP |= DP_ENHANCED_FRAMING; | |
a4fc5ed6 KP |
741 | } |
742 | ||
e3421a18 ZW |
743 | /* CPT DP's pipe select is decided in TRANS_DP_CTL */ |
744 | if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev)) | |
ea5b213a | 745 | intel_dp->DP |= DP_PIPEB_SELECT; |
32f9d658 | 746 | |
ea5b213a | 747 | if (IS_eDP(intel_dp)) { |
32f9d658 | 748 | /* don't miss out required setting for eDP */ |
ea5b213a | 749 | intel_dp->DP |= DP_PLL_ENABLE; |
32f9d658 | 750 | if (adjusted_mode->clock < 200000) |
ea5b213a | 751 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
32f9d658 | 752 | else |
ea5b213a | 753 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
32f9d658 | 754 | } |
a4fc5ed6 KP |
755 | } |
756 | ||
9934c132 JB |
757 | static void ironlake_edp_panel_on (struct drm_device *dev) |
758 | { | |
759 | struct drm_i915_private *dev_priv = dev->dev_private; | |
913d8d11 | 760 | u32 pp; |
9934c132 | 761 | |
913d8d11 | 762 | if (I915_READ(PCH_PP_STATUS) & PP_ON) |
9934c132 JB |
763 | return; |
764 | ||
765 | pp = I915_READ(PCH_PP_CONTROL); | |
37c6c9b0 JB |
766 | |
767 | /* ILK workaround: disable reset around power sequence */ | |
768 | pp &= ~PANEL_POWER_RESET; | |
769 | I915_WRITE(PCH_PP_CONTROL, pp); | |
770 | POSTING_READ(PCH_PP_CONTROL); | |
771 | ||
9934c132 JB |
772 | pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON; |
773 | I915_WRITE(PCH_PP_CONTROL, pp); | |
9934c132 | 774 | |
913d8d11 CW |
775 | if (wait_for(I915_READ(PCH_PP_STATUS) & PP_ON, 5000, 10)) |
776 | DRM_ERROR("panel on wait timed out: 0x%08x\n", | |
777 | I915_READ(PCH_PP_STATUS)); | |
9934c132 JB |
778 | |
779 | pp &= ~(PANEL_UNLOCK_REGS | EDP_FORCE_VDD); | |
37c6c9b0 | 780 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
9934c132 | 781 | I915_WRITE(PCH_PP_CONTROL, pp); |
37c6c9b0 | 782 | POSTING_READ(PCH_PP_CONTROL); |
9934c132 JB |
783 | } |
784 | ||
785 | static void ironlake_edp_panel_off (struct drm_device *dev) | |
786 | { | |
787 | struct drm_i915_private *dev_priv = dev->dev_private; | |
913d8d11 | 788 | u32 pp; |
9934c132 JB |
789 | |
790 | pp = I915_READ(PCH_PP_CONTROL); | |
37c6c9b0 JB |
791 | |
792 | /* ILK workaround: disable reset around power sequence */ | |
793 | pp &= ~PANEL_POWER_RESET; | |
794 | I915_WRITE(PCH_PP_CONTROL, pp); | |
795 | POSTING_READ(PCH_PP_CONTROL); | |
796 | ||
9934c132 JB |
797 | pp &= ~POWER_TARGET_ON; |
798 | I915_WRITE(PCH_PP_CONTROL, pp); | |
9934c132 | 799 | |
913d8d11 CW |
800 | if (wait_for((I915_READ(PCH_PP_STATUS) & PP_ON) == 0, 5000, 10)) |
801 | DRM_ERROR("panel off wait timed out: 0x%08x\n", | |
802 | I915_READ(PCH_PP_STATUS)); | |
9934c132 JB |
803 | |
804 | /* Make sure VDD is enabled so DP AUX will work */ | |
37c6c9b0 | 805 | pp |= EDP_FORCE_VDD | PANEL_POWER_RESET; /* restore panel reset bit */ |
9934c132 | 806 | I915_WRITE(PCH_PP_CONTROL, pp); |
37c6c9b0 | 807 | POSTING_READ(PCH_PP_CONTROL); |
9934c132 JB |
808 | } |
809 | ||
f2b115e6 | 810 | static void ironlake_edp_backlight_on (struct drm_device *dev) |
32f9d658 ZW |
811 | { |
812 | struct drm_i915_private *dev_priv = dev->dev_private; | |
813 | u32 pp; | |
814 | ||
28c97730 | 815 | DRM_DEBUG_KMS("\n"); |
32f9d658 ZW |
816 | pp = I915_READ(PCH_PP_CONTROL); |
817 | pp |= EDP_BLC_ENABLE; | |
818 | I915_WRITE(PCH_PP_CONTROL, pp); | |
819 | } | |
820 | ||
f2b115e6 | 821 | static void ironlake_edp_backlight_off (struct drm_device *dev) |
32f9d658 ZW |
822 | { |
823 | struct drm_i915_private *dev_priv = dev->dev_private; | |
824 | u32 pp; | |
825 | ||
28c97730 | 826 | DRM_DEBUG_KMS("\n"); |
32f9d658 ZW |
827 | pp = I915_READ(PCH_PP_CONTROL); |
828 | pp &= ~EDP_BLC_ENABLE; | |
829 | I915_WRITE(PCH_PP_CONTROL, pp); | |
830 | } | |
a4fc5ed6 | 831 | |
d240f20f JB |
832 | static void ironlake_edp_pll_on(struct drm_encoder *encoder) |
833 | { | |
834 | struct drm_device *dev = encoder->dev; | |
835 | struct drm_i915_private *dev_priv = dev->dev_private; | |
836 | u32 dpa_ctl; | |
837 | ||
838 | DRM_DEBUG_KMS("\n"); | |
839 | dpa_ctl = I915_READ(DP_A); | |
840 | dpa_ctl &= ~DP_PLL_ENABLE; | |
841 | I915_WRITE(DP_A, dpa_ctl); | |
842 | } | |
843 | ||
844 | static void ironlake_edp_pll_off(struct drm_encoder *encoder) | |
845 | { | |
846 | struct drm_device *dev = encoder->dev; | |
847 | struct drm_i915_private *dev_priv = dev->dev_private; | |
848 | u32 dpa_ctl; | |
849 | ||
850 | dpa_ctl = I915_READ(DP_A); | |
851 | dpa_ctl |= DP_PLL_ENABLE; | |
852 | I915_WRITE(DP_A, dpa_ctl); | |
853 | udelay(200); | |
854 | } | |
855 | ||
856 | static void intel_dp_prepare(struct drm_encoder *encoder) | |
857 | { | |
858 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
859 | struct drm_device *dev = encoder->dev; | |
860 | struct drm_i915_private *dev_priv = dev->dev_private; | |
861 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); | |
862 | ||
863 | if (IS_eDP(intel_dp)) { | |
864 | ironlake_edp_backlight_off(dev); | |
865 | ironlake_edp_panel_on(dev); | |
866 | ironlake_edp_pll_on(encoder); | |
867 | } | |
868 | if (dp_reg & DP_PORT_EN) | |
869 | intel_dp_link_down(intel_dp); | |
870 | } | |
871 | ||
872 | static void intel_dp_commit(struct drm_encoder *encoder) | |
873 | { | |
874 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
875 | struct drm_device *dev = encoder->dev; | |
876 | struct drm_i915_private *dev_priv = dev->dev_private; | |
877 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); | |
878 | ||
879 | if (!(dp_reg & DP_PORT_EN)) { | |
880 | intel_dp_link_train(intel_dp); | |
881 | } | |
882 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) | |
883 | ironlake_edp_backlight_on(dev); | |
884 | } | |
885 | ||
a4fc5ed6 KP |
886 | static void |
887 | intel_dp_dpms(struct drm_encoder *encoder, int mode) | |
888 | { | |
ea5b213a | 889 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
55f78c43 | 890 | struct drm_device *dev = encoder->dev; |
a4fc5ed6 | 891 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 892 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
a4fc5ed6 KP |
893 | |
894 | if (mode != DRM_MODE_DPMS_ON) { | |
7643a7fa JB |
895 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) { |
896 | ironlake_edp_backlight_off(dev); | |
897 | ironlake_edp_panel_off(dev); | |
32f9d658 | 898 | } |
7643a7fa JB |
899 | if (dp_reg & DP_PORT_EN) |
900 | intel_dp_link_down(intel_dp); | |
d240f20f JB |
901 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) |
902 | ironlake_edp_pll_off(encoder); | |
a4fc5ed6 | 903 | } else { |
32f9d658 | 904 | if (!(dp_reg & DP_PORT_EN)) { |
7643a7fa | 905 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) |
9934c132 | 906 | ironlake_edp_panel_on(dev); |
7643a7fa JB |
907 | intel_dp_link_train(intel_dp); |
908 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) | |
f2b115e6 | 909 | ironlake_edp_backlight_on(dev); |
32f9d658 | 910 | } |
a4fc5ed6 | 911 | } |
ea5b213a | 912 | intel_dp->dpms_mode = mode; |
a4fc5ed6 KP |
913 | } |
914 | ||
915 | /* | |
916 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
917 | * link status information | |
918 | */ | |
919 | static bool | |
ea5b213a | 920 | intel_dp_get_link_status(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
921 | uint8_t link_status[DP_LINK_STATUS_SIZE]) |
922 | { | |
923 | int ret; | |
924 | ||
ea5b213a | 925 | ret = intel_dp_aux_native_read(intel_dp, |
a4fc5ed6 KP |
926 | DP_LANE0_1_STATUS, |
927 | link_status, DP_LINK_STATUS_SIZE); | |
928 | if (ret != DP_LINK_STATUS_SIZE) | |
929 | return false; | |
930 | return true; | |
931 | } | |
932 | ||
933 | static uint8_t | |
934 | intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
935 | int r) | |
936 | { | |
937 | return link_status[r - DP_LANE0_1_STATUS]; | |
938 | } | |
939 | ||
a4fc5ed6 KP |
940 | static uint8_t |
941 | intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
942 | int lane) | |
943 | { | |
944 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); | |
945 | int s = ((lane & 1) ? | |
946 | DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : | |
947 | DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); | |
948 | uint8_t l = intel_dp_link_status(link_status, i); | |
949 | ||
950 | return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; | |
951 | } | |
952 | ||
953 | static uint8_t | |
954 | intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
955 | int lane) | |
956 | { | |
957 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); | |
958 | int s = ((lane & 1) ? | |
959 | DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : | |
960 | DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); | |
961 | uint8_t l = intel_dp_link_status(link_status, i); | |
962 | ||
963 | return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; | |
964 | } | |
965 | ||
966 | ||
967 | #if 0 | |
968 | static char *voltage_names[] = { | |
969 | "0.4V", "0.6V", "0.8V", "1.2V" | |
970 | }; | |
971 | static char *pre_emph_names[] = { | |
972 | "0dB", "3.5dB", "6dB", "9.5dB" | |
973 | }; | |
974 | static char *link_train_names[] = { | |
975 | "pattern 1", "pattern 2", "idle", "off" | |
976 | }; | |
977 | #endif | |
978 | ||
979 | /* | |
980 | * These are source-specific values; current Intel hardware supports | |
981 | * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB | |
982 | */ | |
983 | #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800 | |
984 | ||
985 | static uint8_t | |
986 | intel_dp_pre_emphasis_max(uint8_t voltage_swing) | |
987 | { | |
988 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
989 | case DP_TRAIN_VOLTAGE_SWING_400: | |
990 | return DP_TRAIN_PRE_EMPHASIS_6; | |
991 | case DP_TRAIN_VOLTAGE_SWING_600: | |
992 | return DP_TRAIN_PRE_EMPHASIS_6; | |
993 | case DP_TRAIN_VOLTAGE_SWING_800: | |
994 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
995 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
996 | default: | |
997 | return DP_TRAIN_PRE_EMPHASIS_0; | |
998 | } | |
999 | } | |
1000 | ||
1001 | static void | |
ea5b213a | 1002 | intel_get_adjust_train(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
1003 | uint8_t link_status[DP_LINK_STATUS_SIZE], |
1004 | int lane_count, | |
1005 | uint8_t train_set[4]) | |
1006 | { | |
1007 | uint8_t v = 0; | |
1008 | uint8_t p = 0; | |
1009 | int lane; | |
1010 | ||
1011 | for (lane = 0; lane < lane_count; lane++) { | |
1012 | uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane); | |
1013 | uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane); | |
1014 | ||
1015 | if (this_v > v) | |
1016 | v = this_v; | |
1017 | if (this_p > p) | |
1018 | p = this_p; | |
1019 | } | |
1020 | ||
1021 | if (v >= I830_DP_VOLTAGE_MAX) | |
1022 | v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED; | |
1023 | ||
1024 | if (p >= intel_dp_pre_emphasis_max(v)) | |
1025 | p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; | |
1026 | ||
1027 | for (lane = 0; lane < 4; lane++) | |
1028 | train_set[lane] = v | p; | |
1029 | } | |
1030 | ||
1031 | static uint32_t | |
1032 | intel_dp_signal_levels(uint8_t train_set, int lane_count) | |
1033 | { | |
1034 | uint32_t signal_levels = 0; | |
1035 | ||
1036 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
1037 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1038 | default: | |
1039 | signal_levels |= DP_VOLTAGE_0_4; | |
1040 | break; | |
1041 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1042 | signal_levels |= DP_VOLTAGE_0_6; | |
1043 | break; | |
1044 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1045 | signal_levels |= DP_VOLTAGE_0_8; | |
1046 | break; | |
1047 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1048 | signal_levels |= DP_VOLTAGE_1_2; | |
1049 | break; | |
1050 | } | |
1051 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
1052 | case DP_TRAIN_PRE_EMPHASIS_0: | |
1053 | default: | |
1054 | signal_levels |= DP_PRE_EMPHASIS_0; | |
1055 | break; | |
1056 | case DP_TRAIN_PRE_EMPHASIS_3_5: | |
1057 | signal_levels |= DP_PRE_EMPHASIS_3_5; | |
1058 | break; | |
1059 | case DP_TRAIN_PRE_EMPHASIS_6: | |
1060 | signal_levels |= DP_PRE_EMPHASIS_6; | |
1061 | break; | |
1062 | case DP_TRAIN_PRE_EMPHASIS_9_5: | |
1063 | signal_levels |= DP_PRE_EMPHASIS_9_5; | |
1064 | break; | |
1065 | } | |
1066 | return signal_levels; | |
1067 | } | |
1068 | ||
e3421a18 ZW |
1069 | /* Gen6's DP voltage swing and pre-emphasis control */ |
1070 | static uint32_t | |
1071 | intel_gen6_edp_signal_levels(uint8_t train_set) | |
1072 | { | |
1073 | switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) { | |
1074 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: | |
1075 | return EDP_LINK_TRAIN_400MV_0DB_SNB_B; | |
1076 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: | |
1077 | return EDP_LINK_TRAIN_400MV_6DB_SNB_B; | |
1078 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
1079 | return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B; | |
1080 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: | |
1081 | return EDP_LINK_TRAIN_800MV_0DB_SNB_B; | |
1082 | default: | |
1083 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n"); | |
1084 | return EDP_LINK_TRAIN_400MV_0DB_SNB_B; | |
1085 | } | |
1086 | } | |
1087 | ||
a4fc5ed6 KP |
1088 | static uint8_t |
1089 | intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1090 | int lane) | |
1091 | { | |
1092 | int i = DP_LANE0_1_STATUS + (lane >> 1); | |
1093 | int s = (lane & 1) * 4; | |
1094 | uint8_t l = intel_dp_link_status(link_status, i); | |
1095 | ||
1096 | return (l >> s) & 0xf; | |
1097 | } | |
1098 | ||
1099 | /* Check for clock recovery is done on all channels */ | |
1100 | static bool | |
1101 | intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) | |
1102 | { | |
1103 | int lane; | |
1104 | uint8_t lane_status; | |
1105 | ||
1106 | for (lane = 0; lane < lane_count; lane++) { | |
1107 | lane_status = intel_get_lane_status(link_status, lane); | |
1108 | if ((lane_status & DP_LANE_CR_DONE) == 0) | |
1109 | return false; | |
1110 | } | |
1111 | return true; | |
1112 | } | |
1113 | ||
1114 | /* Check to see if channel eq is done on all channels */ | |
1115 | #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\ | |
1116 | DP_LANE_CHANNEL_EQ_DONE|\ | |
1117 | DP_LANE_SYMBOL_LOCKED) | |
1118 | static bool | |
1119 | intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) | |
1120 | { | |
1121 | uint8_t lane_align; | |
1122 | uint8_t lane_status; | |
1123 | int lane; | |
1124 | ||
1125 | lane_align = intel_dp_link_status(link_status, | |
1126 | DP_LANE_ALIGN_STATUS_UPDATED); | |
1127 | if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) | |
1128 | return false; | |
1129 | for (lane = 0; lane < lane_count; lane++) { | |
1130 | lane_status = intel_get_lane_status(link_status, lane); | |
1131 | if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) | |
1132 | return false; | |
1133 | } | |
1134 | return true; | |
1135 | } | |
1136 | ||
1137 | static bool | |
ea5b213a | 1138 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
1139 | uint32_t dp_reg_value, |
1140 | uint8_t dp_train_pat, | |
1141 | uint8_t train_set[4], | |
1142 | bool first) | |
1143 | { | |
ea5b213a | 1144 | struct drm_device *dev = intel_dp->base.enc.dev; |
a4fc5ed6 | 1145 | struct drm_i915_private *dev_priv = dev->dev_private; |
9d0498a2 | 1146 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.enc.crtc); |
a4fc5ed6 KP |
1147 | int ret; |
1148 | ||
ea5b213a CW |
1149 | I915_WRITE(intel_dp->output_reg, dp_reg_value); |
1150 | POSTING_READ(intel_dp->output_reg); | |
a4fc5ed6 | 1151 | if (first) |
9d0498a2 | 1152 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
a4fc5ed6 | 1153 | |
ea5b213a | 1154 | intel_dp_aux_native_write_1(intel_dp, |
a4fc5ed6 KP |
1155 | DP_TRAINING_PATTERN_SET, |
1156 | dp_train_pat); | |
1157 | ||
ea5b213a | 1158 | ret = intel_dp_aux_native_write(intel_dp, |
a4fc5ed6 KP |
1159 | DP_TRAINING_LANE0_SET, train_set, 4); |
1160 | if (ret != 4) | |
1161 | return false; | |
1162 | ||
1163 | return true; | |
1164 | } | |
1165 | ||
1166 | static void | |
ea5b213a | 1167 | intel_dp_link_train(struct intel_dp *intel_dp) |
a4fc5ed6 | 1168 | { |
ea5b213a | 1169 | struct drm_device *dev = intel_dp->base.enc.dev; |
a4fc5ed6 | 1170 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4fc5ed6 KP |
1171 | uint8_t train_set[4]; |
1172 | uint8_t link_status[DP_LINK_STATUS_SIZE]; | |
1173 | int i; | |
1174 | uint8_t voltage; | |
1175 | bool clock_recovery = false; | |
1176 | bool channel_eq = false; | |
1177 | bool first = true; | |
1178 | int tries; | |
e3421a18 | 1179 | u32 reg; |
ea5b213a | 1180 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 KP |
1181 | |
1182 | /* Write the link configuration data */ | |
ea5b213a CW |
1183 | intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, |
1184 | intel_dp->link_configuration, | |
1185 | DP_LINK_CONFIGURATION_SIZE); | |
a4fc5ed6 KP |
1186 | |
1187 | DP |= DP_PORT_EN; | |
ea5b213a | 1188 | if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) |
e3421a18 ZW |
1189 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
1190 | else | |
1191 | DP &= ~DP_LINK_TRAIN_MASK; | |
a4fc5ed6 KP |
1192 | memset(train_set, 0, 4); |
1193 | voltage = 0xff; | |
1194 | tries = 0; | |
1195 | clock_recovery = false; | |
1196 | for (;;) { | |
1197 | /* Use train_set[0] to set the voltage and pre emphasis values */ | |
e3421a18 | 1198 | uint32_t signal_levels; |
ea5b213a | 1199 | if (IS_GEN6(dev) && IS_eDP(intel_dp)) { |
e3421a18 ZW |
1200 | signal_levels = intel_gen6_edp_signal_levels(train_set[0]); |
1201 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; | |
1202 | } else { | |
ea5b213a | 1203 | signal_levels = intel_dp_signal_levels(train_set[0], intel_dp->lane_count); |
e3421a18 ZW |
1204 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1205 | } | |
a4fc5ed6 | 1206 | |
ea5b213a | 1207 | if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) |
e3421a18 ZW |
1208 | reg = DP | DP_LINK_TRAIN_PAT_1_CPT; |
1209 | else | |
1210 | reg = DP | DP_LINK_TRAIN_PAT_1; | |
1211 | ||
ea5b213a | 1212 | if (!intel_dp_set_link_train(intel_dp, reg, |
a4fc5ed6 KP |
1213 | DP_TRAINING_PATTERN_1, train_set, first)) |
1214 | break; | |
1215 | first = false; | |
1216 | /* Set training pattern 1 */ | |
1217 | ||
1218 | udelay(100); | |
ea5b213a | 1219 | if (!intel_dp_get_link_status(intel_dp, link_status)) |
a4fc5ed6 KP |
1220 | break; |
1221 | ||
ea5b213a | 1222 | if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
a4fc5ed6 KP |
1223 | clock_recovery = true; |
1224 | break; | |
1225 | } | |
1226 | ||
1227 | /* Check to see if we've tried the max voltage */ | |
ea5b213a | 1228 | for (i = 0; i < intel_dp->lane_count; i++) |
a4fc5ed6 KP |
1229 | if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) |
1230 | break; | |
ea5b213a | 1231 | if (i == intel_dp->lane_count) |
a4fc5ed6 KP |
1232 | break; |
1233 | ||
1234 | /* Check to see if we've tried the same voltage 5 times */ | |
1235 | if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { | |
1236 | ++tries; | |
1237 | if (tries == 5) | |
1238 | break; | |
1239 | } else | |
1240 | tries = 0; | |
1241 | voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; | |
1242 | ||
1243 | /* Compute new train_set as requested by target */ | |
ea5b213a | 1244 | intel_get_adjust_train(intel_dp, link_status, intel_dp->lane_count, train_set); |
a4fc5ed6 KP |
1245 | } |
1246 | ||
1247 | /* channel equalization */ | |
1248 | tries = 0; | |
1249 | channel_eq = false; | |
1250 | for (;;) { | |
1251 | /* Use train_set[0] to set the voltage and pre emphasis values */ | |
e3421a18 ZW |
1252 | uint32_t signal_levels; |
1253 | ||
ea5b213a | 1254 | if (IS_GEN6(dev) && IS_eDP(intel_dp)) { |
e3421a18 ZW |
1255 | signal_levels = intel_gen6_edp_signal_levels(train_set[0]); |
1256 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; | |
1257 | } else { | |
ea5b213a | 1258 | signal_levels = intel_dp_signal_levels(train_set[0], intel_dp->lane_count); |
e3421a18 ZW |
1259 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1260 | } | |
1261 | ||
ea5b213a | 1262 | if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) |
e3421a18 ZW |
1263 | reg = DP | DP_LINK_TRAIN_PAT_2_CPT; |
1264 | else | |
1265 | reg = DP | DP_LINK_TRAIN_PAT_2; | |
a4fc5ed6 KP |
1266 | |
1267 | /* channel eq pattern */ | |
ea5b213a | 1268 | if (!intel_dp_set_link_train(intel_dp, reg, |
a4fc5ed6 KP |
1269 | DP_TRAINING_PATTERN_2, train_set, |
1270 | false)) | |
1271 | break; | |
1272 | ||
1273 | udelay(400); | |
ea5b213a | 1274 | if (!intel_dp_get_link_status(intel_dp, link_status)) |
a4fc5ed6 KP |
1275 | break; |
1276 | ||
ea5b213a | 1277 | if (intel_channel_eq_ok(link_status, intel_dp->lane_count)) { |
a4fc5ed6 KP |
1278 | channel_eq = true; |
1279 | break; | |
1280 | } | |
1281 | ||
1282 | /* Try 5 times */ | |
1283 | if (tries > 5) | |
1284 | break; | |
1285 | ||
1286 | /* Compute new train_set as requested by target */ | |
ea5b213a | 1287 | intel_get_adjust_train(intel_dp, link_status, intel_dp->lane_count, train_set); |
a4fc5ed6 KP |
1288 | ++tries; |
1289 | } | |
1290 | ||
ea5b213a | 1291 | if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) |
e3421a18 ZW |
1292 | reg = DP | DP_LINK_TRAIN_OFF_CPT; |
1293 | else | |
1294 | reg = DP | DP_LINK_TRAIN_OFF; | |
1295 | ||
ea5b213a CW |
1296 | I915_WRITE(intel_dp->output_reg, reg); |
1297 | POSTING_READ(intel_dp->output_reg); | |
1298 | intel_dp_aux_native_write_1(intel_dp, | |
a4fc5ed6 KP |
1299 | DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); |
1300 | } | |
1301 | ||
1302 | static void | |
ea5b213a | 1303 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 1304 | { |
ea5b213a | 1305 | struct drm_device *dev = intel_dp->base.enc.dev; |
a4fc5ed6 | 1306 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 1307 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 1308 | |
28c97730 | 1309 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 1310 | |
ea5b213a | 1311 | if (IS_eDP(intel_dp)) { |
32f9d658 | 1312 | DP &= ~DP_PLL_ENABLE; |
ea5b213a CW |
1313 | I915_WRITE(intel_dp->output_reg, DP); |
1314 | POSTING_READ(intel_dp->output_reg); | |
32f9d658 ZW |
1315 | udelay(100); |
1316 | } | |
1317 | ||
ea5b213a | 1318 | if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) { |
e3421a18 | 1319 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
ea5b213a CW |
1320 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
1321 | POSTING_READ(intel_dp->output_reg); | |
e3421a18 ZW |
1322 | } else { |
1323 | DP &= ~DP_LINK_TRAIN_MASK; | |
ea5b213a CW |
1324 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
1325 | POSTING_READ(intel_dp->output_reg); | |
e3421a18 | 1326 | } |
5eb08b69 ZW |
1327 | |
1328 | udelay(17000); | |
1329 | ||
ea5b213a | 1330 | if (IS_eDP(intel_dp)) |
32f9d658 | 1331 | DP |= DP_LINK_TRAIN_OFF; |
ea5b213a CW |
1332 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
1333 | POSTING_READ(intel_dp->output_reg); | |
a4fc5ed6 KP |
1334 | } |
1335 | ||
a4fc5ed6 KP |
1336 | /* |
1337 | * According to DP spec | |
1338 | * 5.1.2: | |
1339 | * 1. Read DPCD | |
1340 | * 2. Configure link according to Receiver Capabilities | |
1341 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
1342 | * 4. Check link status on receipt of hot-plug interrupt | |
1343 | */ | |
1344 | ||
1345 | static void | |
ea5b213a | 1346 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
a4fc5ed6 | 1347 | { |
a4fc5ed6 KP |
1348 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
1349 | ||
ea5b213a | 1350 | if (!intel_dp->base.enc.crtc) |
a4fc5ed6 KP |
1351 | return; |
1352 | ||
ea5b213a CW |
1353 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
1354 | intel_dp_link_down(intel_dp); | |
a4fc5ed6 KP |
1355 | return; |
1356 | } | |
1357 | ||
ea5b213a CW |
1358 | if (!intel_channel_eq_ok(link_status, intel_dp->lane_count)) |
1359 | intel_dp_link_train(intel_dp); | |
a4fc5ed6 | 1360 | } |
a4fc5ed6 | 1361 | |
5eb08b69 | 1362 | static enum drm_connector_status |
f2b115e6 | 1363 | ironlake_dp_detect(struct drm_connector *connector) |
5eb08b69 | 1364 | { |
55f78c43 | 1365 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
ea5b213a | 1366 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
5eb08b69 ZW |
1367 | enum drm_connector_status status; |
1368 | ||
1369 | status = connector_status_disconnected; | |
ea5b213a CW |
1370 | if (intel_dp_aux_native_read(intel_dp, |
1371 | 0x000, intel_dp->dpcd, | |
1372 | sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) | |
5eb08b69 | 1373 | { |
ea5b213a | 1374 | if (intel_dp->dpcd[0] != 0) |
5eb08b69 ZW |
1375 | status = connector_status_connected; |
1376 | } | |
ea5b213a CW |
1377 | DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0], |
1378 | intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]); | |
5eb08b69 ZW |
1379 | return status; |
1380 | } | |
1381 | ||
a4fc5ed6 KP |
1382 | /** |
1383 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. | |
1384 | * | |
1385 | * \return true if DP port is connected. | |
1386 | * \return false if DP port is disconnected. | |
1387 | */ | |
1388 | static enum drm_connector_status | |
1389 | intel_dp_detect(struct drm_connector *connector) | |
1390 | { | |
55f78c43 | 1391 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
ea5b213a CW |
1392 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
1393 | struct drm_device *dev = intel_dp->base.enc.dev; | |
a4fc5ed6 | 1394 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4fc5ed6 KP |
1395 | uint32_t temp, bit; |
1396 | enum drm_connector_status status; | |
1397 | ||
ea5b213a | 1398 | intel_dp->has_audio = false; |
a4fc5ed6 | 1399 | |
c619eed4 | 1400 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 1401 | return ironlake_dp_detect(connector); |
5eb08b69 | 1402 | |
ea5b213a | 1403 | switch (intel_dp->output_reg) { |
a4fc5ed6 KP |
1404 | case DP_B: |
1405 | bit = DPB_HOTPLUG_INT_STATUS; | |
1406 | break; | |
1407 | case DP_C: | |
1408 | bit = DPC_HOTPLUG_INT_STATUS; | |
1409 | break; | |
1410 | case DP_D: | |
1411 | bit = DPD_HOTPLUG_INT_STATUS; | |
1412 | break; | |
1413 | default: | |
1414 | return connector_status_unknown; | |
1415 | } | |
1416 | ||
1417 | temp = I915_READ(PORT_HOTPLUG_STAT); | |
1418 | ||
1419 | if ((temp & bit) == 0) | |
1420 | return connector_status_disconnected; | |
1421 | ||
1422 | status = connector_status_disconnected; | |
ea5b213a CW |
1423 | if (intel_dp_aux_native_read(intel_dp, |
1424 | 0x000, intel_dp->dpcd, | |
1425 | sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) | |
a4fc5ed6 | 1426 | { |
ea5b213a | 1427 | if (intel_dp->dpcd[0] != 0) |
a4fc5ed6 KP |
1428 | status = connector_status_connected; |
1429 | } | |
1430 | return status; | |
1431 | } | |
1432 | ||
1433 | static int intel_dp_get_modes(struct drm_connector *connector) | |
1434 | { | |
55f78c43 | 1435 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
ea5b213a CW |
1436 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
1437 | struct drm_device *dev = intel_dp->base.enc.dev; | |
32f9d658 ZW |
1438 | struct drm_i915_private *dev_priv = dev->dev_private; |
1439 | int ret; | |
a4fc5ed6 KP |
1440 | |
1441 | /* We should parse the EDID data and find out if it has an audio sink | |
1442 | */ | |
1443 | ||
ea5b213a | 1444 | ret = intel_ddc_get_modes(connector, intel_dp->base.ddc_bus); |
b9efc480 | 1445 | if (ret) { |
ea5b213a | 1446 | if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) && |
b9efc480 ZY |
1447 | !dev_priv->panel_fixed_mode) { |
1448 | struct drm_display_mode *newmode; | |
1449 | list_for_each_entry(newmode, &connector->probed_modes, | |
1450 | head) { | |
1451 | if (newmode->type & DRM_MODE_TYPE_PREFERRED) { | |
1452 | dev_priv->panel_fixed_mode = | |
1453 | drm_mode_duplicate(dev, newmode); | |
1454 | break; | |
1455 | } | |
1456 | } | |
1457 | } | |
1458 | ||
32f9d658 | 1459 | return ret; |
b9efc480 | 1460 | } |
32f9d658 ZW |
1461 | |
1462 | /* if eDP has no EDID, try to use fixed panel mode from VBT */ | |
ea5b213a | 1463 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) { |
32f9d658 ZW |
1464 | if (dev_priv->panel_fixed_mode != NULL) { |
1465 | struct drm_display_mode *mode; | |
1466 | mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode); | |
1467 | drm_mode_probed_add(connector, mode); | |
1468 | return 1; | |
1469 | } | |
1470 | } | |
1471 | return 0; | |
a4fc5ed6 KP |
1472 | } |
1473 | ||
1474 | static void | |
1475 | intel_dp_destroy (struct drm_connector *connector) | |
1476 | { | |
a4fc5ed6 KP |
1477 | drm_sysfs_connector_remove(connector); |
1478 | drm_connector_cleanup(connector); | |
55f78c43 | 1479 | kfree(connector); |
a4fc5ed6 KP |
1480 | } |
1481 | ||
1482 | static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { | |
1483 | .dpms = intel_dp_dpms, | |
1484 | .mode_fixup = intel_dp_mode_fixup, | |
d240f20f | 1485 | .prepare = intel_dp_prepare, |
a4fc5ed6 | 1486 | .mode_set = intel_dp_mode_set, |
d240f20f | 1487 | .commit = intel_dp_commit, |
a4fc5ed6 KP |
1488 | }; |
1489 | ||
1490 | static const struct drm_connector_funcs intel_dp_connector_funcs = { | |
1491 | .dpms = drm_helper_connector_dpms, | |
a4fc5ed6 KP |
1492 | .detect = intel_dp_detect, |
1493 | .fill_modes = drm_helper_probe_single_connector_modes, | |
1494 | .destroy = intel_dp_destroy, | |
1495 | }; | |
1496 | ||
1497 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
1498 | .get_modes = intel_dp_get_modes, | |
1499 | .mode_valid = intel_dp_mode_valid, | |
55f78c43 | 1500 | .best_encoder = intel_attached_encoder, |
a4fc5ed6 KP |
1501 | }; |
1502 | ||
a4fc5ed6 | 1503 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
ea5b213a | 1504 | .destroy = intel_encoder_destroy, |
a4fc5ed6 KP |
1505 | }; |
1506 | ||
c8110e52 | 1507 | void |
21d40d37 | 1508 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
c8110e52 | 1509 | { |
ea5b213a | 1510 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
c8110e52 | 1511 | |
ea5b213a CW |
1512 | if (intel_dp->dpms_mode == DRM_MODE_DPMS_ON) |
1513 | intel_dp_check_link_status(intel_dp); | |
c8110e52 | 1514 | } |
6207937d | 1515 | |
e3421a18 ZW |
1516 | /* Return which DP Port should be selected for Transcoder DP control */ |
1517 | int | |
1518 | intel_trans_dp_port_sel (struct drm_crtc *crtc) | |
1519 | { | |
1520 | struct drm_device *dev = crtc->dev; | |
1521 | struct drm_mode_config *mode_config = &dev->mode_config; | |
1522 | struct drm_encoder *encoder; | |
e3421a18 ZW |
1523 | |
1524 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { | |
ea5b213a CW |
1525 | struct intel_dp *intel_dp; |
1526 | ||
d8201ab6 | 1527 | if (encoder->crtc != crtc) |
e3421a18 ZW |
1528 | continue; |
1529 | ||
ea5b213a CW |
1530 | intel_dp = enc_to_intel_dp(encoder); |
1531 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) | |
1532 | return intel_dp->output_reg; | |
e3421a18 | 1533 | } |
ea5b213a | 1534 | |
e3421a18 ZW |
1535 | return -1; |
1536 | } | |
1537 | ||
36e83a18 | 1538 | /* check the VBT to see whether the eDP is on DP-D port */ |
cb0953d7 | 1539 | bool intel_dpd_is_edp(struct drm_device *dev) |
36e83a18 ZY |
1540 | { |
1541 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1542 | struct child_device_config *p_child; | |
1543 | int i; | |
1544 | ||
1545 | if (!dev_priv->child_dev_num) | |
1546 | return false; | |
1547 | ||
1548 | for (i = 0; i < dev_priv->child_dev_num; i++) { | |
1549 | p_child = dev_priv->child_dev + i; | |
1550 | ||
1551 | if (p_child->dvo_port == PORT_IDPD && | |
1552 | p_child->device_type == DEVICE_TYPE_eDP) | |
1553 | return true; | |
1554 | } | |
1555 | return false; | |
1556 | } | |
1557 | ||
a4fc5ed6 KP |
1558 | void |
1559 | intel_dp_init(struct drm_device *dev, int output_reg) | |
1560 | { | |
1561 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1562 | struct drm_connector *connector; | |
ea5b213a | 1563 | struct intel_dp *intel_dp; |
21d40d37 | 1564 | struct intel_encoder *intel_encoder; |
55f78c43 | 1565 | struct intel_connector *intel_connector; |
5eb08b69 | 1566 | const char *name = NULL; |
b329530c | 1567 | int type; |
a4fc5ed6 | 1568 | |
ea5b213a CW |
1569 | intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL); |
1570 | if (!intel_dp) | |
a4fc5ed6 KP |
1571 | return; |
1572 | ||
55f78c43 ZW |
1573 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
1574 | if (!intel_connector) { | |
ea5b213a | 1575 | kfree(intel_dp); |
55f78c43 ZW |
1576 | return; |
1577 | } | |
ea5b213a | 1578 | intel_encoder = &intel_dp->base; |
55f78c43 | 1579 | |
ea5b213a | 1580 | if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D) |
b329530c | 1581 | if (intel_dpd_is_edp(dev)) |
ea5b213a | 1582 | intel_dp->is_pch_edp = true; |
b329530c | 1583 | |
ea5b213a | 1584 | if (output_reg == DP_A || IS_PCH_eDP(intel_dp)) { |
b329530c AJ |
1585 | type = DRM_MODE_CONNECTOR_eDP; |
1586 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
1587 | } else { | |
1588 | type = DRM_MODE_CONNECTOR_DisplayPort; | |
1589 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
1590 | } | |
1591 | ||
55f78c43 | 1592 | connector = &intel_connector->base; |
b329530c | 1593 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
1594 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
1595 | ||
eb1f8e4f DA |
1596 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
1597 | ||
652af9d7 | 1598 | if (output_reg == DP_B || output_reg == PCH_DP_B) |
21d40d37 | 1599 | intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT); |
652af9d7 | 1600 | else if (output_reg == DP_C || output_reg == PCH_DP_C) |
21d40d37 | 1601 | intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT); |
652af9d7 | 1602 | else if (output_reg == DP_D || output_reg == PCH_DP_D) |
21d40d37 | 1603 | intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); |
f8aed700 | 1604 | |
ea5b213a | 1605 | if (IS_eDP(intel_dp)) |
21d40d37 | 1606 | intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT); |
6251ec0a | 1607 | |
21d40d37 | 1608 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
a4fc5ed6 KP |
1609 | connector->interlace_allowed = true; |
1610 | connector->doublescan_allowed = 0; | |
1611 | ||
ea5b213a CW |
1612 | intel_dp->output_reg = output_reg; |
1613 | intel_dp->has_audio = false; | |
1614 | intel_dp->dpms_mode = DRM_MODE_DPMS_ON; | |
a4fc5ed6 | 1615 | |
21d40d37 | 1616 | drm_encoder_init(dev, &intel_encoder->enc, &intel_dp_enc_funcs, |
a4fc5ed6 | 1617 | DRM_MODE_ENCODER_TMDS); |
21d40d37 | 1618 | drm_encoder_helper_add(&intel_encoder->enc, &intel_dp_helper_funcs); |
a4fc5ed6 | 1619 | |
55f78c43 | 1620 | drm_mode_connector_attach_encoder(&intel_connector->base, |
21d40d37 | 1621 | &intel_encoder->enc); |
a4fc5ed6 KP |
1622 | drm_sysfs_connector_add(connector); |
1623 | ||
1624 | /* Set up the DDC bus. */ | |
5eb08b69 | 1625 | switch (output_reg) { |
32f9d658 ZW |
1626 | case DP_A: |
1627 | name = "DPDDC-A"; | |
1628 | break; | |
5eb08b69 ZW |
1629 | case DP_B: |
1630 | case PCH_DP_B: | |
b01f2c3a JB |
1631 | dev_priv->hotplug_supported_mask |= |
1632 | HDMIB_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
1633 | name = "DPDDC-B"; |
1634 | break; | |
1635 | case DP_C: | |
1636 | case PCH_DP_C: | |
b01f2c3a JB |
1637 | dev_priv->hotplug_supported_mask |= |
1638 | HDMIC_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
1639 | name = "DPDDC-C"; |
1640 | break; | |
1641 | case DP_D: | |
1642 | case PCH_DP_D: | |
b01f2c3a JB |
1643 | dev_priv->hotplug_supported_mask |= |
1644 | HDMID_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
1645 | name = "DPDDC-D"; |
1646 | break; | |
1647 | } | |
1648 | ||
ea5b213a | 1649 | intel_dp_i2c_init(intel_dp, intel_connector, name); |
32f9d658 | 1650 | |
ea5b213a | 1651 | intel_encoder->ddc_bus = &intel_dp->adapter; |
21d40d37 | 1652 | intel_encoder->hot_plug = intel_dp_hot_plug; |
a4fc5ed6 | 1653 | |
ea5b213a | 1654 | if (output_reg == DP_A || IS_PCH_eDP(intel_dp)) { |
32f9d658 ZW |
1655 | /* initialize panel mode from VBT if available for eDP */ |
1656 | if (dev_priv->lfp_lvds_vbt_mode) { | |
1657 | dev_priv->panel_fixed_mode = | |
1658 | drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); | |
1659 | if (dev_priv->panel_fixed_mode) { | |
1660 | dev_priv->panel_fixed_mode->type |= | |
1661 | DRM_MODE_TYPE_PREFERRED; | |
1662 | } | |
1663 | } | |
1664 | } | |
1665 | ||
a4fc5ed6 KP |
1666 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
1667 | * 0xd. Failure to do so will result in spurious interrupts being | |
1668 | * generated on the port when a cable is not attached. | |
1669 | */ | |
1670 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
1671 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
1672 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
1673 | } | |
1674 | } |