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drm/i915: properly disable the VDD when disabling the panel
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
65ce4bf5
CML		 60static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
58f6e632 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
cfcb0fc9
JB		 67/**
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
70 *
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
73 */
74static bool is_edp(struct intel_dp *intel_dp)
75{
da63a9f2
PZ		 76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
77
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 79}
80
68b4d824 81static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 82{
68b4d824
ID		 83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
84
85 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 86}
87
df0e9248
CW		 88static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
89{
fa90ecef 90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 91}
92
ea5b213a 93static void intel_dp_link_down(struct intel_dp *intel_dp);
4be73780 94static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 95
a4fc5ed6 96static int
ea5b213a 97intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 98{
7183dc29 99 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 100 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 101
102 switch (max_link_bw) {
103 case DP_LINK_BW_1_62:
104 case DP_LINK_BW_2_7:
105 break;
d4eead50 106 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
06ea66b6
TP		 107 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
108 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
109 max_link_bw = DP_LINK_BW_5_4;
110 else
111 max_link_bw = DP_LINK_BW_2_7;
d4eead50 112 break;
a4fc5ed6 113 default:
d4eead50
ID		 114 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
115 max_link_bw);
a4fc5ed6
KP		 116 max_link_bw = DP_LINK_BW_1_62;
117 break;
118 }
119 return max_link_bw;
120}
121
cd9dde44
AJ		 122/*
123 * The units on the numbers in the next two are... bizarre. Examples will
124 * make it clearer; this one parallels an example in the eDP spec.
125 *
126 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
127 *
128 * 270000 * 1 * 8 / 10 == 216000
129 *
130 * The actual data capacity of that configuration is 2.16Gbit/s, so the
131 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
132 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
133 * 119000. At 18bpp that's 2142000 kilobits per second.
134 *
135 * Thus the strange-looking division by 10 in intel_dp_link_required, to
136 * get the result in decakilobits instead of kilobits.
137 */
138
a4fc5ed6 139static int
c898261c 140intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 141{
cd9dde44 142 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 143}
144
fe27d53e
DA		 145static int
146intel_dp_max_data_rate(int max_link_clock, int max_lanes)
147{
148 return (max_link_clock * max_lanes * 8) / 10;
149}
150
c19de8eb 151static enum drm_mode_status
a4fc5ed6
KP		 152intel_dp_mode_valid(struct drm_connector *connector,
153 struct drm_display_mode *mode)
154{
df0e9248 155 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 156 struct intel_connector *intel_connector = to_intel_connector(connector);
157 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 158 int target_clock = mode->clock;
159 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 160
dd06f90e
JN		 161 if (is_edp(intel_dp) && fixed_mode) {
162 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 163 return MODE_PANEL;
164
dd06f90e 165 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 166 return MODE_PANEL;
03afc4a2
DV		 167
168 target_clock = fixed_mode->clock;
7de56f43
ZY		 169 }
170
36008365
DV		 171 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
172 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
173
174 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
175 mode_rate = intel_dp_link_required(target_clock, 18);
176
177 if (mode_rate > max_rate)
c4867936 178 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 179
180 if (mode->clock < 10000)
181 return MODE_CLOCK_LOW;
182
0af78a2b
DV		 183 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
184 return MODE_H_ILLEGAL;
185
a4fc5ed6
KP		 186 return MODE_OK;
187}
188
189static uint32_t
190pack_aux(uint8_t *src, int src_bytes)
191{
192 int i;
193 uint32_t v = 0;
194
195 if (src_bytes > 4)
196 src_bytes = 4;
197 for (i = 0; i < src_bytes; i++)
198 v |= ((uint32_t) src[i]) << ((3-i) * 8);
199 return v;
200}
201
202static void
203unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
204{
205 int i;
206 if (dst_bytes > 4)
207 dst_bytes = 4;
208 for (i = 0; i < dst_bytes; i++)
209 dst[i] = src >> ((3-i) * 8);
210}
211
fb0f8fbf
KP		 212/* hrawclock is 1/4 the FSB frequency */
213static int
214intel_hrawclk(struct drm_device *dev)
215{
216 struct drm_i915_private *dev_priv = dev->dev_private;
217 uint32_t clkcfg;
218
9473c8f4
VP		 219 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
220 if (IS_VALLEYVIEW(dev))
221 return 200;
222
fb0f8fbf
KP		 223 clkcfg = I915_READ(CLKCFG);
224 switch (clkcfg & CLKCFG_FSB_MASK) {
225 case CLKCFG_FSB_400:
226 return 100;
227 case CLKCFG_FSB_533:
228 return 133;
229 case CLKCFG_FSB_667:
230 return 166;
231 case CLKCFG_FSB_800:
232 return 200;
233 case CLKCFG_FSB_1067:
234 return 266;
235 case CLKCFG_FSB_1333:
236 return 333;
237 /* these two are just a guess; one of them might be right */
238 case CLKCFG_FSB_1600:
239 case CLKCFG_FSB_1600_ALT:
240 return 400;
241 default:
242 return 133;
243 }
244}
245
bf13e81b
JN		 246static void
247intel_dp_init_panel_power_sequencer(struct drm_device *dev,
248 struct intel_dp *intel_dp,
249 struct edp_power_seq *out);
250static void
251intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
252 struct intel_dp *intel_dp,
253 struct edp_power_seq *out);
254
255static enum pipe
256vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
257{
258 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
259 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
260 struct drm_device *dev = intel_dig_port->base.base.dev;
261 struct drm_i915_private *dev_priv = dev->dev_private;
262 enum port port = intel_dig_port->port;
263 enum pipe pipe;
264
265 /* modeset should have pipe */
266 if (crtc)
267 return to_intel_crtc(crtc)->pipe;
268
269 /* init time, try to find a pipe with this port selected */
270 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
271 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
272 PANEL_PORT_SELECT_MASK;
273 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
274 return pipe;
275 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
276 return pipe;
277 }
278
279 /* shrug */
280 return PIPE_A;
281}
282
283static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
284{
285 struct drm_device *dev = intel_dp_to_dev(intel_dp);
286
287 if (HAS_PCH_SPLIT(dev))
288 return PCH_PP_CONTROL;
289 else
290 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
291}
292
293static u32 _pp_stat_reg(struct intel_dp *intel_dp)
294{
295 struct drm_device *dev = intel_dp_to_dev(intel_dp);
296
297 if (HAS_PCH_SPLIT(dev))
298 return PCH_PP_STATUS;
299 else
300 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
301}
302
4be73780 303static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 304{
30add22d 305 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 306 struct drm_i915_private *dev_priv = dev->dev_private;
307
bf13e81b 308 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 309}
310
4be73780 311static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 312{
30add22d 313 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 314 struct drm_i915_private *dev_priv = dev->dev_private;
315
bf13e81b 316 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 317}
318
9b984dae
KP		 319static void
320intel_dp_check_edp(struct intel_dp *intel_dp)
321{
30add22d 322 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 323 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 324
9b984dae
KP		 325 if (!is_edp(intel_dp))
326 return;
453c5420 327
4be73780 328 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 329 WARN(1, "eDP powered off while attempting aux channel communication.\n");
330 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 331 I915_READ(_pp_stat_reg(intel_dp)),
332 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 333 }
334}
335
9ee32fea
DV		 336static uint32_t
337intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
338{
339 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
340 struct drm_device *dev = intel_dig_port->base.base.dev;
341 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 342 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 343 uint32_t status;
344 bool done;
345
ef04f00d 346#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 347 if (has_aux_irq)
b18ac466 348 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 349 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 350 else
351 done = wait_for_atomic(C, 10) == 0;
352 if (!done)
353 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
354 has_aux_irq);
355#undef C
356
357 return status;
358}
359
ec5b01dd 360static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 361{
174edf1f
PZ		 362 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
363 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 364
ec5b01dd
DL		 365 /*
366 * The clock divider is based off the hrawclk, and would like to run at
367 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 368 */
ec5b01dd
DL		 369 return index ? 0 : intel_hrawclk(dev) / 2;
370}
371
372static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
373{
374 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
375 struct drm_device *dev = intel_dig_port->base.base.dev;
376
377 if (index)
378 return 0;
379
380 if (intel_dig_port->port == PORT_A) {
381 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 382 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 383 else
b84a1cf8 384 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 385 } else {
386 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
387 }
388}
389
390static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
391{
392 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
393 struct drm_device *dev = intel_dig_port->base.base.dev;
394 struct drm_i915_private *dev_priv = dev->dev_private;
395
396 if (intel_dig_port->port == PORT_A) {
397 if (index)
398 return 0;
399 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 400 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
401 /* Workaround for non-ULT HSW */
bc86625a
CW		 402 switch (index) {
403 case 0: return 63;
404 case 1: return 72;
405 default: return 0;
406 }
ec5b01dd 407 } else {
bc86625a 408 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 409 }
b84a1cf8
RV		 410}
411
ec5b01dd
DL		 412static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
413{
414 return index ? 0 : 100;
415}
416
5ed12a19
DL		 417static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
418 bool has_aux_irq,
419 int send_bytes,
420 uint32_t aux_clock_divider)
421{
422 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
423 struct drm_device *dev = intel_dig_port->base.base.dev;
424 uint32_t precharge, timeout;
425
426 if (IS_GEN6(dev))
427 precharge = 3;
428 else
429 precharge = 5;
430
431 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
432 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
433 else
434 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
435
436 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 437 DP_AUX_CH_CTL_DONE |
5ed12a19 438 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 439 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 440 timeout |
788d4433 441 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 442 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
443 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 444 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 445}
446
b84a1cf8
RV		 447static int
448intel_dp_aux_ch(struct intel_dp *intel_dp,
449 uint8_t *send, int send_bytes,
450 uint8_t *recv, int recv_size)
451{
452 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
453 struct drm_device *dev = intel_dig_port->base.base.dev;
454 struct drm_i915_private *dev_priv = dev->dev_private;
455 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
456 uint32_t ch_data = ch_ctl + 4;
bc86625a 457 uint32_t aux_clock_divider;
b84a1cf8
RV		 458 int i, ret, recv_bytes;
459 uint32_t status;
5ed12a19 460 int try, clock = 0;
4e6b788c 461 bool has_aux_irq = HAS_AUX_IRQ(dev);
b84a1cf8
RV		 462
463 /* dp aux is extremely sensitive to irq latency, hence request the
464 * lowest possible wakeup latency and so prevent the cpu from going into
465 * deep sleep states.
466 */
467 pm_qos_update_request(&dev_priv->pm_qos, 0);
468
469 intel_dp_check_edp(intel_dp);
5eb08b69 470
c67a470b
PZ		 471 intel_aux_display_runtime_get(dev_priv);
472
11bee43e
JB		 473 /* Try to wait for any previous AUX channel activity */
474 for (try = 0; try < 3; try++) {
ef04f00d 475 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 476 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
477 break;
478 msleep(1);
479 }
480
481 if (try == 3) {
482 WARN(1, "dp_aux_ch not started status 0x%08x\n",
483 I915_READ(ch_ctl));
9ee32fea
DV		 484 ret = -EBUSY;
485 goto out;
4f7f7b7e
CW		 486 }
487
46a5ae9f
PZ		 488 /* Only 5 data registers! */
489 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
490 ret = -E2BIG;
491 goto out;
492 }
493
ec5b01dd 494 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 495 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
496 has_aux_irq,
497 send_bytes,
498 aux_clock_divider);
5ed12a19 499
bc86625a
CW		 500 /* Must try at least 3 times according to DP spec */
501 for (try = 0; try < 5; try++) {
502 /* Load the send data into the aux channel data registers */
503 for (i = 0; i < send_bytes; i += 4)
504 I915_WRITE(ch_data + i,
505 pack_aux(send + i, send_bytes - i));
506
507 /* Send the command and wait for it to complete */
5ed12a19 508 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 509
510 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
511
512 /* Clear done status and any errors */
513 I915_WRITE(ch_ctl,
514 status |
515 DP_AUX_CH_CTL_DONE |
516 DP_AUX_CH_CTL_TIME_OUT_ERROR |
517 DP_AUX_CH_CTL_RECEIVE_ERROR);
518
519 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
520 DP_AUX_CH_CTL_RECEIVE_ERROR))
521 continue;
522 if (status & DP_AUX_CH_CTL_DONE)
523 break;
524 }
4f7f7b7e 525 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 526 break;
527 }
528
a4fc5ed6 529 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 530 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 531 ret = -EBUSY;
532 goto out;
a4fc5ed6
KP		 533 }
534
535 /* Check for timeout or receive error.
536 * Timeouts occur when the sink is not connected
537 */
a5b3da54 538 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 539 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 540 ret = -EIO;
541 goto out;
a5b3da54 542 }
1ae8c0a5
KP		 543
544 /* Timeouts occur when the device isn't connected, so they're
545 * "normal" -- don't fill the kernel log with these */
a5b3da54 546 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 547 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 548 ret = -ETIMEDOUT;
549 goto out;
a4fc5ed6
KP		 550 }
551
552 /* Unload any bytes sent back from the other side */
553 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
554 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 555 if (recv_bytes > recv_size)
556 recv_bytes = recv_size;
0206e353 557
4f7f7b7e
CW		 558 for (i = 0; i < recv_bytes; i += 4)
559 unpack_aux(I915_READ(ch_data + i),
560 recv + i, recv_bytes - i);
a4fc5ed6 561
9ee32fea
DV		 562 ret = recv_bytes;
563out:
564 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 565 intel_aux_display_runtime_put(dev_priv);
9ee32fea
DV		 566
567 return ret;
a4fc5ed6
KP		 568}
569
570/* Write data to the aux channel in native mode */
571static int
ea5b213a 572intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 573 uint16_t address, uint8_t *send, int send_bytes)
574{
575 int ret;
576 uint8_t msg[20];
577 int msg_bytes;
578 uint8_t ack;
f51a44b9 579 int retry;
a4fc5ed6 580
46a5ae9f
PZ		 581 if (WARN_ON(send_bytes > 16))
582 return -E2BIG;
583
9b984dae 584 intel_dp_check_edp(intel_dp);
6b27f7f0 585 msg[0] = DP_AUX_NATIVE_WRITE << 4;
a4fc5ed6 586 msg[1] = address >> 8;
eebc863e 587 msg[2] = address & 0xff;
a4fc5ed6
KP		 588 msg[3] = send_bytes - 1;
589 memcpy(&msg[4], send, send_bytes);
590 msg_bytes = send_bytes + 4;
f51a44b9 591 for (retry = 0; retry < 7; retry++) {
ea5b213a 592 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 593 if (ret < 0)
594 return ret;
6b27f7f0
TR		 595 ack >>= 4;
596 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
f51a44b9 597 return send_bytes;
6b27f7f0 598 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
04eada25 599 usleep_range(400, 500);
a4fc5ed6 600 else
a5b3da54 601 return -EIO;
a4fc5ed6 602 }
f51a44b9
JN		 603
604 DRM_ERROR("too many retries, giving up\n");
605 return -EIO;
a4fc5ed6
KP		 606}
607
608/* Write a single byte to the aux channel in native mode */
609static int
ea5b213a 610intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 611 uint16_t address, uint8_t byte)
612{
ea5b213a 613 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 614}
615
616/* read bytes from a native aux channel */
617static int
ea5b213a 618intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 619 uint16_t address, uint8_t *recv, int recv_bytes)
620{
621 uint8_t msg[4];
622 int msg_bytes;
623 uint8_t reply[20];
624 int reply_bytes;
625 uint8_t ack;
626 int ret;
f51a44b9 627 int retry;
a4fc5ed6 628
46a5ae9f
PZ		 629 if (WARN_ON(recv_bytes > 19))
630 return -E2BIG;
631
9b984dae 632 intel_dp_check_edp(intel_dp);
6b27f7f0 633 msg[0] = DP_AUX_NATIVE_READ << 4;
a4fc5ed6
KP		 634 msg[1] = address >> 8;
635 msg[2] = address & 0xff;
636 msg[3] = recv_bytes - 1;
637
638 msg_bytes = 4;
639 reply_bytes = recv_bytes + 1;
640
f51a44b9 641 for (retry = 0; retry < 7; retry++) {
ea5b213a 642 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 643 reply, reply_bytes);
a5b3da54
KP		 644 if (ret == 0)
645 return -EPROTO;
646 if (ret < 0)
a4fc5ed6 647 return ret;
6b27f7f0
TR		 648 ack = reply[0] >> 4;
649 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) {
a4fc5ed6
KP		 650 memcpy(recv, reply + 1, ret - 1);
651 return ret - 1;
652 }
6b27f7f0 653 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
04eada25 654 usleep_range(400, 500);
a4fc5ed6 655 else
a5b3da54 656 return -EIO;
a4fc5ed6 657 }
f51a44b9
JN		 658
659 DRM_ERROR("too many retries, giving up\n");
660 return -EIO;
a4fc5ed6
KP		 661}
662
663static int
ab2c0672
DA		 664intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
665 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 666{
ab2c0672 667 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 668 struct intel_dp *intel_dp = container_of(adapter,
669 struct intel_dp,
670 adapter);
ab2c0672
DA		 671 uint16_t address = algo_data->address;
672 uint8_t msg[5];
673 uint8_t reply[2];
8316f337 674 unsigned retry;
ab2c0672
DA		 675 int msg_bytes;
676 int reply_bytes;
677 int ret;
678
4be73780 679 edp_panel_vdd_on(intel_dp);
9b984dae 680 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 681 /* Set up the command byte */
682 if (mode & MODE_I2C_READ)
6b27f7f0 683 msg[0] = DP_AUX_I2C_READ << 4;
ab2c0672 684 else
6b27f7f0 685 msg[0] = DP_AUX_I2C_WRITE << 4;
ab2c0672
DA		 686
687 if (!(mode & MODE_I2C_STOP))
6b27f7f0 688 msg[0] |= DP_AUX_I2C_MOT << 4;
a4fc5ed6 689
ab2c0672
DA		 690 msg[1] = address >> 8;
691 msg[2] = address;
692
693 switch (mode) {
694 case MODE_I2C_WRITE:
695 msg[3] = 0;
696 msg[4] = write_byte;
697 msg_bytes = 5;
698 reply_bytes = 1;
699 break;
700 case MODE_I2C_READ:
701 msg[3] = 0;
702 msg_bytes = 4;
703 reply_bytes = 2;
704 break;
705 default:
706 msg_bytes = 3;
707 reply_bytes = 1;
708 break;
709 }
710
58c67ce9
JN		 711 /*
712 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
713 * required to retry at least seven times upon receiving AUX_DEFER
714 * before giving up the AUX transaction.
715 */
716 for (retry = 0; retry < 7; retry++) {
8316f337
DF		 717 ret = intel_dp_aux_ch(intel_dp,
718 msg, msg_bytes,
719 reply, reply_bytes);
ab2c0672 720 if (ret < 0) {
3ff99164 721 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
8a5e6aeb 722 goto out;
ab2c0672 723 }
8316f337 724
6b27f7f0
TR		 725 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
726 case DP_AUX_NATIVE_REPLY_ACK:
8316f337
DF		 727 /* I2C-over-AUX Reply field is only valid
728 * when paired with AUX ACK.
729 */
730 break;
6b27f7f0 731 case DP_AUX_NATIVE_REPLY_NACK:
8316f337 732 DRM_DEBUG_KMS("aux_ch native nack\n");
8a5e6aeb
PZ		 733 ret = -EREMOTEIO;
734 goto out;
6b27f7f0 735 case DP_AUX_NATIVE_REPLY_DEFER:
8d16f258
JN		 736 /*
737 * For now, just give more slack to branch devices. We
738 * could check the DPCD for I2C bit rate capabilities,
739 * and if available, adjust the interval. We could also
740 * be more careful with DP-to-Legacy adapters where a
741 * long legacy cable may force very low I2C bit rates.
742 */
743 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
744 DP_DWN_STRM_PORT_PRESENT)
745 usleep_range(500, 600);
746 else
747 usleep_range(300, 400);
8316f337
DF		 748 continue;
749 default:
750 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
751 reply[0]);
8a5e6aeb
PZ		 752 ret = -EREMOTEIO;
753 goto out;
8316f337
DF		 754 }
755
6b27f7f0
TR		 756 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) {
757 case DP_AUX_I2C_REPLY_ACK:
ab2c0672
DA		 758 if (mode == MODE_I2C_READ) {
759 *read_byte = reply[1];
760 }
8a5e6aeb
PZ		 761 ret = reply_bytes - 1;
762 goto out;
6b27f7f0 763 case DP_AUX_I2C_REPLY_NACK:
8316f337 764 DRM_DEBUG_KMS("aux_i2c nack\n");
8a5e6aeb
PZ		 765 ret = -EREMOTEIO;
766 goto out;
6b27f7f0 767 case DP_AUX_I2C_REPLY_DEFER:
8316f337 768 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 769 udelay(100);
770 break;
771 default:
8316f337 772 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
8a5e6aeb
PZ		 773 ret = -EREMOTEIO;
774 goto out;
ab2c0672
DA		 775 }
776 }
8316f337
DF		 777
778 DRM_ERROR("too many retries, giving up\n");
8a5e6aeb
PZ		 779 ret = -EREMOTEIO;
780
781out:
4be73780 782 edp_panel_vdd_off(intel_dp, false);
8a5e6aeb 783 return ret;
a4fc5ed6
KP		 784}
785
80f65de3
ID		 786static void
787intel_dp_connector_unregister(struct intel_connector *intel_connector)
788{
789 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
790
791 sysfs_remove_link(&intel_connector->base.kdev->kobj,
792 intel_dp->adapter.dev.kobj.name);
793 intel_connector_unregister(intel_connector);
794}
795
a4fc5ed6 796static int
ea5b213a 797intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 798 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 799{
0b5c541b
KP		 800 int ret;
801
d54e9d28 802 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 803 intel_dp->algo.running = false;
804 intel_dp->algo.address = 0;
805 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
806
0206e353 807 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 808 intel_dp->adapter.owner = THIS_MODULE;
809 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 810 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 811 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
812 intel_dp->adapter.algo_data = &intel_dp->algo;
80f65de3 813 intel_dp->adapter.dev.parent = intel_connector->base.dev->dev;
ea5b213a 814
0b5c541b 815 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
80f65de3
ID		 816 if (ret < 0)
817 return ret;
818
819 ret = sysfs_create_link(&intel_connector->base.kdev->kobj,
820 &intel_dp->adapter.dev.kobj,
821 intel_dp->adapter.dev.kobj.name);
822
823 if (ret < 0)
824 i2c_del_adapter(&intel_dp->adapter);
825
0b5c541b 826 return ret;
a4fc5ed6
KP		 827}
828
c6bb3538
DV		 829static void
830intel_dp_set_clock(struct intel_encoder *encoder,
831 struct intel_crtc_config *pipe_config, int link_bw)
832{
833 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 834 const struct dp_link_dpll *divisor = NULL;
835 int i, count = 0;
c6bb3538
DV		 836
837 if (IS_G4X(dev)) {
9dd4ffdf
CML		 838 divisor = gen4_dpll;
839 count = ARRAY_SIZE(gen4_dpll);
c6bb3538
DV		 840 } else if (IS_HASWELL(dev)) {
841 /* Haswell has special-purpose DP DDI clocks. */
842 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 843 divisor = pch_dpll;
844 count = ARRAY_SIZE(pch_dpll);
c6bb3538 845 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 846 divisor = vlv_dpll;
847 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 848 }
9dd4ffdf
CML		 849
850 if (divisor && count) {
851 for (i = 0; i < count; i++) {
852 if (link_bw == divisor[i].link_bw) {
853 pipe_config->dpll = divisor[i].dpll;
854 pipe_config->clock_set = true;
855 break;
856 }
857 }
c6bb3538
DV		 858 }
859}
860
00c09d70 861bool
5bfe2ac0
DV		 862intel_dp_compute_config(struct intel_encoder *encoder,
863 struct intel_crtc_config *pipe_config)
a4fc5ed6 864{
5bfe2ac0 865 struct drm_device *dev = encoder->base.dev;
36008365 866 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 867 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 868 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 869 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 870 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 871 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 872 int lane_count, clock;
397fe157 873 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
06ea66b6
TP		 874 /* Conveniently, the link BW constants become indices with a shift...*/
875 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 876 int bpp, mode_rate;
06ea66b6 877 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 878 int link_avail, link_clock;
a4fc5ed6 879
bc7d38a4 880 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 881 pipe_config->has_pch_encoder = true;
882
03afc4a2 883 pipe_config->has_dp_encoder = true;
a4fc5ed6 884
dd06f90e
JN		 885 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
886 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
887 adjusted_mode);
2dd24552
JB		 888 if (!HAS_PCH_SPLIT(dev))
889 intel_gmch_panel_fitting(intel_crtc, pipe_config,
890 intel_connector->panel.fitting_mode);
891 else
b074cec8
JB		 892 intel_pch_panel_fitting(intel_crtc, pipe_config,
893 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 894 }
895
cb1793ce 896 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 897 return false;
898
083f9560
DV		 899 DRM_DEBUG_KMS("DP link computation with max lane count %i "
900 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 901 max_lane_count, bws[max_clock],
902 adjusted_mode->crtc_clock);
083f9560 903
36008365
DV		 904 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
905 * bpc in between. */
3e7ca985 906 bpp = pipe_config->pipe_bpp;
6da7f10d
JN		 907 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
908 dev_priv->vbt.edp_bpp < bpp) {
7984211e
ID		 909 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
910 dev_priv->vbt.edp_bpp);
6da7f10d 911 bpp = dev_priv->vbt.edp_bpp;
7984211e 912 }
657445fe 913
36008365 914 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 915 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
916 bpp);
36008365 917
38aecea0
DV		 918 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
919 for (clock = 0; clock <= max_clock; clock++) {
36008365
DV		 920 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
921 link_avail = intel_dp_max_data_rate(link_clock,
922 lane_count);
923
924 if (mode_rate <= link_avail) {
925 goto found;
926 }
927 }
928 }
929 }
c4867936 930
36008365 931 return false;
3685a8f3 932
36008365 933found:
55bc60db
VS		 934 if (intel_dp->color_range_auto) {
935 /*
936 * See:
937 * CEA-861-E - 5.1 Default Encoding Parameters
938 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
939 */
18316c8c 940 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 941 intel_dp->color_range = DP_COLOR_RANGE_16_235;
942 else
943 intel_dp->color_range = 0;
944 }
945
3685a8f3 946 if (intel_dp->color_range)
50f3b016 947 pipe_config->limited_color_range = true;
a4fc5ed6 948
36008365
DV		 949 intel_dp->link_bw = bws[clock];
950 intel_dp->lane_count = lane_count;
657445fe 951 pipe_config->pipe_bpp = bpp;
ff9a6750 952 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 953
36008365
DV		 954 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
955 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 956 pipe_config->port_clock, bpp);
36008365
DV		 957 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
958 mode_rate, link_avail);
a4fc5ed6 959
03afc4a2 960 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 961 adjusted_mode->crtc_clock,
962 pipe_config->port_clock,
03afc4a2 963 &pipe_config->dp_m_n);
9d1a455b 964
c6bb3538
DV		 965 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
966
03afc4a2 967 return true;
a4fc5ed6
KP		 968}
969
7c62a164 970static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 971{
7c62a164
DV		 972 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
973 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
974 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 975 struct drm_i915_private *dev_priv = dev->dev_private;
976 u32 dpa_ctl;
977
ff9a6750 978 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 979 dpa_ctl = I915_READ(DP_A);
980 dpa_ctl &= ~DP_PLL_FREQ_MASK;
981
ff9a6750 982 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 983 /* For a long time we've carried around a ILK-DevA w/a for the
984 * 160MHz clock. If we're really unlucky, it's still required.
985 */
986 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 987 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 988 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 989 } else {
990 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 991 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 992 }
1ce17038 993
ea9b6006
DV		 994 I915_WRITE(DP_A, dpa_ctl);
995
996 POSTING_READ(DP_A);
997 udelay(500);
998}
999
b934223d 1000static void intel_dp_mode_set(struct intel_encoder *encoder)
a4fc5ed6 1001{
b934223d 1002 struct drm_device *dev = encoder->base.dev;
417e822d 1003 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1004 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1005 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1006 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1007 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1008
417e822d 1009 /*
1a2eb460 1010 * There are four kinds of DP registers:
417e822d
KP		 1011 *
1012 * IBX PCH
1a2eb460
KP		 1013 * SNB CPU
1014 * IVB CPU
417e822d
KP		 1015 * CPT PCH
1016 *
1017 * IBX PCH and CPU are the same for almost everything,
1018 * except that the CPU DP PLL is configured in this
1019 * register
1020 *
1021 * CPT PCH is quite different, having many bits moved
1022 * to the TRANS_DP_CTL register instead. That
1023 * configuration happens (oddly) in ironlake_pch_enable
1024 */
9c9e7927 1025
417e822d
KP		 1026 /* Preserve the BIOS-computed detected bit. This is
1027 * supposed to be read-only.
1028 */
1029 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1030
417e822d 1031 /* Handle DP bits in common between all three register formats */
417e822d 1032 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1033 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1034
e0dac65e
WF		 1035 if (intel_dp->has_audio) {
1036 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1037 pipe_name(crtc->pipe));
ea5b213a 1038 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1039 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1040 }
247d89f6 1041
417e822d 1042 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1043
bc7d38a4 1044 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1045 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1046 intel_dp->DP |= DP_SYNC_HS_HIGH;
1047 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1048 intel_dp->DP |= DP_SYNC_VS_HIGH;
1049 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1050
6aba5b6c 1051 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1052 intel_dp->DP |= DP_ENHANCED_FRAMING;
1053
7c62a164 1054 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1055 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1056 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1057 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1058
1059 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1060 intel_dp->DP |= DP_SYNC_HS_HIGH;
1061 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1062 intel_dp->DP |= DP_SYNC_VS_HIGH;
1063 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1064
6aba5b6c 1065 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1066 intel_dp->DP |= DP_ENHANCED_FRAMING;
1067
7c62a164 1068 if (crtc->pipe == 1)
417e822d 1069 intel_dp->DP |= DP_PIPEB_SELECT;
417e822d
KP		 1070 } else {
1071 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1072 }
ea9b6006 1073
bc7d38a4 1074 if (port == PORT_A && !IS_VALLEYVIEW(dev))
7c62a164 1075 ironlake_set_pll_cpu_edp(intel_dp);
a4fc5ed6
KP		 1076}
1077
ffd6749d
PZ		 1078#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1079#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1080
1a5ef5b7
PZ		 1081#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1082#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1083
ffd6749d
PZ		 1084#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1085#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1086
4be73780 1087static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1088 u32 mask,
1089 u32 value)
bd943159 1090{
30add22d 1091 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1092 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1093 u32 pp_stat_reg, pp_ctrl_reg;
1094
bf13e81b
JN		 1095 pp_stat_reg = _pp_stat_reg(intel_dp);
1096 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1097
99ea7127 1098 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1099 mask, value,
1100 I915_READ(pp_stat_reg),
1101 I915_READ(pp_ctrl_reg));
32ce697c 1102
453c5420 1103 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1104 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1105 I915_READ(pp_stat_reg),
1106 I915_READ(pp_ctrl_reg));
32ce697c 1107 }
54c136d4
CW		 1108
1109 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1110}
32ce697c 1111
4be73780 1112static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1113{
1114 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1115 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1116}
1117
4be73780 1118static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1119{
1120 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1121 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1122}
1123
4be73780 1124static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1125{
1126 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1127
1128 /* When we disable the VDD override bit last we have to do the manual
1129 * wait. */
1130 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1131 intel_dp->panel_power_cycle_delay);
1132
4be73780 1133 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1134}
1135
4be73780 1136static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1137{
1138 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1139 intel_dp->backlight_on_delay);
1140}
1141
4be73780 1142static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1143{
1144 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1145 intel_dp->backlight_off_delay);
1146}
99ea7127 1147
832dd3c1
KP		 1148/* Read the current pp_control value, unlocking the register if it
1149 * is locked
1150 */
1151
453c5420 1152static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1153{
453c5420
JB		 1154 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1155 struct drm_i915_private *dev_priv = dev->dev_private;
1156 u32 control;
832dd3c1 1157
bf13e81b 1158 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1159 control &= ~PANEL_UNLOCK_MASK;
1160 control |= PANEL_UNLOCK_REGS;
1161 return control;
bd943159
KP		 1162}
1163
849e39f5 1164void edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1165{
30add22d 1166 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1167 struct drm_i915_private *dev_priv = dev->dev_private;
1168 u32 pp;
453c5420 1169 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1170
97af61f5
KP		 1171 if (!is_edp(intel_dp))
1172 return;
5d613501 1173
bd943159
KP		 1174 WARN(intel_dp->want_panel_vdd,
1175 "eDP VDD already requested on\n");
1176
1177 intel_dp->want_panel_vdd = true;
99ea7127 1178
4be73780 1179 if (edp_have_panel_vdd(intel_dp))
bd943159 1180 return;
b0665d57 1181
e9cb81a2
PZ		 1182 intel_runtime_pm_get(dev_priv);
1183
b0665d57 1184 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1185
4be73780
DV		 1186 if (!edp_have_panel_power(intel_dp))
1187 wait_panel_power_cycle(intel_dp);
99ea7127 1188
453c5420 1189 pp = ironlake_get_pp_control(intel_dp);
5d613501 1190 pp |= EDP_FORCE_VDD;
ebf33b18 1191
bf13e81b
JN		 1192 pp_stat_reg = _pp_stat_reg(intel_dp);
1193 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1194
1195 I915_WRITE(pp_ctrl_reg, pp);
1196 POSTING_READ(pp_ctrl_reg);
1197 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1198 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1199 /*
1200 * If the panel wasn't on, delay before accessing aux channel
1201 */
4be73780 1202 if (!edp_have_panel_power(intel_dp)) {
bd943159 1203 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1204 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1205 }
5d613501
JB		 1206}
1207
4be73780 1208static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1209{
30add22d 1210 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1211 struct drm_i915_private *dev_priv = dev->dev_private;
1212 u32 pp;
453c5420 1213 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1214
a0e99e68
DV		 1215 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1216
4be73780 1217 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
b0665d57
PZ		 1218 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1219
453c5420 1220 pp = ironlake_get_pp_control(intel_dp);
bd943159 1221 pp &= ~EDP_FORCE_VDD;
bd943159 1222
9f08ef59
PZ		 1223 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1224 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1225
1226 I915_WRITE(pp_ctrl_reg, pp);
1227 POSTING_READ(pp_ctrl_reg);
99ea7127 1228
453c5420
JB		 1229 /* Make sure sequencer is idle before allowing subsequent activity */
1230 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1231 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c
PZ		 1232
1233 if ((pp & POWER_TARGET_ON) == 0)
dce56b3c 1234 intel_dp->last_power_cycle = jiffies;
e9cb81a2
PZ		 1235
1236 intel_runtime_pm_put(dev_priv);
bd943159
KP		 1237 }
1238}
5d613501 1239
4be73780 1240static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1241{
1242 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1243 struct intel_dp, panel_vdd_work);
30add22d 1244 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1245
627f7675 1246 mutex_lock(&dev->mode_config.mutex);
4be73780 1247 edp_panel_vdd_off_sync(intel_dp);
627f7675 1248 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1249}
1250
4be73780 1251static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1252{
97af61f5
KP		 1253 if (!is_edp(intel_dp))
1254 return;
5d613501 1255
bd943159 1256 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1257
bd943159
KP		 1258 intel_dp->want_panel_vdd = false;
1259
1260 if (sync) {
4be73780 1261 edp_panel_vdd_off_sync(intel_dp);
bd943159
KP		 1262 } else {
1263 /*
1264 * Queue the timer to fire a long
1265 * time from now (relative to the power down delay)
1266 * to keep the panel power up across a sequence of operations
1267 */
1268 schedule_delayed_work(&intel_dp->panel_vdd_work,
1269 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1270 }
5d613501
JB		 1271}
1272
4be73780 1273void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1274{
30add22d 1275 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1276 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1277 u32 pp;
453c5420 1278 u32 pp_ctrl_reg;
9934c132 1279
97af61f5 1280 if (!is_edp(intel_dp))
bd943159 1281 return;
99ea7127
KP		 1282
1283 DRM_DEBUG_KMS("Turn eDP power on\n");
1284
4be73780 1285 if (edp_have_panel_power(intel_dp)) {
99ea7127 1286 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1287 return;
99ea7127 1288 }
9934c132 1289
4be73780 1290 wait_panel_power_cycle(intel_dp);
37c6c9b0 1291
bf13e81b 1292 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1293 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1294 if (IS_GEN5(dev)) {
1295 /* ILK workaround: disable reset around power sequence */
1296 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1297 I915_WRITE(pp_ctrl_reg, pp);
1298 POSTING_READ(pp_ctrl_reg);
05ce1a49 1299 }
37c6c9b0 1300
1c0ae80a 1301 pp |= POWER_TARGET_ON;
99ea7127
KP		 1302 if (!IS_GEN5(dev))
1303 pp |= PANEL_POWER_RESET;
1304
453c5420
JB		 1305 I915_WRITE(pp_ctrl_reg, pp);
1306 POSTING_READ(pp_ctrl_reg);
9934c132 1307
4be73780 1308 wait_panel_on(intel_dp);
dce56b3c 1309 intel_dp->last_power_on = jiffies;
9934c132 1310
05ce1a49
KP		 1311 if (IS_GEN5(dev)) {
1312 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1313 I915_WRITE(pp_ctrl_reg, pp);
1314 POSTING_READ(pp_ctrl_reg);
05ce1a49 1315 }
9934c132
JB		 1316}
1317
4be73780 1318void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1319{
30add22d 1320 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1321 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1322 u32 pp;
453c5420 1323 u32 pp_ctrl_reg;
9934c132 1324
97af61f5
KP		 1325 if (!is_edp(intel_dp))
1326 return;
37c6c9b0 1327
99ea7127 1328 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1329
4be73780 1330 edp_wait_backlight_off(intel_dp);
dce56b3c 1331
453c5420 1332 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1333 /* We need to switch off panel power _and_ force vdd, for otherwise some
1334 * panels get very unhappy and cease to work. */
b3064154
PJ		 1335 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1336 EDP_BLC_ENABLE);
453c5420 1337
bf13e81b 1338 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1339
849e39f5
PZ		 1340 intel_dp->want_panel_vdd = false;
1341
453c5420
JB		 1342 I915_WRITE(pp_ctrl_reg, pp);
1343 POSTING_READ(pp_ctrl_reg);
9934c132 1344
dce56b3c 1345 intel_dp->last_power_cycle = jiffies;
4be73780 1346 wait_panel_off(intel_dp);
849e39f5
PZ		 1347
1348 /* We got a reference when we enabled the VDD. */
1349 intel_runtime_pm_put(dev_priv);
9934c132
JB		 1350}
1351
4be73780 1352void intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1353{
da63a9f2
PZ		 1354 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1355 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1356 struct drm_i915_private *dev_priv = dev->dev_private;
1357 u32 pp;
453c5420 1358 u32 pp_ctrl_reg;
32f9d658 1359
f01eca2e
KP		 1360 if (!is_edp(intel_dp))
1361 return;
1362
28c97730 1363 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1364 /*
1365 * If we enable the backlight right away following a panel power
1366 * on, we may see slight flicker as the panel syncs with the eDP
1367 * link. So delay a bit to make sure the image is solid before
1368 * allowing it to appear.
1369 */
4be73780 1370 wait_backlight_on(intel_dp);
453c5420 1371 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1372 pp |= EDP_BLC_ENABLE;
453c5420 1373
bf13e81b 1374 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1375
1376 I915_WRITE(pp_ctrl_reg, pp);
1377 POSTING_READ(pp_ctrl_reg);
035aa3de 1378
752aa88a 1379 intel_panel_enable_backlight(intel_dp->attached_connector);
32f9d658
ZW		 1380}
1381
4be73780 1382void intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1383{
30add22d 1384 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1385 struct drm_i915_private *dev_priv = dev->dev_private;
1386 u32 pp;
453c5420 1387 u32 pp_ctrl_reg;
32f9d658 1388
f01eca2e
KP		 1389 if (!is_edp(intel_dp))
1390 return;
1391
752aa88a 1392 intel_panel_disable_backlight(intel_dp->attached_connector);
035aa3de 1393
28c97730 1394 DRM_DEBUG_KMS("\n");
453c5420 1395 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1396 pp &= ~EDP_BLC_ENABLE;
453c5420 1397
bf13e81b 1398 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1399
1400 I915_WRITE(pp_ctrl_reg, pp);
1401 POSTING_READ(pp_ctrl_reg);
dce56b3c 1402 intel_dp->last_backlight_off = jiffies;
32f9d658 1403}
a4fc5ed6 1404
2bd2ad64 1405static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1406{
da63a9f2
PZ		 1407 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1408 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1409 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1410 struct drm_i915_private *dev_priv = dev->dev_private;
1411 u32 dpa_ctl;
1412
2bd2ad64
DV		 1413 assert_pipe_disabled(dev_priv,
1414 to_intel_crtc(crtc)->pipe);
1415
d240f20f
JB		 1416 DRM_DEBUG_KMS("\n");
1417 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1418 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1419 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1420
1421 /* We don't adjust intel_dp->DP while tearing down the link, to
1422 * facilitate link retraining (e.g. after hotplug). Hence clear all
1423 * enable bits here to ensure that we don't enable too much. */
1424 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1425 intel_dp->DP |= DP_PLL_ENABLE;
1426 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1427 POSTING_READ(DP_A);
1428 udelay(200);
d240f20f
JB		 1429}
1430
2bd2ad64 1431static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1432{
da63a9f2
PZ		 1433 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1434 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1435 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1436 struct drm_i915_private *dev_priv = dev->dev_private;
1437 u32 dpa_ctl;
1438
2bd2ad64
DV		 1439 assert_pipe_disabled(dev_priv,
1440 to_intel_crtc(crtc)->pipe);
1441
d240f20f 1442 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1443 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1444 "dp pll off, should be on\n");
1445 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1446
1447 /* We can't rely on the value tracked for the DP register in
1448 * intel_dp->DP because link_down must not change that (otherwise link
1449 * re-training will fail. */
298b0b39 1450 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1451 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1452 POSTING_READ(DP_A);
d240f20f
JB		 1453 udelay(200);
1454}
1455
c7ad3810 1456/* If the sink supports it, try to set the power state appropriately */
c19b0669 1457void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1458{
1459 int ret, i;
1460
1461 /* Should have a valid DPCD by this point */
1462 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1463 return;
1464
1465 if (mode != DRM_MODE_DPMS_ON) {
1466 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1467 DP_SET_POWER_D3);
1468 if (ret != 1)
1469 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1470 } else {
1471 /*
1472 * When turning on, we need to retry for 1ms to give the sink
1473 * time to wake up.
1474 */
1475 for (i = 0; i < 3; i++) {
1476 ret = intel_dp_aux_native_write_1(intel_dp,
1477 DP_SET_POWER,
1478 DP_SET_POWER_D0);
1479 if (ret == 1)
1480 break;
1481 msleep(1);
1482 }
1483 }
1484}
1485
19d8fe15
DV		 1486static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1487 enum pipe *pipe)
d240f20f 1488{
19d8fe15 1489 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1490 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1491 struct drm_device *dev = encoder->base.dev;
1492 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1493 enum intel_display_power_domain power_domain;
1494 u32 tmp;
1495
1496 power_domain = intel_display_port_power_domain(encoder);
1497 if (!intel_display_power_enabled(dev_priv, power_domain))
1498 return false;
1499
1500 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1501
1502 if (!(tmp & DP_PORT_EN))
1503 return false;
1504
bc7d38a4 1505 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1506 *pipe = PORT_TO_PIPE_CPT(tmp);
bc7d38a4 1507 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1508 *pipe = PORT_TO_PIPE(tmp);
1509 } else {
1510 u32 trans_sel;
1511 u32 trans_dp;
1512 int i;
1513
1514 switch (intel_dp->output_reg) {
1515 case PCH_DP_B:
1516 trans_sel = TRANS_DP_PORT_SEL_B;
1517 break;
1518 case PCH_DP_C:
1519 trans_sel = TRANS_DP_PORT_SEL_C;
1520 break;
1521 case PCH_DP_D:
1522 trans_sel = TRANS_DP_PORT_SEL_D;
1523 break;
1524 default:
1525 return true;
1526 }
1527
1528 for_each_pipe(i) {
1529 trans_dp = I915_READ(TRANS_DP_CTL(i));
1530 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1531 *pipe = i;
1532 return true;
1533 }
1534 }
19d8fe15 1535
4a0833ec
DV		 1536 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1537 intel_dp->output_reg);
1538 }
d240f20f 1539
19d8fe15
DV		 1540 return true;
1541}
d240f20f 1542
045ac3b5
JB		 1543static void intel_dp_get_config(struct intel_encoder *encoder,
1544 struct intel_crtc_config *pipe_config)
1545{
1546 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1547 u32 tmp, flags = 0;
63000ef6
XZ		 1548 struct drm_device *dev = encoder->base.dev;
1549 struct drm_i915_private *dev_priv = dev->dev_private;
1550 enum port port = dp_to_dig_port(intel_dp)->port;
1551 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1552 int dotclock;
045ac3b5 1553
63000ef6
XZ		 1554 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1555 tmp = I915_READ(intel_dp->output_reg);
1556 if (tmp & DP_SYNC_HS_HIGH)
1557 flags |= DRM_MODE_FLAG_PHSYNC;
1558 else
1559 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1560
63000ef6
XZ		 1561 if (tmp & DP_SYNC_VS_HIGH)
1562 flags |= DRM_MODE_FLAG_PVSYNC;
1563 else
1564 flags |= DRM_MODE_FLAG_NVSYNC;
1565 } else {
1566 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1567 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1568 flags |= DRM_MODE_FLAG_PHSYNC;
1569 else
1570 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1571
63000ef6
XZ		 1572 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1573 flags |= DRM_MODE_FLAG_PVSYNC;
1574 else
1575 flags |= DRM_MODE_FLAG_NVSYNC;
1576 }
045ac3b5
JB		 1577
1578 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1579
eb14cb74
VS		 1580 pipe_config->has_dp_encoder = true;
1581
1582 intel_dp_get_m_n(crtc, pipe_config);
1583
18442d08 1584 if (port == PORT_A) {
f1f644dc
JB		 1585 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1586 pipe_config->port_clock = 162000;
1587 else
1588 pipe_config->port_clock = 270000;
1589 }
18442d08
VS		 1590
1591 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1592 &pipe_config->dp_m_n);
1593
1594 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1595 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1596
241bfc38 1597 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1598
c6cd2ee2
JN		 1599 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1600 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1601 /*
1602 * This is a big fat ugly hack.
1603 *
1604 * Some machines in UEFI boot mode provide us a VBT that has 18
1605 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1606 * unknown we fail to light up. Yet the same BIOS boots up with
1607 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1608 * max, not what it tells us to use.
1609 *
1610 * Note: This will still be broken if the eDP panel is not lit
1611 * up by the BIOS, and thus we can't get the mode at module
1612 * load.
1613 */
1614 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1615 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1616 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1617 }
045ac3b5
JB		 1618}
1619
a031d709 1620static bool is_edp_psr(struct drm_device *dev)
2293bb5c 1621{
a031d709
RV		 1622 struct drm_i915_private *dev_priv = dev->dev_private;
1623
1624 return dev_priv->psr.sink_support;
2293bb5c
SK		 1625}
1626
2b28bb1b
RV		 1627static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1628{
1629 struct drm_i915_private *dev_priv = dev->dev_private;
1630
18b5992c 1631 if (!HAS_PSR(dev))
2b28bb1b
RV		 1632 return false;
1633
18b5992c 1634 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1635}
1636
1637static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1638 struct edp_vsc_psr *vsc_psr)
1639{
1640 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1641 struct drm_device *dev = dig_port->base.base.dev;
1642 struct drm_i915_private *dev_priv = dev->dev_private;
1643 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1644 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1645 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1646 uint32_t *data = (uint32_t *) vsc_psr;
1647 unsigned int i;
1648
1649 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1650 the video DIP being updated before program video DIP data buffer
1651 registers for DIP being updated. */
1652 I915_WRITE(ctl_reg, 0);
1653 POSTING_READ(ctl_reg);
1654
1655 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1656 if (i < sizeof(struct edp_vsc_psr))
1657 I915_WRITE(data_reg + i, *data++);
1658 else
1659 I915_WRITE(data_reg + i, 0);
1660 }
1661
1662 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1663 POSTING_READ(ctl_reg);
1664}
1665
1666static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1667{
1668 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1669 struct drm_i915_private *dev_priv = dev->dev_private;
1670 struct edp_vsc_psr psr_vsc;
1671
1672 if (intel_dp->psr_setup_done)
1673 return;
1674
1675 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1676 memset(&psr_vsc, 0, sizeof(psr_vsc));
1677 psr_vsc.sdp_header.HB0 = 0;
1678 psr_vsc.sdp_header.HB1 = 0x7;
1679 psr_vsc.sdp_header.HB2 = 0x2;
1680 psr_vsc.sdp_header.HB3 = 0x8;
1681 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1682
1683 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1684 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1685 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1686
1687 intel_dp->psr_setup_done = true;
1688}
1689
1690static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1691{
1692 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1693 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1694 uint32_t aux_clock_divider;
2b28bb1b
RV		 1695 int precharge = 0x3;
1696 int msg_size = 5; /* Header(4) + Message(1) */
1697
ec5b01dd
DL		 1698 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1699
2b28bb1b
RV		 1700 /* Enable PSR in sink */
1701 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1702 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1703 DP_PSR_ENABLE &
1704 ~DP_PSR_MAIN_LINK_ACTIVE);
1705 else
1706 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1707 DP_PSR_ENABLE |
1708 DP_PSR_MAIN_LINK_ACTIVE);
1709
1710 /* Setup AUX registers */
18b5992c
BW		 1711 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1712 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1713 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1714 DP_AUX_CH_CTL_TIME_OUT_400us |
1715 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1716 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1717 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1718}
1719
1720static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1721{
1722 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1723 struct drm_i915_private *dev_priv = dev->dev_private;
1724 uint32_t max_sleep_time = 0x1f;
1725 uint32_t idle_frames = 1;
1726 uint32_t val = 0x0;
ed8546ac 1727 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
2b28bb1b
RV		 1728
1729 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1730 val |= EDP_PSR_LINK_STANDBY;
1731 val |= EDP_PSR_TP2_TP3_TIME_0us;
1732 val |= EDP_PSR_TP1_TIME_0us;
1733 val |= EDP_PSR_SKIP_AUX_EXIT;
1734 } else
1735 val |= EDP_PSR_LINK_DISABLE;
1736
18b5992c 1737 I915_WRITE(EDP_PSR_CTL(dev), val |
ed8546ac 1738 IS_BROADWELL(dev) ? 0 : link_entry_time |
2b28bb1b
RV		 1739 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1740 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1741 EDP_PSR_ENABLE);
1742}
1743
3f51e471
RV		 1744static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1745{
1746 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1747 struct drm_device *dev = dig_port->base.base.dev;
1748 struct drm_i915_private *dev_priv = dev->dev_private;
1749 struct drm_crtc *crtc = dig_port->base.base.crtc;
1750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1751 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1752 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1753
a031d709
RV		 1754 dev_priv->psr.source_ok = false;
1755
18b5992c 1756 if (!HAS_PSR(dev)) {
3f51e471 1757 DRM_DEBUG_KMS("PSR not supported on this platform\n");
3f51e471
RV		 1758 return false;
1759 }
1760
1761 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1762 (dig_port->port != PORT_A)) {
1763 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1764 return false;
1765 }
1766
d330a953 1767 if (!i915.enable_psr) {
105b7c11 1768 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1769 return false;
1770 }
1771
cd234b0b
CW		 1772 crtc = dig_port->base.base.crtc;
1773 if (crtc == NULL) {
1774 DRM_DEBUG_KMS("crtc not active for PSR\n");
cd234b0b
CW		 1775 return false;
1776 }
1777
1778 intel_crtc = to_intel_crtc(crtc);
20ddf665 1779 if (!intel_crtc_active(crtc)) {
3f51e471 1780 DRM_DEBUG_KMS("crtc not active for PSR\n");
3f51e471
RV		 1781 return false;
1782 }
1783
cd234b0b 1784 obj = to_intel_framebuffer(crtc->fb)->obj;
3f51e471
RV		 1785 if (obj->tiling_mode != I915_TILING_X ||
1786 obj->fence_reg == I915_FENCE_REG_NONE) {
1787 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
3f51e471
RV		 1788 return false;
1789 }
1790
1791 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1792 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
3f51e471
RV		 1793 return false;
1794 }
1795
1796 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1797 S3D_ENABLE) {
1798 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1799 return false;
1800 }
1801
ca73b4f0 1802 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1803 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1804 return false;
1805 }
1806
a031d709 1807 dev_priv->psr.source_ok = true;
3f51e471
RV		 1808 return true;
1809}
1810
3d739d92 1811static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1812{
1813 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1814
3f51e471
RV		 1815 if (!intel_edp_psr_match_conditions(intel_dp) ||
1816 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1817 return;
1818
1819 /* Setup PSR once */
1820 intel_edp_psr_setup(intel_dp);
1821
1822 /* Enable PSR on the panel */
1823 intel_edp_psr_enable_sink(intel_dp);
1824
1825 /* Enable PSR on the host */
1826 intel_edp_psr_enable_source(intel_dp);
1827}
1828
3d739d92
RV		 1829void intel_edp_psr_enable(struct intel_dp *intel_dp)
1830{
1831 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1832
1833 if (intel_edp_psr_match_conditions(intel_dp) &&
1834 !intel_edp_is_psr_enabled(dev))
1835 intel_edp_psr_do_enable(intel_dp);
1836}
1837
2b28bb1b
RV		 1838void intel_edp_psr_disable(struct intel_dp *intel_dp)
1839{
1840 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1841 struct drm_i915_private *dev_priv = dev->dev_private;
1842
1843 if (!intel_edp_is_psr_enabled(dev))
1844 return;
1845
18b5992c
BW		 1846 I915_WRITE(EDP_PSR_CTL(dev),
1847 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2b28bb1b
RV		 1848
1849 /* Wait till PSR is idle */
18b5992c 1850 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2b28bb1b
RV		 1851 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1852 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1853}
1854
3d739d92
RV		 1855void intel_edp_psr_update(struct drm_device *dev)
1856{
1857 struct intel_encoder *encoder;
1858 struct intel_dp *intel_dp = NULL;
1859
1860 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1861 if (encoder->type == INTEL_OUTPUT_EDP) {
1862 intel_dp = enc_to_intel_dp(&encoder->base);
1863
a031d709 1864 if (!is_edp_psr(dev))
3d739d92
RV		 1865 return;
1866
1867 if (!intel_edp_psr_match_conditions(intel_dp))
1868 intel_edp_psr_disable(intel_dp);
1869 else
1870 if (!intel_edp_is_psr_enabled(dev))
1871 intel_edp_psr_do_enable(intel_dp);
1872 }
1873}
1874
e8cb4558 1875static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1876{
e8cb4558 1877 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1878 enum port port = dp_to_dig_port(intel_dp)->port;
1879 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1880
1881 /* Make sure the panel is off before trying to change the mode. But also
1882 * ensure that we have vdd while we switch off the panel. */
b3064154 1883 edp_panel_vdd_on(intel_dp);
4be73780 1884 intel_edp_backlight_off(intel_dp);
fdbc3b1f 1885 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 1886 intel_edp_panel_off(intel_dp);
3739850b
DV		 1887
1888 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1889 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1890 intel_dp_link_down(intel_dp);
d240f20f
JB		 1891}
1892
2bd2ad64 1893static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1894{
2bd2ad64 1895 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1896 enum port port = dp_to_dig_port(intel_dp)->port;
b2634017 1897 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1898
982a3866 1899 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
3739850b 1900 intel_dp_link_down(intel_dp);
b2634017
JB		 1901 if (!IS_VALLEYVIEW(dev))
1902 ironlake_edp_pll_off(intel_dp);
3739850b 1903 }
2bd2ad64
DV		 1904}
1905
e8cb4558 1906static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1907{
e8cb4558
DV		 1908 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1909 struct drm_device *dev = encoder->base.dev;
1910 struct drm_i915_private *dev_priv = dev->dev_private;
1911 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1912
0c33d8d7
DV		 1913 if (WARN_ON(dp_reg & DP_PORT_EN))
1914 return;
5d613501 1915
4be73780 1916 edp_panel_vdd_on(intel_dp);
f01eca2e 1917 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1918 intel_dp_start_link_train(intel_dp);
4be73780
DV		 1919 intel_edp_panel_on(intel_dp);
1920 edp_panel_vdd_off(intel_dp, true);
33a34e4e 1921 intel_dp_complete_link_train(intel_dp);
3ab9c637 1922 intel_dp_stop_link_train(intel_dp);
ab1f90f9 1923}
89b667f8 1924
ecff4f3b
JN		 1925static void g4x_enable_dp(struct intel_encoder *encoder)
1926{
828f5c6e
JN		 1927 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1928
ecff4f3b 1929 intel_enable_dp(encoder);
4be73780 1930 intel_edp_backlight_on(intel_dp);
ab1f90f9 1931}
89b667f8 1932
ab1f90f9
JN		 1933static void vlv_enable_dp(struct intel_encoder *encoder)
1934{
828f5c6e
JN		 1935 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1936
4be73780 1937 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 1938}
1939
ecff4f3b 1940static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 1941{
1942 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1943 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1944
1945 if (dport->port == PORT_A)
1946 ironlake_edp_pll_on(intel_dp);
1947}
1948
1949static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1950{
2bd2ad64 1951 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1952 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1953 struct drm_device *dev = encoder->base.dev;
89b667f8 1954 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 1955 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 1956 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 1957 int pipe = intel_crtc->pipe;
bf13e81b 1958 struct edp_power_seq power_seq;
ab1f90f9 1959 u32 val;
a4fc5ed6 1960
ab1f90f9 1961 mutex_lock(&dev_priv->dpio_lock);
89b667f8 1962
ab3c759a 1963 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 1964 val = 0;
1965 if (pipe)
1966 val |= (1<<21);
1967 else
1968 val &= ~(1<<21);
1969 val |= 0x001000c4;
ab3c759a
CML		 1970 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1971 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1972 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 1973
ab1f90f9
JN		 1974 mutex_unlock(&dev_priv->dpio_lock);
1975
2cac613b
ID		 1976 if (is_edp(intel_dp)) {
1977 /* init power sequencer on this pipe and port */
1978 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1979 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1980 &power_seq);
1981 }
bf13e81b 1982
ab1f90f9
JN		 1983 intel_enable_dp(encoder);
1984
e4607fcf 1985 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 1986}
1987
ecff4f3b 1988static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 1989{
1990 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1991 struct drm_device *dev = encoder->base.dev;
1992 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 1993 struct intel_crtc *intel_crtc =
1994 to_intel_crtc(encoder->base.crtc);
e4607fcf 1995 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 1996 int pipe = intel_crtc->pipe;
89b667f8 1997
89b667f8 1998 /* Program Tx lane resets to default */
0980a60f 1999 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2000 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2001 DPIO_PCS_TX_LANE2_RESET |
2002 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2003 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2004 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2005 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2006 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2007 DPIO_PCS_CLK_SOFT_RESET);
2008
2009 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2010 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2011 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2012 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2013 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2014}
2015
2016/*
df0c237d
JB		 2017 * Native read with retry for link status and receiver capability reads for
2018 * cases where the sink may still be asleep.
a4fc5ed6
KP		 2019 */
2020static bool
df0c237d
JB		 2021intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
2022 uint8_t *recv, int recv_bytes)
a4fc5ed6 2023{
61da5fab
JB		 2024 int ret, i;
2025
df0c237d
JB		 2026 /*
2027 * Sinks are *supposed* to come up within 1ms from an off state,
2028 * but we're also supposed to retry 3 times per the spec.
2029 */
61da5fab 2030 for (i = 0; i < 3; i++) {
df0c237d
JB		 2031 ret = intel_dp_aux_native_read(intel_dp, address, recv,
2032 recv_bytes);
2033 if (ret == recv_bytes)
61da5fab
JB		 2034 return true;
2035 msleep(1);
2036 }
a4fc5ed6 2037
61da5fab 2038 return false;
a4fc5ed6
KP		 2039}
2040
2041/*
2042 * Fetch AUX CH registers 0x202 - 0x207 which contain
2043 * link status information
2044 */
2045static bool
93f62dad 2046intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2047{
df0c237d
JB		 2048 return intel_dp_aux_native_read_retry(intel_dp,
2049 DP_LANE0_1_STATUS,
93f62dad 2050 link_status,
df0c237d 2051 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 2052}
2053
a4fc5ed6
KP		 2054/*
2055 * These are source-specific values; current Intel hardware supports
2056 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
2057 */
a4fc5ed6
KP		 2058
2059static uint8_t
1a2eb460 2060intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2061{
30add22d 2062 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2063 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2064
8f93f4f1 2065 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
e2fa6fba 2066 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 2067 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 2068 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 2069 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 2070 return DP_TRAIN_VOLTAGE_SWING_1200;
2071 else
2072 return DP_TRAIN_VOLTAGE_SWING_800;
2073}
2074
2075static uint8_t
2076intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2077{
30add22d 2078 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2079 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2080
8f93f4f1
PZ		 2081 if (IS_BROADWELL(dev)) {
2082 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2083 case DP_TRAIN_VOLTAGE_SWING_400:
2084 case DP_TRAIN_VOLTAGE_SWING_600:
2085 return DP_TRAIN_PRE_EMPHASIS_6;
2086 case DP_TRAIN_VOLTAGE_SWING_800:
2087 return DP_TRAIN_PRE_EMPHASIS_3_5;
2088 case DP_TRAIN_VOLTAGE_SWING_1200:
2089 default:
2090 return DP_TRAIN_PRE_EMPHASIS_0;
2091 }
2092 } else if (IS_HASWELL(dev)) {
d6c0d722
PZ		 2093 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2094 case DP_TRAIN_VOLTAGE_SWING_400:
2095 return DP_TRAIN_PRE_EMPHASIS_9_5;
2096 case DP_TRAIN_VOLTAGE_SWING_600:
2097 return DP_TRAIN_PRE_EMPHASIS_6;
2098 case DP_TRAIN_VOLTAGE_SWING_800:
2099 return DP_TRAIN_PRE_EMPHASIS_3_5;
2100 case DP_TRAIN_VOLTAGE_SWING_1200:
2101 default:
2102 return DP_TRAIN_PRE_EMPHASIS_0;
2103 }
e2fa6fba
P		 2104 } else if (IS_VALLEYVIEW(dev)) {
2105 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2106 case DP_TRAIN_VOLTAGE_SWING_400:
2107 return DP_TRAIN_PRE_EMPHASIS_9_5;
2108 case DP_TRAIN_VOLTAGE_SWING_600:
2109 return DP_TRAIN_PRE_EMPHASIS_6;
2110 case DP_TRAIN_VOLTAGE_SWING_800:
2111 return DP_TRAIN_PRE_EMPHASIS_3_5;
2112 case DP_TRAIN_VOLTAGE_SWING_1200:
2113 default:
2114 return DP_TRAIN_PRE_EMPHASIS_0;
2115 }
bc7d38a4 2116 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2117 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2118 case DP_TRAIN_VOLTAGE_SWING_400:
2119 return DP_TRAIN_PRE_EMPHASIS_6;
2120 case DP_TRAIN_VOLTAGE_SWING_600:
2121 case DP_TRAIN_VOLTAGE_SWING_800:
2122 return DP_TRAIN_PRE_EMPHASIS_3_5;
2123 default:
2124 return DP_TRAIN_PRE_EMPHASIS_0;
2125 }
2126 } else {
2127 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2128 case DP_TRAIN_VOLTAGE_SWING_400:
2129 return DP_TRAIN_PRE_EMPHASIS_6;
2130 case DP_TRAIN_VOLTAGE_SWING_600:
2131 return DP_TRAIN_PRE_EMPHASIS_6;
2132 case DP_TRAIN_VOLTAGE_SWING_800:
2133 return DP_TRAIN_PRE_EMPHASIS_3_5;
2134 case DP_TRAIN_VOLTAGE_SWING_1200:
2135 default:
2136 return DP_TRAIN_PRE_EMPHASIS_0;
2137 }
a4fc5ed6
KP		 2138 }
2139}
2140
e2fa6fba
P		 2141static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2142{
2143 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2144 struct drm_i915_private *dev_priv = dev->dev_private;
2145 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2146 struct intel_crtc *intel_crtc =
2147 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2148 unsigned long demph_reg_value, preemph_reg_value,
2149 uniqtranscale_reg_value;
2150 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2151 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2152 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2153
2154 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2155 case DP_TRAIN_PRE_EMPHASIS_0:
2156 preemph_reg_value = 0x0004000;
2157 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2158 case DP_TRAIN_VOLTAGE_SWING_400:
2159 demph_reg_value = 0x2B405555;
2160 uniqtranscale_reg_value = 0x552AB83A;
2161 break;
2162 case DP_TRAIN_VOLTAGE_SWING_600:
2163 demph_reg_value = 0x2B404040;
2164 uniqtranscale_reg_value = 0x5548B83A;
2165 break;
2166 case DP_TRAIN_VOLTAGE_SWING_800:
2167 demph_reg_value = 0x2B245555;
2168 uniqtranscale_reg_value = 0x5560B83A;
2169 break;
2170 case DP_TRAIN_VOLTAGE_SWING_1200:
2171 demph_reg_value = 0x2B405555;
2172 uniqtranscale_reg_value = 0x5598DA3A;
2173 break;
2174 default:
2175 return 0;
2176 }
2177 break;
2178 case DP_TRAIN_PRE_EMPHASIS_3_5:
2179 preemph_reg_value = 0x0002000;
2180 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2181 case DP_TRAIN_VOLTAGE_SWING_400:
2182 demph_reg_value = 0x2B404040;
2183 uniqtranscale_reg_value = 0x5552B83A;
2184 break;
2185 case DP_TRAIN_VOLTAGE_SWING_600:
2186 demph_reg_value = 0x2B404848;
2187 uniqtranscale_reg_value = 0x5580B83A;
2188 break;
2189 case DP_TRAIN_VOLTAGE_SWING_800:
2190 demph_reg_value = 0x2B404040;
2191 uniqtranscale_reg_value = 0x55ADDA3A;
2192 break;
2193 default:
2194 return 0;
2195 }
2196 break;
2197 case DP_TRAIN_PRE_EMPHASIS_6:
2198 preemph_reg_value = 0x0000000;
2199 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2200 case DP_TRAIN_VOLTAGE_SWING_400:
2201 demph_reg_value = 0x2B305555;
2202 uniqtranscale_reg_value = 0x5570B83A;
2203 break;
2204 case DP_TRAIN_VOLTAGE_SWING_600:
2205 demph_reg_value = 0x2B2B4040;
2206 uniqtranscale_reg_value = 0x55ADDA3A;
2207 break;
2208 default:
2209 return 0;
2210 }
2211 break;
2212 case DP_TRAIN_PRE_EMPHASIS_9_5:
2213 preemph_reg_value = 0x0006000;
2214 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2215 case DP_TRAIN_VOLTAGE_SWING_400:
2216 demph_reg_value = 0x1B405555;
2217 uniqtranscale_reg_value = 0x55ADDA3A;
2218 break;
2219 default:
2220 return 0;
2221 }
2222 break;
2223 default:
2224 return 0;
2225 }
2226
0980a60f 2227 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2228 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2229 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2230 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2231 uniqtranscale_reg_value);
ab3c759a
CML		 2232 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2233 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2234 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2235 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2236 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2237
2238 return 0;
2239}
2240
a4fc5ed6 2241static void
0301b3ac
JN		 2242intel_get_adjust_train(struct intel_dp *intel_dp,
2243 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2244{
2245 uint8_t v = 0;
2246 uint8_t p = 0;
2247 int lane;
1a2eb460
KP		 2248 uint8_t voltage_max;
2249 uint8_t preemph_max;
a4fc5ed6 2250
33a34e4e 2251 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2252 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2253 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2254
2255 if (this_v > v)
2256 v = this_v;
2257 if (this_p > p)
2258 p = this_p;
2259 }
2260
1a2eb460 2261 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2262 if (v >= voltage_max)
2263 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2264
1a2eb460
KP		 2265 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2266 if (p >= preemph_max)
2267 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2268
2269 for (lane = 0; lane < 4; lane++)
33a34e4e 2270 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2271}
2272
2273static uint32_t
f0a3424e 2274intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2275{
3cf2efb1 2276 uint32_t signal_levels = 0;
a4fc5ed6 2277
3cf2efb1 2278 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2279 case DP_TRAIN_VOLTAGE_SWING_400:
2280 default:
2281 signal_levels |= DP_VOLTAGE_0_4;
2282 break;
2283 case DP_TRAIN_VOLTAGE_SWING_600:
2284 signal_levels |= DP_VOLTAGE_0_6;
2285 break;
2286 case DP_TRAIN_VOLTAGE_SWING_800:
2287 signal_levels |= DP_VOLTAGE_0_8;
2288 break;
2289 case DP_TRAIN_VOLTAGE_SWING_1200:
2290 signal_levels |= DP_VOLTAGE_1_2;
2291 break;
2292 }
3cf2efb1 2293 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2294 case DP_TRAIN_PRE_EMPHASIS_0:
2295 default:
2296 signal_levels |= DP_PRE_EMPHASIS_0;
2297 break;
2298 case DP_TRAIN_PRE_EMPHASIS_3_5:
2299 signal_levels |= DP_PRE_EMPHASIS_3_5;
2300 break;
2301 case DP_TRAIN_PRE_EMPHASIS_6:
2302 signal_levels |= DP_PRE_EMPHASIS_6;
2303 break;
2304 case DP_TRAIN_PRE_EMPHASIS_9_5:
2305 signal_levels |= DP_PRE_EMPHASIS_9_5;
2306 break;
2307 }
2308 return signal_levels;
2309}
2310
e3421a18
ZW		 2311/* Gen6's DP voltage swing and pre-emphasis control */
2312static uint32_t
2313intel_gen6_edp_signal_levels(uint8_t train_set)
2314{
3c5a62b5
YL		 2315 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2316 DP_TRAIN_PRE_EMPHASIS_MASK);
2317 switch (signal_levels) {
e3421a18 2318 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2319 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2320 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2321 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2322 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2323 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2324 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2325 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2326 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2327 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2328 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2329 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2330 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2331 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2332 default:
3c5a62b5
YL		 2333 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2334 "0x%x\n", signal_levels);
2335 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2336 }
2337}
2338
1a2eb460
KP		 2339/* Gen7's DP voltage swing and pre-emphasis control */
2340static uint32_t
2341intel_gen7_edp_signal_levels(uint8_t train_set)
2342{
2343 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2344 DP_TRAIN_PRE_EMPHASIS_MASK);
2345 switch (signal_levels) {
2346 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2347 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2348 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2349 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2350 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2351 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2352
2353 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2354 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2355 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2356 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2357
2358 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2359 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2360 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2361 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2362
2363 default:
2364 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2365 "0x%x\n", signal_levels);
2366 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2367 }
2368}
2369
d6c0d722
PZ		 2370/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2371static uint32_t
f0a3424e 2372intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2373{
d6c0d722
PZ		 2374 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2375 DP_TRAIN_PRE_EMPHASIS_MASK);
2376 switch (signal_levels) {
2377 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2378 return DDI_BUF_EMP_400MV_0DB_HSW;
2379 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2380 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2381 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2382 return DDI_BUF_EMP_400MV_6DB_HSW;
2383 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2384 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2385
d6c0d722
PZ		 2386 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2387 return DDI_BUF_EMP_600MV_0DB_HSW;
2388 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2389 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2390 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2391 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2392
d6c0d722
PZ		 2393 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2394 return DDI_BUF_EMP_800MV_0DB_HSW;
2395 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2396 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2397 default:
2398 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2399 "0x%x\n", signal_levels);
2400 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2401 }
a4fc5ed6
KP		 2402}
2403
8f93f4f1
PZ		 2404static uint32_t
2405intel_bdw_signal_levels(uint8_t train_set)
2406{
2407 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2408 DP_TRAIN_PRE_EMPHASIS_MASK);
2409 switch (signal_levels) {
2410 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2411 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2412 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2413 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2414 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2415 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2416
2417 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2418 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2419 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2420 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2421 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2422 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2423
2424 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2425 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2426 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2427 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2428
2429 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2430 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2431
2432 default:
2433 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2434 "0x%x\n", signal_levels);
2435 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2436 }
2437}
2438
f0a3424e
PZ		 2439/* Properly updates "DP" with the correct signal levels. */
2440static void
2441intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2442{
2443 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2444 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2445 struct drm_device *dev = intel_dig_port->base.base.dev;
2446 uint32_t signal_levels, mask;
2447 uint8_t train_set = intel_dp->train_set[0];
2448
8f93f4f1
PZ		 2449 if (IS_BROADWELL(dev)) {
2450 signal_levels = intel_bdw_signal_levels(train_set);
2451 mask = DDI_BUF_EMP_MASK;
2452 } else if (IS_HASWELL(dev)) {
f0a3424e
PZ		 2453 signal_levels = intel_hsw_signal_levels(train_set);
2454 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 2455 } else if (IS_VALLEYVIEW(dev)) {
2456 signal_levels = intel_vlv_signal_levels(intel_dp);
2457 mask = 0;
bc7d38a4 2458 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2459 signal_levels = intel_gen7_edp_signal_levels(train_set);
2460 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2461 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2462 signal_levels = intel_gen6_edp_signal_levels(train_set);
2463 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2464 } else {
2465 signal_levels = intel_gen4_signal_levels(train_set);
2466 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2467 }
2468
2469 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2470
2471 *DP = (*DP & ~mask) | signal_levels;
2472}
2473
a4fc5ed6 2474static bool
ea5b213a 2475intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2476 uint32_t *DP,
58e10eb9 2477 uint8_t dp_train_pat)
a4fc5ed6 2478{
174edf1f
PZ		 2479 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2480 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2481 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2482 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2483 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2484 int ret, len;
a4fc5ed6 2485
22b8bf17 2486 if (HAS_DDI(dev)) {
3ab9c637 2487 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2488
2489 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2490 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2491 else
2492 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2493
2494 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2495 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2496 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2497 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2498
2499 break;
2500 case DP_TRAINING_PATTERN_1:
2501 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2502 break;
2503 case DP_TRAINING_PATTERN_2:
2504 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2505 break;
2506 case DP_TRAINING_PATTERN_3:
2507 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2508 break;
2509 }
174edf1f 2510 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2511
bc7d38a4 2512 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2513 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2514
2515 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2516 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2517 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2518 break;
2519 case DP_TRAINING_PATTERN_1:
70aff66c 2520 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2521 break;
2522 case DP_TRAINING_PATTERN_2:
70aff66c 2523 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2524 break;
2525 case DP_TRAINING_PATTERN_3:
2526 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2527 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2528 break;
2529 }
2530
2531 } else {
70aff66c 2532 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2533
2534 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2535 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2536 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2537 break;
2538 case DP_TRAINING_PATTERN_1:
70aff66c 2539 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2540 break;
2541 case DP_TRAINING_PATTERN_2:
70aff66c 2542 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2543 break;
2544 case DP_TRAINING_PATTERN_3:
2545 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2546 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2547 break;
2548 }
2549 }
2550
70aff66c 2551 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 2552 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2553
2cdfe6c8
JN		 2554 buf[0] = dp_train_pat;
2555 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 2556 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 2557 /* don't write DP_TRAINING_LANEx_SET on disable */
2558 len = 1;
2559 } else {
2560 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2561 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2562 len = intel_dp->lane_count + 1;
47ea7542 2563 }
a4fc5ed6 2564
2cdfe6c8
JN		 2565 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET,
2566 buf, len);
2567
2568 return ret == len;
a4fc5ed6
KP		 2569}
2570
70aff66c
JN		 2571static bool
2572intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2573 uint8_t dp_train_pat)
2574{
953d22e8 2575 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 2576 intel_dp_set_signal_levels(intel_dp, DP);
2577 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2578}
2579
2580static bool
2581intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 2582 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 2583{
2584 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2585 struct drm_device *dev = intel_dig_port->base.base.dev;
2586 struct drm_i915_private *dev_priv = dev->dev_private;
2587 int ret;
2588
2589 intel_get_adjust_train(intel_dp, link_status);
2590 intel_dp_set_signal_levels(intel_dp, DP);
2591
2592 I915_WRITE(intel_dp->output_reg, *DP);
2593 POSTING_READ(intel_dp->output_reg);
2594
2595 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET,
2596 intel_dp->train_set,
2597 intel_dp->lane_count);
2598
2599 return ret == intel_dp->lane_count;
2600}
2601
3ab9c637
ID		 2602static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2603{
2604 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2605 struct drm_device *dev = intel_dig_port->base.base.dev;
2606 struct drm_i915_private *dev_priv = dev->dev_private;
2607 enum port port = intel_dig_port->port;
2608 uint32_t val;
2609
2610 if (!HAS_DDI(dev))
2611 return;
2612
2613 val = I915_READ(DP_TP_CTL(port));
2614 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2615 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2616 I915_WRITE(DP_TP_CTL(port), val);
2617
2618 /*
2619 * On PORT_A we can have only eDP in SST mode. There the only reason
2620 * we need to set idle transmission mode is to work around a HW issue
2621 * where we enable the pipe while not in idle link-training mode.
2622 * In this case there is requirement to wait for a minimum number of
2623 * idle patterns to be sent.
2624 */
2625 if (port == PORT_A)
2626 return;
2627
2628 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2629 1))
2630 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2631}
2632
33a34e4e 2633/* Enable corresponding port and start training pattern 1 */
c19b0669 2634void
33a34e4e 2635intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2636{
da63a9f2 2637 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2638 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2639 int i;
2640 uint8_t voltage;
cdb0e95b 2641 int voltage_tries, loop_tries;
ea5b213a 2642 uint32_t DP = intel_dp->DP;
6aba5b6c 2643 uint8_t link_config[2];
a4fc5ed6 2644
affa9354 2645 if (HAS_DDI(dev))
c19b0669
PZ		 2646 intel_ddi_prepare_link_retrain(encoder);
2647
3cf2efb1 2648 /* Write the link configuration data */
6aba5b6c
JN		 2649 link_config[0] = intel_dp->link_bw;
2650 link_config[1] = intel_dp->lane_count;
2651 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2652 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2653 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2);
2654
2655 link_config[0] = 0;
2656 link_config[1] = DP_SET_ANSI_8B10B;
2657 intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 2658
2659 DP |= DP_PORT_EN;
1a2eb460 2660
70aff66c
JN		 2661 /* clock recovery */
2662 if (!intel_dp_reset_link_train(intel_dp, &DP,
2663 DP_TRAINING_PATTERN_1 |
2664 DP_LINK_SCRAMBLING_DISABLE)) {
2665 DRM_ERROR("failed to enable link training\n");
2666 return;
2667 }
2668
a4fc5ed6 2669 voltage = 0xff;
cdb0e95b
KP		 2670 voltage_tries = 0;
2671 loop_tries = 0;
a4fc5ed6 2672 for (;;) {
70aff66c 2673 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 2674
a7c9655f 2675 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2676 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2677 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2678 break;
93f62dad 2679 }
a4fc5ed6 2680
01916270 2681 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2682 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2683 break;
2684 }
2685
2686 /* Check to see if we've tried the max voltage */
2687 for (i = 0; i < intel_dp->lane_count; i++)
2688 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2689 break;
3b4f819d 2690 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2691 ++loop_tries;
2692 if (loop_tries == 5) {
3def84b3 2693 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 2694 break;
2695 }
70aff66c
JN		 2696 intel_dp_reset_link_train(intel_dp, &DP,
2697 DP_TRAINING_PATTERN_1 |
2698 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 2699 voltage_tries = 0;
2700 continue;
2701 }
a4fc5ed6 2702
3cf2efb1 2703 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2704 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2705 ++voltage_tries;
b06fbda3 2706 if (voltage_tries == 5) {
3def84b3 2707 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 2708 break;
2709 }
2710 } else
2711 voltage_tries = 0;
2712 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2713
70aff66c
JN		 2714 /* Update training set as requested by target */
2715 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2716 DRM_ERROR("failed to update link training\n");
2717 break;
2718 }
a4fc5ed6
KP		 2719 }
2720
33a34e4e
JB		 2721 intel_dp->DP = DP;
2722}
2723
c19b0669 2724void
33a34e4e
JB		 2725intel_dp_complete_link_train(struct intel_dp *intel_dp)
2726{
33a34e4e 2727 bool channel_eq = false;
37f80975 2728 int tries, cr_tries;
33a34e4e 2729 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 2730 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2731
2732 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2733 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2734 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 2735
a4fc5ed6 2736 /* channel equalization */
70aff66c 2737 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2738 training_pattern |
70aff66c
JN		 2739 DP_LINK_SCRAMBLING_DISABLE)) {
2740 DRM_ERROR("failed to start channel equalization\n");
2741 return;
2742 }
2743
a4fc5ed6 2744 tries = 0;
37f80975 2745 cr_tries = 0;
a4fc5ed6
KP		 2746 channel_eq = false;
2747 for (;;) {
70aff66c 2748 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2749
37f80975
JB		 2750 if (cr_tries > 5) {
2751 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 2752 break;
2753 }
2754
a7c9655f 2755 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 2756 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2757 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2758 break;
70aff66c 2759 }
a4fc5ed6 2760
37f80975 2761 /* Make sure clock is still ok */
01916270 2762 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 2763 intel_dp_start_link_train(intel_dp);
70aff66c 2764 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2765 training_pattern |
70aff66c 2766 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2767 cr_tries++;
2768 continue;
2769 }
2770
1ffdff13 2771 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2772 channel_eq = true;
2773 break;
2774 }
a4fc5ed6 2775
37f80975
JB		 2776 /* Try 5 times, then try clock recovery if that fails */
2777 if (tries > 5) {
2778 intel_dp_link_down(intel_dp);
2779 intel_dp_start_link_train(intel_dp);
70aff66c 2780 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2781 training_pattern |
70aff66c 2782 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2783 tries = 0;
2784 cr_tries++;
2785 continue;
2786 }
a4fc5ed6 2787
70aff66c
JN		 2788 /* Update training set as requested by target */
2789 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2790 DRM_ERROR("failed to update link training\n");
2791 break;
2792 }
3cf2efb1 2793 ++tries;
869184a6 2794 }
3cf2efb1 2795
3ab9c637
ID		 2796 intel_dp_set_idle_link_train(intel_dp);
2797
2798 intel_dp->DP = DP;
2799
d6c0d722 2800 if (channel_eq)
07f42258 2801 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2802
3ab9c637
ID		 2803}
2804
2805void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2806{
70aff66c 2807 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 2808 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2809}
2810
2811static void
ea5b213a 2812intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2813{
da63a9f2 2814 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2815 enum port port = intel_dig_port->port;
da63a9f2 2816 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2817 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2818 struct intel_crtc *intel_crtc =
2819 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2820 uint32_t DP = intel_dp->DP;
a4fc5ed6 2821
c19b0669
PZ		 2822 /*
2823 * DDI code has a strict mode set sequence and we should try to respect
2824 * it, otherwise we might hang the machine in many different ways. So we
2825 * really should be disabling the port only on a complete crtc_disable
2826 * sequence. This function is just called under two conditions on DDI
2827 * code:
2828 * - Link train failed while doing crtc_enable, and on this case we
2829 * really should respect the mode set sequence and wait for a
2830 * crtc_disable.
2831 * - Someone turned the monitor off and intel_dp_check_link_status
2832 * called us. We don't need to disable the whole port on this case, so
2833 * when someone turns the monitor on again,
2834 * intel_ddi_prepare_link_retrain will take care of redoing the link
2835 * train.
2836 */
affa9354 2837 if (HAS_DDI(dev))
c19b0669
PZ		 2838 return;
2839
0c33d8d7 2840 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2841 return;
2842
28c97730 2843 DRM_DEBUG_KMS("\n");
32f9d658 2844
bc7d38a4 2845 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 2846 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2847 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2848 } else {
2849 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2850 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2851 }
fe255d00 2852 POSTING_READ(intel_dp->output_reg);
5eb08b69 2853
ab527efc
DV		 2854 /* We don't really know why we're doing this */
2855 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2856
493a7081 2857 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2858 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2859 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2860
5bddd17f
EA		 2861 /* Hardware workaround: leaving our transcoder select
2862 * set to transcoder B while it's off will prevent the
2863 * corresponding HDMI output on transcoder A.
2864 *
2865 * Combine this with another hardware workaround:
2866 * transcoder select bit can only be cleared while the
2867 * port is enabled.
2868 */
2869 DP &= ~DP_PIPEB_SELECT;
2870 I915_WRITE(intel_dp->output_reg, DP);
2871
2872 /* Changes to enable or select take place the vblank
2873 * after being written.
2874 */
ff50afe9
DV		 2875 if (WARN_ON(crtc == NULL)) {
2876 /* We should never try to disable a port without a crtc
2877 * attached. For paranoia keep the code around for a
2878 * bit. */
31acbcc4
CW		 2879 POSTING_READ(intel_dp->output_reg);
2880 msleep(50);
2881 } else
ab527efc 2882 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2883 }
2884
832afda6 2885 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2886 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2887 POSTING_READ(intel_dp->output_reg);
f01eca2e 2888 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2889}
2890
26d61aad
KP		 2891static bool
2892intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2893{
a031d709
RV		 2894 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2895 struct drm_device *dev = dig_port->base.base.dev;
2896 struct drm_i915_private *dev_priv = dev->dev_private;
2897
577c7a50
DL		 2898 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2899
92fd8fd1 2900 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2901 sizeof(intel_dp->dpcd)) == 0)
2902 return false; /* aux transfer failed */
92fd8fd1 2903
577c7a50
DL		 2904 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2905 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2906 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2907
edb39244
AJ		 2908 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2909 return false; /* DPCD not present */
2910
2293bb5c
SK		 2911 /* Check if the panel supports PSR */
2912 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939
JN		 2913 if (is_edp(intel_dp)) {
2914 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2915 intel_dp->psr_dpcd,
2916 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 2917 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2918 dev_priv->psr.sink_support = true;
50003939 2919 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 2920 }
50003939
JN		 2921 }
2922
06ea66b6
TP		 2923 /* Training Pattern 3 support */
2924 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
2925 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
2926 intel_dp->use_tps3 = true;
2927 DRM_DEBUG_KMS("Displayport TPS3 supported");
2928 } else
2929 intel_dp->use_tps3 = false;
2930
edb39244
AJ		 2931 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2932 DP_DWN_STRM_PORT_PRESENT))
2933 return true; /* native DP sink */
2934
2935 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2936 return true; /* no per-port downstream info */
2937
2938 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2939 intel_dp->downstream_ports,
2940 DP_MAX_DOWNSTREAM_PORTS) == 0)
2941 return false; /* downstream port status fetch failed */
2942
2943 return true;
92fd8fd1
KP		 2944}
2945
0d198328
AJ		 2946static void
2947intel_dp_probe_oui(struct intel_dp *intel_dp)
2948{
2949 u8 buf[3];
2950
2951 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2952 return;
2953
4be73780 2954 edp_panel_vdd_on(intel_dp);
351cfc34 2955
0d198328
AJ		 2956 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2957 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2958 buf[0], buf[1], buf[2]);
2959
2960 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2961 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2962 buf[0], buf[1], buf[2]);
351cfc34 2963
4be73780 2964 edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2965}
2966
d2e216d0
RV		 2967int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
2968{
2969 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2970 struct drm_device *dev = intel_dig_port->base.base.dev;
2971 struct intel_crtc *intel_crtc =
2972 to_intel_crtc(intel_dig_port->base.base.crtc);
2973 u8 buf[1];
2974
2975 if (!intel_dp_aux_native_read(intel_dp, DP_TEST_SINK_MISC, buf, 1))
2976 return -EAGAIN;
2977
2978 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
2979 return -ENOTTY;
2980
2981 if (!intel_dp_aux_native_write_1(intel_dp, DP_TEST_SINK,
2982 DP_TEST_SINK_START))
2983 return -EAGAIN;
2984
2985 /* Wait 2 vblanks to be sure we will have the correct CRC value */
2986 intel_wait_for_vblank(dev, intel_crtc->pipe);
2987 intel_wait_for_vblank(dev, intel_crtc->pipe);
2988
2989 if (!intel_dp_aux_native_read(intel_dp, DP_TEST_CRC_R_CR, crc, 6))
2990 return -EAGAIN;
2991
2992 intel_dp_aux_native_write_1(intel_dp, DP_TEST_SINK, 0);
2993 return 0;
2994}
2995
a60f0e38
JB		 2996static bool
2997intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2998{
2999 int ret;
3000
3001 ret = intel_dp_aux_native_read_retry(intel_dp,
3002 DP_DEVICE_SERVICE_IRQ_VECTOR,
3003 sink_irq_vector, 1);
3004 if (!ret)
3005 return false;
3006
3007 return true;
3008}
3009
3010static void
3011intel_dp_handle_test_request(struct intel_dp *intel_dp)
3012{
3013 /* NAK by default */
9324cf7f 3014 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3015}
3016
a4fc5ed6
KP		 3017/*
3018 * According to DP spec
3019 * 5.1.2:
3020 * 1. Read DPCD
3021 * 2. Configure link according to Receiver Capabilities
3022 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3023 * 4. Check link status on receipt of hot-plug interrupt
3024 */
3025
00c09d70 3026void
ea5b213a 3027intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3028{
da63a9f2 3029 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3030 u8 sink_irq_vector;
93f62dad 3031 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3032
da63a9f2 3033 if (!intel_encoder->connectors_active)
d2b996ac 3034 return;
59cd09e1 3035
da63a9f2 3036 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3037 return;
3038
92fd8fd1 3039 /* Try to read receiver status if the link appears to be up */
93f62dad 3040 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3041 return;
3042 }
3043
92fd8fd1 3044 /* Now read the DPCD to see if it's actually running */
26d61aad 3045 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3046 return;
3047 }
3048
a60f0e38
JB		 3049 /* Try to read the source of the interrupt */
3050 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3051 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3052 /* Clear interrupt source */
3053 intel_dp_aux_native_write_1(intel_dp,
3054 DP_DEVICE_SERVICE_IRQ_VECTOR,
3055 sink_irq_vector);
3056
3057 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3058 intel_dp_handle_test_request(intel_dp);
3059 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3060 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3061 }
3062
1ffdff13 3063 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3064 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 3065 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 3066 intel_dp_start_link_train(intel_dp);
3067 intel_dp_complete_link_train(intel_dp);
3ab9c637 3068 intel_dp_stop_link_train(intel_dp);
33a34e4e 3069 }
a4fc5ed6 3070}
a4fc5ed6 3071
caf9ab24 3072/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3073static enum drm_connector_status
26d61aad 3074intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3075{
caf9ab24 3076 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3077 uint8_t type;
3078
3079 if (!intel_dp_get_dpcd(intel_dp))
3080 return connector_status_disconnected;
3081
3082 /* if there's no downstream port, we're done */
3083 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3084 return connector_status_connected;
caf9ab24
AJ		 3085
3086 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3087 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3088 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3089 uint8_t reg;
caf9ab24 3090 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 3091 &reg, 1))
caf9ab24 3092 return connector_status_unknown;
23235177
AJ		 3093 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3094 : connector_status_disconnected;
caf9ab24
AJ		 3095 }
3096
3097 /* If no HPD, poke DDC gently */
3098 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 3099 return connector_status_connected;
caf9ab24
AJ		 3100
3101 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3102 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3103 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3104 if (type == DP_DS_PORT_TYPE_VGA ||
3105 type == DP_DS_PORT_TYPE_NON_EDID)
3106 return connector_status_unknown;
3107 } else {
3108 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3109 DP_DWN_STRM_PORT_TYPE_MASK;
3110 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3111 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3112 return connector_status_unknown;
3113 }
caf9ab24
AJ		 3114
3115 /* Anything else is out of spec, warn and ignore */
3116 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3117 return connector_status_disconnected;
71ba9000
AJ		 3118}
3119
5eb08b69 3120static enum drm_connector_status
a9756bb5 3121ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3122{
30add22d 3123 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3124 struct drm_i915_private *dev_priv = dev->dev_private;
3125 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 3126 enum drm_connector_status status;
3127
fe16d949
CW		 3128 /* Can't disconnect eDP, but you can close the lid... */
3129 if (is_edp(intel_dp)) {
30add22d 3130 status = intel_panel_detect(dev);
fe16d949
CW		 3131 if (status == connector_status_unknown)
3132 status = connector_status_connected;
3133 return status;
3134 }
01cb9ea6 3135
1b469639
DL		 3136 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3137 return connector_status_disconnected;
3138
26d61aad 3139 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3140}
3141
a4fc5ed6 3142static enum drm_connector_status
a9756bb5 3143g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3144{
30add22d 3145 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3146 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3147 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3148 uint32_t bit;
5eb08b69 3149
35aad75f
JB		 3150 /* Can't disconnect eDP, but you can close the lid... */
3151 if (is_edp(intel_dp)) {
3152 enum drm_connector_status status;
3153
3154 status = intel_panel_detect(dev);
3155 if (status == connector_status_unknown)
3156 status = connector_status_connected;
3157 return status;
3158 }
3159
232a6ee9
TP		 3160 if (IS_VALLEYVIEW(dev)) {
3161 switch (intel_dig_port->port) {
3162 case PORT_B:
3163 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3164 break;
3165 case PORT_C:
3166 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3167 break;
3168 case PORT_D:
3169 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3170 break;
3171 default:
3172 return connector_status_unknown;
3173 }
3174 } else {
3175 switch (intel_dig_port->port) {
3176 case PORT_B:
3177 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3178 break;
3179 case PORT_C:
3180 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3181 break;
3182 case PORT_D:
3183 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3184 break;
3185 default:
3186 return connector_status_unknown;
3187 }
a4fc5ed6
KP		 3188 }
3189
10f76a38 3190 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3191 return connector_status_disconnected;
3192
26d61aad 3193 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3194}
3195
8c241fef
KP		 3196static struct edid *
3197intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3198{
9cd300e0 3199 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3200
9cd300e0
JN		 3201 /* use cached edid if we have one */
3202 if (intel_connector->edid) {
9cd300e0
JN		 3203 /* invalid edid */
3204 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3205 return NULL;
3206
55e9edeb 3207 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3208 }
8c241fef 3209
9cd300e0 3210 return drm_get_edid(connector, adapter);
8c241fef
KP		 3211}
3212
3213static int
3214intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3215{
9cd300e0 3216 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3217
9cd300e0
JN		 3218 /* use cached edid if we have one */
3219 if (intel_connector->edid) {
3220 /* invalid edid */
3221 if (IS_ERR(intel_connector->edid))
3222 return 0;
3223
3224 return intel_connector_update_modes(connector,
3225 intel_connector->edid);
d6f24d0f
JB		 3226 }
3227
9cd300e0 3228 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3229}
3230
a9756bb5
ZW		 3231static enum drm_connector_status
3232intel_dp_detect(struct drm_connector *connector, bool force)
3233{
3234 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3235 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3236 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3237 struct drm_device *dev = connector->dev;
c8c8fb33 3238 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 3239 enum drm_connector_status status;
671dedd2 3240 enum intel_display_power_domain power_domain;
a9756bb5
ZW		 3241 struct edid *edid = NULL;
3242
c8c8fb33
PZ		 3243 intel_runtime_pm_get(dev_priv);
3244
671dedd2
ID		 3245 power_domain = intel_display_port_power_domain(intel_encoder);
3246 intel_display_power_get(dev_priv, power_domain);
3247
164c8598
CW		 3248 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3249 connector->base.id, drm_get_connector_name(connector));
3250
a9756bb5
ZW		 3251 intel_dp->has_audio = false;
3252
3253 if (HAS_PCH_SPLIT(dev))
3254 status = ironlake_dp_detect(intel_dp);
3255 else
3256 status = g4x_dp_detect(intel_dp);
1b9be9d0 3257
a9756bb5 3258 if (status != connector_status_connected)
c8c8fb33 3259 goto out;
a9756bb5 3260
0d198328
AJ		 3261 intel_dp_probe_oui(intel_dp);
3262
c3e5f67b
DV		 3263 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3264 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3265 } else {
8c241fef 3266 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 3267 if (edid) {
3268 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3269 kfree(edid);
3270 }
a9756bb5
ZW		 3271 }
3272
d63885da
PZ		 3273 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3274 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3275 status = connector_status_connected;
3276
3277out:
671dedd2
ID		 3278 intel_display_power_put(dev_priv, power_domain);
3279
c8c8fb33 3280 intel_runtime_pm_put(dev_priv);
671dedd2 3281
c8c8fb33 3282 return status;
a4fc5ed6
KP		 3283}
3284
3285static int intel_dp_get_modes(struct drm_connector *connector)
3286{
df0e9248 3287 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3288 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3289 struct intel_encoder *intel_encoder = &intel_dig_port->base;
dd06f90e 3290 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3291 struct drm_device *dev = connector->dev;
671dedd2
ID		 3292 struct drm_i915_private *dev_priv = dev->dev_private;
3293 enum intel_display_power_domain power_domain;
32f9d658 3294 int ret;
a4fc5ed6
KP		 3295
3296 /* We should parse the EDID data and find out if it has an audio sink
3297 */
3298
671dedd2
ID		 3299 power_domain = intel_display_port_power_domain(intel_encoder);
3300 intel_display_power_get(dev_priv, power_domain);
3301
8c241fef 3302 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
671dedd2 3303 intel_display_power_put(dev_priv, power_domain);
f8779fda 3304 if (ret)
32f9d658
ZW		 3305 return ret;
3306
f8779fda 3307 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3308 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3309 struct drm_display_mode *mode;
dd06f90e
JN		 3310 mode = drm_mode_duplicate(dev,
3311 intel_connector->panel.fixed_mode);
f8779fda 3312 if (mode) {
32f9d658
ZW		 3313 drm_mode_probed_add(connector, mode);
3314 return 1;
3315 }
3316 }
3317 return 0;
a4fc5ed6
KP		 3318}
3319
1aad7ac0
CW		 3320static bool
3321intel_dp_detect_audio(struct drm_connector *connector)
3322{
3323 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3324 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3325 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3326 struct drm_device *dev = connector->dev;
3327 struct drm_i915_private *dev_priv = dev->dev_private;
3328 enum intel_display_power_domain power_domain;
1aad7ac0
CW		 3329 struct edid *edid;
3330 bool has_audio = false;
3331
671dedd2
ID		 3332 power_domain = intel_display_port_power_domain(intel_encoder);
3333 intel_display_power_get(dev_priv, power_domain);
3334
8c241fef 3335 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 3336 if (edid) {
3337 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3338 kfree(edid);
3339 }
3340
671dedd2
ID		 3341 intel_display_power_put(dev_priv, power_domain);
3342
1aad7ac0
CW		 3343 return has_audio;
3344}
3345
f684960e
CW		 3346static int
3347intel_dp_set_property(struct drm_connector *connector,
3348 struct drm_property *property,
3349 uint64_t val)
3350{
e953fd7b 3351 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3352 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3353 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3354 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3355 int ret;
3356
662595df 3357 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3358 if (ret)
3359 return ret;
3360
3f43c48d 3361 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3362 int i = val;
3363 bool has_audio;
3364
3365 if (i == intel_dp->force_audio)
f684960e
CW		 3366 return 0;
3367
1aad7ac0 3368 intel_dp->force_audio = i;
f684960e 3369
c3e5f67b 3370 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3371 has_audio = intel_dp_detect_audio(connector);
3372 else
c3e5f67b 3373 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3374
3375 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3376 return 0;
3377
1aad7ac0 3378 intel_dp->has_audio = has_audio;
f684960e
CW		 3379 goto done;
3380 }
3381
e953fd7b 3382 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3383 bool old_auto = intel_dp->color_range_auto;
3384 uint32_t old_range = intel_dp->color_range;
3385
55bc60db
VS		 3386 switch (val) {
3387 case INTEL_BROADCAST_RGB_AUTO:
3388 intel_dp->color_range_auto = true;
3389 break;
3390 case INTEL_BROADCAST_RGB_FULL:
3391 intel_dp->color_range_auto = false;
3392 intel_dp->color_range = 0;
3393 break;
3394 case INTEL_BROADCAST_RGB_LIMITED:
3395 intel_dp->color_range_auto = false;
3396 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3397 break;
3398 default:
3399 return -EINVAL;
3400 }
ae4edb80
DV		 3401
3402 if (old_auto == intel_dp->color_range_auto &&
3403 old_range == intel_dp->color_range)
3404 return 0;
3405
e953fd7b
CW		 3406 goto done;
3407 }
3408
53b41837
YN		 3409 if (is_edp(intel_dp) &&
3410 property == connector->dev->mode_config.scaling_mode_property) {
3411 if (val == DRM_MODE_SCALE_NONE) {
3412 DRM_DEBUG_KMS("no scaling not supported\n");
3413 return -EINVAL;
3414 }
3415
3416 if (intel_connector->panel.fitting_mode == val) {
3417 /* the eDP scaling property is not changed */
3418 return 0;
3419 }
3420 intel_connector->panel.fitting_mode = val;
3421
3422 goto done;
3423 }
3424
f684960e
CW		 3425 return -EINVAL;
3426
3427done:
c0c36b94
CW		 3428 if (intel_encoder->base.crtc)
3429 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3430
3431 return 0;
3432}
3433
a4fc5ed6 3434static void
73845adf 3435intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3436{
1d508706 3437 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3438
9cd300e0
JN		 3439 if (!IS_ERR_OR_NULL(intel_connector->edid))
3440 kfree(intel_connector->edid);
3441
acd8db10
PZ		 3442 /* Can't call is_edp() since the encoder may have been destroyed
3443 * already. */
3444 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3445 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3446
a4fc5ed6 3447 drm_connector_cleanup(connector);
55f78c43 3448 kfree(connector);
a4fc5ed6
KP		 3449}
3450
00c09d70 3451void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3452{
da63a9f2
PZ		 3453 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3454 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3455 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927
DV		 3456
3457 i2c_del_adapter(&intel_dp->adapter);
3458 drm_encoder_cleanup(encoder);
bd943159
KP		 3459 if (is_edp(intel_dp)) {
3460 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 3461 mutex_lock(&dev->mode_config.mutex);
4be73780 3462 edp_panel_vdd_off_sync(intel_dp);
bd173813 3463 mutex_unlock(&dev->mode_config.mutex);
bd943159 3464 }
da63a9f2 3465 kfree(intel_dig_port);
24d05927
DV		 3466}
3467
a4fc5ed6 3468static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3469 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3470 .detect = intel_dp_detect,
3471 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3472 .set_property = intel_dp_set_property,
73845adf 3473 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3474};
3475
3476static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3477 .get_modes = intel_dp_get_modes,
3478 .mode_valid = intel_dp_mode_valid,
df0e9248 3479 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3480};
3481
a4fc5ed6 3482static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3483 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3484};
3485
995b6762 3486static void
21d40d37 3487intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3488{
fa90ecef 3489 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3490
885a5014 3491 intel_dp_check_link_status(intel_dp);
c8110e52 3492}
6207937d 3493
e3421a18
ZW		 3494/* Return which DP Port should be selected for Transcoder DP control */
3495int
0206e353 3496intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3497{
3498 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3499 struct intel_encoder *intel_encoder;
3500 struct intel_dp *intel_dp;
e3421a18 3501
fa90ecef
PZ		 3502 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3503 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3504
fa90ecef
PZ		 3505 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3506 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3507 return intel_dp->output_reg;
e3421a18 3508 }
ea5b213a 3509
e3421a18
ZW		 3510 return -1;
3511}
3512
36e83a18 3513/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 3514bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 3515{
3516 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 3517 union child_device_config *p_child;
36e83a18 3518 int i;
5d8a7752
VS		 3519 static const short port_mapping[] = {
3520 [PORT_B] = PORT_IDPB,
3521 [PORT_C] = PORT_IDPC,
3522 [PORT_D] = PORT_IDPD,
3523 };
36e83a18 3524
3b32a35b
VS		 3525 if (port == PORT_A)
3526 return true;
3527
41aa3448 3528 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3529 return false;
3530
41aa3448
RV		 3531 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3532 p_child = dev_priv->vbt.child_dev + i;
36e83a18 3533
5d8a7752 3534 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 3535 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3536 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 3537 return true;
3538 }
3539 return false;
3540}
3541
f684960e
CW		 3542static void
3543intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3544{
53b41837
YN		 3545 struct intel_connector *intel_connector = to_intel_connector(connector);
3546
3f43c48d 3547 intel_attach_force_audio_property(connector);
e953fd7b 3548 intel_attach_broadcast_rgb_property(connector);
55bc60db 3549 intel_dp->color_range_auto = true;
53b41837
YN		 3550
3551 if (is_edp(intel_dp)) {
3552 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3553 drm_object_attach_property(
3554 &connector->base,
53b41837 3555 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3556 DRM_MODE_SCALE_ASPECT);
3557 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3558 }
f684960e
CW		 3559}
3560
dada1a9f
ID		 3561static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3562{
3563 intel_dp->last_power_cycle = jiffies;
3564 intel_dp->last_power_on = jiffies;
3565 intel_dp->last_backlight_off = jiffies;
3566}
3567
67a54566
DV		 3568static void
3569intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3570 struct intel_dp *intel_dp,
3571 struct edp_power_seq *out)
67a54566
DV		 3572{
3573 struct drm_i915_private *dev_priv = dev->dev_private;
3574 struct edp_power_seq cur, vbt, spec, final;
3575 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 3576 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 3577
3578 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 3579 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 3580 pp_on_reg = PCH_PP_ON_DELAYS;
3581 pp_off_reg = PCH_PP_OFF_DELAYS;
3582 pp_div_reg = PCH_PP_DIVISOR;
3583 } else {
bf13e81b
JN		 3584 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3585
3586 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3587 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3588 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3589 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 3590 }
67a54566
DV		 3591
3592 /* Workaround: Need to write PP_CONTROL with the unlock key as
3593 * the very first thing. */
453c5420 3594 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 3595 I915_WRITE(pp_ctrl_reg, pp);
67a54566 3596
453c5420
JB		 3597 pp_on = I915_READ(pp_on_reg);
3598 pp_off = I915_READ(pp_off_reg);
3599 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3600
3601 /* Pull timing values out of registers */
3602 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3603 PANEL_POWER_UP_DELAY_SHIFT;
3604
3605 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3606 PANEL_LIGHT_ON_DELAY_SHIFT;
3607
3608 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3609 PANEL_LIGHT_OFF_DELAY_SHIFT;
3610
3611 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3612 PANEL_POWER_DOWN_DELAY_SHIFT;
3613
3614 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3615 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3616
3617 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3618 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3619
41aa3448 3620 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3621
3622 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3623 * our hw here, which are all in 100usec. */
3624 spec.t1_t3 = 210 * 10;
3625 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3626 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3627 spec.t10 = 500 * 10;
3628 /* This one is special and actually in units of 100ms, but zero
3629 * based in the hw (so we need to add 100 ms). But the sw vbt
3630 * table multiplies it with 1000 to make it in units of 100usec,
3631 * too. */
3632 spec.t11_t12 = (510 + 100) * 10;
3633
3634 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3635 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3636
3637 /* Use the max of the register settings and vbt. If both are
3638 * unset, fall back to the spec limits. */
3639#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3640 spec.field : \
3641 max(cur.field, vbt.field))
3642 assign_final(t1_t3);
3643 assign_final(t8);
3644 assign_final(t9);
3645 assign_final(t10);
3646 assign_final(t11_t12);
3647#undef assign_final
3648
3649#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3650 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3651 intel_dp->backlight_on_delay = get_delay(t8);
3652 intel_dp->backlight_off_delay = get_delay(t9);
3653 intel_dp->panel_power_down_delay = get_delay(t10);
3654 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3655#undef get_delay
3656
f30d26e4
JN		 3657 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3658 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3659 intel_dp->panel_power_cycle_delay);
3660
3661 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3662 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3663
3664 if (out)
3665 *out = final;
3666}
3667
3668static void
3669intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3670 struct intel_dp *intel_dp,
3671 struct edp_power_seq *seq)
3672{
3673 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3674 u32 pp_on, pp_off, pp_div, port_sel = 0;
3675 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3676 int pp_on_reg, pp_off_reg, pp_div_reg;
3677
3678 if (HAS_PCH_SPLIT(dev)) {
3679 pp_on_reg = PCH_PP_ON_DELAYS;
3680 pp_off_reg = PCH_PP_OFF_DELAYS;
3681 pp_div_reg = PCH_PP_DIVISOR;
3682 } else {
bf13e81b
JN		 3683 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3684
3685 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3686 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3687 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 3688 }
3689
b2f19d1a
PZ		 3690 /*
3691 * And finally store the new values in the power sequencer. The
3692 * backlight delays are set to 1 because we do manual waits on them. For
3693 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3694 * we'll end up waiting for the backlight off delay twice: once when we
3695 * do the manual sleep, and once when we disable the panel and wait for
3696 * the PP_STATUS bit to become zero.
3697 */
f30d26e4 3698 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 3699 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3700 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 3701 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 3702 /* Compute the divisor for the pp clock, simply match the Bspec
3703 * formula. */
453c5420 3704 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 3705 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 3706 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3707
3708 /* Haswell doesn't have any port selection bits for the panel
3709 * power sequencer any more. */
bc7d38a4 3710 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 3711 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3712 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3713 else
3714 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 3715 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3716 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 3717 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 3718 else
a24c144c 3719 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 3720 }
3721
453c5420
JB		 3722 pp_on |= port_sel;
3723
3724 I915_WRITE(pp_on_reg, pp_on);
3725 I915_WRITE(pp_off_reg, pp_off);
3726 I915_WRITE(pp_div_reg, pp_div);
67a54566 3727
67a54566 3728 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 3729 I915_READ(pp_on_reg),
3730 I915_READ(pp_off_reg),
3731 I915_READ(pp_div_reg));
f684960e
CW		 3732}
3733
ed92f0b2 3734static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 3735 struct intel_connector *intel_connector,
3736 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 3737{
3738 struct drm_connector *connector = &intel_connector->base;
3739 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3740 struct drm_device *dev = intel_dig_port->base.base.dev;
3741 struct drm_i915_private *dev_priv = dev->dev_private;
3742 struct drm_display_mode *fixed_mode = NULL;
ed92f0b2
PZ		 3743 bool has_dpcd;
3744 struct drm_display_mode *scan;
3745 struct edid *edid;
3746
3747 if (!is_edp(intel_dp))
3748 return true;
3749
ed92f0b2 3750 /* Cache DPCD and EDID for edp. */
4be73780 3751 edp_panel_vdd_on(intel_dp);
ed92f0b2 3752 has_dpcd = intel_dp_get_dpcd(intel_dp);
4be73780 3753 edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 3754
3755 if (has_dpcd) {
3756 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3757 dev_priv->no_aux_handshake =
3758 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3759 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3760 } else {
3761 /* if this fails, presume the device is a ghost */
3762 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 3763 return false;
3764 }
3765
3766 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 3767 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 3768
ed92f0b2
PZ		 3769 edid = drm_get_edid(connector, &intel_dp->adapter);
3770 if (edid) {
3771 if (drm_add_edid_modes(connector, edid)) {
3772 drm_mode_connector_update_edid_property(connector,
3773 edid);
3774 drm_edid_to_eld(connector, edid);
3775 } else {
3776 kfree(edid);
3777 edid = ERR_PTR(-EINVAL);
3778 }
3779 } else {
3780 edid = ERR_PTR(-ENOENT);
3781 }
3782 intel_connector->edid = edid;
3783
3784 /* prefer fixed mode from EDID if available */
3785 list_for_each_entry(scan, &connector->probed_modes, head) {
3786 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3787 fixed_mode = drm_mode_duplicate(dev, scan);
3788 break;
3789 }
3790 }
3791
3792 /* fallback to VBT if available for eDP */
3793 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3794 fixed_mode = drm_mode_duplicate(dev,
3795 dev_priv->vbt.lfp_lvds_vbt_mode);
3796 if (fixed_mode)
3797 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3798 }
3799
4b6ed685 3800 intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
ed92f0b2
PZ		 3801 intel_panel_setup_backlight(connector);
3802
3803 return true;
3804}
3805
16c25533 3806bool
f0fec3f2
PZ		 3807intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3808 struct intel_connector *intel_connector)
a4fc5ed6 3809{
f0fec3f2
PZ		 3810 struct drm_connector *connector = &intel_connector->base;
3811 struct intel_dp *intel_dp = &intel_dig_port->dp;
3812 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3813 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 3814 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3815 enum port port = intel_dig_port->port;
0095e6dc 3816 struct edp_power_seq power_seq = { 0 };
5eb08b69 3817 const char *name = NULL;
b2a14755 3818 int type, error;
a4fc5ed6 3819
ec5b01dd
DL		 3820 /* intel_dp vfuncs */
3821 if (IS_VALLEYVIEW(dev))
3822 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
3823 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3824 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
3825 else if (HAS_PCH_SPLIT(dev))
3826 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
3827 else
3828 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
3829
153b1100
DL		 3830 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
3831
0767935e
DV		 3832 /* Preserve the current hw state. */
3833 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 3834 intel_dp->attached_connector = intel_connector;
3d3dc149 3835
3b32a35b 3836 if (intel_dp_is_edp(dev, port))
b329530c 3837 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 3838 else
3839 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 3840
f7d24902
ID		 3841 /*
3842 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3843 * for DP the encoder type can be set by the caller to
3844 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3845 */
3846 if (type == DRM_MODE_CONNECTOR_eDP)
3847 intel_encoder->type = INTEL_OUTPUT_EDP;
3848
e7281eab
ID		 3849 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3850 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3851 port_name(port));
3852
b329530c 3853 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3854 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3855
a4fc5ed6
KP		 3856 connector->interlace_allowed = true;
3857 connector->doublescan_allowed = 0;
3858
f0fec3f2 3859 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 3860 edp_panel_vdd_work);
a4fc5ed6 3861
df0e9248 3862 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3863 drm_sysfs_connector_add(connector);
3864
affa9354 3865 if (HAS_DDI(dev))
bcbc889b
PZ		 3866 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3867 else
3868 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 3869 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 3870
9ed35ab1
PZ		 3871 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3872 if (HAS_DDI(dev)) {
3873 switch (intel_dig_port->port) {
3874 case PORT_A:
3875 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3876 break;
3877 case PORT_B:
3878 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3879 break;
3880 case PORT_C:
3881 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3882 break;
3883 case PORT_D:
3884 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3885 break;
3886 default:
3887 BUG();
3888 }
3889 }
e8cb4558 3890
a4fc5ed6 3891 /* Set up the DDC bus. */
ab9d7c30
PZ		 3892 switch (port) {
3893 case PORT_A:
1d843f9d 3894 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3895 name = "DPDDC-A";
3896 break;
3897 case PORT_B:
1d843f9d 3898 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3899 name = "DPDDC-B";
3900 break;
3901 case PORT_C:
1d843f9d 3902 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3903 name = "DPDDC-C";
3904 break;
3905 case PORT_D:
1d843f9d 3906 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3907 name = "DPDDC-D";
3908 break;
3909 default:
ad1c0b19 3910 BUG();
5eb08b69
ZW		 3911 }
3912
dada1a9f
ID		 3913 if (is_edp(intel_dp)) {
3914 intel_dp_init_panel_power_timestamps(intel_dp);
0095e6dc 3915 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
dada1a9f 3916 }
0095e6dc 3917
b2a14755
PZ		 3918 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3919 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3920 error, port_name(port));
c1f05264 3921
2b28bb1b
RV		 3922 intel_dp->psr_setup_done = false;
3923
0095e6dc 3924 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
15b1d171
PZ		 3925 i2c_del_adapter(&intel_dp->adapter);
3926 if (is_edp(intel_dp)) {
3927 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3928 mutex_lock(&dev->mode_config.mutex);
4be73780 3929 edp_panel_vdd_off_sync(intel_dp);
15b1d171
PZ		 3930 mutex_unlock(&dev->mode_config.mutex);
3931 }
b2f246a8
PZ		 3932 drm_sysfs_connector_remove(connector);
3933 drm_connector_cleanup(connector);
16c25533 3934 return false;
b2f246a8 3935 }
32f9d658 3936
f684960e
CW		 3937 intel_dp_add_properties(intel_dp, connector);
3938
a4fc5ed6
KP		 3939 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3940 * 0xd. Failure to do so will result in spurious interrupts being
3941 * generated on the port when a cable is not attached.
3942 */
3943 if (IS_G4X(dev) && !IS_GM45(dev)) {
3944 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3945 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3946 }
16c25533
PZ		 3947
3948 return true;
a4fc5ed6 3949}
f0fec3f2
PZ		 3950
3951void
3952intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3953{
3954 struct intel_digital_port *intel_dig_port;
3955 struct intel_encoder *intel_encoder;
3956 struct drm_encoder *encoder;
3957 struct intel_connector *intel_connector;
3958
b14c5679 3959 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 3960 if (!intel_dig_port)
3961 return;
3962
b14c5679 3963 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 3964 if (!intel_connector) {
3965 kfree(intel_dig_port);
3966 return;
3967 }
3968
3969 intel_encoder = &intel_dig_port->base;
3970 encoder = &intel_encoder->base;
3971
3972 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3973 DRM_MODE_ENCODER_TMDS);
3974
5bfe2ac0 3975 intel_encoder->compute_config = intel_dp_compute_config;
b934223d 3976 intel_encoder->mode_set = intel_dp_mode_set;
00c09d70
PZ		 3977 intel_encoder->disable = intel_disable_dp;
3978 intel_encoder->post_disable = intel_post_disable_dp;
3979 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 3980 intel_encoder->get_config = intel_dp_get_config;
ab1f90f9 3981 if (IS_VALLEYVIEW(dev)) {
ecff4f3b 3982 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 3983 intel_encoder->pre_enable = vlv_pre_enable_dp;
3984 intel_encoder->enable = vlv_enable_dp;
3985 } else {
ecff4f3b
JN		 3986 intel_encoder->pre_enable = g4x_pre_enable_dp;
3987 intel_encoder->enable = g4x_enable_dp;
ab1f90f9 3988 }
f0fec3f2 3989
174edf1f 3990 intel_dig_port->port = port;
f0fec3f2
PZ		 3991 intel_dig_port->dp.output_reg = output_reg;
3992
00c09d70 3993 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2 3994 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 3995 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 3996 intel_encoder->hot_plug = intel_dp_hot_plug;
3997
15b1d171
PZ		 3998 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3999 drm_encoder_cleanup(encoder);
4000 kfree(intel_dig_port);
b2f246a8 4001 kfree(intel_connector);
15b1d171 4002 }
f0fec3f2 4003}
Linux kernel - Deliverables
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