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drm/i915: Steal power sequencer in vlv_power_sequencer_pipe()
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 114static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 116static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a8c3344e
VS		 117static void vlv_steal_power_sequencer(struct drm_device *dev,
118 enum pipe pipe);
a4fc5ed6 119
0e32b39c 120int
ea5b213a 121intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 122{
7183dc29 123 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 124 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 125
126 switch (max_link_bw) {
127 case DP_LINK_BW_1_62:
128 case DP_LINK_BW_2_7:
129 break;
d4eead50 130 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 131 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
132 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 133 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
134 max_link_bw = DP_LINK_BW_5_4;
135 else
136 max_link_bw = DP_LINK_BW_2_7;
d4eead50 137 break;
a4fc5ed6 138 default:
d4eead50
ID		 139 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
140 max_link_bw);
a4fc5ed6
KP		 141 max_link_bw = DP_LINK_BW_1_62;
142 break;
143 }
144 return max_link_bw;
145}
146
eeb6324d
PZ		 147static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
148{
149 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
150 struct drm_device *dev = intel_dig_port->base.base.dev;
151 u8 source_max, sink_max;
152
153 source_max = 4;
154 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
155 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
156 source_max = 2;
157
158 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
159
160 return min(source_max, sink_max);
161}
162
cd9dde44
AJ		 163/*
164 * The units on the numbers in the next two are... bizarre. Examples will
165 * make it clearer; this one parallels an example in the eDP spec.
166 *
167 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
168 *
169 * 270000 * 1 * 8 / 10 == 216000
170 *
171 * The actual data capacity of that configuration is 2.16Gbit/s, so the
172 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
173 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
174 * 119000. At 18bpp that's 2142000 kilobits per second.
175 *
176 * Thus the strange-looking division by 10 in intel_dp_link_required, to
177 * get the result in decakilobits instead of kilobits.
178 */
179
a4fc5ed6 180static int
c898261c 181intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 182{
cd9dde44 183 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 184}
185
fe27d53e
DA		 186static int
187intel_dp_max_data_rate(int max_link_clock, int max_lanes)
188{
189 return (max_link_clock * max_lanes * 8) / 10;
190}
191
c19de8eb 192static enum drm_mode_status
a4fc5ed6
KP		 193intel_dp_mode_valid(struct drm_connector *connector,
194 struct drm_display_mode *mode)
195{
df0e9248 196 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 197 struct intel_connector *intel_connector = to_intel_connector(connector);
198 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 199 int target_clock = mode->clock;
200 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 201
dd06f90e
JN		 202 if (is_edp(intel_dp) && fixed_mode) {
203 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 204 return MODE_PANEL;
205
dd06f90e 206 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 207 return MODE_PANEL;
03afc4a2
DV		 208
209 target_clock = fixed_mode->clock;
7de56f43
ZY		 210 }
211
36008365 212 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 213 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 214
215 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
216 mode_rate = intel_dp_link_required(target_clock, 18);
217
218 if (mode_rate > max_rate)
c4867936 219 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 220
221 if (mode->clock < 10000)
222 return MODE_CLOCK_LOW;
223
0af78a2b
DV		 224 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
225 return MODE_H_ILLEGAL;
226
a4fc5ed6
KP		 227 return MODE_OK;
228}
229
230static uint32_t
5ca476f8 231pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 232{
233 int i;
234 uint32_t v = 0;
235
236 if (src_bytes > 4)
237 src_bytes = 4;
238 for (i = 0; i < src_bytes; i++)
239 v |= ((uint32_t) src[i]) << ((3-i) * 8);
240 return v;
241}
242
243static void
244unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
245{
246 int i;
247 if (dst_bytes > 4)
248 dst_bytes = 4;
249 for (i = 0; i < dst_bytes; i++)
250 dst[i] = src >> ((3-i) * 8);
251}
252
fb0f8fbf
KP		 253/* hrawclock is 1/4 the FSB frequency */
254static int
255intel_hrawclk(struct drm_device *dev)
256{
257 struct drm_i915_private *dev_priv = dev->dev_private;
258 uint32_t clkcfg;
259
9473c8f4
VP		 260 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
261 if (IS_VALLEYVIEW(dev))
262 return 200;
263
fb0f8fbf
KP		 264 clkcfg = I915_READ(CLKCFG);
265 switch (clkcfg & CLKCFG_FSB_MASK) {
266 case CLKCFG_FSB_400:
267 return 100;
268 case CLKCFG_FSB_533:
269 return 133;
270 case CLKCFG_FSB_667:
271 return 166;
272 case CLKCFG_FSB_800:
273 return 200;
274 case CLKCFG_FSB_1067:
275 return 266;
276 case CLKCFG_FSB_1333:
277 return 333;
278 /* these two are just a guess; one of them might be right */
279 case CLKCFG_FSB_1600:
280 case CLKCFG_FSB_1600_ALT:
281 return 400;
282 default:
283 return 133;
284 }
285}
286
bf13e81b
JN		 287static void
288intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 289 struct intel_dp *intel_dp);
bf13e81b
JN		 290static void
291intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 292 struct intel_dp *intel_dp);
bf13e81b 293
773538e8
VS		 294static void pps_lock(struct intel_dp *intel_dp)
295{
296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
297 struct intel_encoder *encoder = &intel_dig_port->base;
298 struct drm_device *dev = encoder->base.dev;
299 struct drm_i915_private *dev_priv = dev->dev_private;
300 enum intel_display_power_domain power_domain;
301
302 /*
303 * See vlv_power_sequencer_reset() why we need
304 * a power domain reference here.
305 */
306 power_domain = intel_display_port_power_domain(encoder);
307 intel_display_power_get(dev_priv, power_domain);
308
309 mutex_lock(&dev_priv->pps_mutex);
310}
311
312static void pps_unlock(struct intel_dp *intel_dp)
313{
314 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
315 struct intel_encoder *encoder = &intel_dig_port->base;
316 struct drm_device *dev = encoder->base.dev;
317 struct drm_i915_private *dev_priv = dev->dev_private;
318 enum intel_display_power_domain power_domain;
319
320 mutex_unlock(&dev_priv->pps_mutex);
321
322 power_domain = intel_display_port_power_domain(encoder);
323 intel_display_power_put(dev_priv, power_domain);
324}
325
961a0db0
VS		 326static void
327vlv_power_sequencer_kick(struct intel_dp *intel_dp)
328{
329 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
330 struct drm_device *dev = intel_dig_port->base.base.dev;
331 struct drm_i915_private *dev_priv = dev->dev_private;
332 enum pipe pipe = intel_dp->pps_pipe;
333 uint32_t DP;
334
335 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
336 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
337 pipe_name(pipe), port_name(intel_dig_port->port)))
338 return;
339
340 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
341 pipe_name(pipe), port_name(intel_dig_port->port));
342
343 /* Preserve the BIOS-computed detected bit. This is
344 * supposed to be read-only.
345 */
346 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
347 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
348 DP |= DP_PORT_WIDTH(1);
349 DP |= DP_LINK_TRAIN_PAT_1;
350
351 if (IS_CHERRYVIEW(dev))
352 DP |= DP_PIPE_SELECT_CHV(pipe);
353 else if (pipe == PIPE_B)
354 DP |= DP_PIPEB_SELECT;
355
356 /*
357 * Similar magic as in intel_dp_enable_port().
358 * We _must_ do this port enable + disable trick
359 * to make this power seqeuencer lock onto the port.
360 * Otherwise even VDD force bit won't work.
361 */
362 I915_WRITE(intel_dp->output_reg, DP);
363 POSTING_READ(intel_dp->output_reg);
364
365 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
366 POSTING_READ(intel_dp->output_reg);
367
368 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
369 POSTING_READ(intel_dp->output_reg);
370}
371
bf13e81b
JN		 372static enum pipe
373vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
374{
375 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 376 struct drm_device *dev = intel_dig_port->base.base.dev;
377 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 378 struct intel_encoder *encoder;
379 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
a8c3344e 380 enum pipe pipe;
bf13e81b 381
e39b999a 382 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 383
a8c3344e
VS		 384 /* We should never land here with regular DP ports */
385 WARN_ON(!is_edp(intel_dp));
386
a4a5d2f8
VS		 387 if (intel_dp->pps_pipe != INVALID_PIPE)
388 return intel_dp->pps_pipe;
389
390 /*
391 * We don't have power sequencer currently.
392 * Pick one that's not used by other ports.
393 */
394 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
395 base.head) {
396 struct intel_dp *tmp;
397
398 if (encoder->type != INTEL_OUTPUT_EDP)
399 continue;
400
401 tmp = enc_to_intel_dp(&encoder->base);
402
403 if (tmp->pps_pipe != INVALID_PIPE)
404 pipes &= ~(1 << tmp->pps_pipe);
405 }
406
407 /*
408 * Didn't find one. This should not happen since there
409 * are two power sequencers and up to two eDP ports.
410 */
411 if (WARN_ON(pipes == 0))
a8c3344e
VS		 412 pipe = PIPE_A;
413 else
414 pipe = ffs(pipes) - 1;
a4a5d2f8 415
a8c3344e
VS		 416 vlv_steal_power_sequencer(dev, pipe);
417 intel_dp->pps_pipe = pipe;
a4a5d2f8
VS		 418
419 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
420 pipe_name(intel_dp->pps_pipe),
421 port_name(intel_dig_port->port));
422
423 /* init power sequencer on this pipe and port */
36b5f425
VS		 424 intel_dp_init_panel_power_sequencer(dev, intel_dp);
425 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8 426
961a0db0
VS		 427 /*
428 * Even vdd force doesn't work until we've made
429 * the power sequencer lock in on the port.
430 */
431 vlv_power_sequencer_kick(intel_dp);
432
a4a5d2f8
VS		 433 return intel_dp->pps_pipe;
434}
435
6491ab27
VS		 436typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
437 enum pipe pipe);
438
439static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
440 enum pipe pipe)
441{
442 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
443}
444
445static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
446 enum pipe pipe)
447{
448 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
449}
450
451static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
452 enum pipe pipe)
453{
454 return true;
455}
bf13e81b 456
a4a5d2f8 457static enum pipe
6491ab27
VS		 458vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
459 enum port port,
460 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 461{
462 enum pipe pipe;
bf13e81b 463
bf13e81b
JN		 464 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
465 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
466 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 467
468 if (port_sel != PANEL_PORT_SELECT_VLV(port))
469 continue;
470
6491ab27
VS		 471 if (!pipe_check(dev_priv, pipe))
472 continue;
473
a4a5d2f8 474 return pipe;
bf13e81b
JN		 475 }
476
a4a5d2f8
VS		 477 return INVALID_PIPE;
478}
479
480static void
481vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
482{
483 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
484 struct drm_device *dev = intel_dig_port->base.base.dev;
485 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 486 enum port port = intel_dig_port->port;
487
488 lockdep_assert_held(&dev_priv->pps_mutex);
489
490 /* try to find a pipe with this port selected */
6491ab27
VS		 491 /* first pick one where the panel is on */
492 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
493 vlv_pipe_has_pp_on);
494 /* didn't find one? pick one where vdd is on */
495 if (intel_dp->pps_pipe == INVALID_PIPE)
496 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
497 vlv_pipe_has_vdd_on);
498 /* didn't find one? pick one with just the correct port */
499 if (intel_dp->pps_pipe == INVALID_PIPE)
500 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
501 vlv_pipe_any);
a4a5d2f8
VS		 502
503 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
504 if (intel_dp->pps_pipe == INVALID_PIPE) {
505 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
506 port_name(port));
507 return;
bf13e81b
JN		 508 }
509
a4a5d2f8
VS		 510 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
511 port_name(port), pipe_name(intel_dp->pps_pipe));
512
36b5f425
VS		 513 intel_dp_init_panel_power_sequencer(dev, intel_dp);
514 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 515}
516
773538e8
VS		 517void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
518{
519 struct drm_device *dev = dev_priv->dev;
520 struct intel_encoder *encoder;
521
522 if (WARN_ON(!IS_VALLEYVIEW(dev)))
523 return;
524
525 /*
526 * We can't grab pps_mutex here due to deadlock with power_domain
527 * mutex when power_domain functions are called while holding pps_mutex.
528 * That also means that in order to use pps_pipe the code needs to
529 * hold both a power domain reference and pps_mutex, and the power domain
530 * reference get/put must be done while _not_ holding pps_mutex.
531 * pps_{lock,unlock}() do these steps in the correct order, so one
532 * should use them always.
533 */
534
535 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
536 struct intel_dp *intel_dp;
537
538 if (encoder->type != INTEL_OUTPUT_EDP)
539 continue;
540
541 intel_dp = enc_to_intel_dp(&encoder->base);
542 intel_dp->pps_pipe = INVALID_PIPE;
543 }
bf13e81b
JN		 544}
545
546static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
547{
548 struct drm_device *dev = intel_dp_to_dev(intel_dp);
549
550 if (HAS_PCH_SPLIT(dev))
551 return PCH_PP_CONTROL;
552 else
553 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
554}
555
556static u32 _pp_stat_reg(struct intel_dp *intel_dp)
557{
558 struct drm_device *dev = intel_dp_to_dev(intel_dp);
559
560 if (HAS_PCH_SPLIT(dev))
561 return PCH_PP_STATUS;
562 else
563 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
564}
565
01527b31
CT		 566/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
567 This function only applicable when panel PM state is not to be tracked */
568static int edp_notify_handler(struct notifier_block *this, unsigned long code,
569 void *unused)
570{
571 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
572 edp_notifier);
573 struct drm_device *dev = intel_dp_to_dev(intel_dp);
574 struct drm_i915_private *dev_priv = dev->dev_private;
575 u32 pp_div;
576 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 577
578 if (!is_edp(intel_dp) || code != SYS_RESTART)
579 return 0;
580
773538e8 581 pps_lock(intel_dp);
e39b999a 582
01527b31 583 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 584 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
585
01527b31
CT		 586 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
587 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
588 pp_div = I915_READ(pp_div_reg);
589 pp_div &= PP_REFERENCE_DIVIDER_MASK;
590
591 /* 0x1F write to PP_DIV_REG sets max cycle delay */
592 I915_WRITE(pp_div_reg, pp_div | 0x1F);
593 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
594 msleep(intel_dp->panel_power_cycle_delay);
595 }
596
773538e8 597 pps_unlock(intel_dp);
e39b999a 598
01527b31
CT		 599 return 0;
600}
601
4be73780 602static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 603{
30add22d 604 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 605 struct drm_i915_private *dev_priv = dev->dev_private;
606
e39b999a
VS		 607 lockdep_assert_held(&dev_priv->pps_mutex);
608
9a42356b
VS		 609 if (IS_VALLEYVIEW(dev) &&
610 intel_dp->pps_pipe == INVALID_PIPE)
611 return false;
612
bf13e81b 613 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 614}
615
4be73780 616static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 617{
30add22d 618 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 619 struct drm_i915_private *dev_priv = dev->dev_private;
620
e39b999a
VS		 621 lockdep_assert_held(&dev_priv->pps_mutex);
622
9a42356b
VS		 623 if (IS_VALLEYVIEW(dev) &&
624 intel_dp->pps_pipe == INVALID_PIPE)
625 return false;
626
773538e8 627 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 628}
629
9b984dae
KP		 630static void
631intel_dp_check_edp(struct intel_dp *intel_dp)
632{
30add22d 633 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 634 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 635
9b984dae
KP		 636 if (!is_edp(intel_dp))
637 return;
453c5420 638
4be73780 639 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 640 WARN(1, "eDP powered off while attempting aux channel communication.\n");
641 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 642 I915_READ(_pp_stat_reg(intel_dp)),
643 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 644 }
645}
646
9ee32fea
DV		 647static uint32_t
648intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
649{
650 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
651 struct drm_device *dev = intel_dig_port->base.base.dev;
652 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 653 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 654 uint32_t status;
655 bool done;
656
ef04f00d 657#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 658 if (has_aux_irq)
b18ac466 659 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 660 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 661 else
662 done = wait_for_atomic(C, 10) == 0;
663 if (!done)
664 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
665 has_aux_irq);
666#undef C
667
668 return status;
669}
670
ec5b01dd 671static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 672{
174edf1f
PZ		 673 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
674 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 675
ec5b01dd
DL		 676 /*
677 * The clock divider is based off the hrawclk, and would like to run at
678 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 679 */
ec5b01dd
DL		 680 return index ? 0 : intel_hrawclk(dev) / 2;
681}
682
683static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
684{
685 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
686 struct drm_device *dev = intel_dig_port->base.base.dev;
687
688 if (index)
689 return 0;
690
691 if (intel_dig_port->port == PORT_A) {
692 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 693 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 694 else
b84a1cf8 695 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 696 } else {
697 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
698 }
699}
700
701static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
702{
703 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
704 struct drm_device *dev = intel_dig_port->base.base.dev;
705 struct drm_i915_private *dev_priv = dev->dev_private;
706
707 if (intel_dig_port->port == PORT_A) {
708 if (index)
709 return 0;
710 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 711 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
712 /* Workaround for non-ULT HSW */
bc86625a
CW		 713 switch (index) {
714 case 0: return 63;
715 case 1: return 72;
716 default: return 0;
717 }
ec5b01dd 718 } else {
bc86625a 719 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 720 }
b84a1cf8
RV		 721}
722
ec5b01dd
DL		 723static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
724{
725 return index ? 0 : 100;
726}
727
b6b5e383
DL		 728static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
729{
730 /*
731 * SKL doesn't need us to program the AUX clock divider (Hardware will
732 * derive the clock from CDCLK automatically). We still implement the
733 * get_aux_clock_divider vfunc to plug-in into the existing code.
734 */
735 return index ? 0 : 1;
736}
737
5ed12a19
DL		 738static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
739 bool has_aux_irq,
740 int send_bytes,
741 uint32_t aux_clock_divider)
742{
743 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
744 struct drm_device *dev = intel_dig_port->base.base.dev;
745 uint32_t precharge, timeout;
746
747 if (IS_GEN6(dev))
748 precharge = 3;
749 else
750 precharge = 5;
751
752 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
753 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
754 else
755 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
756
757 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 758 DP_AUX_CH_CTL_DONE |
5ed12a19 759 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 760 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 761 timeout |
788d4433 762 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 763 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
764 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 765 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 766}
767
b9ca5fad
DL		 768static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
769 bool has_aux_irq,
770 int send_bytes,
771 uint32_t unused)
772{
773 return DP_AUX_CH_CTL_SEND_BUSY |
774 DP_AUX_CH_CTL_DONE |
775 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
776 DP_AUX_CH_CTL_TIME_OUT_ERROR |
777 DP_AUX_CH_CTL_TIME_OUT_1600us |
778 DP_AUX_CH_CTL_RECEIVE_ERROR |
779 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
780 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
781}
782
b84a1cf8
RV		 783static int
784intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 785 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 786 uint8_t *recv, int recv_size)
787{
788 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
789 struct drm_device *dev = intel_dig_port->base.base.dev;
790 struct drm_i915_private *dev_priv = dev->dev_private;
791 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
792 uint32_t ch_data = ch_ctl + 4;
bc86625a 793 uint32_t aux_clock_divider;
b84a1cf8
RV		 794 int i, ret, recv_bytes;
795 uint32_t status;
5ed12a19 796 int try, clock = 0;
4e6b788c 797 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 798 bool vdd;
799
773538e8 800 pps_lock(intel_dp);
e39b999a 801
72c3500a
VS		 802 /*
803 * We will be called with VDD already enabled for dpcd/edid/oui reads.
804 * In such cases we want to leave VDD enabled and it's up to upper layers
805 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
806 * ourselves.
807 */
1e0560e0 808 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 809
810 /* dp aux is extremely sensitive to irq latency, hence request the
811 * lowest possible wakeup latency and so prevent the cpu from going into
812 * deep sleep states.
813 */
814 pm_qos_update_request(&dev_priv->pm_qos, 0);
815
816 intel_dp_check_edp(intel_dp);
5eb08b69 817
c67a470b
PZ		 818 intel_aux_display_runtime_get(dev_priv);
819
11bee43e
JB		 820 /* Try to wait for any previous AUX channel activity */
821 for (try = 0; try < 3; try++) {
ef04f00d 822 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 823 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
824 break;
825 msleep(1);
826 }
827
828 if (try == 3) {
829 WARN(1, "dp_aux_ch not started status 0x%08x\n",
830 I915_READ(ch_ctl));
9ee32fea
DV		 831 ret = -EBUSY;
832 goto out;
4f7f7b7e
CW		 833 }
834
46a5ae9f
PZ		 835 /* Only 5 data registers! */
836 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
837 ret = -E2BIG;
838 goto out;
839 }
840
ec5b01dd 841 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 842 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
843 has_aux_irq,
844 send_bytes,
845 aux_clock_divider);
5ed12a19 846
bc86625a
CW		 847 /* Must try at least 3 times according to DP spec */
848 for (try = 0; try < 5; try++) {
849 /* Load the send data into the aux channel data registers */
850 for (i = 0; i < send_bytes; i += 4)
851 I915_WRITE(ch_data + i,
852 pack_aux(send + i, send_bytes - i));
853
854 /* Send the command and wait for it to complete */
5ed12a19 855 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 856
857 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
858
859 /* Clear done status and any errors */
860 I915_WRITE(ch_ctl,
861 status |
862 DP_AUX_CH_CTL_DONE |
863 DP_AUX_CH_CTL_TIME_OUT_ERROR |
864 DP_AUX_CH_CTL_RECEIVE_ERROR);
865
866 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
867 DP_AUX_CH_CTL_RECEIVE_ERROR))
868 continue;
869 if (status & DP_AUX_CH_CTL_DONE)
870 break;
871 }
4f7f7b7e 872 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 873 break;
874 }
875
a4fc5ed6 876 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 877 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 878 ret = -EBUSY;
879 goto out;
a4fc5ed6
KP		 880 }
881
882 /* Check for timeout or receive error.
883 * Timeouts occur when the sink is not connected
884 */
a5b3da54 885 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 886 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 887 ret = -EIO;
888 goto out;
a5b3da54 889 }
1ae8c0a5
KP		 890
891 /* Timeouts occur when the device isn't connected, so they're
892 * "normal" -- don't fill the kernel log with these */
a5b3da54 893 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 894 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 895 ret = -ETIMEDOUT;
896 goto out;
a4fc5ed6
KP		 897 }
898
899 /* Unload any bytes sent back from the other side */
900 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
901 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 902 if (recv_bytes > recv_size)
903 recv_bytes = recv_size;
0206e353 904
4f7f7b7e
CW		 905 for (i = 0; i < recv_bytes; i += 4)
906 unpack_aux(I915_READ(ch_data + i),
907 recv + i, recv_bytes - i);
a4fc5ed6 908
9ee32fea
DV		 909 ret = recv_bytes;
910out:
911 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 912 intel_aux_display_runtime_put(dev_priv);
9ee32fea 913
884f19e9
JN		 914 if (vdd)
915 edp_panel_vdd_off(intel_dp, false);
916
773538e8 917 pps_unlock(intel_dp);
e39b999a 918
9ee32fea 919 return ret;
a4fc5ed6
KP		 920}
921
a6c8aff0
JN		 922#define BARE_ADDRESS_SIZE 3
923#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 924static ssize_t
925intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 926{
9d1a1031
JN		 927 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
928 uint8_t txbuf[20], rxbuf[20];
929 size_t txsize, rxsize;
a4fc5ed6 930 int ret;
a4fc5ed6 931
9d1a1031
JN		 932 txbuf[0] = msg->request << 4;
933 txbuf[1] = msg->address >> 8;
934 txbuf[2] = msg->address & 0xff;
935 txbuf[3] = msg->size - 1;
46a5ae9f 936
9d1a1031
JN		 937 switch (msg->request & ~DP_AUX_I2C_MOT) {
938 case DP_AUX_NATIVE_WRITE:
939 case DP_AUX_I2C_WRITE:
a6c8aff0 940 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 941 rxsize = 1;
f51a44b9 942
9d1a1031
JN		 943 if (WARN_ON(txsize > 20))
944 return -E2BIG;
a4fc5ed6 945
9d1a1031 946 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 947
9d1a1031
JN		 948 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
949 if (ret > 0) {
950 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 951
9d1a1031
JN		 952 /* Return payload size. */
953 ret = msg->size;
954 }
955 break;
46a5ae9f 956
9d1a1031
JN		 957 case DP_AUX_NATIVE_READ:
958 case DP_AUX_I2C_READ:
a6c8aff0 959 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 960 rxsize = msg->size + 1;
a4fc5ed6 961
9d1a1031
JN		 962 if (WARN_ON(rxsize > 20))
963 return -E2BIG;
a4fc5ed6 964
9d1a1031
JN		 965 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
966 if (ret > 0) {
967 msg->reply = rxbuf[0] >> 4;
968 /*
969 * Assume happy day, and copy the data. The caller is
970 * expected to check msg->reply before touching it.
971 *
972 * Return payload size.
973 */
974 ret--;
975 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 976 }
9d1a1031
JN		 977 break;
978
979 default:
980 ret = -EINVAL;
981 break;
a4fc5ed6 982 }
f51a44b9 983
9d1a1031 984 return ret;
a4fc5ed6
KP		 985}
986
9d1a1031
JN		 987static void
988intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
989{
990 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 991 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
992 enum port port = intel_dig_port->port;
0b99836f 993 const char *name = NULL;
ab2c0672
DA		 994 int ret;
995
33ad6626
JN		 996 switch (port) {
997 case PORT_A:
998 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 999 name = "DPDDC-A";
ab2c0672 1000 break;
33ad6626
JN		 1001 case PORT_B:
1002 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 1003 name = "DPDDC-B";
ab2c0672 1004 break;
33ad6626
JN		 1005 case PORT_C:
1006 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 1007 name = "DPDDC-C";
ab2c0672 1008 break;
33ad6626
JN		 1009 case PORT_D:
1010 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 1011 name = "DPDDC-D";
33ad6626
JN		 1012 break;
1013 default:
1014 BUG();
ab2c0672
DA		 1015 }
1016
1b1aad75
DL		 1017 /*
1018 * The AUX_CTL register is usually DP_CTL + 0x10.
1019 *
1020 * On Haswell and Broadwell though:
1021 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1022 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1023 *
1024 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1025 */
1026 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
33ad6626 1027 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 1028
0b99836f 1029 intel_dp->aux.name = name;
9d1a1031
JN		 1030 intel_dp->aux.dev = dev->dev;
1031 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 1032
0b99836f
JN		 1033 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
1034 connector->base.kdev->kobj.name);
8316f337 1035
4f71d0cb 1036 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 1037 if (ret < 0) {
4f71d0cb 1038 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 1039 name, ret);
1040 return;
ab2c0672 1041 }
8a5e6aeb 1042
0b99836f
JN		 1043 ret = sysfs_create_link(&connector->base.kdev->kobj,
1044 &intel_dp->aux.ddc.dev.kobj,
1045 intel_dp->aux.ddc.dev.kobj.name);
1046 if (ret < 0) {
1047 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 1048 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 1049 }
a4fc5ed6
KP		 1050}
1051
80f65de3
ID		 1052static void
1053intel_dp_connector_unregister(struct intel_connector *intel_connector)
1054{
1055 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1056
0e32b39c
DA		 1057 if (!intel_connector->mst_port)
1058 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1059 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 1060 intel_connector_unregister(intel_connector);
1061}
1062
0e50338c
DV		 1063static void
1064hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
1065{
1066 switch (link_bw) {
1067 case DP_LINK_BW_1_62:
1068 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1069 break;
1070 case DP_LINK_BW_2_7:
1071 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1072 break;
1073 case DP_LINK_BW_5_4:
1074 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1075 break;
1076 }
1077}
1078
c6bb3538
DV		 1079static void
1080intel_dp_set_clock(struct intel_encoder *encoder,
1081 struct intel_crtc_config *pipe_config, int link_bw)
1082{
1083 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1084 const struct dp_link_dpll *divisor = NULL;
1085 int i, count = 0;
c6bb3538
DV		 1086
1087 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1088 divisor = gen4_dpll;
1089 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1090 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1091 divisor = pch_dpll;
1092 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1093 } else if (IS_CHERRYVIEW(dev)) {
1094 divisor = chv_dpll;
1095 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1096 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1097 divisor = vlv_dpll;
1098 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1099 }
9dd4ffdf
CML		 1100
1101 if (divisor && count) {
1102 for (i = 0; i < count; i++) {
1103 if (link_bw == divisor[i].link_bw) {
1104 pipe_config->dpll = divisor[i].dpll;
1105 pipe_config->clock_set = true;
1106 break;
1107 }
1108 }
c6bb3538
DV		 1109 }
1110}
1111
00c09d70 1112bool
5bfe2ac0
DV		 1113intel_dp_compute_config(struct intel_encoder *encoder,
1114 struct intel_crtc_config *pipe_config)
a4fc5ed6 1115{
5bfe2ac0 1116 struct drm_device *dev = encoder->base.dev;
36008365 1117 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 1118 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 1119 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1120 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 1121 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 1122 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1123 int lane_count, clock;
56071a20 1124 int min_lane_count = 1;
eeb6324d 1125 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1126 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1127 int min_clock = 0;
06ea66b6 1128 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 1129 int bpp, mode_rate;
06ea66b6 1130 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 1131 int link_avail, link_clock;
a4fc5ed6 1132
bc7d38a4 1133 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1134 pipe_config->has_pch_encoder = true;
1135
03afc4a2 1136 pipe_config->has_dp_encoder = true;
f769cd24 1137 pipe_config->has_drrs = false;
9ed109a7 1138 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 1139
dd06f90e
JN		 1140 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1141 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1142 adjusted_mode);
2dd24552
JB		 1143 if (!HAS_PCH_SPLIT(dev))
1144 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1145 intel_connector->panel.fitting_mode);
1146 else
b074cec8
JB		 1147 intel_pch_panel_fitting(intel_crtc, pipe_config,
1148 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1149 }
1150
cb1793ce 1151 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1152 return false;
1153
083f9560
DV		 1154 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1155 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 1156 max_lane_count, bws[max_clock],
1157 adjusted_mode->crtc_clock);
083f9560 1158
36008365
DV		 1159 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1160 * bpc in between. */
3e7ca985 1161 bpp = pipe_config->pipe_bpp;
56071a20
JN		 1162 if (is_edp(intel_dp)) {
1163 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1164 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1165 dev_priv->vbt.edp_bpp);
1166 bpp = dev_priv->vbt.edp_bpp;
1167 }
1168
344c5bbc
JN		 1169 /*
1170 * Use the maximum clock and number of lanes the eDP panel
1171 * advertizes being capable of. The panels are generally
1172 * designed to support only a single clock and lane
1173 * configuration, and typically these values correspond to the
1174 * native resolution of the panel.
1175 */
1176 min_lane_count = max_lane_count;
1177 min_clock = max_clock;
7984211e 1178 }
657445fe 1179
36008365 1180 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1181 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1182 bpp);
36008365 1183
c6930992
DA		 1184 for (clock = min_clock; clock <= max_clock; clock++) {
1185 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 1186 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1187 link_avail = intel_dp_max_data_rate(link_clock,
1188 lane_count);
1189
1190 if (mode_rate <= link_avail) {
1191 goto found;
1192 }
1193 }
1194 }
1195 }
c4867936 1196
36008365 1197 return false;
3685a8f3 1198
36008365 1199found:
55bc60db
VS		 1200 if (intel_dp->color_range_auto) {
1201 /*
1202 * See:
1203 * CEA-861-E - 5.1 Default Encoding Parameters
1204 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1205 */
18316c8c 1206 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 1207 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1208 else
1209 intel_dp->color_range = 0;
1210 }
1211
3685a8f3 1212 if (intel_dp->color_range)
50f3b016 1213 pipe_config->limited_color_range = true;
a4fc5ed6 1214
36008365
DV		 1215 intel_dp->link_bw = bws[clock];
1216 intel_dp->lane_count = lane_count;
657445fe 1217 pipe_config->pipe_bpp = bpp;
ff9a6750 1218 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 1219
36008365
DV		 1220 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1221 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 1222 pipe_config->port_clock, bpp);
36008365
DV		 1223 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1224 mode_rate, link_avail);
a4fc5ed6 1225
03afc4a2 1226 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1227 adjusted_mode->crtc_clock,
1228 pipe_config->port_clock,
03afc4a2 1229 &pipe_config->dp_m_n);
9d1a455b 1230
439d7ac0
PB		 1231 if (intel_connector->panel.downclock_mode != NULL &&
1232 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1233 pipe_config->has_drrs = true;
439d7ac0
PB		 1234 intel_link_compute_m_n(bpp, lane_count,
1235 intel_connector->panel.downclock_mode->clock,
1236 pipe_config->port_clock,
1237 &pipe_config->dp_m2_n2);
1238 }
1239
ea155f32 1240 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 1241 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1242 else
1243 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 1244
03afc4a2 1245 return true;
a4fc5ed6
KP		 1246}
1247
7c62a164 1248static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1249{
7c62a164
DV		 1250 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1251 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1252 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1253 struct drm_i915_private *dev_priv = dev->dev_private;
1254 u32 dpa_ctl;
1255
ff9a6750 1256 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 1257 dpa_ctl = I915_READ(DP_A);
1258 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1259
ff9a6750 1260 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 1261 /* For a long time we've carried around a ILK-DevA w/a for the
1262 * 160MHz clock. If we're really unlucky, it's still required.
1263 */
1264 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1265 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1266 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1267 } else {
1268 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1269 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1270 }
1ce17038 1271
ea9b6006
DV		 1272 I915_WRITE(DP_A, dpa_ctl);
1273
1274 POSTING_READ(DP_A);
1275 udelay(500);
1276}
1277
8ac33ed3 1278static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1279{
b934223d 1280 struct drm_device *dev = encoder->base.dev;
417e822d 1281 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1282 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1283 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1284 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1285 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1286
417e822d 1287 /*
1a2eb460 1288 * There are four kinds of DP registers:
417e822d
KP		 1289 *
1290 * IBX PCH
1a2eb460
KP		 1291 * SNB CPU
1292 * IVB CPU
417e822d
KP		 1293 * CPT PCH
1294 *
1295 * IBX PCH and CPU are the same for almost everything,
1296 * except that the CPU DP PLL is configured in this
1297 * register
1298 *
1299 * CPT PCH is quite different, having many bits moved
1300 * to the TRANS_DP_CTL register instead. That
1301 * configuration happens (oddly) in ironlake_pch_enable
1302 */
9c9e7927 1303
417e822d
KP		 1304 /* Preserve the BIOS-computed detected bit. This is
1305 * supposed to be read-only.
1306 */
1307 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1308
417e822d 1309 /* Handle DP bits in common between all three register formats */
417e822d 1310 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1311 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1312
9ed109a7 1313 if (crtc->config.has_audio) {
e0dac65e 1314 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1315 pipe_name(crtc->pipe));
ea5b213a 1316 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
33d1e7c6 1317 intel_write_eld(encoder);
e0dac65e 1318 }
247d89f6 1319
417e822d 1320 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1321
bc7d38a4 1322 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1323 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1324 intel_dp->DP |= DP_SYNC_HS_HIGH;
1325 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1326 intel_dp->DP |= DP_SYNC_VS_HIGH;
1327 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1328
6aba5b6c 1329 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1330 intel_dp->DP |= DP_ENHANCED_FRAMING;
1331
7c62a164 1332 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1333 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1334 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1335 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1336
1337 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1338 intel_dp->DP |= DP_SYNC_HS_HIGH;
1339 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1340 intel_dp->DP |= DP_SYNC_VS_HIGH;
1341 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1342
6aba5b6c 1343 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1344 intel_dp->DP |= DP_ENHANCED_FRAMING;
1345
44f37d1f
CML		 1346 if (!IS_CHERRYVIEW(dev)) {
1347 if (crtc->pipe == 1)
1348 intel_dp->DP |= DP_PIPEB_SELECT;
1349 } else {
1350 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1351 }
417e822d
KP		 1352 } else {
1353 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1354 }
a4fc5ed6
KP		 1355}
1356
ffd6749d
PZ		 1357#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1358#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1359
1a5ef5b7
PZ		 1360#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1361#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1362
ffd6749d
PZ		 1363#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1364#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1365
4be73780 1366static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1367 u32 mask,
1368 u32 value)
bd943159 1369{
30add22d 1370 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1371 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1372 u32 pp_stat_reg, pp_ctrl_reg;
1373
e39b999a
VS		 1374 lockdep_assert_held(&dev_priv->pps_mutex);
1375
bf13e81b
JN		 1376 pp_stat_reg = _pp_stat_reg(intel_dp);
1377 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1378
99ea7127 1379 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1380 mask, value,
1381 I915_READ(pp_stat_reg),
1382 I915_READ(pp_ctrl_reg));
32ce697c 1383
453c5420 1384 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1385 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1386 I915_READ(pp_stat_reg),
1387 I915_READ(pp_ctrl_reg));
32ce697c 1388 }
54c136d4
CW		 1389
1390 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1391}
32ce697c 1392
4be73780 1393static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1394{
1395 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1396 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1397}
1398
4be73780 1399static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1400{
1401 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1402 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1403}
1404
4be73780 1405static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1406{
1407 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1408
1409 /* When we disable the VDD override bit last we have to do the manual
1410 * wait. */
1411 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1412 intel_dp->panel_power_cycle_delay);
1413
4be73780 1414 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1415}
1416
4be73780 1417static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1418{
1419 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1420 intel_dp->backlight_on_delay);
1421}
1422
4be73780 1423static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1424{
1425 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1426 intel_dp->backlight_off_delay);
1427}
99ea7127 1428
832dd3c1
KP		 1429/* Read the current pp_control value, unlocking the register if it
1430 * is locked
1431 */
1432
453c5420 1433static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1434{
453c5420
JB		 1435 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1436 struct drm_i915_private *dev_priv = dev->dev_private;
1437 u32 control;
832dd3c1 1438
e39b999a
VS		 1439 lockdep_assert_held(&dev_priv->pps_mutex);
1440
bf13e81b 1441 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1442 control &= ~PANEL_UNLOCK_MASK;
1443 control |= PANEL_UNLOCK_REGS;
1444 return control;
bd943159
KP		 1445}
1446
951468f3
VS		 1447/*
1448 * Must be paired with edp_panel_vdd_off().
1449 * Must hold pps_mutex around the whole on/off sequence.
1450 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1451 */
1e0560e0 1452static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1453{
30add22d 1454 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1455 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1456 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1457 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1458 enum intel_display_power_domain power_domain;
5d613501 1459 u32 pp;
453c5420 1460 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1461 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1462
e39b999a
VS		 1463 lockdep_assert_held(&dev_priv->pps_mutex);
1464
97af61f5 1465 if (!is_edp(intel_dp))
adddaaf4 1466 return false;
bd943159
KP		 1467
1468 intel_dp->want_panel_vdd = true;
99ea7127 1469
4be73780 1470 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1471 return need_to_disable;
b0665d57 1472
4e6e1a54
ID		 1473 power_domain = intel_display_port_power_domain(intel_encoder);
1474 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1475
b0665d57 1476 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1477
4be73780
DV		 1478 if (!edp_have_panel_power(intel_dp))
1479 wait_panel_power_cycle(intel_dp);
99ea7127 1480
453c5420 1481 pp = ironlake_get_pp_control(intel_dp);
5d613501 1482 pp |= EDP_FORCE_VDD;
ebf33b18 1483
bf13e81b
JN		 1484 pp_stat_reg = _pp_stat_reg(intel_dp);
1485 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1486
1487 I915_WRITE(pp_ctrl_reg, pp);
1488 POSTING_READ(pp_ctrl_reg);
1489 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1490 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1491 /*
1492 * If the panel wasn't on, delay before accessing aux channel
1493 */
4be73780 1494 if (!edp_have_panel_power(intel_dp)) {
bd943159 1495 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1496 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1497 }
adddaaf4
JN		 1498
1499 return need_to_disable;
1500}
1501
951468f3
VS		 1502/*
1503 * Must be paired with intel_edp_panel_vdd_off() or
1504 * intel_edp_panel_off().
1505 * Nested calls to these functions are not allowed since
1506 * we drop the lock. Caller must use some higher level
1507 * locking to prevent nested calls from other threads.
1508 */
b80d6c78 1509void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1510{
c695b6b6 1511 bool vdd;
adddaaf4 1512
c695b6b6
VS		 1513 if (!is_edp(intel_dp))
1514 return;
1515
773538e8 1516 pps_lock(intel_dp);
c695b6b6 1517 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1518 pps_unlock(intel_dp);
c695b6b6
VS		 1519
1520 WARN(!vdd, "eDP VDD already requested on\n");
5d613501
JB		 1521}
1522
4be73780 1523static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1524{
30add22d 1525 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1526 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1527 struct intel_digital_port *intel_dig_port =
1528 dp_to_dig_port(intel_dp);
1529 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1530 enum intel_display_power_domain power_domain;
5d613501 1531 u32 pp;
453c5420 1532 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1533
e39b999a 1534 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1535
15e899a0 1536 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1537
15e899a0 1538 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1539 return;
b0665d57 1540
be2c9196 1541 DRM_DEBUG_KMS("Turning eDP VDD off\n");
bd943159 1542
be2c9196
VS		 1543 pp = ironlake_get_pp_control(intel_dp);
1544 pp &= ~EDP_FORCE_VDD;
453c5420 1545
be2c9196
VS		 1546 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1547 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1548
be2c9196
VS		 1549 I915_WRITE(pp_ctrl_reg, pp);
1550 POSTING_READ(pp_ctrl_reg);
90791a5c 1551
be2c9196
VS		 1552 /* Make sure sequencer is idle before allowing subsequent activity */
1553 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1554 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1555
be2c9196
VS		 1556 if ((pp & POWER_TARGET_ON) == 0)
1557 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1558
be2c9196
VS		 1559 power_domain = intel_display_port_power_domain(intel_encoder);
1560 intel_display_power_put(dev_priv, power_domain);
bd943159 1561}
5d613501 1562
4be73780 1563static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1564{
1565 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1566 struct intel_dp, panel_vdd_work);
bd943159 1567
773538e8 1568 pps_lock(intel_dp);
15e899a0
VS		 1569 if (!intel_dp->want_panel_vdd)
1570 edp_panel_vdd_off_sync(intel_dp);
773538e8 1571 pps_unlock(intel_dp);
bd943159
KP		 1572}
1573
aba86890
ID		 1574static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1575{
1576 unsigned long delay;
1577
1578 /*
1579 * Queue the timer to fire a long time from now (relative to the power
1580 * down delay) to keep the panel power up across a sequence of
1581 * operations.
1582 */
1583 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1584 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1585}
1586
951468f3
VS		 1587/*
1588 * Must be paired with edp_panel_vdd_on().
1589 * Must hold pps_mutex around the whole on/off sequence.
1590 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1591 */
4be73780 1592static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1593{
e39b999a
VS		 1594 struct drm_i915_private *dev_priv =
1595 intel_dp_to_dev(intel_dp)->dev_private;
1596
1597 lockdep_assert_held(&dev_priv->pps_mutex);
1598
97af61f5
KP		 1599 if (!is_edp(intel_dp))
1600 return;
5d613501 1601
bd943159 1602 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1603
bd943159
KP		 1604 intel_dp->want_panel_vdd = false;
1605
aba86890 1606 if (sync)
4be73780 1607 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1608 else
1609 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1610}
1611
9f0fb5be 1612static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 1613{
30add22d 1614 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1615 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1616 u32 pp;
453c5420 1617 u32 pp_ctrl_reg;
9934c132 1618
9f0fb5be
VS		 1619 lockdep_assert_held(&dev_priv->pps_mutex);
1620
97af61f5 1621 if (!is_edp(intel_dp))
bd943159 1622 return;
99ea7127
KP		 1623
1624 DRM_DEBUG_KMS("Turn eDP power on\n");
1625
4be73780 1626 if (edp_have_panel_power(intel_dp)) {
99ea7127 1627 DRM_DEBUG_KMS("eDP power already on\n");
9f0fb5be 1628 return;
99ea7127 1629 }
9934c132 1630
4be73780 1631 wait_panel_power_cycle(intel_dp);
37c6c9b0 1632
bf13e81b 1633 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1634 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1635 if (IS_GEN5(dev)) {
1636 /* ILK workaround: disable reset around power sequence */
1637 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1638 I915_WRITE(pp_ctrl_reg, pp);
1639 POSTING_READ(pp_ctrl_reg);
05ce1a49 1640 }
37c6c9b0 1641
1c0ae80a 1642 pp |= POWER_TARGET_ON;
99ea7127
KP		 1643 if (!IS_GEN5(dev))
1644 pp |= PANEL_POWER_RESET;
1645
453c5420
JB		 1646 I915_WRITE(pp_ctrl_reg, pp);
1647 POSTING_READ(pp_ctrl_reg);
9934c132 1648
4be73780 1649 wait_panel_on(intel_dp);
dce56b3c 1650 intel_dp->last_power_on = jiffies;
9934c132 1651
05ce1a49
KP		 1652 if (IS_GEN5(dev)) {
1653 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1654 I915_WRITE(pp_ctrl_reg, pp);
1655 POSTING_READ(pp_ctrl_reg);
05ce1a49 1656 }
9f0fb5be 1657}
e39b999a 1658
9f0fb5be
VS		 1659void intel_edp_panel_on(struct intel_dp *intel_dp)
1660{
1661 if (!is_edp(intel_dp))
1662 return;
1663
1664 pps_lock(intel_dp);
1665 edp_panel_on(intel_dp);
773538e8 1666 pps_unlock(intel_dp);
9934c132
JB		 1667}
1668
9f0fb5be
VS		 1669
1670static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 1671{
4e6e1a54
ID		 1672 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1673 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1674 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1675 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1676 enum intel_display_power_domain power_domain;
99ea7127 1677 u32 pp;
453c5420 1678 u32 pp_ctrl_reg;
9934c132 1679
9f0fb5be
VS		 1680 lockdep_assert_held(&dev_priv->pps_mutex);
1681
97af61f5
KP		 1682 if (!is_edp(intel_dp))
1683 return;
37c6c9b0 1684
99ea7127 1685 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1686
24f3e092
JN		 1687 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1688
453c5420 1689 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1690 /* We need to switch off panel power _and_ force vdd, for otherwise some
1691 * panels get very unhappy and cease to work. */
b3064154
PJ		 1692 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1693 EDP_BLC_ENABLE);
453c5420 1694
bf13e81b 1695 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1696
849e39f5
PZ		 1697 intel_dp->want_panel_vdd = false;
1698
453c5420
JB		 1699 I915_WRITE(pp_ctrl_reg, pp);
1700 POSTING_READ(pp_ctrl_reg);
9934c132 1701
dce56b3c 1702 intel_dp->last_power_cycle = jiffies;
4be73780 1703 wait_panel_off(intel_dp);
849e39f5
PZ		 1704
1705 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1706 power_domain = intel_display_port_power_domain(intel_encoder);
1707 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 1708}
e39b999a 1709
9f0fb5be
VS		 1710void intel_edp_panel_off(struct intel_dp *intel_dp)
1711{
1712 if (!is_edp(intel_dp))
1713 return;
1714
1715 pps_lock(intel_dp);
1716 edp_panel_off(intel_dp);
773538e8 1717 pps_unlock(intel_dp);
9934c132
JB		 1718}
1719
1250d107
JN		 1720/* Enable backlight in the panel power control. */
1721static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1722{
da63a9f2
PZ		 1723 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1724 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1725 struct drm_i915_private *dev_priv = dev->dev_private;
1726 u32 pp;
453c5420 1727 u32 pp_ctrl_reg;
32f9d658 1728
01cb9ea6
JB		 1729 /*
1730 * If we enable the backlight right away following a panel power
1731 * on, we may see slight flicker as the panel syncs with the eDP
1732 * link. So delay a bit to make sure the image is solid before
1733 * allowing it to appear.
1734 */
4be73780 1735 wait_backlight_on(intel_dp);
e39b999a 1736
773538e8 1737 pps_lock(intel_dp);
e39b999a 1738
453c5420 1739 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1740 pp |= EDP_BLC_ENABLE;
453c5420 1741
bf13e81b 1742 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1743
1744 I915_WRITE(pp_ctrl_reg, pp);
1745 POSTING_READ(pp_ctrl_reg);
e39b999a 1746
773538e8 1747 pps_unlock(intel_dp);
32f9d658
ZW		 1748}
1749
1250d107
JN		 1750/* Enable backlight PWM and backlight PP control. */
1751void intel_edp_backlight_on(struct intel_dp *intel_dp)
1752{
1753 if (!is_edp(intel_dp))
1754 return;
1755
1756 DRM_DEBUG_KMS("\n");
1757
1758 intel_panel_enable_backlight(intel_dp->attached_connector);
1759 _intel_edp_backlight_on(intel_dp);
1760}
1761
1762/* Disable backlight in the panel power control. */
1763static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1764{
30add22d 1765 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1766 struct drm_i915_private *dev_priv = dev->dev_private;
1767 u32 pp;
453c5420 1768 u32 pp_ctrl_reg;
32f9d658 1769
f01eca2e
KP		 1770 if (!is_edp(intel_dp))
1771 return;
1772
773538e8 1773 pps_lock(intel_dp);
e39b999a 1774
453c5420 1775 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1776 pp &= ~EDP_BLC_ENABLE;
453c5420 1777
bf13e81b 1778 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1779
1780 I915_WRITE(pp_ctrl_reg, pp);
1781 POSTING_READ(pp_ctrl_reg);
f7d2323c 1782
773538e8 1783 pps_unlock(intel_dp);
e39b999a
VS		 1784
1785 intel_dp->last_backlight_off = jiffies;
f7d2323c 1786 edp_wait_backlight_off(intel_dp);
1250d107 1787}
f7d2323c 1788
1250d107
JN		 1789/* Disable backlight PP control and backlight PWM. */
1790void intel_edp_backlight_off(struct intel_dp *intel_dp)
1791{
1792 if (!is_edp(intel_dp))
1793 return;
1794
1795 DRM_DEBUG_KMS("\n");
f7d2323c 1796
1250d107 1797 _intel_edp_backlight_off(intel_dp);
f7d2323c 1798 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1799}
a4fc5ed6 1800
73580fb7
JN		 1801/*
1802 * Hook for controlling the panel power control backlight through the bl_power
1803 * sysfs attribute. Take care to handle multiple calls.
1804 */
1805static void intel_edp_backlight_power(struct intel_connector *connector,
1806 bool enable)
1807{
1808 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 1809 bool is_enabled;
1810
773538e8 1811 pps_lock(intel_dp);
e39b999a 1812 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 1813 pps_unlock(intel_dp);
73580fb7
JN		 1814
1815 if (is_enabled == enable)
1816 return;
1817
23ba9373
JN		 1818 DRM_DEBUG_KMS("panel power control backlight %s\n",
1819 enable ? "enable" : "disable");
73580fb7
JN		 1820
1821 if (enable)
1822 _intel_edp_backlight_on(intel_dp);
1823 else
1824 _intel_edp_backlight_off(intel_dp);
1825}
1826
2bd2ad64 1827static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1828{
da63a9f2
PZ		 1829 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1830 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1831 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1832 struct drm_i915_private *dev_priv = dev->dev_private;
1833 u32 dpa_ctl;
1834
2bd2ad64
DV		 1835 assert_pipe_disabled(dev_priv,
1836 to_intel_crtc(crtc)->pipe);
1837
d240f20f
JB		 1838 DRM_DEBUG_KMS("\n");
1839 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1840 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1841 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1842
1843 /* We don't adjust intel_dp->DP while tearing down the link, to
1844 * facilitate link retraining (e.g. after hotplug). Hence clear all
1845 * enable bits here to ensure that we don't enable too much. */
1846 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1847 intel_dp->DP |= DP_PLL_ENABLE;
1848 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1849 POSTING_READ(DP_A);
1850 udelay(200);
d240f20f
JB		 1851}
1852
2bd2ad64 1853static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1854{
da63a9f2
PZ		 1855 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1856 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1857 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1858 struct drm_i915_private *dev_priv = dev->dev_private;
1859 u32 dpa_ctl;
1860
2bd2ad64
DV		 1861 assert_pipe_disabled(dev_priv,
1862 to_intel_crtc(crtc)->pipe);
1863
d240f20f 1864 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1865 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1866 "dp pll off, should be on\n");
1867 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1868
1869 /* We can't rely on the value tracked for the DP register in
1870 * intel_dp->DP because link_down must not change that (otherwise link
1871 * re-training will fail. */
298b0b39 1872 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1873 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1874 POSTING_READ(DP_A);
d240f20f
JB		 1875 udelay(200);
1876}
1877
c7ad3810 1878/* If the sink supports it, try to set the power state appropriately */
c19b0669 1879void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1880{
1881 int ret, i;
1882
1883 /* Should have a valid DPCD by this point */
1884 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1885 return;
1886
1887 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1888 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1889 DP_SET_POWER_D3);
c7ad3810
JB		 1890 } else {
1891 /*
1892 * When turning on, we need to retry for 1ms to give the sink
1893 * time to wake up.
1894 */
1895 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1896 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1897 DP_SET_POWER_D0);
c7ad3810
JB		 1898 if (ret == 1)
1899 break;
1900 msleep(1);
1901 }
1902 }
f9cac721
JN		 1903
1904 if (ret != 1)
1905 DRM_DEBUG_KMS("failed to %s sink power state\n",
1906 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 1907}
1908
19d8fe15
DV		 1909static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1910 enum pipe *pipe)
d240f20f 1911{
19d8fe15 1912 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1913 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1914 struct drm_device *dev = encoder->base.dev;
1915 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1916 enum intel_display_power_domain power_domain;
1917 u32 tmp;
1918
1919 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 1920 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 1921 return false;
1922
1923 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1924
1925 if (!(tmp & DP_PORT_EN))
1926 return false;
1927
bc7d38a4 1928 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1929 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1930 } else if (IS_CHERRYVIEW(dev)) {
1931 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1932 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1933 *pipe = PORT_TO_PIPE(tmp);
1934 } else {
1935 u32 trans_sel;
1936 u32 trans_dp;
1937 int i;
1938
1939 switch (intel_dp->output_reg) {
1940 case PCH_DP_B:
1941 trans_sel = TRANS_DP_PORT_SEL_B;
1942 break;
1943 case PCH_DP_C:
1944 trans_sel = TRANS_DP_PORT_SEL_C;
1945 break;
1946 case PCH_DP_D:
1947 trans_sel = TRANS_DP_PORT_SEL_D;
1948 break;
1949 default:
1950 return true;
1951 }
1952
055e393f 1953 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 1954 trans_dp = I915_READ(TRANS_DP_CTL(i));
1955 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1956 *pipe = i;
1957 return true;
1958 }
1959 }
19d8fe15 1960
4a0833ec
DV		 1961 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1962 intel_dp->output_reg);
1963 }
d240f20f 1964
19d8fe15
DV		 1965 return true;
1966}
d240f20f 1967
045ac3b5
JB		 1968static void intel_dp_get_config(struct intel_encoder *encoder,
1969 struct intel_crtc_config *pipe_config)
1970{
1971 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1972 u32 tmp, flags = 0;
63000ef6
XZ		 1973 struct drm_device *dev = encoder->base.dev;
1974 struct drm_i915_private *dev_priv = dev->dev_private;
1975 enum port port = dp_to_dig_port(intel_dp)->port;
1976 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1977 int dotclock;
045ac3b5 1978
9ed109a7
DV		 1979 tmp = I915_READ(intel_dp->output_reg);
1980 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1981 pipe_config->has_audio = true;
1982
63000ef6 1983 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1984 if (tmp & DP_SYNC_HS_HIGH)
1985 flags |= DRM_MODE_FLAG_PHSYNC;
1986 else
1987 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1988
63000ef6
XZ		 1989 if (tmp & DP_SYNC_VS_HIGH)
1990 flags |= DRM_MODE_FLAG_PVSYNC;
1991 else
1992 flags |= DRM_MODE_FLAG_NVSYNC;
1993 } else {
1994 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1995 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1996 flags |= DRM_MODE_FLAG_PHSYNC;
1997 else
1998 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1999
63000ef6
XZ		 2000 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2001 flags |= DRM_MODE_FLAG_PVSYNC;
2002 else
2003 flags |= DRM_MODE_FLAG_NVSYNC;
2004 }
045ac3b5
JB		 2005
2006 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 2007
8c875fca
VS		 2008 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2009 tmp & DP_COLOR_RANGE_16_235)
2010 pipe_config->limited_color_range = true;
2011
eb14cb74
VS		 2012 pipe_config->has_dp_encoder = true;
2013
2014 intel_dp_get_m_n(crtc, pipe_config);
2015
18442d08 2016 if (port == PORT_A) {
f1f644dc
JB		 2017 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
2018 pipe_config->port_clock = 162000;
2019 else
2020 pipe_config->port_clock = 270000;
2021 }
18442d08
VS		 2022
2023 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2024 &pipe_config->dp_m_n);
2025
2026 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2027 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2028
241bfc38 2029 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 2030
c6cd2ee2
JN		 2031 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2032 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2033 /*
2034 * This is a big fat ugly hack.
2035 *
2036 * Some machines in UEFI boot mode provide us a VBT that has 18
2037 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2038 * unknown we fail to light up. Yet the same BIOS boots up with
2039 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2040 * max, not what it tells us to use.
2041 *
2042 * Note: This will still be broken if the eDP panel is not lit
2043 * up by the BIOS, and thus we can't get the mode at module
2044 * load.
2045 */
2046 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2047 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2048 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2049 }
045ac3b5
JB		 2050}
2051
34eb7579 2052static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 2053{
34eb7579 2054 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 2055}
2056
2b28bb1b
RV		 2057static bool intel_edp_is_psr_enabled(struct drm_device *dev)
2058{
2059 struct drm_i915_private *dev_priv = dev->dev_private;
2060
18b5992c 2061 if (!HAS_PSR(dev))
2b28bb1b
RV		 2062 return false;
2063
18b5992c 2064 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 2065}
2066
2067static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
2068 struct edp_vsc_psr *vsc_psr)
2069{
2070 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2071 struct drm_device *dev = dig_port->base.base.dev;
2072 struct drm_i915_private *dev_priv = dev->dev_private;
2073 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
2074 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
2075 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
2076 uint32_t *data = (uint32_t *) vsc_psr;
2077 unsigned int i;
2078
2079 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
2080 the video DIP being updated before program video DIP data buffer
2081 registers for DIP being updated. */
2082 I915_WRITE(ctl_reg, 0);
2083 POSTING_READ(ctl_reg);
2084
2085 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
2086 if (i < sizeof(struct edp_vsc_psr))
2087 I915_WRITE(data_reg + i, *data++);
2088 else
2089 I915_WRITE(data_reg + i, 0);
2090 }
2091
2092 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
2093 POSTING_READ(ctl_reg);
2094}
2095
ba80f4d4 2096static void intel_edp_psr_setup_vsc(struct intel_dp *intel_dp)
2b28bb1b 2097{
2b28bb1b
RV		 2098 struct edp_vsc_psr psr_vsc;
2099
2b28bb1b
RV		 2100 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
2101 memset(&psr_vsc, 0, sizeof(psr_vsc));
2102 psr_vsc.sdp_header.HB0 = 0;
2103 psr_vsc.sdp_header.HB1 = 0x7;
2104 psr_vsc.sdp_header.HB2 = 0x2;
2105 psr_vsc.sdp_header.HB3 = 0x8;
2106 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
2b28bb1b
RV		 2107}
2108
2109static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
2110{
0e0ae652
RV		 2111 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2112 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 2113 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 2114 uint32_t aux_clock_divider;
2b28bb1b 2115 int precharge = 0x3;
0e0ae652 2116 bool only_standby = false;
5ca476f8
VS		 2117 static const uint8_t aux_msg[] = {
2118 [0] = DP_AUX_NATIVE_WRITE << 4,
2119 [1] = DP_SET_POWER >> 8,
2120 [2] = DP_SET_POWER & 0xff,
2121 [3] = 1 - 1,
2122 [4] = DP_SET_POWER_D0,
2123 };
2124 int i;
2125
2126 BUILD_BUG_ON(sizeof(aux_msg) > 20);
2b28bb1b 2127
ec5b01dd
DL		 2128 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
2129
0e0ae652
RV		 2130 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2131 only_standby = true;
2132
2b28bb1b 2133 /* Enable PSR in sink */
0e0ae652 2134 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 2135 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2136 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 2137 else
9d1a1031
JN		 2138 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2139 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 2140
2141 /* Setup AUX registers */
5ca476f8
VS		 2142 for (i = 0; i < sizeof(aux_msg); i += 4)
2143 I915_WRITE(EDP_PSR_AUX_DATA1(dev) + i,
2144 pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
2145
18b5992c 2146 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b 2147 DP_AUX_CH_CTL_TIME_OUT_400us |
5ca476f8 2148 (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
2b28bb1b
RV		 2149 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
2150 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
2151}
2152
2153static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
2154{
0e0ae652
RV		 2155 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2156 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 2157 struct drm_i915_private *dev_priv = dev->dev_private;
2158 uint32_t max_sleep_time = 0x1f;
2159 uint32_t idle_frames = 1;
2160 uint32_t val = 0x0;
ed8546ac 2161 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 2162 bool only_standby = false;
2163
2164 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2165 only_standby = true;
2b28bb1b 2166
0e0ae652 2167 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 2168 val |= EDP_PSR_LINK_STANDBY;
2169 val |= EDP_PSR_TP2_TP3_TIME_0us;
2170 val |= EDP_PSR_TP1_TIME_0us;
2171 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 2172 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 2173 } else
2174 val |= EDP_PSR_LINK_DISABLE;
2175
18b5992c 2176 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 2177 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 2178 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
2179 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
2180 EDP_PSR_ENABLE);
2181}
2182
3f51e471
RV		 2183static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
2184{
2185 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2186 struct drm_device *dev = dig_port->base.base.dev;
2187 struct drm_i915_private *dev_priv = dev->dev_private;
2188 struct drm_crtc *crtc = dig_port->base.base.crtc;
2189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3f51e471 2190
f0355c4a 2191 lockdep_assert_held(&dev_priv->psr.lock);
f0355c4a
DV		 2192 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
2193 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
2194
a031d709
RV		 2195 dev_priv->psr.source_ok = false;
2196
9ca15301 2197 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
3f51e471 2198 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 2199 return false;
2200 }
2201
d330a953 2202 if (!i915.enable_psr) {
105b7c11 2203 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 2204 return false;
2205 }
2206
4c8c7000
RV		 2207 /* Below limitations aren't valid for Broadwell */
2208 if (IS_BROADWELL(dev))
2209 goto out;
2210
3f51e471
RV		 2211 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
2212 S3D_ENABLE) {
2213 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 2214 return false;
2215 }
2216
ca73b4f0 2217 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 2218 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 2219 return false;
2220 }
2221
4c8c7000 2222 out:
a031d709 2223 dev_priv->psr.source_ok = true;
3f51e471
RV		 2224 return true;
2225}
2226
3d739d92 2227static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 2228{
7c8f8a70
RV		 2229 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2230 struct drm_device *dev = intel_dig_port->base.base.dev;
2231 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 2232
3638379c
DV		 2233 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2234 WARN_ON(dev_priv->psr.active);
f0355c4a 2235 lockdep_assert_held(&dev_priv->psr.lock);
2b28bb1b 2236
7ca5a41f 2237 /* Enable/Re-enable PSR on the host */
2b28bb1b 2238 intel_edp_psr_enable_source(intel_dp);
7c8f8a70 2239
7c8f8a70 2240 dev_priv->psr.active = true;
2b28bb1b
RV		 2241}
2242
3d739d92
RV		 2243void intel_edp_psr_enable(struct intel_dp *intel_dp)
2244{
2245 struct drm_device *dev = intel_dp_to_dev(intel_dp);
109fc2ad 2246 struct drm_i915_private *dev_priv = dev->dev_private;
3d739d92 2247
4704c573
RV		 2248 if (!HAS_PSR(dev)) {
2249 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2250 return;
2251 }
2252
34eb7579
RV		 2253 if (!is_edp_psr(intel_dp)) {
2254 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2255 return;
2256 }
2257
f0355c4a 2258 mutex_lock(&dev_priv->psr.lock);
109fc2ad
DV		 2259 if (dev_priv->psr.enabled) {
2260 DRM_DEBUG_KMS("PSR already in use\n");
0aa48783 2261 goto unlock;
109fc2ad
DV		 2262 }
2263
0aa48783
RV		 2264 if (!intel_edp_psr_match_conditions(intel_dp))
2265 goto unlock;
2266
9ca15301
DV		 2267 dev_priv->psr.busy_frontbuffer_bits = 0;
2268
ba80f4d4 2269 intel_edp_psr_setup_vsc(intel_dp);
16487254 2270
ba80f4d4
RV		 2271 /* Avoid continuous PSR exit by masking memup and hpd */
2272 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
2273 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
16487254 2274
7ca5a41f
RV		 2275 /* Enable PSR on the panel */
2276 intel_edp_psr_enable_sink(intel_dp);
2277
0aa48783
RV		 2278 dev_priv->psr.enabled = intel_dp;
2279unlock:
f0355c4a 2280 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2281}
2282
2b28bb1b
RV		 2283void intel_edp_psr_disable(struct intel_dp *intel_dp)
2284{
2285 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2286 struct drm_i915_private *dev_priv = dev->dev_private;
2287
f0355c4a
DV		 2288 mutex_lock(&dev_priv->psr.lock);
2289 if (!dev_priv->psr.enabled) {
2290 mutex_unlock(&dev_priv->psr.lock);
2291 return;
2292 }
2293
3638379c
DV		 2294 if (dev_priv->psr.active) {
2295 I915_WRITE(EDP_PSR_CTL(dev),
2296 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2297
2298 /* Wait till PSR is idle */
2299 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2300 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
2301 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2b28bb1b 2302
3638379c
DV		 2303 dev_priv->psr.active = false;
2304 } else {
2305 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2306 }
7c8f8a70 2307
2807cf69 2308 dev_priv->psr.enabled = NULL;
f0355c4a 2309 mutex_unlock(&dev_priv->psr.lock);
9ca15301
DV		 2310
2311 cancel_delayed_work_sync(&dev_priv->psr.work);
2b28bb1b
RV		 2312}
2313
f02a326e 2314static void intel_edp_psr_work(struct work_struct *work)
7c8f8a70
RV		 2315{
2316 struct drm_i915_private *dev_priv =
2317 container_of(work, typeof(*dev_priv), psr.work.work);
2807cf69
DV		 2318 struct intel_dp *intel_dp = dev_priv->psr.enabled;
2319
8d7f4fe9
RV		 2320 /* We have to make sure PSR is ready for re-enable
2321 * otherwise it keeps disabled until next full enable/disable cycle.
2322 * PSR might take some time to get fully disabled
2323 * and be ready for re-enable.
2324 */
2325 if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
2326 EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
2327 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
2328 return;
2329 }
2330
f0355c4a
DV		 2331 mutex_lock(&dev_priv->psr.lock);
2332 intel_dp = dev_priv->psr.enabled;
2333
2807cf69 2334 if (!intel_dp)
f0355c4a 2335 goto unlock;
2807cf69 2336
9ca15301
DV		 2337 /*
2338 * The delayed work can race with an invalidate hence we need to
2339 * recheck. Since psr_flush first clears this and then reschedules we
2340 * won't ever miss a flush when bailing out here.
2341 */
2342 if (dev_priv->psr.busy_frontbuffer_bits)
2343 goto unlock;
2344
2345 intel_edp_psr_do_enable(intel_dp);
f0355c4a
DV		 2346unlock:
2347 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2348}
2349
9ca15301 2350static void intel_edp_psr_do_exit(struct drm_device *dev)
7c8f8a70
RV		 2351{
2352 struct drm_i915_private *dev_priv = dev->dev_private;
2353
3638379c
DV		 2354 if (dev_priv->psr.active) {
2355 u32 val = I915_READ(EDP_PSR_CTL(dev));
2356
2357 WARN_ON(!(val & EDP_PSR_ENABLE));
2358
2359 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
2360
2361 dev_priv->psr.active = false;
2362 }
7c8f8a70 2363
9ca15301
DV		 2364}
2365
2366void intel_edp_psr_invalidate(struct drm_device *dev,
2367 unsigned frontbuffer_bits)
2368{
2369 struct drm_i915_private *dev_priv = dev->dev_private;
2370 struct drm_crtc *crtc;
2371 enum pipe pipe;
2372
9ca15301
DV		 2373 mutex_lock(&dev_priv->psr.lock);
2374 if (!dev_priv->psr.enabled) {
2375 mutex_unlock(&dev_priv->psr.lock);
2376 return;
2377 }
2378
2379 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2380 pipe = to_intel_crtc(crtc)->pipe;
2381
2382 intel_edp_psr_do_exit(dev);
2383
2384 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2385
2386 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2387 mutex_unlock(&dev_priv->psr.lock);
2388}
2389
2390void intel_edp_psr_flush(struct drm_device *dev,
2391 unsigned frontbuffer_bits)
2392{
2393 struct drm_i915_private *dev_priv = dev->dev_private;
2394 struct drm_crtc *crtc;
2395 enum pipe pipe;
2396
9ca15301
DV		 2397 mutex_lock(&dev_priv->psr.lock);
2398 if (!dev_priv->psr.enabled) {
2399 mutex_unlock(&dev_priv->psr.lock);
2400 return;
2401 }
2402
2403 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2404 pipe = to_intel_crtc(crtc)->pipe;
2405 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2406
2407 /*
2408 * On Haswell sprite plane updates don't result in a psr invalidating
2409 * signal in the hardware. Which means we need to manually fake this in
2410 * software for all flushes, not just when we've seen a preceding
2411 * invalidation through frontbuffer rendering.
2412 */
2413 if (IS_HASWELL(dev) &&
2414 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2415 intel_edp_psr_do_exit(dev);
2416
2417 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2418 schedule_delayed_work(&dev_priv->psr.work,
2419 msecs_to_jiffies(100));
f0355c4a 2420 mutex_unlock(&dev_priv->psr.lock);
7c8f8a70
RV		 2421}
2422
2423void intel_edp_psr_init(struct drm_device *dev)
2424{
2425 struct drm_i915_private *dev_priv = dev->dev_private;
2426
7c8f8a70 2427 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
f0355c4a 2428 mutex_init(&dev_priv->psr.lock);
7c8f8a70
RV		 2429}
2430
e8cb4558 2431static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2432{
e8cb4558 2433 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2434 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 2435
2436 /* Make sure the panel is off before trying to change the mode. But also
2437 * ensure that we have vdd while we switch off the panel. */
24f3e092 2438 intel_edp_panel_vdd_on(intel_dp);
4be73780 2439 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2440 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2441 intel_edp_panel_off(intel_dp);
3739850b 2442
08aff3fe
VS		 2443 /* disable the port before the pipe on g4x */
2444 if (INTEL_INFO(dev)->gen < 5)
3739850b 2445 intel_dp_link_down(intel_dp);
d240f20f
JB		 2446}
2447
08aff3fe 2448static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2449{
2bd2ad64 2450 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2451 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2452
49277c31 2453 intel_dp_link_down(intel_dp);
08aff3fe
VS		 2454 if (port == PORT_A)
2455 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2456}
2457
2458static void vlv_post_disable_dp(struct intel_encoder *encoder)
2459{
2460 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2461
2462 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2463}
2464
580d3811
VS		 2465static void chv_post_disable_dp(struct intel_encoder *encoder)
2466{
2467 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2468 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2469 struct drm_device *dev = encoder->base.dev;
2470 struct drm_i915_private *dev_priv = dev->dev_private;
2471 struct intel_crtc *intel_crtc =
2472 to_intel_crtc(encoder->base.crtc);
2473 enum dpio_channel ch = vlv_dport_to_channel(dport);
2474 enum pipe pipe = intel_crtc->pipe;
2475 u32 val;
2476
2477 intel_dp_link_down(intel_dp);
2478
2479 mutex_lock(&dev_priv->dpio_lock);
2480
2481 /* Propagate soft reset to data lane reset */
97fd4d5c 2482 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2483 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2484 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2485
97fd4d5c
VS		 2486 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2487 val |= CHV_PCS_REQ_SOFTRESET_EN;
2488 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2489
2490 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2491 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2492 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2493
2494 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2495 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2496 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2497
2498 mutex_unlock(&dev_priv->dpio_lock);
2499}
2500
7b13b58a
VS		 2501static void
2502_intel_dp_set_link_train(struct intel_dp *intel_dp,
2503 uint32_t *DP,
2504 uint8_t dp_train_pat)
2505{
2506 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2507 struct drm_device *dev = intel_dig_port->base.base.dev;
2508 struct drm_i915_private *dev_priv = dev->dev_private;
2509 enum port port = intel_dig_port->port;
2510
2511 if (HAS_DDI(dev)) {
2512 uint32_t temp = I915_READ(DP_TP_CTL(port));
2513
2514 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2515 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2516 else
2517 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2518
2519 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2520 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2521 case DP_TRAINING_PATTERN_DISABLE:
2522 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2523
2524 break;
2525 case DP_TRAINING_PATTERN_1:
2526 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2527 break;
2528 case DP_TRAINING_PATTERN_2:
2529 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2530 break;
2531 case DP_TRAINING_PATTERN_3:
2532 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2533 break;
2534 }
2535 I915_WRITE(DP_TP_CTL(port), temp);
2536
2537 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2538 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2539
2540 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2541 case DP_TRAINING_PATTERN_DISABLE:
2542 *DP |= DP_LINK_TRAIN_OFF_CPT;
2543 break;
2544 case DP_TRAINING_PATTERN_1:
2545 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2546 break;
2547 case DP_TRAINING_PATTERN_2:
2548 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2549 break;
2550 case DP_TRAINING_PATTERN_3:
2551 DRM_ERROR("DP training pattern 3 not supported\n");
2552 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2553 break;
2554 }
2555
2556 } else {
2557 if (IS_CHERRYVIEW(dev))
2558 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2559 else
2560 *DP &= ~DP_LINK_TRAIN_MASK;
2561
2562 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2563 case DP_TRAINING_PATTERN_DISABLE:
2564 *DP |= DP_LINK_TRAIN_OFF;
2565 break;
2566 case DP_TRAINING_PATTERN_1:
2567 *DP |= DP_LINK_TRAIN_PAT_1;
2568 break;
2569 case DP_TRAINING_PATTERN_2:
2570 *DP |= DP_LINK_TRAIN_PAT_2;
2571 break;
2572 case DP_TRAINING_PATTERN_3:
2573 if (IS_CHERRYVIEW(dev)) {
2574 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2575 } else {
2576 DRM_ERROR("DP training pattern 3 not supported\n");
2577 *DP |= DP_LINK_TRAIN_PAT_2;
2578 }
2579 break;
2580 }
2581 }
2582}
2583
2584static void intel_dp_enable_port(struct intel_dp *intel_dp)
2585{
2586 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2587 struct drm_i915_private *dev_priv = dev->dev_private;
2588
7b13b58a
VS		 2589 /* enable with pattern 1 (as per spec) */
2590 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2591 DP_TRAINING_PATTERN_1);
2592
2593 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2594 POSTING_READ(intel_dp->output_reg);
7b713f50
VS		 2595
2596 /*
2597 * Magic for VLV/CHV. We _must_ first set up the register
2598 * without actually enabling the port, and then do another
2599 * write to enable the port. Otherwise link training will
2600 * fail when the power sequencer is freshly used for this port.
2601 */
2602 intel_dp->DP |= DP_PORT_EN;
2603
2604 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2605 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2606}
2607
e8cb4558 2608static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2609{
e8cb4558
DV		 2610 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2611 struct drm_device *dev = encoder->base.dev;
2612 struct drm_i915_private *dev_priv = dev->dev_private;
2613 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2614
0c33d8d7
DV		 2615 if (WARN_ON(dp_reg & DP_PORT_EN))
2616 return;
5d613501 2617
093e3f13
VS		 2618 pps_lock(intel_dp);
2619
2620 if (IS_VALLEYVIEW(dev))
2621 vlv_init_panel_power_sequencer(intel_dp);
2622
7b13b58a 2623 intel_dp_enable_port(intel_dp);
093e3f13
VS		 2624
2625 edp_panel_vdd_on(intel_dp);
2626 edp_panel_on(intel_dp);
2627 edp_panel_vdd_off(intel_dp, true);
2628
2629 pps_unlock(intel_dp);
2630
61234fa5
VS		 2631 if (IS_VALLEYVIEW(dev))
2632 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp));
2633
f01eca2e 2634 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2635 intel_dp_start_link_train(intel_dp);
33a34e4e 2636 intel_dp_complete_link_train(intel_dp);
3ab9c637 2637 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2638}
89b667f8 2639
ecff4f3b
JN		 2640static void g4x_enable_dp(struct intel_encoder *encoder)
2641{
828f5c6e
JN		 2642 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2643
ecff4f3b 2644 intel_enable_dp(encoder);
4be73780 2645 intel_edp_backlight_on(intel_dp);
ab1f90f9 2646}
89b667f8 2647
ab1f90f9
JN		 2648static void vlv_enable_dp(struct intel_encoder *encoder)
2649{
828f5c6e
JN		 2650 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2651
4be73780 2652 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2653}
2654
ecff4f3b 2655static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2656{
2657 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2658 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2659
8ac33ed3
DV		 2660 intel_dp_prepare(encoder);
2661
d41f1efb
DV		 2662 /* Only ilk+ has port A */
2663 if (dport->port == PORT_A) {
2664 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2665 ironlake_edp_pll_on(intel_dp);
d41f1efb 2666 }
ab1f90f9
JN		 2667}
2668
83b84597
VS		 2669static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2670{
2671 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2672 struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2673 enum pipe pipe = intel_dp->pps_pipe;
2674 int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2675
2676 edp_panel_vdd_off_sync(intel_dp);
2677
2678 /*
2679 * VLV seems to get confused when multiple power seqeuencers
2680 * have the same port selected (even if only one has power/vdd
2681 * enabled). The failure manifests as vlv_wait_port_ready() failing
2682 * CHV on the other hand doesn't seem to mind having the same port
2683 * selected in multiple power seqeuencers, but let's clear the
2684 * port select always when logically disconnecting a power sequencer
2685 * from a port.
2686 */
2687 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2688 pipe_name(pipe), port_name(intel_dig_port->port));
2689 I915_WRITE(pp_on_reg, 0);
2690 POSTING_READ(pp_on_reg);
2691
2692 intel_dp->pps_pipe = INVALID_PIPE;
2693}
2694
a4a5d2f8
VS		 2695static void vlv_steal_power_sequencer(struct drm_device *dev,
2696 enum pipe pipe)
2697{
2698 struct drm_i915_private *dev_priv = dev->dev_private;
2699 struct intel_encoder *encoder;
2700
2701 lockdep_assert_held(&dev_priv->pps_mutex);
2702
ac3c12e4
VS		 2703 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2704 return;
2705
a4a5d2f8
VS		 2706 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2707 base.head) {
2708 struct intel_dp *intel_dp;
773538e8 2709 enum port port;
a4a5d2f8
VS		 2710
2711 if (encoder->type != INTEL_OUTPUT_EDP)
2712 continue;
2713
2714 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2715 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2716
2717 if (intel_dp->pps_pipe != pipe)
2718 continue;
2719
2720 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2721 pipe_name(pipe), port_name(port));
a4a5d2f8
VS		 2722
2723 /* make sure vdd is off before we steal it */
83b84597 2724 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2725 }
2726}
2727
2728static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2729{
2730 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2731 struct intel_encoder *encoder = &intel_dig_port->base;
2732 struct drm_device *dev = encoder->base.dev;
2733 struct drm_i915_private *dev_priv = dev->dev_private;
2734 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2735
2736 lockdep_assert_held(&dev_priv->pps_mutex);
2737
093e3f13
VS		 2738 if (!is_edp(intel_dp))
2739 return;
2740
a4a5d2f8
VS		 2741 if (intel_dp->pps_pipe == crtc->pipe)
2742 return;
2743
2744 /*
2745 * If another power sequencer was being used on this
2746 * port previously make sure to turn off vdd there while
2747 * we still have control of it.
2748 */
2749 if (intel_dp->pps_pipe != INVALID_PIPE)
83b84597 2750 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2751
2752 /*
2753 * We may be stealing the power
2754 * sequencer from another port.
2755 */
2756 vlv_steal_power_sequencer(dev, crtc->pipe);
2757
2758 /* now it's all ours */
2759 intel_dp->pps_pipe = crtc->pipe;
2760
2761 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2762 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2763
2764 /* init power sequencer on this pipe and port */
36b5f425
VS		 2765 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2766 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2767}
2768
ab1f90f9 2769static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2770{
2bd2ad64 2771 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2772 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2773 struct drm_device *dev = encoder->base.dev;
89b667f8 2774 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2775 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2776 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2777 int pipe = intel_crtc->pipe;
2778 u32 val;
a4fc5ed6 2779
ab1f90f9 2780 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2781
ab3c759a 2782 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2783 val = 0;
2784 if (pipe)
2785 val |= (1<<21);
2786 else
2787 val &= ~(1<<21);
2788 val |= 0x001000c4;
ab3c759a
CML		 2789 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2790 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2791 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2792
ab1f90f9
JN		 2793 mutex_unlock(&dev_priv->dpio_lock);
2794
2795 intel_enable_dp(encoder);
89b667f8
JB		 2796}
2797
ecff4f3b 2798static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2799{
2800 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2801 struct drm_device *dev = encoder->base.dev;
2802 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2803 struct intel_crtc *intel_crtc =
2804 to_intel_crtc(encoder->base.crtc);
e4607fcf 2805 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2806 int pipe = intel_crtc->pipe;
89b667f8 2807
8ac33ed3
DV		 2808 intel_dp_prepare(encoder);
2809
89b667f8 2810 /* Program Tx lane resets to default */
0980a60f 2811 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2812 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2813 DPIO_PCS_TX_LANE2_RESET |
2814 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2815 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2816 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2817 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2818 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2819 DPIO_PCS_CLK_SOFT_RESET);
2820
2821 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2822 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2823 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2824 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2825 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2826}
2827
e4a1d846
CML		 2828static void chv_pre_enable_dp(struct intel_encoder *encoder)
2829{
2830 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2831 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2832 struct drm_device *dev = encoder->base.dev;
2833 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2834 struct intel_crtc *intel_crtc =
2835 to_intel_crtc(encoder->base.crtc);
2836 enum dpio_channel ch = vlv_dport_to_channel(dport);
2837 int pipe = intel_crtc->pipe;
2838 int data, i;
949c1d43 2839 u32 val;
e4a1d846 2840
e4a1d846 2841 mutex_lock(&dev_priv->dpio_lock);
949c1d43 2842
570e2a74
VS		 2843 /* allow hardware to manage TX FIFO reset source */
2844 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2845 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2846 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2847
2848 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2849 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2850 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2851
949c1d43 2852 /* Deassert soft data lane reset*/
97fd4d5c 2853 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2854 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2855 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2856
2857 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2858 val |= CHV_PCS_REQ_SOFTRESET_EN;
2859 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2860
2861 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2862 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2863 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2864
97fd4d5c 2865 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2866 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2867 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2868
2869 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2870 for (i = 0; i < 4; i++) {
2871 /* Set the latency optimal bit */
2872 data = (i == 1) ? 0x0 : 0x6;
2873 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2874 data << DPIO_FRC_LATENCY_SHFIT);
2875
2876 /* Set the upar bit */
2877 data = (i == 1) ? 0x0 : 0x1;
2878 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2879 data << DPIO_UPAR_SHIFT);
2880 }
2881
2882 /* Data lane stagger programming */
2883 /* FIXME: Fix up value only after power analysis */
2884
2885 mutex_unlock(&dev_priv->dpio_lock);
2886
e4a1d846 2887 intel_enable_dp(encoder);
e4a1d846
CML		 2888}
2889
9197c88b
VS		 2890static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2891{
2892 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2893 struct drm_device *dev = encoder->base.dev;
2894 struct drm_i915_private *dev_priv = dev->dev_private;
2895 struct intel_crtc *intel_crtc =
2896 to_intel_crtc(encoder->base.crtc);
2897 enum dpio_channel ch = vlv_dport_to_channel(dport);
2898 enum pipe pipe = intel_crtc->pipe;
2899 u32 val;
2900
625695f8
VS		 2901 intel_dp_prepare(encoder);
2902
9197c88b
VS		 2903 mutex_lock(&dev_priv->dpio_lock);
2904
b9e5ac3c
VS		 2905 /* program left/right clock distribution */
2906 if (pipe != PIPE_B) {
2907 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2908 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2909 if (ch == DPIO_CH0)
2910 val |= CHV_BUFLEFTENA1_FORCE;
2911 if (ch == DPIO_CH1)
2912 val |= CHV_BUFRIGHTENA1_FORCE;
2913 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2914 } else {
2915 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2916 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2917 if (ch == DPIO_CH0)
2918 val |= CHV_BUFLEFTENA2_FORCE;
2919 if (ch == DPIO_CH1)
2920 val |= CHV_BUFRIGHTENA2_FORCE;
2921 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2922 }
2923
9197c88b
VS		 2924 /* program clock channel usage */
2925 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2926 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2927 if (pipe != PIPE_B)
2928 val &= ~CHV_PCS_USEDCLKCHANNEL;
2929 else
2930 val |= CHV_PCS_USEDCLKCHANNEL;
2931 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2932
2933 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2934 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2935 if (pipe != PIPE_B)
2936 val &= ~CHV_PCS_USEDCLKCHANNEL;
2937 else
2938 val |= CHV_PCS_USEDCLKCHANNEL;
2939 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2940
2941 /*
2942 * This a a bit weird since generally CL
2943 * matches the pipe, but here we need to
2944 * pick the CL based on the port.
2945 */
2946 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2947 if (pipe != PIPE_B)
2948 val &= ~CHV_CMN_USEDCLKCHANNEL;
2949 else
2950 val |= CHV_CMN_USEDCLKCHANNEL;
2951 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2952
2953 mutex_unlock(&dev_priv->dpio_lock);
2954}
2955
a4fc5ed6 2956/*
df0c237d
JB		 2957 * Native read with retry for link status and receiver capability reads for
2958 * cases where the sink may still be asleep.
9d1a1031
JN		 2959 *
2960 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2961 * supposed to retry 3 times per the spec.
a4fc5ed6 2962 */
9d1a1031
JN		 2963static ssize_t
2964intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2965 void *buffer, size_t size)
a4fc5ed6 2966{
9d1a1031
JN		 2967 ssize_t ret;
2968 int i;
61da5fab 2969
61da5fab 2970 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2971 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2972 if (ret == size)
2973 return ret;
61da5fab
JB		 2974 msleep(1);
2975 }
a4fc5ed6 2976
9d1a1031 2977 return ret;
a4fc5ed6
KP		 2978}
2979
2980/*
2981 * Fetch AUX CH registers 0x202 - 0x207 which contain
2982 * link status information
2983 */
2984static bool
93f62dad 2985intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2986{
9d1a1031
JN		 2987 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2988 DP_LANE0_1_STATUS,
2989 link_status,
2990 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2991}
2992
1100244e 2993/* These are source-specific values. */
a4fc5ed6 2994static uint8_t
1a2eb460 2995intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2996{
30add22d 2997 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2998 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2999
5a9d1f1a
DL		 3000 if (INTEL_INFO(dev)->gen >= 9)
3001 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3002 else if (IS_VALLEYVIEW(dev))
bd60018a 3003 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 3004 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 3005 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 3006 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 3007 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 3008 else
bd60018a 3009 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 3010}
3011
3012static uint8_t
3013intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3014{
30add22d 3015 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 3016 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 3017
5a9d1f1a
DL		 3018 if (INTEL_INFO(dev)->gen >= 9) {
3019 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3020 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3021 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3022 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3023 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3024 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3025 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3026 default:
3027 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3028 }
3029 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 3030 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3031 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3032 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3033 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3034 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3035 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3036 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3037 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 3038 default:
bd60018a 3039 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 3040 }
e2fa6fba
P		 3041 } else if (IS_VALLEYVIEW(dev)) {
3042 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3043 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3044 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3045 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3046 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3047 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3048 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3049 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 3050 default:
bd60018a 3051 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 3052 }
bc7d38a4 3053 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 3054 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3055 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3056 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3057 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3058 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3059 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 3060 default:
bd60018a 3061 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 3062 }
3063 } else {
3064 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3065 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3066 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3067 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3068 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3069 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3070 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3071 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 3072 default:
bd60018a 3073 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 3074 }
a4fc5ed6
KP		 3075 }
3076}
3077
e2fa6fba
P		 3078static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
3079{
3080 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3081 struct drm_i915_private *dev_priv = dev->dev_private;
3082 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 3083 struct intel_crtc *intel_crtc =
3084 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 3085 unsigned long demph_reg_value, preemph_reg_value,
3086 uniqtranscale_reg_value;
3087 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 3088 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 3089 int pipe = intel_crtc->pipe;
e2fa6fba
P		 3090
3091 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3092 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 3093 preemph_reg_value = 0x0004000;
3094 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3095 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3096 demph_reg_value = 0x2B405555;
3097 uniqtranscale_reg_value = 0x552AB83A;
3098 break;
bd60018a 3099 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3100 demph_reg_value = 0x2B404040;
3101 uniqtranscale_reg_value = 0x5548B83A;
3102 break;
bd60018a 3103 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3104 demph_reg_value = 0x2B245555;
3105 uniqtranscale_reg_value = 0x5560B83A;
3106 break;
bd60018a 3107 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 3108 demph_reg_value = 0x2B405555;
3109 uniqtranscale_reg_value = 0x5598DA3A;
3110 break;
3111 default:
3112 return 0;
3113 }
3114 break;
bd60018a 3115 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 3116 preemph_reg_value = 0x0002000;
3117 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3118 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3119 demph_reg_value = 0x2B404040;
3120 uniqtranscale_reg_value = 0x5552B83A;
3121 break;
bd60018a 3122 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3123 demph_reg_value = 0x2B404848;
3124 uniqtranscale_reg_value = 0x5580B83A;
3125 break;
bd60018a 3126 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3127 demph_reg_value = 0x2B404040;
3128 uniqtranscale_reg_value = 0x55ADDA3A;
3129 break;
3130 default:
3131 return 0;
3132 }
3133 break;
bd60018a 3134 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 3135 preemph_reg_value = 0x0000000;
3136 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3137 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3138 demph_reg_value = 0x2B305555;
3139 uniqtranscale_reg_value = 0x5570B83A;
3140 break;
bd60018a 3141 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3142 demph_reg_value = 0x2B2B4040;
3143 uniqtranscale_reg_value = 0x55ADDA3A;
3144 break;
3145 default:
3146 return 0;
3147 }
3148 break;
bd60018a 3149 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3150 preemph_reg_value = 0x0006000;
3151 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3152 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3153 demph_reg_value = 0x1B405555;
3154 uniqtranscale_reg_value = 0x55ADDA3A;
3155 break;
3156 default:
3157 return 0;
3158 }
3159 break;
3160 default:
3161 return 0;
3162 }
3163
0980a60f 3164 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 3165 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3166 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3167 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 3168 uniqtranscale_reg_value);
ab3c759a
CML		 3169 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3170 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3171 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3172 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 3173 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 3174
3175 return 0;
3176}
3177
e4a1d846
CML		 3178static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
3179{
3180 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3181 struct drm_i915_private *dev_priv = dev->dev_private;
3182 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3183 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 3184 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 3185 uint8_t train_set = intel_dp->train_set[0];
3186 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 3187 enum pipe pipe = intel_crtc->pipe;
3188 int i;
e4a1d846
CML		 3189
3190 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3191 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3192 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3193 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3194 deemph_reg_value = 128;
3195 margin_reg_value = 52;
3196 break;
bd60018a 3197 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3198 deemph_reg_value = 128;
3199 margin_reg_value = 77;
3200 break;
bd60018a 3201 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3202 deemph_reg_value = 128;
3203 margin_reg_value = 102;
3204 break;
bd60018a 3205 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3206 deemph_reg_value = 128;
3207 margin_reg_value = 154;
3208 /* FIXME extra to set for 1200 */
3209 break;
3210 default:
3211 return 0;
3212 }
3213 break;
bd60018a 3214 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3215 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3216 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3217 deemph_reg_value = 85;
3218 margin_reg_value = 78;
3219 break;
bd60018a 3220 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3221 deemph_reg_value = 85;
3222 margin_reg_value = 116;
3223 break;
bd60018a 3224 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3225 deemph_reg_value = 85;
3226 margin_reg_value = 154;
3227 break;
3228 default:
3229 return 0;
3230 }
3231 break;
bd60018a 3232 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3233 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3234 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3235 deemph_reg_value = 64;
3236 margin_reg_value = 104;
3237 break;
bd60018a 3238 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3239 deemph_reg_value = 64;
3240 margin_reg_value = 154;
3241 break;
3242 default:
3243 return 0;
3244 }
3245 break;
bd60018a 3246 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3247 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3248 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3249 deemph_reg_value = 43;
3250 margin_reg_value = 154;
3251 break;
3252 default:
3253 return 0;
3254 }
3255 break;
3256 default:
3257 return 0;
3258 }
3259
3260 mutex_lock(&dev_priv->dpio_lock);
3261
3262 /* Clear calc init */
1966e59e
VS		 3263 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3264 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3265 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3266 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e
VS		 3267 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3268
3269 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3270 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3271 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3272 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e 3273 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846 3274
a02ef3c7
VS		 3275 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3276 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3277 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3278 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3279
3280 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3281 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3282 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3283 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3284
e4a1d846 3285 /* Program swing deemph */
f72df8db
VS		 3286 for (i = 0; i < 4; i++) {
3287 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3288 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3289 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3290 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3291 }
e4a1d846
CML		 3292
3293 /* Program swing margin */
f72df8db
VS		 3294 for (i = 0; i < 4; i++) {
3295 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 3296 val &= ~DPIO_SWING_MARGIN000_MASK;
3297 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 3298 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3299 }
e4a1d846
CML		 3300
3301 /* Disable unique transition scale */
f72df8db
VS		 3302 for (i = 0; i < 4; i++) {
3303 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3304 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3305 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3306 }
e4a1d846
CML		 3307
3308 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 3309 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 3310 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 3311 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 3312
3313 /*
3314 * The document said it needs to set bit 27 for ch0 and bit 26
3315 * for ch1. Might be a typo in the doc.
3316 * For now, for this unique transition scale selection, set bit
3317 * 27 for ch0 and ch1.
3318 */
f72df8db
VS		 3319 for (i = 0; i < 4; i++) {
3320 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3321 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3322 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3323 }
e4a1d846 3324
f72df8db
VS		 3325 for (i = 0; i < 4; i++) {
3326 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3327 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3328 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3329 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3330 }
e4a1d846
CML		 3331 }
3332
3333 /* Start swing calculation */
1966e59e
VS		 3334 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3335 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3336 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3337
3338 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3339 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3340 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3341
3342 /* LRC Bypass */
3343 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3344 val |= DPIO_LRC_BYPASS;
3345 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3346
3347 mutex_unlock(&dev_priv->dpio_lock);
3348
3349 return 0;
3350}
3351
a4fc5ed6 3352static void
0301b3ac
JN		 3353intel_get_adjust_train(struct intel_dp *intel_dp,
3354 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 3355{
3356 uint8_t v = 0;
3357 uint8_t p = 0;
3358 int lane;
1a2eb460
KP		 3359 uint8_t voltage_max;
3360 uint8_t preemph_max;
a4fc5ed6 3361
33a34e4e 3362 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 3363 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3364 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 3365
3366 if (this_v > v)
3367 v = this_v;
3368 if (this_p > p)
3369 p = this_p;
3370 }
3371
1a2eb460 3372 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 3373 if (v >= voltage_max)
3374 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 3375
1a2eb460
KP		 3376 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3377 if (p >= preemph_max)
3378 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 3379
3380 for (lane = 0; lane < 4; lane++)
33a34e4e 3381 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 3382}
3383
3384static uint32_t
f0a3424e 3385intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3386{
3cf2efb1 3387 uint32_t signal_levels = 0;
a4fc5ed6 3388
3cf2efb1 3389 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3390 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3391 default:
3392 signal_levels |= DP_VOLTAGE_0_4;
3393 break;
bd60018a 3394 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3395 signal_levels |= DP_VOLTAGE_0_6;
3396 break;
bd60018a 3397 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3398 signal_levels |= DP_VOLTAGE_0_8;
3399 break;
bd60018a 3400 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3401 signal_levels |= DP_VOLTAGE_1_2;
3402 break;
3403 }
3cf2efb1 3404 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3405 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3406 default:
3407 signal_levels |= DP_PRE_EMPHASIS_0;
3408 break;
bd60018a 3409 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3410 signal_levels |= DP_PRE_EMPHASIS_3_5;
3411 break;
bd60018a 3412 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3413 signal_levels |= DP_PRE_EMPHASIS_6;
3414 break;
bd60018a 3415 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3416 signal_levels |= DP_PRE_EMPHASIS_9_5;
3417 break;
3418 }
3419 return signal_levels;
3420}
3421
e3421a18
ZW		 3422/* Gen6's DP voltage swing and pre-emphasis control */
3423static uint32_t
3424intel_gen6_edp_signal_levels(uint8_t train_set)
3425{
3c5a62b5
YL		 3426 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3427 DP_TRAIN_PRE_EMPHASIS_MASK);
3428 switch (signal_levels) {
bd60018a
SJ		 3429 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3430 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3431 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3432 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3433 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3434 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3435 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3436 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3437 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3438 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3439 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3440 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3441 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3442 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3443 default:
3c5a62b5
YL		 3444 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3445 "0x%x\n", signal_levels);
3446 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3447 }
3448}
3449
1a2eb460
KP		 3450/* Gen7's DP voltage swing and pre-emphasis control */
3451static uint32_t
3452intel_gen7_edp_signal_levels(uint8_t train_set)
3453{
3454 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3455 DP_TRAIN_PRE_EMPHASIS_MASK);
3456 switch (signal_levels) {
bd60018a 3457 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3458 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3459 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3460 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3461 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3462 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3463
bd60018a 3464 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3465 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3466 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3467 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3468
bd60018a 3469 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3470 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3471 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3472 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3473
3474 default:
3475 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3476 "0x%x\n", signal_levels);
3477 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3478 }
3479}
3480
d6c0d722
PZ		 3481/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3482static uint32_t
f0a3424e 3483intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 3484{
d6c0d722
PZ		 3485 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3486 DP_TRAIN_PRE_EMPHASIS_MASK);
3487 switch (signal_levels) {
bd60018a 3488 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3489 return DDI_BUF_TRANS_SELECT(0);
bd60018a 3490 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3491 return DDI_BUF_TRANS_SELECT(1);
bd60018a 3492 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3493 return DDI_BUF_TRANS_SELECT(2);
bd60018a 3494 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
c5fe6a06 3495 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 3496
bd60018a 3497 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3498 return DDI_BUF_TRANS_SELECT(4);
bd60018a 3499 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3500 return DDI_BUF_TRANS_SELECT(5);
bd60018a 3501 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3502 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 3503
bd60018a 3504 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3505 return DDI_BUF_TRANS_SELECT(7);
bd60018a 3506 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3507 return DDI_BUF_TRANS_SELECT(8);
d6c0d722
PZ		 3508 default:
3509 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3510 "0x%x\n", signal_levels);
c5fe6a06 3511 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 3512 }
a4fc5ed6
KP		 3513}
3514
f0a3424e
PZ		 3515/* Properly updates "DP" with the correct signal levels. */
3516static void
3517intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3518{
3519 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3520 enum port port = intel_dig_port->port;
f0a3424e
PZ		 3521 struct drm_device *dev = intel_dig_port->base.base.dev;
3522 uint32_t signal_levels, mask;
3523 uint8_t train_set = intel_dp->train_set[0];
3524
5a9d1f1a 3525 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
f0a3424e
PZ		 3526 signal_levels = intel_hsw_signal_levels(train_set);
3527 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 3528 } else if (IS_CHERRYVIEW(dev)) {
3529 signal_levels = intel_chv_signal_levels(intel_dp);
3530 mask = 0;
e2fa6fba
P		 3531 } else if (IS_VALLEYVIEW(dev)) {
3532 signal_levels = intel_vlv_signal_levels(intel_dp);
3533 mask = 0;
bc7d38a4 3534 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 3535 signal_levels = intel_gen7_edp_signal_levels(train_set);
3536 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3537 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 3538 signal_levels = intel_gen6_edp_signal_levels(train_set);
3539 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3540 } else {
3541 signal_levels = intel_gen4_signal_levels(train_set);
3542 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3543 }
3544
3545 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3546
3547 *DP = (*DP & ~mask) | signal_levels;
3548}
3549
a4fc5ed6 3550static bool
ea5b213a 3551intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3552 uint32_t *DP,
58e10eb9 3553 uint8_t dp_train_pat)
a4fc5ed6 3554{
174edf1f
PZ		 3555 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3556 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3557 struct drm_i915_private *dev_priv = dev->dev_private;
2cdfe6c8
JN		 3558 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3559 int ret, len;
a4fc5ed6 3560
7b13b58a 3561 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
47ea7542 3562
70aff66c 3563 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3564 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3565
2cdfe6c8
JN		 3566 buf[0] = dp_train_pat;
3567 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3568 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3569 /* don't write DP_TRAINING_LANEx_SET on disable */
3570 len = 1;
3571 } else {
3572 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3573 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3574 len = intel_dp->lane_count + 1;
47ea7542 3575 }
a4fc5ed6 3576
9d1a1031
JN		 3577 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3578 buf, len);
2cdfe6c8
JN		 3579
3580 return ret == len;
a4fc5ed6
KP		 3581}
3582
70aff66c
JN		 3583static bool
3584intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3585 uint8_t dp_train_pat)
3586{
953d22e8 3587 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3588 intel_dp_set_signal_levels(intel_dp, DP);
3589 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3590}
3591
3592static bool
3593intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3594 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3595{
3596 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3597 struct drm_device *dev = intel_dig_port->base.base.dev;
3598 struct drm_i915_private *dev_priv = dev->dev_private;
3599 int ret;
3600
3601 intel_get_adjust_train(intel_dp, link_status);
3602 intel_dp_set_signal_levels(intel_dp, DP);
3603
3604 I915_WRITE(intel_dp->output_reg, *DP);
3605 POSTING_READ(intel_dp->output_reg);
3606
9d1a1031
JN		 3607 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3608 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3609
3610 return ret == intel_dp->lane_count;
3611}
3612
3ab9c637
ID		 3613static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3614{
3615 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3616 struct drm_device *dev = intel_dig_port->base.base.dev;
3617 struct drm_i915_private *dev_priv = dev->dev_private;
3618 enum port port = intel_dig_port->port;
3619 uint32_t val;
3620
3621 if (!HAS_DDI(dev))
3622 return;
3623
3624 val = I915_READ(DP_TP_CTL(port));
3625 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3626 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3627 I915_WRITE(DP_TP_CTL(port), val);
3628
3629 /*
3630 * On PORT_A we can have only eDP in SST mode. There the only reason
3631 * we need to set idle transmission mode is to work around a HW issue
3632 * where we enable the pipe while not in idle link-training mode.
3633 * In this case there is requirement to wait for a minimum number of
3634 * idle patterns to be sent.
3635 */
3636 if (port == PORT_A)
3637 return;
3638
3639 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3640 1))
3641 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3642}
3643
33a34e4e 3644/* Enable corresponding port and start training pattern 1 */
c19b0669 3645void
33a34e4e 3646intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3647{
da63a9f2 3648 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3649 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3650 int i;
3651 uint8_t voltage;
cdb0e95b 3652 int voltage_tries, loop_tries;
ea5b213a 3653 uint32_t DP = intel_dp->DP;
6aba5b6c 3654 uint8_t link_config[2];
a4fc5ed6 3655
affa9354 3656 if (HAS_DDI(dev))
c19b0669
PZ		 3657 intel_ddi_prepare_link_retrain(encoder);
3658
3cf2efb1 3659 /* Write the link configuration data */
6aba5b6c
JN		 3660 link_config[0] = intel_dp->link_bw;
3661 link_config[1] = intel_dp->lane_count;
3662 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3663 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3664 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3665
3666 link_config[0] = 0;
3667 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3668 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3669
3670 DP |= DP_PORT_EN;
1a2eb460 3671
70aff66c
JN		 3672 /* clock recovery */
3673 if (!intel_dp_reset_link_train(intel_dp, &DP,
3674 DP_TRAINING_PATTERN_1 |
3675 DP_LINK_SCRAMBLING_DISABLE)) {
3676 DRM_ERROR("failed to enable link training\n");
3677 return;
3678 }
3679
a4fc5ed6 3680 voltage = 0xff;
cdb0e95b
KP		 3681 voltage_tries = 0;
3682 loop_tries = 0;
a4fc5ed6 3683 for (;;) {
70aff66c 3684 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3685
a7c9655f 3686 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3687 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3688 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3689 break;
93f62dad 3690 }
a4fc5ed6 3691
01916270 3692 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3693 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3694 break;
3695 }
3696
3697 /* Check to see if we've tried the max voltage */
3698 for (i = 0; i < intel_dp->lane_count; i++)
3699 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3700 break;
3b4f819d 3701 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3702 ++loop_tries;
3703 if (loop_tries == 5) {
3def84b3 3704 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3705 break;
3706 }
70aff66c
JN		 3707 intel_dp_reset_link_train(intel_dp, &DP,
3708 DP_TRAINING_PATTERN_1 |
3709 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3710 voltage_tries = 0;
3711 continue;
3712 }
a4fc5ed6 3713
3cf2efb1 3714 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3715 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3716 ++voltage_tries;
b06fbda3 3717 if (voltage_tries == 5) {
3def84b3 3718 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3719 break;
3720 }
3721 } else
3722 voltage_tries = 0;
3723 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3724
70aff66c
JN		 3725 /* Update training set as requested by target */
3726 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3727 DRM_ERROR("failed to update link training\n");
3728 break;
3729 }
a4fc5ed6
KP		 3730 }
3731
33a34e4e
JB		 3732 intel_dp->DP = DP;
3733}
3734
c19b0669 3735void
33a34e4e
JB		 3736intel_dp_complete_link_train(struct intel_dp *intel_dp)
3737{
33a34e4e 3738 bool channel_eq = false;
37f80975 3739 int tries, cr_tries;
33a34e4e 3740 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3741 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3742
3743 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3744 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3745 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3746
a4fc5ed6 3747 /* channel equalization */
70aff66c 3748 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3749 training_pattern |
70aff66c
JN		 3750 DP_LINK_SCRAMBLING_DISABLE)) {
3751 DRM_ERROR("failed to start channel equalization\n");
3752 return;
3753 }
3754
a4fc5ed6 3755 tries = 0;
37f80975 3756 cr_tries = 0;
a4fc5ed6
KP		 3757 channel_eq = false;
3758 for (;;) {
70aff66c 3759 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3760
37f80975
JB		 3761 if (cr_tries > 5) {
3762 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3763 break;
3764 }
3765
a7c9655f 3766 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3767 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3768 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3769 break;
70aff66c 3770 }
a4fc5ed6 3771
37f80975 3772 /* Make sure clock is still ok */
01916270 3773 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3774 intel_dp_start_link_train(intel_dp);
70aff66c 3775 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3776 training_pattern |
70aff66c 3777 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3778 cr_tries++;
3779 continue;
3780 }
3781
1ffdff13 3782 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3783 channel_eq = true;
3784 break;
3785 }
a4fc5ed6 3786
37f80975
JB		 3787 /* Try 5 times, then try clock recovery if that fails */
3788 if (tries > 5) {
3789 intel_dp_link_down(intel_dp);
3790 intel_dp_start_link_train(intel_dp);
70aff66c 3791 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3792 training_pattern |
70aff66c 3793 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3794 tries = 0;
3795 cr_tries++;
3796 continue;
3797 }
a4fc5ed6 3798
70aff66c
JN		 3799 /* Update training set as requested by target */
3800 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3801 DRM_ERROR("failed to update link training\n");
3802 break;
3803 }
3cf2efb1 3804 ++tries;
869184a6 3805 }
3cf2efb1 3806
3ab9c637
ID		 3807 intel_dp_set_idle_link_train(intel_dp);
3808
3809 intel_dp->DP = DP;
3810
d6c0d722 3811 if (channel_eq)
07f42258 3812 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3813
3ab9c637
ID		 3814}
3815
3816void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3817{
70aff66c 3818 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3819 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3820}
3821
3822static void
ea5b213a 3823intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3824{
da63a9f2 3825 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3826 enum port port = intel_dig_port->port;
da63a9f2 3827 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3828 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3829 struct intel_crtc *intel_crtc =
3830 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3831 uint32_t DP = intel_dp->DP;
a4fc5ed6 3832
bc76e320 3833 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3834 return;
3835
0c33d8d7 3836 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3837 return;
3838
28c97730 3839 DRM_DEBUG_KMS("\n");
32f9d658 3840
bc7d38a4 3841 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3842 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3843 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3844 } else {
aad3d14d
VS		 3845 if (IS_CHERRYVIEW(dev))
3846 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3847 else
3848 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3849 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3850 }
fe255d00 3851 POSTING_READ(intel_dp->output_reg);
5eb08b69 3852
493a7081 3853 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3854 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3855 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3856
5bddd17f
EA		 3857 /* Hardware workaround: leaving our transcoder select
3858 * set to transcoder B while it's off will prevent the
3859 * corresponding HDMI output on transcoder A.
3860 *
3861 * Combine this with another hardware workaround:
3862 * transcoder select bit can only be cleared while the
3863 * port is enabled.
3864 */
3865 DP &= ~DP_PIPEB_SELECT;
3866 I915_WRITE(intel_dp->output_reg, DP);
3867
3868 /* Changes to enable or select take place the vblank
3869 * after being written.
3870 */
ff50afe9
DV		 3871 if (WARN_ON(crtc == NULL)) {
3872 /* We should never try to disable a port without a crtc
3873 * attached. For paranoia keep the code around for a
3874 * bit. */
31acbcc4
CW		 3875 POSTING_READ(intel_dp->output_reg);
3876 msleep(50);
3877 } else
ab527efc 3878 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3879 }
3880
832afda6 3881 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3882 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3883 POSTING_READ(intel_dp->output_reg);
f01eca2e 3884 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3885}
3886
26d61aad
KP		 3887static bool
3888intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3889{
a031d709
RV		 3890 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3891 struct drm_device *dev = dig_port->base.base.dev;
3892 struct drm_i915_private *dev_priv = dev->dev_private;
3893
9d1a1031
JN		 3894 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3895 sizeof(intel_dp->dpcd)) < 0)
edb39244 3896 return false; /* aux transfer failed */
92fd8fd1 3897
a8e98153 3898 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3899
edb39244
AJ		 3900 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3901 return false; /* DPCD not present */
3902
2293bb5c
SK		 3903 /* Check if the panel supports PSR */
3904 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3905 if (is_edp(intel_dp)) {
9d1a1031
JN		 3906 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3907 intel_dp->psr_dpcd,
3908 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3909 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3910 dev_priv->psr.sink_support = true;
50003939 3911 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3912 }
50003939
JN		 3913 }
3914
06ea66b6
TP		 3915 /* Training Pattern 3 support */
3916 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3917 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3918 intel_dp->use_tps3 = true;
f8d8a672 3919 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
06ea66b6
TP		 3920 } else
3921 intel_dp->use_tps3 = false;
3922
edb39244
AJ		 3923 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3924 DP_DWN_STRM_PORT_PRESENT))
3925 return true; /* native DP sink */
3926
3927 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3928 return true; /* no per-port downstream info */
3929
9d1a1031
JN		 3930 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3931 intel_dp->downstream_ports,
3932 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3933 return false; /* downstream port status fetch failed */
3934
3935 return true;
92fd8fd1
KP		 3936}
3937
0d198328
AJ		 3938static void
3939intel_dp_probe_oui(struct intel_dp *intel_dp)
3940{
3941 u8 buf[3];
3942
3943 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3944 return;
3945
9d1a1031 3946 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3947 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3948 buf[0], buf[1], buf[2]);
3949
9d1a1031 3950 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3951 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3952 buf[0], buf[1], buf[2]);
3953}
3954
0e32b39c
DA		 3955static bool
3956intel_dp_probe_mst(struct intel_dp *intel_dp)
3957{
3958 u8 buf[1];
3959
3960 if (!intel_dp->can_mst)
3961 return false;
3962
3963 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3964 return false;
3965
0e32b39c
DA		 3966 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3967 if (buf[0] & DP_MST_CAP) {
3968 DRM_DEBUG_KMS("Sink is MST capable\n");
3969 intel_dp->is_mst = true;
3970 } else {
3971 DRM_DEBUG_KMS("Sink is not MST capable\n");
3972 intel_dp->is_mst = false;
3973 }
3974 }
0e32b39c
DA		 3975
3976 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3977 return intel_dp->is_mst;
3978}
3979
d2e216d0
RV		 3980int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3981{
3982 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3983 struct drm_device *dev = intel_dig_port->base.base.dev;
3984 struct intel_crtc *intel_crtc =
3985 to_intel_crtc(intel_dig_port->base.base.crtc);
ad9dc91b
RV		 3986 u8 buf;
3987 int test_crc_count;
3988 int attempts = 6;
d2e216d0 3989
ad9dc91b 3990 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3991 return -EIO;
d2e216d0 3992
ad9dc91b 3993 if (!(buf & DP_TEST_CRC_SUPPORTED))
d2e216d0
RV		 3994 return -ENOTTY;
3995
1dda5f93
RV		 3996 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3997 return -EIO;
3998
9d1a1031 3999 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
ce31d9f4 4000 buf | DP_TEST_SINK_START) < 0)
bda0381e 4001 return -EIO;
d2e216d0 4002
1dda5f93 4003 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 4004 return -EIO;
ad9dc91b 4005 test_crc_count = buf & DP_TEST_COUNT_MASK;
d2e216d0 4006
ad9dc91b 4007 do {
1dda5f93
RV		 4008 if (drm_dp_dpcd_readb(&intel_dp->aux,
4009 DP_TEST_SINK_MISC, &buf) < 0)
4010 return -EIO;
ad9dc91b
RV		 4011 intel_wait_for_vblank(dev, intel_crtc->pipe);
4012 } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
4013
4014 if (attempts == 0) {
4015 DRM_ERROR("Panel is unable to calculate CRC after 6 vblanks\n");
4016 return -EIO;
4017 }
d2e216d0 4018
9d1a1031 4019 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
bda0381e 4020 return -EIO;
d2e216d0 4021
1dda5f93
RV		 4022 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
4023 return -EIO;
4024 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
4025 buf & ~DP_TEST_SINK_START) < 0)
4026 return -EIO;
ce31d9f4 4027
d2e216d0
RV		 4028 return 0;
4029}
4030
a60f0e38
JB		 4031static bool
4032intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4033{
9d1a1031
JN		 4034 return intel_dp_dpcd_read_wake(&intel_dp->aux,
4035 DP_DEVICE_SERVICE_IRQ_VECTOR,
4036 sink_irq_vector, 1) == 1;
a60f0e38
JB		 4037}
4038
0e32b39c
DA		 4039static bool
4040intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4041{
4042 int ret;
4043
4044 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
4045 DP_SINK_COUNT_ESI,
4046 sink_irq_vector, 14);
4047 if (ret != 14)
4048 return false;
4049
4050 return true;
4051}
4052
a60f0e38
JB		 4053static void
4054intel_dp_handle_test_request(struct intel_dp *intel_dp)
4055{
4056 /* NAK by default */
9d1a1031 4057 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 4058}
4059
0e32b39c
DA		 4060static int
4061intel_dp_check_mst_status(struct intel_dp *intel_dp)
4062{
4063 bool bret;
4064
4065 if (intel_dp->is_mst) {
4066 u8 esi[16] = { 0 };
4067 int ret = 0;
4068 int retry;
4069 bool handled;
4070 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4071go_again:
4072 if (bret == true) {
4073
4074 /* check link status - esi[10] = 0x200c */
4075 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4076 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4077 intel_dp_start_link_train(intel_dp);
4078 intel_dp_complete_link_train(intel_dp);
4079 intel_dp_stop_link_train(intel_dp);
4080 }
4081
4082 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4083 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4084
4085 if (handled) {
4086 for (retry = 0; retry < 3; retry++) {
4087 int wret;
4088 wret = drm_dp_dpcd_write(&intel_dp->aux,
4089 DP_SINK_COUNT_ESI+1,
4090 &esi[1], 3);
4091 if (wret == 3) {
4092 break;
4093 }
4094 }
4095
4096 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4097 if (bret == true) {
4098 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4099 goto go_again;
4100 }
4101 } else
4102 ret = 0;
4103
4104 return ret;
4105 } else {
4106 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4107 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4108 intel_dp->is_mst = false;
4109 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4110 /* send a hotplug event */
4111 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4112 }
4113 }
4114 return -EINVAL;
4115}
4116
a4fc5ed6
KP		 4117/*
4118 * According to DP spec
4119 * 5.1.2:
4120 * 1. Read DPCD
4121 * 2. Configure link according to Receiver Capabilities
4122 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4123 * 4. Check link status on receipt of hot-plug interrupt
4124 */
00c09d70 4125void
ea5b213a 4126intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 4127{
5b215bcf 4128 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 4129 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 4130 u8 sink_irq_vector;
93f62dad 4131 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 4132
5b215bcf
DA		 4133 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4134
da63a9f2 4135 if (!intel_encoder->connectors_active)
d2b996ac 4136 return;
59cd09e1 4137
da63a9f2 4138 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 4139 return;
4140
1a125d8a
ID		 4141 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4142 return;
4143
92fd8fd1 4144 /* Try to read receiver status if the link appears to be up */
93f62dad 4145 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 4146 return;
4147 }
4148
92fd8fd1 4149 /* Now read the DPCD to see if it's actually running */
26d61aad 4150 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 4151 return;
4152 }
4153
a60f0e38
JB		 4154 /* Try to read the source of the interrupt */
4155 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4156 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4157 /* Clear interrupt source */
9d1a1031
JN		 4158 drm_dp_dpcd_writeb(&intel_dp->aux,
4159 DP_DEVICE_SERVICE_IRQ_VECTOR,
4160 sink_irq_vector);
a60f0e38
JB		 4161
4162 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4163 intel_dp_handle_test_request(intel_dp);
4164 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4165 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4166 }
4167
1ffdff13 4168 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 4169 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 4170 intel_encoder->base.name);
33a34e4e
JB		 4171 intel_dp_start_link_train(intel_dp);
4172 intel_dp_complete_link_train(intel_dp);
3ab9c637 4173 intel_dp_stop_link_train(intel_dp);
33a34e4e 4174 }
a4fc5ed6 4175}
a4fc5ed6 4176
caf9ab24 4177/* XXX this is probably wrong for multiple downstream ports */
71ba9000 4178static enum drm_connector_status
26d61aad 4179intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 4180{
caf9ab24 4181 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 4182 uint8_t type;
4183
4184 if (!intel_dp_get_dpcd(intel_dp))
4185 return connector_status_disconnected;
4186
4187 /* if there's no downstream port, we're done */
4188 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 4189 return connector_status_connected;
caf9ab24
AJ		 4190
4191 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 4192 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4193 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 4194 uint8_t reg;
9d1a1031
JN		 4195
4196 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4197 &reg, 1) < 0)
caf9ab24 4198 return connector_status_unknown;
9d1a1031 4199
23235177
AJ		 4200 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4201 : connector_status_disconnected;
caf9ab24
AJ		 4202 }
4203
4204 /* If no HPD, poke DDC gently */
0b99836f 4205 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4206 return connector_status_connected;
caf9ab24
AJ		 4207
4208 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4209 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4210 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4211 if (type == DP_DS_PORT_TYPE_VGA ||
4212 type == DP_DS_PORT_TYPE_NON_EDID)
4213 return connector_status_unknown;
4214 } else {
4215 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4216 DP_DWN_STRM_PORT_TYPE_MASK;
4217 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4218 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4219 return connector_status_unknown;
4220 }
caf9ab24
AJ		 4221
4222 /* Anything else is out of spec, warn and ignore */
4223 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4224 return connector_status_disconnected;
71ba9000
AJ		 4225}
4226
d410b56d
CW		 4227static enum drm_connector_status
4228edp_detect(struct intel_dp *intel_dp)
4229{
4230 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4231 enum drm_connector_status status;
4232
4233 status = intel_panel_detect(dev);
4234 if (status == connector_status_unknown)
4235 status = connector_status_connected;
4236
4237 return status;
4238}
4239
5eb08b69 4240static enum drm_connector_status
a9756bb5 4241ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 4242{
30add22d 4243 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 4244 struct drm_i915_private *dev_priv = dev->dev_private;
4245 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 4246
1b469639
DL		 4247 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4248 return connector_status_disconnected;
4249
26d61aad 4250 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 4251}
4252
2a592bec
DA		 4253static int g4x_digital_port_connected(struct drm_device *dev,
4254 struct intel_digital_port *intel_dig_port)
a4fc5ed6 4255{
a4fc5ed6 4256 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 4257 uint32_t bit;
5eb08b69 4258
232a6ee9
TP		 4259 if (IS_VALLEYVIEW(dev)) {
4260 switch (intel_dig_port->port) {
4261 case PORT_B:
4262 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4263 break;
4264 case PORT_C:
4265 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4266 break;
4267 case PORT_D:
4268 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4269 break;
4270 default:
2a592bec 4271 return -EINVAL;
232a6ee9
TP		 4272 }
4273 } else {
4274 switch (intel_dig_port->port) {
4275 case PORT_B:
4276 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4277 break;
4278 case PORT_C:
4279 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4280 break;
4281 case PORT_D:
4282 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4283 break;
4284 default:
2a592bec 4285 return -EINVAL;
232a6ee9 4286 }
a4fc5ed6
KP		 4287 }
4288
10f76a38 4289 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2a592bec
DA		 4290 return 0;
4291 return 1;
4292}
4293
4294static enum drm_connector_status
4295g4x_dp_detect(struct intel_dp *intel_dp)
4296{
4297 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4298 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4299 int ret;
4300
4301 /* Can't disconnect eDP, but you can close the lid... */
4302 if (is_edp(intel_dp)) {
4303 enum drm_connector_status status;
4304
4305 status = intel_panel_detect(dev);
4306 if (status == connector_status_unknown)
4307 status = connector_status_connected;
4308 return status;
4309 }
4310
4311 ret = g4x_digital_port_connected(dev, intel_dig_port);
4312 if (ret == -EINVAL)
4313 return connector_status_unknown;
4314 else if (ret == 0)
a4fc5ed6
KP		 4315 return connector_status_disconnected;
4316
26d61aad 4317 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4318}
4319
8c241fef 4320static struct edid *
beb60608 4321intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4322{
beb60608 4323 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4324
9cd300e0
JN		 4325 /* use cached edid if we have one */
4326 if (intel_connector->edid) {
9cd300e0
JN		 4327 /* invalid edid */
4328 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4329 return NULL;
4330
55e9edeb 4331 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4332 } else
4333 return drm_get_edid(&intel_connector->base,
4334 &intel_dp->aux.ddc);
4335}
8c241fef 4336
beb60608
CW		 4337static void
4338intel_dp_set_edid(struct intel_dp *intel_dp)
4339{
4340 struct intel_connector *intel_connector = intel_dp->attached_connector;
4341 struct edid *edid;
8c241fef 4342
beb60608
CW		 4343 edid = intel_dp_get_edid(intel_dp);
4344 intel_connector->detect_edid = edid;
4345
4346 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4347 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4348 else
4349 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4350}
4351
beb60608
CW		 4352static void
4353intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4354{
beb60608 4355 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4356
beb60608
CW		 4357 kfree(intel_connector->detect_edid);
4358 intel_connector->detect_edid = NULL;
9cd300e0 4359
beb60608
CW		 4360 intel_dp->has_audio = false;
4361}
d6f24d0f 4362
beb60608
CW		 4363static enum intel_display_power_domain
4364intel_dp_power_get(struct intel_dp *dp)
4365{
4366 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4367 enum intel_display_power_domain power_domain;
4368
4369 power_domain = intel_display_port_power_domain(encoder);
4370 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4371
4372 return power_domain;
4373}
d6f24d0f 4374
beb60608
CW		 4375static void
4376intel_dp_power_put(struct intel_dp *dp,
4377 enum intel_display_power_domain power_domain)
4378{
4379 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4380 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4381}
4382
a9756bb5
ZW		 4383static enum drm_connector_status
4384intel_dp_detect(struct drm_connector *connector, bool force)
4385{
4386 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4387 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4388 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4389 struct drm_device *dev = connector->dev;
a9756bb5 4390 enum drm_connector_status status;
671dedd2 4391 enum intel_display_power_domain power_domain;
0e32b39c 4392 bool ret;
a9756bb5 4393
164c8598 4394 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4395 connector->base.id, connector->name);
beb60608 4396 intel_dp_unset_edid(intel_dp);
164c8598 4397
0e32b39c
DA		 4398 if (intel_dp->is_mst) {
4399 /* MST devices are disconnected from a monitor POV */
4400 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4401 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4402 return connector_status_disconnected;
0e32b39c
DA		 4403 }
4404
beb60608 4405 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4406
d410b56d
CW		 4407 /* Can't disconnect eDP, but you can close the lid... */
4408 if (is_edp(intel_dp))
4409 status = edp_detect(intel_dp);
4410 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4411 status = ironlake_dp_detect(intel_dp);
4412 else
4413 status = g4x_dp_detect(intel_dp);
4414 if (status != connector_status_connected)
c8c8fb33 4415 goto out;
a9756bb5 4416
0d198328
AJ		 4417 intel_dp_probe_oui(intel_dp);
4418
0e32b39c
DA		 4419 ret = intel_dp_probe_mst(intel_dp);
4420 if (ret) {
4421 /* if we are in MST mode then this connector
4422 won't appear connected or have anything with EDID on it */
4423 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4424 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4425 status = connector_status_disconnected;
4426 goto out;
4427 }
4428
beb60608 4429 intel_dp_set_edid(intel_dp);
a9756bb5 4430
d63885da
PZ		 4431 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4432 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4433 status = connector_status_connected;
4434
4435out:
beb60608 4436 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4437 return status;
a4fc5ed6
KP		 4438}
4439
beb60608
CW		 4440static void
4441intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4442{
df0e9248 4443 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4444 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4445 enum intel_display_power_domain power_domain;
a4fc5ed6 4446
beb60608
CW		 4447 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4448 connector->base.id, connector->name);
4449 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4450
beb60608
CW		 4451 if (connector->status != connector_status_connected)
4452 return;
671dedd2 4453
beb60608
CW		 4454 power_domain = intel_dp_power_get(intel_dp);
4455
4456 intel_dp_set_edid(intel_dp);
4457
4458 intel_dp_power_put(intel_dp, power_domain);
4459
4460 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4461 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4462}
4463
4464static int intel_dp_get_modes(struct drm_connector *connector)
4465{
4466 struct intel_connector *intel_connector = to_intel_connector(connector);
4467 struct edid *edid;
4468
4469 edid = intel_connector->detect_edid;
4470 if (edid) {
4471 int ret = intel_connector_update_modes(connector, edid);
4472 if (ret)
4473 return ret;
4474 }
32f9d658 4475
f8779fda 4476 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4477 if (is_edp(intel_attached_dp(connector)) &&
4478 intel_connector->panel.fixed_mode) {
f8779fda 4479 struct drm_display_mode *mode;
beb60608
CW		 4480
4481 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4482 intel_connector->panel.fixed_mode);
f8779fda 4483 if (mode) {
32f9d658
ZW		 4484 drm_mode_probed_add(connector, mode);
4485 return 1;
4486 }
4487 }
beb60608 4488
32f9d658 4489 return 0;
a4fc5ed6
KP		 4490}
4491
1aad7ac0
CW		 4492static bool
4493intel_dp_detect_audio(struct drm_connector *connector)
4494{
1aad7ac0 4495 bool has_audio = false;
beb60608 4496 struct edid *edid;
1aad7ac0 4497
beb60608
CW		 4498 edid = to_intel_connector(connector)->detect_edid;
4499 if (edid)
1aad7ac0 4500 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4501
1aad7ac0
CW		 4502 return has_audio;
4503}
4504
f684960e
CW		 4505static int
4506intel_dp_set_property(struct drm_connector *connector,
4507 struct drm_property *property,
4508 uint64_t val)
4509{
e953fd7b 4510 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4511 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4512 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4513 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4514 int ret;
4515
662595df 4516 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4517 if (ret)
4518 return ret;
4519
3f43c48d 4520 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4521 int i = val;
4522 bool has_audio;
4523
4524 if (i == intel_dp->force_audio)
f684960e
CW		 4525 return 0;
4526
1aad7ac0 4527 intel_dp->force_audio = i;
f684960e 4528
c3e5f67b 4529 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4530 has_audio = intel_dp_detect_audio(connector);
4531 else
c3e5f67b 4532 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4533
4534 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4535 return 0;
4536
1aad7ac0 4537 intel_dp->has_audio = has_audio;
f684960e
CW		 4538 goto done;
4539 }
4540
e953fd7b 4541 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4542 bool old_auto = intel_dp->color_range_auto;
4543 uint32_t old_range = intel_dp->color_range;
4544
55bc60db
VS		 4545 switch (val) {
4546 case INTEL_BROADCAST_RGB_AUTO:
4547 intel_dp->color_range_auto = true;
4548 break;
4549 case INTEL_BROADCAST_RGB_FULL:
4550 intel_dp->color_range_auto = false;
4551 intel_dp->color_range = 0;
4552 break;
4553 case INTEL_BROADCAST_RGB_LIMITED:
4554 intel_dp->color_range_auto = false;
4555 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4556 break;
4557 default:
4558 return -EINVAL;
4559 }
ae4edb80
DV		 4560
4561 if (old_auto == intel_dp->color_range_auto &&
4562 old_range == intel_dp->color_range)
4563 return 0;
4564
e953fd7b
CW		 4565 goto done;
4566 }
4567
53b41837
YN		 4568 if (is_edp(intel_dp) &&
4569 property == connector->dev->mode_config.scaling_mode_property) {
4570 if (val == DRM_MODE_SCALE_NONE) {
4571 DRM_DEBUG_KMS("no scaling not supported\n");
4572 return -EINVAL;
4573 }
4574
4575 if (intel_connector->panel.fitting_mode == val) {
4576 /* the eDP scaling property is not changed */
4577 return 0;
4578 }
4579 intel_connector->panel.fitting_mode = val;
4580
4581 goto done;
4582 }
4583
f684960e
CW		 4584 return -EINVAL;
4585
4586done:
c0c36b94
CW		 4587 if (intel_encoder->base.crtc)
4588 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4589
4590 return 0;
4591}
4592
a4fc5ed6 4593static void
73845adf 4594intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4595{
1d508706 4596 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4597
10e972d3 4598 kfree(intel_connector->detect_edid);
beb60608 4599
9cd300e0
JN		 4600 if (!IS_ERR_OR_NULL(intel_connector->edid))
4601 kfree(intel_connector->edid);
4602
acd8db10
PZ		 4603 /* Can't call is_edp() since the encoder may have been destroyed
4604 * already. */
4605 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4606 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4607
a4fc5ed6 4608 drm_connector_cleanup(connector);
55f78c43 4609 kfree(connector);
a4fc5ed6
KP		 4610}
4611
00c09d70 4612void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4613{
da63a9f2
PZ		 4614 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4615 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4616
4f71d0cb 4617 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4618 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 4619 drm_encoder_cleanup(encoder);
bd943159
KP		 4620 if (is_edp(intel_dp)) {
4621 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4622 /*
4623 * vdd might still be enabled do to the delayed vdd off.
4624 * Make sure vdd is actually turned off here.
4625 */
773538e8 4626 pps_lock(intel_dp);
4be73780 4627 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4628 pps_unlock(intel_dp);
4629
01527b31
CT		 4630 if (intel_dp->edp_notifier.notifier_call) {
4631 unregister_reboot_notifier(&intel_dp->edp_notifier);
4632 intel_dp->edp_notifier.notifier_call = NULL;
4633 }
bd943159 4634 }
da63a9f2 4635 kfree(intel_dig_port);
24d05927
DV		 4636}
4637
07f9cd0b
ID		 4638static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4639{
4640 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4641
4642 if (!is_edp(intel_dp))
4643 return;
4644
951468f3
VS		 4645 /*
4646 * vdd might still be enabled do to the delayed vdd off.
4647 * Make sure vdd is actually turned off here.
4648 */
773538e8 4649 pps_lock(intel_dp);
07f9cd0b 4650 edp_panel_vdd_off_sync(intel_dp);
773538e8 4651 pps_unlock(intel_dp);
07f9cd0b
ID		 4652}
4653
6d93c0c4
ID		 4654static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4655{
4656 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4657}
4658
a4fc5ed6 4659static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4660 .dpms = intel_connector_dpms,
a4fc5ed6 4661 .detect = intel_dp_detect,
beb60608 4662 .force = intel_dp_force,
a4fc5ed6 4663 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4664 .set_property = intel_dp_set_property,
73845adf 4665 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4666};
4667
4668static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4669 .get_modes = intel_dp_get_modes,
4670 .mode_valid = intel_dp_mode_valid,
df0e9248 4671 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4672};
4673
a4fc5ed6 4674static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4675 .reset = intel_dp_encoder_reset,
24d05927 4676 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4677};
4678
0e32b39c 4679void
21d40d37 4680intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4681{
0e32b39c 4682 return;
c8110e52 4683}
6207937d 4684
13cf5504
DA		 4685bool
4686intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4687{
4688 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4689 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4690 struct drm_device *dev = intel_dig_port->base.base.dev;
4691 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33
ID		 4692 enum intel_display_power_domain power_domain;
4693 bool ret = true;
4694
0e32b39c
DA		 4695 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4696 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4697
26fbb774
VS		 4698 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4699 port_name(intel_dig_port->port),
0e32b39c 4700 long_hpd ? "long" : "short");
13cf5504 4701
1c767b33
ID		 4702 power_domain = intel_display_port_power_domain(intel_encoder);
4703 intel_display_power_get(dev_priv, power_domain);
4704
0e32b39c 4705 if (long_hpd) {
2a592bec
DA		 4706
4707 if (HAS_PCH_SPLIT(dev)) {
4708 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4709 goto mst_fail;
4710 } else {
4711 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4712 goto mst_fail;
4713 }
0e32b39c
DA		 4714
4715 if (!intel_dp_get_dpcd(intel_dp)) {
4716 goto mst_fail;
4717 }
4718
4719 intel_dp_probe_oui(intel_dp);
4720
4721 if (!intel_dp_probe_mst(intel_dp))
4722 goto mst_fail;
4723
4724 } else {
4725 if (intel_dp->is_mst) {
1c767b33 4726 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4727 goto mst_fail;
4728 }
4729
4730 if (!intel_dp->is_mst) {
4731 /*
4732 * we'll check the link status via the normal hot plug path later -
4733 * but for short hpds we should check it now
4734 */
5b215bcf 4735 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4736 intel_dp_check_link_status(intel_dp);
5b215bcf 4737 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4738 }
4739 }
1c767b33
ID		 4740 ret = false;
4741 goto put_power;
0e32b39c
DA		 4742mst_fail:
4743 /* if we were in MST mode, and device is not there get out of MST mode */
4744 if (intel_dp->is_mst) {
4745 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4746 intel_dp->is_mst = false;
4747 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4748 }
1c767b33
ID		 4749put_power:
4750 intel_display_power_put(dev_priv, power_domain);
4751
4752 return ret;
13cf5504
DA		 4753}
4754
e3421a18
ZW		 4755/* Return which DP Port should be selected for Transcoder DP control */
4756int
0206e353 4757intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4758{
4759 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4760 struct intel_encoder *intel_encoder;
4761 struct intel_dp *intel_dp;
e3421a18 4762
fa90ecef
PZ		 4763 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4764 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4765
fa90ecef
PZ		 4766 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4767 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4768 return intel_dp->output_reg;
e3421a18 4769 }
ea5b213a 4770
e3421a18
ZW		 4771 return -1;
4772}
4773
36e83a18 4774/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4775bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4776{
4777 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4778 union child_device_config *p_child;
36e83a18 4779 int i;
5d8a7752
VS		 4780 static const short port_mapping[] = {
4781 [PORT_B] = PORT_IDPB,
4782 [PORT_C] = PORT_IDPC,
4783 [PORT_D] = PORT_IDPD,
4784 };
36e83a18 4785
3b32a35b
VS		 4786 if (port == PORT_A)
4787 return true;
4788
41aa3448 4789 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4790 return false;
4791
41aa3448
RV		 4792 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4793 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4794
5d8a7752 4795 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4796 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4797 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4798 return true;
4799 }
4800 return false;
4801}
4802
0e32b39c 4803void
f684960e
CW		 4804intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4805{
53b41837
YN		 4806 struct intel_connector *intel_connector = to_intel_connector(connector);
4807
3f43c48d 4808 intel_attach_force_audio_property(connector);
e953fd7b 4809 intel_attach_broadcast_rgb_property(connector);
55bc60db 4810 intel_dp->color_range_auto = true;
53b41837
YN		 4811
4812 if (is_edp(intel_dp)) {
4813 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4814 drm_object_attach_property(
4815 &connector->base,
53b41837 4816 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4817 DRM_MODE_SCALE_ASPECT);
4818 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4819 }
f684960e
CW		 4820}
4821
dada1a9f
ID		 4822static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4823{
4824 intel_dp->last_power_cycle = jiffies;
4825 intel_dp->last_power_on = jiffies;
4826 intel_dp->last_backlight_off = jiffies;
4827}
4828
67a54566
DV		 4829static void
4830intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 4831 struct intel_dp *intel_dp)
67a54566
DV		 4832{
4833 struct drm_i915_private *dev_priv = dev->dev_private;
36b5f425
VS		 4834 struct edp_power_seq cur, vbt, spec,
4835 *final = &intel_dp->pps_delays;
67a54566 4836 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4837 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 4838
e39b999a
VS		 4839 lockdep_assert_held(&dev_priv->pps_mutex);
4840
81ddbc69
VS		 4841 /* already initialized? */
4842 if (final->t11_t12 != 0)
4843 return;
4844
453c5420 4845 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4846 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4847 pp_on_reg = PCH_PP_ON_DELAYS;
4848 pp_off_reg = PCH_PP_OFF_DELAYS;
4849 pp_div_reg = PCH_PP_DIVISOR;
4850 } else {
bf13e81b
JN		 4851 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4852
4853 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4854 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4855 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4856 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4857 }
67a54566
DV		 4858
4859 /* Workaround: Need to write PP_CONTROL with the unlock key as
4860 * the very first thing. */
453c5420 4861 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4862 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4863
453c5420
JB		 4864 pp_on = I915_READ(pp_on_reg);
4865 pp_off = I915_READ(pp_off_reg);
4866 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4867
4868 /* Pull timing values out of registers */
4869 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4870 PANEL_POWER_UP_DELAY_SHIFT;
4871
4872 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4873 PANEL_LIGHT_ON_DELAY_SHIFT;
4874
4875 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4876 PANEL_LIGHT_OFF_DELAY_SHIFT;
4877
4878 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4879 PANEL_POWER_DOWN_DELAY_SHIFT;
4880
4881 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4882 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4883
4884 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4885 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4886
41aa3448 4887 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4888
4889 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4890 * our hw here, which are all in 100usec. */
4891 spec.t1_t3 = 210 * 10;
4892 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4893 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4894 spec.t10 = 500 * 10;
4895 /* This one is special and actually in units of 100ms, but zero
4896 * based in the hw (so we need to add 100 ms). But the sw vbt
4897 * table multiplies it with 1000 to make it in units of 100usec,
4898 * too. */
4899 spec.t11_t12 = (510 + 100) * 10;
4900
4901 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4902 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4903
4904 /* Use the max of the register settings and vbt. If both are
4905 * unset, fall back to the spec limits. */
36b5f425 4906#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 4907 spec.field : \
4908 max(cur.field, vbt.field))
4909 assign_final(t1_t3);
4910 assign_final(t8);
4911 assign_final(t9);
4912 assign_final(t10);
4913 assign_final(t11_t12);
4914#undef assign_final
4915
36b5f425 4916#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 4917 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4918 intel_dp->backlight_on_delay = get_delay(t8);
4919 intel_dp->backlight_off_delay = get_delay(t9);
4920 intel_dp->panel_power_down_delay = get_delay(t10);
4921 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4922#undef get_delay
4923
f30d26e4
JN		 4924 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4925 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4926 intel_dp->panel_power_cycle_delay);
4927
4928 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4929 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
f30d26e4
JN		 4930}
4931
4932static void
4933intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 4934 struct intel_dp *intel_dp)
f30d26e4
JN		 4935{
4936 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4937 u32 pp_on, pp_off, pp_div, port_sel = 0;
4938 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4939 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 4940 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 4941 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 4942
e39b999a 4943 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420
JB		 4944
4945 if (HAS_PCH_SPLIT(dev)) {
4946 pp_on_reg = PCH_PP_ON_DELAYS;
4947 pp_off_reg = PCH_PP_OFF_DELAYS;
4948 pp_div_reg = PCH_PP_DIVISOR;
4949 } else {
bf13e81b
JN		 4950 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4951
4952 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4953 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4954 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4955 }
4956
b2f19d1a
PZ		 4957 /*
4958 * And finally store the new values in the power sequencer. The
4959 * backlight delays are set to 1 because we do manual waits on them. For
4960 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4961 * we'll end up waiting for the backlight off delay twice: once when we
4962 * do the manual sleep, and once when we disable the panel and wait for
4963 * the PP_STATUS bit to become zero.
4964 */
f30d26e4 4965 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4966 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4967 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4968 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4969 /* Compute the divisor for the pp clock, simply match the Bspec
4970 * formula. */
453c5420 4971 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4972 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4973 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4974
4975 /* Haswell doesn't have any port selection bits for the panel
4976 * power sequencer any more. */
bc7d38a4 4977 if (IS_VALLEYVIEW(dev)) {
ad933b56 4978 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4979 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4980 if (port == PORT_A)
a24c144c 4981 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4982 else
a24c144c 4983 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4984 }
4985
453c5420
JB		 4986 pp_on |= port_sel;
4987
4988 I915_WRITE(pp_on_reg, pp_on);
4989 I915_WRITE(pp_off_reg, pp_off);
4990 I915_WRITE(pp_div_reg, pp_div);
67a54566 4991
67a54566 4992 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4993 I915_READ(pp_on_reg),
4994 I915_READ(pp_off_reg),
4995 I915_READ(pp_div_reg));
f684960e
CW		 4996}
4997
439d7ac0
PB		 4998void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4999{
5000 struct drm_i915_private *dev_priv = dev->dev_private;
5001 struct intel_encoder *encoder;
5002 struct intel_dp *intel_dp = NULL;
5003 struct intel_crtc_config *config = NULL;
5004 struct intel_crtc *intel_crtc = NULL;
5005 struct intel_connector *intel_connector = dev_priv->drrs.connector;
5006 u32 reg, val;
5007 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
5008
5009 if (refresh_rate <= 0) {
5010 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5011 return;
5012 }
5013
5014 if (intel_connector == NULL) {
5015 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
5016 return;
5017 }
5018
1fcc9d1c
DV		 5019 /*
5020 * FIXME: This needs proper synchronization with psr state. But really
5021 * hard to tell without seeing the user of this function of this code.
5022 * Check locking and ordering once that lands.
5023 */
439d7ac0
PB		 5024 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
5025 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
5026 return;
5027 }
5028
5029 encoder = intel_attached_encoder(&intel_connector->base);
5030 intel_dp = enc_to_intel_dp(&encoder->base);
5031 intel_crtc = encoder->new_crtc;
5032
5033 if (!intel_crtc) {
5034 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5035 return;
5036 }
5037
5038 config = &intel_crtc->config;
5039
5040 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
5041 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5042 return;
5043 }
5044
5045 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
5046 index = DRRS_LOW_RR;
5047
5048 if (index == intel_dp->drrs_state.refresh_rate_type) {
5049 DRM_DEBUG_KMS(
5050 "DRRS requested for previously set RR...ignoring\n");
5051 return;
5052 }
5053
5054 if (!intel_crtc->active) {
5055 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5056 return;
5057 }
5058
5059 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
5060 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
5061 val = I915_READ(reg);
5062 if (index > DRRS_HIGH_RR) {
5063 val |= PIPECONF_EDP_RR_MODE_SWITCH;
f769cd24 5064 intel_dp_set_m_n(intel_crtc);
439d7ac0
PB		 5065 } else {
5066 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5067 }
5068 I915_WRITE(reg, val);
5069 }
5070
5071 /*
5072 * mutex taken to ensure that there is no race between differnt
5073 * drrs calls trying to update refresh rate. This scenario may occur
5074 * in future when idleness detection based DRRS in kernel and
5075 * possible calls from user space to set differnt RR are made.
5076 */
5077
5078 mutex_lock(&intel_dp->drrs_state.mutex);
5079
5080 intel_dp->drrs_state.refresh_rate_type = index;
5081
5082 mutex_unlock(&intel_dp->drrs_state.mutex);
5083
5084 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5085}
5086
4f9db5b5
PB		 5087static struct drm_display_mode *
5088intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
5089 struct intel_connector *intel_connector,
5090 struct drm_display_mode *fixed_mode)
5091{
5092 struct drm_connector *connector = &intel_connector->base;
5093 struct intel_dp *intel_dp = &intel_dig_port->dp;
5094 struct drm_device *dev = intel_dig_port->base.base.dev;
5095 struct drm_i915_private *dev_priv = dev->dev_private;
5096 struct drm_display_mode *downclock_mode = NULL;
5097
5098 if (INTEL_INFO(dev)->gen <= 6) {
5099 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5100 return NULL;
5101 }
5102
5103 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 5104 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 5105 return NULL;
5106 }
5107
5108 downclock_mode = intel_find_panel_downclock
5109 (dev, fixed_mode, connector);
5110
5111 if (!downclock_mode) {
4079b8d1 5112 DRM_DEBUG_KMS("DRRS not supported\n");
4f9db5b5
PB		 5113 return NULL;
5114 }
5115
439d7ac0
PB		 5116 dev_priv->drrs.connector = intel_connector;
5117
5118 mutex_init(&intel_dp->drrs_state.mutex);
5119
4f9db5b5
PB		 5120 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
5121
5122 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 5123 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 5124 return downclock_mode;
5125}
5126
aba86890
ID		 5127void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
5128{
5129 struct drm_device *dev = intel_encoder->base.dev;
5130 struct drm_i915_private *dev_priv = dev->dev_private;
5131 struct intel_dp *intel_dp;
5132 enum intel_display_power_domain power_domain;
5133
5134 if (intel_encoder->type != INTEL_OUTPUT_EDP)
5135 return;
5136
5137 intel_dp = enc_to_intel_dp(&intel_encoder->base);
773538e8
VS		 5138
5139 pps_lock(intel_dp);
5140
aba86890 5141 if (!edp_have_panel_vdd(intel_dp))
e39b999a 5142 goto out;
aba86890
ID		 5143 /*
5144 * The VDD bit needs a power domain reference, so if the bit is
5145 * already enabled when we boot or resume, grab this reference and
5146 * schedule a vdd off, so we don't hold on to the reference
5147 * indefinitely.
5148 */
5149 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5150 power_domain = intel_display_port_power_domain(intel_encoder);
5151 intel_display_power_get(dev_priv, power_domain);
5152
5153 edp_panel_vdd_schedule_off(intel_dp);
e39b999a 5154 out:
773538e8 5155 pps_unlock(intel_dp);
aba86890
ID		 5156}
5157
ed92f0b2 5158static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 5159 struct intel_connector *intel_connector)
ed92f0b2
PZ		 5160{
5161 struct drm_connector *connector = &intel_connector->base;
5162 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5163 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5164 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 5165 struct drm_i915_private *dev_priv = dev->dev_private;
5166 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5167 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5168 bool has_dpcd;
5169 struct drm_display_mode *scan;
5170 struct edid *edid;
5171
4f9db5b5
PB		 5172 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
5173
ed92f0b2
PZ		 5174 if (!is_edp(intel_dp))
5175 return true;
5176
aba86890 5177 intel_edp_panel_vdd_sanitize(intel_encoder);
63635217 5178
ed92f0b2 5179 /* Cache DPCD and EDID for edp. */
ed92f0b2 5180 has_dpcd = intel_dp_get_dpcd(intel_dp);
ed92f0b2
PZ		 5181
5182 if (has_dpcd) {
5183 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5184 dev_priv->no_aux_handshake =
5185 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5186 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5187 } else {
5188 /* if this fails, presume the device is a ghost */
5189 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 5190 return false;
5191 }
5192
5193 /* We now know it's not a ghost, init power sequence regs. */
773538e8 5194 pps_lock(intel_dp);
36b5f425 5195 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
773538e8 5196 pps_unlock(intel_dp);
ed92f0b2 5197
060c8778 5198 mutex_lock(&dev->mode_config.mutex);
0b99836f 5199 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5200 if (edid) {
5201 if (drm_add_edid_modes(connector, edid)) {
5202 drm_mode_connector_update_edid_property(connector,
5203 edid);
5204 drm_edid_to_eld(connector, edid);
5205 } else {
5206 kfree(edid);
5207 edid = ERR_PTR(-EINVAL);
5208 }
5209 } else {
5210 edid = ERR_PTR(-ENOENT);
5211 }
5212 intel_connector->edid = edid;
5213
5214 /* prefer fixed mode from EDID if available */
5215 list_for_each_entry(scan, &connector->probed_modes, head) {
5216 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5217 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 5218 downclock_mode = intel_dp_drrs_init(
5219 intel_dig_port,
5220 intel_connector, fixed_mode);
ed92f0b2
PZ		 5221 break;
5222 }
5223 }
5224
5225 /* fallback to VBT if available for eDP */
5226 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5227 fixed_mode = drm_mode_duplicate(dev,
5228 dev_priv->vbt.lfp_lvds_vbt_mode);
5229 if (fixed_mode)
5230 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5231 }
060c8778 5232 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5233
01527b31
CT		 5234 if (IS_VALLEYVIEW(dev)) {
5235 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5236 register_reboot_notifier(&intel_dp->edp_notifier);
5237 }
5238
4f9db5b5 5239 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 5240 intel_connector->panel.backlight_power = intel_edp_backlight_power;
ed92f0b2
PZ		 5241 intel_panel_setup_backlight(connector);
5242
5243 return true;
5244}
5245
16c25533 5246bool
f0fec3f2
PZ		 5247intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5248 struct intel_connector *intel_connector)
a4fc5ed6 5249{
f0fec3f2
PZ		 5250 struct drm_connector *connector = &intel_connector->base;
5251 struct intel_dp *intel_dp = &intel_dig_port->dp;
5252 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5253 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5254 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5255 enum port port = intel_dig_port->port;
0b99836f 5256 int type;
a4fc5ed6 5257
a4a5d2f8
VS		 5258 intel_dp->pps_pipe = INVALID_PIPE;
5259
ec5b01dd 5260 /* intel_dp vfuncs */
b6b5e383
DL		 5261 if (INTEL_INFO(dev)->gen >= 9)
5262 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5263 else if (IS_VALLEYVIEW(dev))
ec5b01dd
DL		 5264 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5265 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5266 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5267 else if (HAS_PCH_SPLIT(dev))
5268 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5269 else
5270 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5271
b9ca5fad
DL		 5272 if (INTEL_INFO(dev)->gen >= 9)
5273 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5274 else
5275 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
153b1100 5276
0767935e
DV		 5277 /* Preserve the current hw state. */
5278 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5279 intel_dp->attached_connector = intel_connector;
3d3dc149 5280
3b32a35b 5281 if (intel_dp_is_edp(dev, port))
b329530c 5282 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5283 else
5284 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5285
f7d24902
ID		 5286 /*
5287 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5288 * for DP the encoder type can be set by the caller to
5289 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5290 */
5291 if (type == DRM_MODE_CONNECTOR_eDP)
5292 intel_encoder->type = INTEL_OUTPUT_EDP;
5293
c17ed5b5
VS		 5294 /* eDP only on port B and/or C on vlv/chv */
5295 if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5296 port != PORT_B && port != PORT_C))
5297 return false;
5298
e7281eab
ID		 5299 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5300 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5301 port_name(port));
5302
b329530c 5303 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5304 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5305
a4fc5ed6
KP		 5306 connector->interlace_allowed = true;
5307 connector->doublescan_allowed = 0;
5308
f0fec3f2 5309 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5310 edp_panel_vdd_work);
a4fc5ed6 5311
df0e9248 5312 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5313 drm_connector_register(connector);
a4fc5ed6 5314
affa9354 5315 if (HAS_DDI(dev))
bcbc889b
PZ		 5316 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5317 else
5318 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5319 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5320
0b99836f 5321 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5322 switch (port) {
5323 case PORT_A:
1d843f9d 5324 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5325 break;
5326 case PORT_B:
1d843f9d 5327 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 5328 break;
5329 case PORT_C:
1d843f9d 5330 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5331 break;
5332 case PORT_D:
1d843f9d 5333 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 5334 break;
5335 default:
ad1c0b19 5336 BUG();
5eb08b69
ZW		 5337 }
5338
dada1a9f 5339 if (is_edp(intel_dp)) {
773538e8 5340 pps_lock(intel_dp);
a4a5d2f8
VS		 5341 if (IS_VALLEYVIEW(dev)) {
5342 vlv_initial_power_sequencer_setup(intel_dp);
5343 } else {
5344 intel_dp_init_panel_power_timestamps(intel_dp);
36b5f425 5345 intel_dp_init_panel_power_sequencer(dev, intel_dp);
a4a5d2f8 5346 }
773538e8 5347 pps_unlock(intel_dp);
dada1a9f 5348 }
0095e6dc 5349
9d1a1031 5350 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5351
0e32b39c
DA		 5352 /* init MST on ports that can support it */
5353 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5354 if (port == PORT_B || port == PORT_C || port == PORT_D) {
a4a5d2f8
VS		 5355 intel_dp_mst_encoder_init(intel_dig_port,
5356 intel_connector->base.base.id);
0e32b39c
DA		 5357 }
5358 }
5359
36b5f425 5360 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
4f71d0cb 5361 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5362 if (is_edp(intel_dp)) {
5363 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 5364 /*
5365 * vdd might still be enabled do to the delayed vdd off.
5366 * Make sure vdd is actually turned off here.
5367 */
773538e8 5368 pps_lock(intel_dp);
4be73780 5369 edp_panel_vdd_off_sync(intel_dp);
773538e8 5370 pps_unlock(intel_dp);
15b1d171 5371 }
34ea3d38 5372 drm_connector_unregister(connector);
b2f246a8 5373 drm_connector_cleanup(connector);
16c25533 5374 return false;
b2f246a8 5375 }
32f9d658 5376
f684960e
CW		 5377 intel_dp_add_properties(intel_dp, connector);
5378
a4fc5ed6
KP		 5379 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5380 * 0xd. Failure to do so will result in spurious interrupts being
5381 * generated on the port when a cable is not attached.
5382 */
5383 if (IS_G4X(dev) && !IS_GM45(dev)) {
5384 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5385 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5386 }
16c25533
PZ		 5387
5388 return true;
a4fc5ed6 5389}
f0fec3f2
PZ		 5390
5391void
5392intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5393{
13cf5504 5394 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5395 struct intel_digital_port *intel_dig_port;
5396 struct intel_encoder *intel_encoder;
5397 struct drm_encoder *encoder;
5398 struct intel_connector *intel_connector;
5399
b14c5679 5400 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5401 if (!intel_dig_port)
5402 return;
5403
b14c5679 5404 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 5405 if (!intel_connector) {
5406 kfree(intel_dig_port);
5407 return;
5408 }
5409
5410 intel_encoder = &intel_dig_port->base;
5411 encoder = &intel_encoder->base;
5412
5413 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5414 DRM_MODE_ENCODER_TMDS);
5415
5bfe2ac0 5416 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5417 intel_encoder->disable = intel_disable_dp;
00c09d70 5418 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5419 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5420 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5421 if (IS_CHERRYVIEW(dev)) {
9197c88b 5422 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5423 intel_encoder->pre_enable = chv_pre_enable_dp;
5424 intel_encoder->enable = vlv_enable_dp;
580d3811 5425 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5426 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5427 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5428 intel_encoder->pre_enable = vlv_pre_enable_dp;
5429 intel_encoder->enable = vlv_enable_dp;
49277c31 5430 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5431 } else {
ecff4f3b
JN		 5432 intel_encoder->pre_enable = g4x_pre_enable_dp;
5433 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5434 if (INTEL_INFO(dev)->gen >= 5)
5435 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5436 }
f0fec3f2 5437
174edf1f 5438 intel_dig_port->port = port;
f0fec3f2
PZ		 5439 intel_dig_port->dp.output_reg = output_reg;
5440
00c09d70 5441 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5442 if (IS_CHERRYVIEW(dev)) {
5443 if (port == PORT_D)
5444 intel_encoder->crtc_mask = 1 << 2;
5445 else
5446 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5447 } else {
5448 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5449 }
bc079e8b 5450 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 5451 intel_encoder->hot_plug = intel_dp_hot_plug;
5452
13cf5504
DA		 5453 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5454 dev_priv->hpd_irq_port[port] = intel_dig_port;
5455
15b1d171
PZ		 5456 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5457 drm_encoder_cleanup(encoder);
5458 kfree(intel_dig_port);
b2f246a8 5459 kfree(intel_connector);
15b1d171 5460 }
f0fec3f2 5461}
0e32b39c
DA		 5462
5463void intel_dp_mst_suspend(struct drm_device *dev)
5464{
5465 struct drm_i915_private *dev_priv = dev->dev_private;
5466 int i;
5467
5468 /* disable MST */
5469 for (i = 0; i < I915_MAX_PORTS; i++) {
5470 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5471 if (!intel_dig_port)
5472 continue;
5473
5474 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5475 if (!intel_dig_port->dp.can_mst)
5476 continue;
5477 if (intel_dig_port->dp.is_mst)
5478 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5479 }
5480 }
5481}
5482
5483void intel_dp_mst_resume(struct drm_device *dev)
5484{
5485 struct drm_i915_private *dev_priv = dev->dev_private;
5486 int i;
5487
5488 for (i = 0; i < I915_MAX_PORTS; i++) {
5489 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5490 if (!intel_dig_port)
5491 continue;
5492 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5493 int ret;
5494
5495 if (!intel_dig_port->dp.can_mst)
5496 continue;
5497
5498 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5499 if (ret != 0) {
5500 intel_dp_check_mst_status(&intel_dig_port->dp);
5501 }
5502 }
5503 }
5504}
Linux kernel - Deliverables
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