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drm/i915: replace for_each_engine()
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7 33#include <drm/drmP.h>
c6f95f27 34#include <drm/drm_atomic_helper.h>
760285e7
DH		 35#include <drm/drm_crtc.h>
36#include <drm/drm_crtc_helper.h>
37#include <drm/drm_edid.h>
a4fc5ed6 38#include "intel_drv.h"
760285e7 39#include <drm/i915_drm.h>
a4fc5ed6 40#include "i915_drv.h"
a4fc5ed6 41
a4fc5ed6
KP		 42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
559be30c
TP		 44/* Compliance test status bits */
45#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46#define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47#define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48#define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
49
9dd4ffdf 50struct dp_link_dpll {
840b32b7 51 int clock;
9dd4ffdf
CML		 52 struct dpll dpll;
53};
54
55static const struct dp_link_dpll gen4_dpll[] = {
840b32b7 56 { 162000,
9dd4ffdf 57 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
840b32b7 58 { 270000,
9dd4ffdf
CML		 59 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
60};
61
62static const struct dp_link_dpll pch_dpll[] = {
840b32b7 63 { 162000,
9dd4ffdf 64 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
840b32b7 65 { 270000,
9dd4ffdf
CML		 66 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
67};
68
65ce4bf5 69static const struct dp_link_dpll vlv_dpll[] = {
840b32b7 70 { 162000,
58f6e632 71 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
840b32b7 72 { 270000,
65ce4bf5
CML		 73 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
74};
75
ef9348c8
CML		 76/*
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
79 */
80static const struct dp_link_dpll chv_dpll[] = {
81 /*
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
85 */
840b32b7 86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
ef9348c8 87 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
840b32b7 88 { 270000, /* m2_int = 27, m2_fraction = 0 */
ef9348c8 89 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
840b32b7 90 { 540000, /* m2_int = 27, m2_fraction = 0 */
ef9348c8
CML		 91 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
92};
637a9c63 93
64987fc5
SJ		 94static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
637a9c63 96static const int skl_rates[] = { 162000, 216000, 270000,
f4896f15
VS		 97 324000, 432000, 540000 };
98static const int default_rates[] = { 162000, 270000, 540000 };
ef9348c8 99
cfcb0fc9
JB		 100/**
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
103 *
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
106 */
107static bool is_edp(struct intel_dp *intel_dp)
108{
da63a9f2
PZ		 109 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
110
111 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 112}
113
68b4d824 114static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 115{
68b4d824
ID		 116 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
117
118 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 119}
120
df0e9248
CW		 121static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
122{
fa90ecef 123 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 124}
125
ea5b213a 126static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 127static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 128static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 129static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a8c3344e
VS		 130static void vlv_steal_power_sequencer(struct drm_device *dev,
131 enum pipe pipe);
a4fc5ed6 132
e0fce78f
VS		 133static unsigned int intel_dp_unused_lane_mask(int lane_count)
134{
135 return ~((1 << lane_count) - 1) & 0xf;
136}
137
ed4e9c1d
VS		 138static int
139intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 140{
7183dc29 141 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 142
143 switch (max_link_bw) {
144 case DP_LINK_BW_1_62:
145 case DP_LINK_BW_2_7:
1db10e28 146 case DP_LINK_BW_5_4:
d4eead50 147 break;
a4fc5ed6 148 default:
d4eead50
ID		 149 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
150 max_link_bw);
a4fc5ed6
KP		 151 max_link_bw = DP_LINK_BW_1_62;
152 break;
153 }
154 return max_link_bw;
155}
156
eeb6324d
PZ		 157static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
158{
159 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
eeb6324d
PZ		 160 u8 source_max, sink_max;
161
ccb1a831 162 source_max = intel_dig_port->max_lanes;
eeb6324d
PZ		 163 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
164
165 return min(source_max, sink_max);
166}
167
cd9dde44
AJ		 168/*
169 * The units on the numbers in the next two are... bizarre. Examples will
170 * make it clearer; this one parallels an example in the eDP spec.
171 *
172 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
173 *
174 * 270000 * 1 * 8 / 10 == 216000
175 *
176 * The actual data capacity of that configuration is 2.16Gbit/s, so the
177 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
178 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
179 * 119000. At 18bpp that's 2142000 kilobits per second.
180 *
181 * Thus the strange-looking division by 10 in intel_dp_link_required, to
182 * get the result in decakilobits instead of kilobits.
183 */
184
a4fc5ed6 185static int
c898261c 186intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 187{
cd9dde44 188 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 189}
190
fe27d53e
DA		 191static int
192intel_dp_max_data_rate(int max_link_clock, int max_lanes)
193{
194 return (max_link_clock * max_lanes * 8) / 10;
195}
196
c19de8eb 197static enum drm_mode_status
a4fc5ed6
KP		 198intel_dp_mode_valid(struct drm_connector *connector,
199 struct drm_display_mode *mode)
200{
df0e9248 201 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 202 struct intel_connector *intel_connector = to_intel_connector(connector);
203 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 204 int target_clock = mode->clock;
205 int max_rate, mode_rate, max_lanes, max_link_clock;
799487f5 206 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
a4fc5ed6 207
dd06f90e
JN		 208 if (is_edp(intel_dp) && fixed_mode) {
209 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 210 return MODE_PANEL;
211
dd06f90e 212 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 213 return MODE_PANEL;
03afc4a2
DV		 214
215 target_clock = fixed_mode->clock;
7de56f43
ZY		 216 }
217
50fec21a 218 max_link_clock = intel_dp_max_link_rate(intel_dp);
eeb6324d 219 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 220
221 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
222 mode_rate = intel_dp_link_required(target_clock, 18);
223
799487f5 224 if (mode_rate > max_rate || target_clock > max_dotclk)
c4867936 225 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 226
227 if (mode->clock < 10000)
228 return MODE_CLOCK_LOW;
229
0af78a2b
DV		 230 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
231 return MODE_H_ILLEGAL;
232
a4fc5ed6
KP		 233 return MODE_OK;
234}
235
a4f1289e 236uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 237{
238 int i;
239 uint32_t v = 0;
240
241 if (src_bytes > 4)
242 src_bytes = 4;
243 for (i = 0; i < src_bytes; i++)
244 v |= ((uint32_t) src[i]) << ((3-i) * 8);
245 return v;
246}
247
c2af70e2 248static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
a4fc5ed6
KP		 249{
250 int i;
251 if (dst_bytes > 4)
252 dst_bytes = 4;
253 for (i = 0; i < dst_bytes; i++)
254 dst[i] = src >> ((3-i) * 8);
255}
256
bf13e81b
JN		 257static void
258intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 259 struct intel_dp *intel_dp);
bf13e81b
JN		 260static void
261intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 262 struct intel_dp *intel_dp);
bf13e81b 263
773538e8
VS		 264static void pps_lock(struct intel_dp *intel_dp)
265{
266 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
267 struct intel_encoder *encoder = &intel_dig_port->base;
268 struct drm_device *dev = encoder->base.dev;
269 struct drm_i915_private *dev_priv = dev->dev_private;
270 enum intel_display_power_domain power_domain;
271
272 /*
273 * See vlv_power_sequencer_reset() why we need
274 * a power domain reference here.
275 */
25f78f58 276 power_domain = intel_display_port_aux_power_domain(encoder);
773538e8
VS		 277 intel_display_power_get(dev_priv, power_domain);
278
279 mutex_lock(&dev_priv->pps_mutex);
280}
281
282static void pps_unlock(struct intel_dp *intel_dp)
283{
284 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
285 struct intel_encoder *encoder = &intel_dig_port->base;
286 struct drm_device *dev = encoder->base.dev;
287 struct drm_i915_private *dev_priv = dev->dev_private;
288 enum intel_display_power_domain power_domain;
289
290 mutex_unlock(&dev_priv->pps_mutex);
291
25f78f58 292 power_domain = intel_display_port_aux_power_domain(encoder);
773538e8
VS		 293 intel_display_power_put(dev_priv, power_domain);
294}
295
961a0db0
VS		 296static void
297vlv_power_sequencer_kick(struct intel_dp *intel_dp)
298{
299 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
300 struct drm_device *dev = intel_dig_port->base.base.dev;
301 struct drm_i915_private *dev_priv = dev->dev_private;
302 enum pipe pipe = intel_dp->pps_pipe;
0047eedc
VS		 303 bool pll_enabled, release_cl_override = false;
304 enum dpio_phy phy = DPIO_PHY(pipe);
305 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
961a0db0
VS		 306 uint32_t DP;
307
308 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
309 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
310 pipe_name(pipe), port_name(intel_dig_port->port)))
311 return;
312
313 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
314 pipe_name(pipe), port_name(intel_dig_port->port));
315
316 /* Preserve the BIOS-computed detected bit. This is
317 * supposed to be read-only.
318 */
319 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
320 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
321 DP |= DP_PORT_WIDTH(1);
322 DP |= DP_LINK_TRAIN_PAT_1;
323
324 if (IS_CHERRYVIEW(dev))
325 DP |= DP_PIPE_SELECT_CHV(pipe);
326 else if (pipe == PIPE_B)
327 DP |= DP_PIPEB_SELECT;
328
d288f65f
VS		 329 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
330
331 /*
332 * The DPLL for the pipe must be enabled for this to work.
333 * So enable temporarily it if it's not already enabled.
334 */
0047eedc
VS		 335 if (!pll_enabled) {
336 release_cl_override = IS_CHERRYVIEW(dev) &&
337 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
338
3f36b937
TU		 339 if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
340 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
341 DRM_ERROR("Failed to force on pll for pipe %c!\n",
342 pipe_name(pipe));
343 return;
344 }
0047eedc 345 }
d288f65f 346
961a0db0
VS		 347 /*
348 * Similar magic as in intel_dp_enable_port().
349 * We _must_ do this port enable + disable trick
350 * to make this power seqeuencer lock onto the port.
351 * Otherwise even VDD force bit won't work.
352 */
353 I915_WRITE(intel_dp->output_reg, DP);
354 POSTING_READ(intel_dp->output_reg);
355
356 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
357 POSTING_READ(intel_dp->output_reg);
358
359 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
360 POSTING_READ(intel_dp->output_reg);
d288f65f 361
0047eedc 362 if (!pll_enabled) {
d288f65f 363 vlv_force_pll_off(dev, pipe);
0047eedc
VS		 364
365 if (release_cl_override)
366 chv_phy_powergate_ch(dev_priv, phy, ch, false);
367 }
961a0db0
VS		 368}
369
bf13e81b
JN		 370static enum pipe
371vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
372{
373 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 374 struct drm_device *dev = intel_dig_port->base.base.dev;
375 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 376 struct intel_encoder *encoder;
377 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
a8c3344e 378 enum pipe pipe;
bf13e81b 379
e39b999a 380 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 381
a8c3344e
VS		 382 /* We should never land here with regular DP ports */
383 WARN_ON(!is_edp(intel_dp));
384
a4a5d2f8
VS		 385 if (intel_dp->pps_pipe != INVALID_PIPE)
386 return intel_dp->pps_pipe;
387
388 /*
389 * We don't have power sequencer currently.
390 * Pick one that's not used by other ports.
391 */
19c8054c 392 for_each_intel_encoder(dev, encoder) {
a4a5d2f8
VS		 393 struct intel_dp *tmp;
394
395 if (encoder->type != INTEL_OUTPUT_EDP)
396 continue;
397
398 tmp = enc_to_intel_dp(&encoder->base);
399
400 if (tmp->pps_pipe != INVALID_PIPE)
401 pipes &= ~(1 << tmp->pps_pipe);
402 }
403
404 /*
405 * Didn't find one. This should not happen since there
406 * are two power sequencers and up to two eDP ports.
407 */
408 if (WARN_ON(pipes == 0))
a8c3344e
VS		 409 pipe = PIPE_A;
410 else
411 pipe = ffs(pipes) - 1;
a4a5d2f8 412
a8c3344e
VS		 413 vlv_steal_power_sequencer(dev, pipe);
414 intel_dp->pps_pipe = pipe;
a4a5d2f8
VS		 415
416 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
417 pipe_name(intel_dp->pps_pipe),
418 port_name(intel_dig_port->port));
419
420 /* init power sequencer on this pipe and port */
36b5f425
VS		 421 intel_dp_init_panel_power_sequencer(dev, intel_dp);
422 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8 423
961a0db0
VS		 424 /*
425 * Even vdd force doesn't work until we've made
426 * the power sequencer lock in on the port.
427 */
428 vlv_power_sequencer_kick(intel_dp);
a4a5d2f8
VS		 429
430 return intel_dp->pps_pipe;
431}
432
6491ab27
VS		 433typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
434 enum pipe pipe);
435
436static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
437 enum pipe pipe)
438{
439 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
440}
441
442static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
443 enum pipe pipe)
444{
445 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
446}
447
448static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
449 enum pipe pipe)
450{
451 return true;
452}
bf13e81b 453
a4a5d2f8 454static enum pipe
6491ab27
VS		 455vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
456 enum port port,
457 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 458{
459 enum pipe pipe;
bf13e81b 460
bf13e81b
JN		 461 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
462 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
463 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 464
465 if (port_sel != PANEL_PORT_SELECT_VLV(port))
466 continue;
467
6491ab27
VS		 468 if (!pipe_check(dev_priv, pipe))
469 continue;
470
a4a5d2f8 471 return pipe;
bf13e81b
JN		 472 }
473
a4a5d2f8
VS		 474 return INVALID_PIPE;
475}
476
477static void
478vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
479{
480 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
481 struct drm_device *dev = intel_dig_port->base.base.dev;
482 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 483 enum port port = intel_dig_port->port;
484
485 lockdep_assert_held(&dev_priv->pps_mutex);
486
487 /* try to find a pipe with this port selected */
6491ab27
VS		 488 /* first pick one where the panel is on */
489 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
490 vlv_pipe_has_pp_on);
491 /* didn't find one? pick one where vdd is on */
492 if (intel_dp->pps_pipe == INVALID_PIPE)
493 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
494 vlv_pipe_has_vdd_on);
495 /* didn't find one? pick one with just the correct port */
496 if (intel_dp->pps_pipe == INVALID_PIPE)
497 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
498 vlv_pipe_any);
a4a5d2f8
VS		 499
500 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
501 if (intel_dp->pps_pipe == INVALID_PIPE) {
502 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
503 port_name(port));
504 return;
bf13e81b
JN		 505 }
506
a4a5d2f8
VS		 507 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
508 port_name(port), pipe_name(intel_dp->pps_pipe));
509
36b5f425
VS		 510 intel_dp_init_panel_power_sequencer(dev, intel_dp);
511 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 512}
513
773538e8
VS		 514void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
515{
516 struct drm_device *dev = dev_priv->dev;
517 struct intel_encoder *encoder;
518
666a4537 519 if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)))
773538e8
VS		 520 return;
521
522 /*
523 * We can't grab pps_mutex here due to deadlock with power_domain
524 * mutex when power_domain functions are called while holding pps_mutex.
525 * That also means that in order to use pps_pipe the code needs to
526 * hold both a power domain reference and pps_mutex, and the power domain
527 * reference get/put must be done while _not_ holding pps_mutex.
528 * pps_{lock,unlock}() do these steps in the correct order, so one
529 * should use them always.
530 */
531
19c8054c 532 for_each_intel_encoder(dev, encoder) {
773538e8
VS		 533 struct intel_dp *intel_dp;
534
535 if (encoder->type != INTEL_OUTPUT_EDP)
536 continue;
537
538 intel_dp = enc_to_intel_dp(&encoder->base);
539 intel_dp->pps_pipe = INVALID_PIPE;
540 }
bf13e81b
JN		 541}
542
f0f59a00
VS		 543static i915_reg_t
544_pp_ctrl_reg(struct intel_dp *intel_dp)
bf13e81b
JN		 545{
546 struct drm_device *dev = intel_dp_to_dev(intel_dp);
547
b0a08bec
VK		 548 if (IS_BROXTON(dev))
549 return BXT_PP_CONTROL(0);
550 else if (HAS_PCH_SPLIT(dev))
bf13e81b
JN		 551 return PCH_PP_CONTROL;
552 else
553 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
554}
555
f0f59a00
VS		 556static i915_reg_t
557_pp_stat_reg(struct intel_dp *intel_dp)
bf13e81b
JN		 558{
559 struct drm_device *dev = intel_dp_to_dev(intel_dp);
560
b0a08bec
VK		 561 if (IS_BROXTON(dev))
562 return BXT_PP_STATUS(0);
563 else if (HAS_PCH_SPLIT(dev))
bf13e81b
JN		 564 return PCH_PP_STATUS;
565 else
566 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
567}
568
01527b31
CT		 569/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
570 This function only applicable when panel PM state is not to be tracked */
571static int edp_notify_handler(struct notifier_block *this, unsigned long code,
572 void *unused)
573{
574 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
575 edp_notifier);
576 struct drm_device *dev = intel_dp_to_dev(intel_dp);
577 struct drm_i915_private *dev_priv = dev->dev_private;
01527b31
CT		 578
579 if (!is_edp(intel_dp) || code != SYS_RESTART)
580 return 0;
581
773538e8 582 pps_lock(intel_dp);
e39b999a 583
666a4537 584 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e39b999a 585 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
f0f59a00 586 i915_reg_t pp_ctrl_reg, pp_div_reg;
649636ef 587 u32 pp_div;
e39b999a 588
01527b31
CT		 589 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
590 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
591 pp_div = I915_READ(pp_div_reg);
592 pp_div &= PP_REFERENCE_DIVIDER_MASK;
593
594 /* 0x1F write to PP_DIV_REG sets max cycle delay */
595 I915_WRITE(pp_div_reg, pp_div | 0x1F);
596 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
597 msleep(intel_dp->panel_power_cycle_delay);
598 }
599
773538e8 600 pps_unlock(intel_dp);
e39b999a 601
01527b31
CT		 602 return 0;
603}
604
4be73780 605static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 606{
30add22d 607 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 608 struct drm_i915_private *dev_priv = dev->dev_private;
609
e39b999a
VS		 610 lockdep_assert_held(&dev_priv->pps_mutex);
611
666a4537 612 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
9a42356b
VS		 613 intel_dp->pps_pipe == INVALID_PIPE)
614 return false;
615
bf13e81b 616 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 617}
618
4be73780 619static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 620{
30add22d 621 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 622 struct drm_i915_private *dev_priv = dev->dev_private;
623
e39b999a
VS		 624 lockdep_assert_held(&dev_priv->pps_mutex);
625
666a4537 626 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
9a42356b
VS		 627 intel_dp->pps_pipe == INVALID_PIPE)
628 return false;
629
773538e8 630 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 631}
632
9b984dae
KP		 633static void
634intel_dp_check_edp(struct intel_dp *intel_dp)
635{
30add22d 636 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 637 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 638
9b984dae
KP		 639 if (!is_edp(intel_dp))
640 return;
453c5420 641
4be73780 642 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 643 WARN(1, "eDP powered off while attempting aux channel communication.\n");
644 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 645 I915_READ(_pp_stat_reg(intel_dp)),
646 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 647 }
648}
649
9ee32fea
DV		 650static uint32_t
651intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
652{
653 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
654 struct drm_device *dev = intel_dig_port->base.base.dev;
655 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 656 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 657 uint32_t status;
658 bool done;
659
ef04f00d 660#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 661 if (has_aux_irq)
b18ac466 662 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 663 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 664 else
665 done = wait_for_atomic(C, 10) == 0;
666 if (!done)
667 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
668 has_aux_irq);
669#undef C
670
671 return status;
672}
673
6ffb1be7 674static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 675{
174edf1f 676 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
e7dc33f3 677 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
9ee32fea 678
a457f54b
VS		 679 if (index)
680 return 0;
681
ec5b01dd
DL		 682 /*
683 * The clock divider is based off the hrawclk, and would like to run at
a457f54b 684 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
a4fc5ed6 685 */
a457f54b 686 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
ec5b01dd
DL		 687}
688
689static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
690{
691 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
a457f54b 692 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
ec5b01dd
DL		 693
694 if (index)
695 return 0;
696
a457f54b
VS		 697 /*
698 * The clock divider is based off the cdclk or PCH rawclk, and would
699 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
700 * divide by 2000 and use that
701 */
e7dc33f3 702 if (intel_dig_port->port == PORT_A)
fce18c4c 703 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
e7dc33f3
VS		 704 else
705 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
ec5b01dd
DL		 706}
707
708static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
709{
710 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
a457f54b 711 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
ec5b01dd 712
a457f54b 713 if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
2c55c336 714 /* Workaround for non-ULT HSW */
bc86625a
CW		 715 switch (index) {
716 case 0: return 63;
717 case 1: return 72;
718 default: return 0;
719 }
2c55c336 720 }
a457f54b
VS		 721
722 return ilk_get_aux_clock_divider(intel_dp, index);
b84a1cf8
RV		 723}
724
b6b5e383
DL		 725static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
726{
727 /*
728 * SKL doesn't need us to program the AUX clock divider (Hardware will
729 * derive the clock from CDCLK automatically). We still implement the
730 * get_aux_clock_divider vfunc to plug-in into the existing code.
731 */
732 return index ? 0 : 1;
733}
734
6ffb1be7
VS		 735static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
736 bool has_aux_irq,
737 int send_bytes,
738 uint32_t aux_clock_divider)
5ed12a19
DL		 739{
740 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
741 struct drm_device *dev = intel_dig_port->base.base.dev;
742 uint32_t precharge, timeout;
743
744 if (IS_GEN6(dev))
745 precharge = 3;
746 else
747 precharge = 5;
748
f3c6a3a7 749 if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A)
5ed12a19
DL		 750 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
751 else
752 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
753
754 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 755 DP_AUX_CH_CTL_DONE |
5ed12a19 756 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 757 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 758 timeout |
788d4433 759 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 760 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
761 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 762 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 763}
764
b9ca5fad
DL		 765static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
766 bool has_aux_irq,
767 int send_bytes,
768 uint32_t unused)
769{
770 return DP_AUX_CH_CTL_SEND_BUSY |
771 DP_AUX_CH_CTL_DONE |
772 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
773 DP_AUX_CH_CTL_TIME_OUT_ERROR |
774 DP_AUX_CH_CTL_TIME_OUT_1600us |
775 DP_AUX_CH_CTL_RECEIVE_ERROR |
776 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
777 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
778}
779
b84a1cf8
RV		 780static int
781intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 782 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 783 uint8_t *recv, int recv_size)
784{
785 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
786 struct drm_device *dev = intel_dig_port->base.base.dev;
787 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 788 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
bc86625a 789 uint32_t aux_clock_divider;
b84a1cf8
RV		 790 int i, ret, recv_bytes;
791 uint32_t status;
5ed12a19 792 int try, clock = 0;
4e6b788c 793 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 794 bool vdd;
795
773538e8 796 pps_lock(intel_dp);
e39b999a 797
72c3500a
VS		 798 /*
799 * We will be called with VDD already enabled for dpcd/edid/oui reads.
800 * In such cases we want to leave VDD enabled and it's up to upper layers
801 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
802 * ourselves.
803 */
1e0560e0 804 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 805
806 /* dp aux is extremely sensitive to irq latency, hence request the
807 * lowest possible wakeup latency and so prevent the cpu from going into
808 * deep sleep states.
809 */
810 pm_qos_update_request(&dev_priv->pm_qos, 0);
811
812 intel_dp_check_edp(intel_dp);
5eb08b69 813
11bee43e
JB		 814 /* Try to wait for any previous AUX channel activity */
815 for (try = 0; try < 3; try++) {
ef04f00d 816 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 817 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
818 break;
819 msleep(1);
820 }
821
822 if (try == 3) {
02196c77
MK		 823 static u32 last_status = -1;
824 const u32 status = I915_READ(ch_ctl);
825
826 if (status != last_status) {
827 WARN(1, "dp_aux_ch not started status 0x%08x\n",
828 status);
829 last_status = status;
830 }
831
9ee32fea
DV		 832 ret = -EBUSY;
833 goto out;
4f7f7b7e
CW		 834 }
835
46a5ae9f
PZ		 836 /* Only 5 data registers! */
837 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
838 ret = -E2BIG;
839 goto out;
840 }
841
ec5b01dd 842 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 843 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
844 has_aux_irq,
845 send_bytes,
846 aux_clock_divider);
5ed12a19 847
bc86625a
CW		 848 /* Must try at least 3 times according to DP spec */
849 for (try = 0; try < 5; try++) {
850 /* Load the send data into the aux channel data registers */
851 for (i = 0; i < send_bytes; i += 4)
330e20ec 852 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
a4f1289e
RV		 853 intel_dp_pack_aux(send + i,
854 send_bytes - i));
bc86625a
CW		 855
856 /* Send the command and wait for it to complete */
5ed12a19 857 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 858
859 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
860
861 /* Clear done status and any errors */
862 I915_WRITE(ch_ctl,
863 status |
864 DP_AUX_CH_CTL_DONE |
865 DP_AUX_CH_CTL_TIME_OUT_ERROR |
866 DP_AUX_CH_CTL_RECEIVE_ERROR);
867
74ebf294 868 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
bc86625a 869 continue;
74ebf294
TP		 870
871 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
872 * 400us delay required for errors and timeouts
873 * Timeout errors from the HW already meet this
874 * requirement so skip to next iteration
875 */
876 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
877 usleep_range(400, 500);
bc86625a 878 continue;
74ebf294 879 }
bc86625a 880 if (status & DP_AUX_CH_CTL_DONE)
e058c945 881 goto done;
bc86625a 882 }
a4fc5ed6
KP		 883 }
884
a4fc5ed6 885 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 886 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 887 ret = -EBUSY;
888 goto out;
a4fc5ed6
KP		 889 }
890
e058c945 891done:
a4fc5ed6
KP		 892 /* Check for timeout or receive error.
893 * Timeouts occur when the sink is not connected
894 */
a5b3da54 895 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 896 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 897 ret = -EIO;
898 goto out;
a5b3da54 899 }
1ae8c0a5
KP		 900
901 /* Timeouts occur when the device isn't connected, so they're
902 * "normal" -- don't fill the kernel log with these */
a5b3da54 903 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 904 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 905 ret = -ETIMEDOUT;
906 goto out;
a4fc5ed6
KP		 907 }
908
909 /* Unload any bytes sent back from the other side */
910 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
911 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
14e01889
RV		 912
913 /*
914 * By BSpec: "Message sizes of 0 or >20 are not allowed."
915 * We have no idea of what happened so we return -EBUSY so
916 * drm layer takes care for the necessary retries.
917 */
918 if (recv_bytes == 0 || recv_bytes > 20) {
919 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
920 recv_bytes);
921 /*
922 * FIXME: This patch was created on top of a series that
923 * organize the retries at drm level. There EBUSY should
924 * also take care for 1ms wait before retrying.
925 * That aux retries re-org is still needed and after that is
926 * merged we remove this sleep from here.
927 */
928 usleep_range(1000, 1500);
929 ret = -EBUSY;
930 goto out;
931 }
932
a4fc5ed6
KP		 933 if (recv_bytes > recv_size)
934 recv_bytes = recv_size;
0206e353 935
4f7f7b7e 936 for (i = 0; i < recv_bytes; i += 4)
330e20ec 937 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
a4f1289e 938 recv + i, recv_bytes - i);
a4fc5ed6 939
9ee32fea
DV		 940 ret = recv_bytes;
941out:
942 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
943
884f19e9
JN		 944 if (vdd)
945 edp_panel_vdd_off(intel_dp, false);
946
773538e8 947 pps_unlock(intel_dp);
e39b999a 948
9ee32fea 949 return ret;
a4fc5ed6
KP		 950}
951
a6c8aff0
JN		 952#define BARE_ADDRESS_SIZE 3
953#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 954static ssize_t
955intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 956{
9d1a1031
JN		 957 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
958 uint8_t txbuf[20], rxbuf[20];
959 size_t txsize, rxsize;
a4fc5ed6 960 int ret;
a4fc5ed6 961
d2d9cbbd
VS		 962 txbuf[0] = (msg->request << 4) |
963 ((msg->address >> 16) & 0xf);
964 txbuf[1] = (msg->address >> 8) & 0xff;
9d1a1031
JN		 965 txbuf[2] = msg->address & 0xff;
966 txbuf[3] = msg->size - 1;
46a5ae9f 967
9d1a1031
JN		 968 switch (msg->request & ~DP_AUX_I2C_MOT) {
969 case DP_AUX_NATIVE_WRITE:
970 case DP_AUX_I2C_WRITE:
c1e74122 971 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
a6c8aff0 972 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
a1ddefd8 973 rxsize = 2; /* 0 or 1 data bytes */
f51a44b9 974
9d1a1031
JN		 975 if (WARN_ON(txsize > 20))
976 return -E2BIG;
a4fc5ed6 977
d81a67cc
ID		 978 if (msg->buffer)
979 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
980 else
981 WARN_ON(msg->size);
a4fc5ed6 982
9d1a1031
JN		 983 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
984 if (ret > 0) {
985 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 986
a1ddefd8
JN		 987 if (ret > 1) {
988 /* Number of bytes written in a short write. */
989 ret = clamp_t(int, rxbuf[1], 0, msg->size);
990 } else {
991 /* Return payload size. */
992 ret = msg->size;
993 }
9d1a1031
JN		 994 }
995 break;
46a5ae9f 996
9d1a1031
JN		 997 case DP_AUX_NATIVE_READ:
998 case DP_AUX_I2C_READ:
a6c8aff0 999 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 1000 rxsize = msg->size + 1;
a4fc5ed6 1001
9d1a1031
JN		 1002 if (WARN_ON(rxsize > 20))
1003 return -E2BIG;
a4fc5ed6 1004
9d1a1031
JN		 1005 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1006 if (ret > 0) {
1007 msg->reply = rxbuf[0] >> 4;
1008 /*
1009 * Assume happy day, and copy the data. The caller is
1010 * expected to check msg->reply before touching it.
1011 *
1012 * Return payload size.
1013 */
1014 ret--;
1015 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 1016 }
9d1a1031
JN		 1017 break;
1018
1019 default:
1020 ret = -EINVAL;
1021 break;
a4fc5ed6 1022 }
f51a44b9 1023
9d1a1031 1024 return ret;
a4fc5ed6
KP		 1025}
1026
f0f59a00
VS		 1027static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1028 enum port port)
da00bdcf
VS		 1029{
1030 switch (port) {
1031 case PORT_B:
1032 case PORT_C:
1033 case PORT_D:
1034 return DP_AUX_CH_CTL(port);
1035 default:
1036 MISSING_CASE(port);
1037 return DP_AUX_CH_CTL(PORT_B);
1038 }
1039}
1040
f0f59a00
VS		 1041static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1042 enum port port, int index)
330e20ec
VS		 1043{
1044 switch (port) {
1045 case PORT_B:
1046 case PORT_C:
1047 case PORT_D:
1048 return DP_AUX_CH_DATA(port, index);
1049 default:
1050 MISSING_CASE(port);
1051 return DP_AUX_CH_DATA(PORT_B, index);
1052 }
1053}
1054
f0f59a00
VS		 1055static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1056 enum port port)
da00bdcf
VS		 1057{
1058 switch (port) {
1059 case PORT_A:
1060 return DP_AUX_CH_CTL(port);
1061 case PORT_B:
1062 case PORT_C:
1063 case PORT_D:
1064 return PCH_DP_AUX_CH_CTL(port);
1065 default:
1066 MISSING_CASE(port);
1067 return DP_AUX_CH_CTL(PORT_A);
1068 }
1069}
1070
f0f59a00
VS		 1071static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1072 enum port port, int index)
330e20ec
VS		 1073{
1074 switch (port) {
1075 case PORT_A:
1076 return DP_AUX_CH_DATA(port, index);
1077 case PORT_B:
1078 case PORT_C:
1079 case PORT_D:
1080 return PCH_DP_AUX_CH_DATA(port, index);
1081 default:
1082 MISSING_CASE(port);
1083 return DP_AUX_CH_DATA(PORT_A, index);
1084 }
1085}
1086
da00bdcf
VS		 1087/*
1088 * On SKL we don't have Aux for port E so we rely
1089 * on VBT to set a proper alternate aux channel.
1090 */
1091static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
1092{
1093 const struct ddi_vbt_port_info *info =
1094 &dev_priv->vbt.ddi_port_info[PORT_E];
1095
1096 switch (info->alternate_aux_channel) {
1097 case DP_AUX_A:
1098 return PORT_A;
1099 case DP_AUX_B:
1100 return PORT_B;
1101 case DP_AUX_C:
1102 return PORT_C;
1103 case DP_AUX_D:
1104 return PORT_D;
1105 default:
1106 MISSING_CASE(info->alternate_aux_channel);
1107 return PORT_A;
1108 }
1109}
1110
f0f59a00
VS		 1111static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1112 enum port port)
da00bdcf
VS		 1113{
1114 if (port == PORT_E)
1115 port = skl_porte_aux_port(dev_priv);
1116
1117 switch (port) {
1118 case PORT_A:
1119 case PORT_B:
1120 case PORT_C:
1121 case PORT_D:
1122 return DP_AUX_CH_CTL(port);
1123 default:
1124 MISSING_CASE(port);
1125 return DP_AUX_CH_CTL(PORT_A);
1126 }
1127}
1128
f0f59a00
VS		 1129static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1130 enum port port, int index)
330e20ec
VS		 1131{
1132 if (port == PORT_E)
1133 port = skl_porte_aux_port(dev_priv);
1134
1135 switch (port) {
1136 case PORT_A:
1137 case PORT_B:
1138 case PORT_C:
1139 case PORT_D:
1140 return DP_AUX_CH_DATA(port, index);
1141 default:
1142 MISSING_CASE(port);
1143 return DP_AUX_CH_DATA(PORT_A, index);
1144 }
1145}
1146
f0f59a00
VS		 1147static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1148 enum port port)
330e20ec
VS		 1149{
1150 if (INTEL_INFO(dev_priv)->gen >= 9)
1151 return skl_aux_ctl_reg(dev_priv, port);
1152 else if (HAS_PCH_SPLIT(dev_priv))
1153 return ilk_aux_ctl_reg(dev_priv, port);
1154 else
1155 return g4x_aux_ctl_reg(dev_priv, port);
1156}
1157
f0f59a00
VS		 1158static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1159 enum port port, int index)
330e20ec
VS		 1160{
1161 if (INTEL_INFO(dev_priv)->gen >= 9)
1162 return skl_aux_data_reg(dev_priv, port, index);
1163 else if (HAS_PCH_SPLIT(dev_priv))
1164 return ilk_aux_data_reg(dev_priv, port, index);
1165 else
1166 return g4x_aux_data_reg(dev_priv, port, index);
1167}
1168
1169static void intel_aux_reg_init(struct intel_dp *intel_dp)
1170{
1171 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1172 enum port port = dp_to_dig_port(intel_dp)->port;
1173 int i;
1174
1175 intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1176 for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1177 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1178}
1179
9d1a1031 1180static void
a121f4e5
VS		 1181intel_dp_aux_fini(struct intel_dp *intel_dp)
1182{
1183 drm_dp_aux_unregister(&intel_dp->aux);
1184 kfree(intel_dp->aux.name);
1185}
1186
1187static int
9d1a1031
JN		 1188intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1189{
33ad6626
JN		 1190 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1191 enum port port = intel_dig_port->port;
ab2c0672
DA		 1192 int ret;
1193
330e20ec 1194 intel_aux_reg_init(intel_dp);
8316f337 1195
a121f4e5
VS		 1196 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1197 if (!intel_dp->aux.name)
1198 return -ENOMEM;
1199
4d32c0d8 1200 intel_dp->aux.dev = connector->base.kdev;
9d1a1031 1201 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 1202
a121f4e5
VS		 1203 DRM_DEBUG_KMS("registering %s bus for %s\n",
1204 intel_dp->aux.name,
0b99836f 1205 connector->base.kdev->kobj.name);
8316f337 1206
4f71d0cb 1207 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 1208 if (ret < 0) {
4f71d0cb 1209 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
a121f4e5
VS		 1210 intel_dp->aux.name, ret);
1211 kfree(intel_dp->aux.name);
1212 return ret;
ab2c0672 1213 }
8a5e6aeb 1214
a121f4e5 1215 return 0;
a4fc5ed6
KP		 1216}
1217
80f65de3
ID		 1218static void
1219intel_dp_connector_unregister(struct intel_connector *intel_connector)
1220{
1221 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1222
4d32c0d8 1223 intel_dp_aux_fini(intel_dp);
80f65de3
ID		 1224 intel_connector_unregister(intel_connector);
1225}
1226
fc0f8e25 1227static int
12f6a2e2 1228intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
fc0f8e25 1229{
94ca719e
VS		 1230 if (intel_dp->num_sink_rates) {
1231 *sink_rates = intel_dp->sink_rates;
1232 return intel_dp->num_sink_rates;
fc0f8e25 1233 }
12f6a2e2
VS		 1234
1235 *sink_rates = default_rates;
1236
1237 return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
fc0f8e25
SJ		 1238}
1239
e588fa18 1240bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
ed63baaf 1241{
e588fa18
ACO		 1242 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1243 struct drm_device *dev = dig_port->base.base.dev;
1244
ed63baaf 1245 /* WaDisableHBR2:skl */
e87a005d 1246 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
ed63baaf
TS		 1247 return false;
1248
1249 if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
1250 (INTEL_INFO(dev)->gen >= 9))
1251 return true;
1252 else
1253 return false;
1254}
1255
a8f3ef61 1256static int
e588fa18 1257intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
a8f3ef61 1258{
e588fa18
ACO		 1259 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1260 struct drm_device *dev = dig_port->base.base.dev;
af7080f5
TS		 1261 int size;
1262
64987fc5
SJ		 1263 if (IS_BROXTON(dev)) {
1264 *source_rates = bxt_rates;
af7080f5 1265 size = ARRAY_SIZE(bxt_rates);
ef11bdb3 1266 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
637a9c63 1267 *source_rates = skl_rates;
af7080f5
TS		 1268 size = ARRAY_SIZE(skl_rates);
1269 } else {
1270 *source_rates = default_rates;
1271 size = ARRAY_SIZE(default_rates);
a8f3ef61 1272 }
636280ba 1273
ed63baaf 1274 /* This depends on the fact that 5.4 is last value in the array */
e588fa18 1275 if (!intel_dp_source_supports_hbr2(intel_dp))
af7080f5 1276 size--;
636280ba 1277
af7080f5 1278 return size;
a8f3ef61
SJ		 1279}
1280
c6bb3538
DV		 1281static void
1282intel_dp_set_clock(struct intel_encoder *encoder,
840b32b7 1283 struct intel_crtc_state *pipe_config)
c6bb3538
DV		 1284{
1285 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1286 const struct dp_link_dpll *divisor = NULL;
1287 int i, count = 0;
c6bb3538
DV		 1288
1289 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1290 divisor = gen4_dpll;
1291 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1292 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1293 divisor = pch_dpll;
1294 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1295 } else if (IS_CHERRYVIEW(dev)) {
1296 divisor = chv_dpll;
1297 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1298 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1299 divisor = vlv_dpll;
1300 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1301 }
9dd4ffdf
CML		 1302
1303 if (divisor && count) {
1304 for (i = 0; i < count; i++) {
840b32b7 1305 if (pipe_config->port_clock == divisor[i].clock) {
9dd4ffdf
CML		 1306 pipe_config->dpll = divisor[i].dpll;
1307 pipe_config->clock_set = true;
1308 break;
1309 }
1310 }
c6bb3538
DV		 1311 }
1312}
1313
2ecae76a
VS		 1314static int intersect_rates(const int *source_rates, int source_len,
1315 const int *sink_rates, int sink_len,
94ca719e 1316 int *common_rates)
a8f3ef61
SJ		 1317{
1318 int i = 0, j = 0, k = 0;
1319
a8f3ef61
SJ		 1320 while (i < source_len && j < sink_len) {
1321 if (source_rates[i] == sink_rates[j]) {
e6bda3e4
VS		 1322 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1323 return k;
94ca719e 1324 common_rates[k] = source_rates[i];
a8f3ef61
SJ		 1325 ++k;
1326 ++i;
1327 ++j;
1328 } else if (source_rates[i] < sink_rates[j]) {
1329 ++i;
1330 } else {
1331 ++j;
1332 }
1333 }
1334 return k;
1335}
1336
94ca719e
VS		 1337static int intel_dp_common_rates(struct intel_dp *intel_dp,
1338 int *common_rates)
2ecae76a 1339{
2ecae76a
VS		 1340 const int *source_rates, *sink_rates;
1341 int source_len, sink_len;
1342
1343 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
e588fa18 1344 source_len = intel_dp_source_rates(intel_dp, &source_rates);
2ecae76a
VS		 1345
1346 return intersect_rates(source_rates, source_len,
1347 sink_rates, sink_len,
94ca719e 1348 common_rates);
2ecae76a
VS		 1349}
1350
0336400e
VS		 1351static void snprintf_int_array(char *str, size_t len,
1352 const int *array, int nelem)
1353{
1354 int i;
1355
1356 str[0] = '\0';
1357
1358 for (i = 0; i < nelem; i++) {
b2f505be 1359 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
0336400e
VS		 1360 if (r >= len)
1361 return;
1362 str += r;
1363 len -= r;
1364 }
1365}
1366
1367static void intel_dp_print_rates(struct intel_dp *intel_dp)
1368{
0336400e 1369 const int *source_rates, *sink_rates;
94ca719e
VS		 1370 int source_len, sink_len, common_len;
1371 int common_rates[DP_MAX_SUPPORTED_RATES];
0336400e
VS		 1372 char str[128]; /* FIXME: too big for stack? */
1373
1374 if ((drm_debug & DRM_UT_KMS) == 0)
1375 return;
1376
e588fa18 1377 source_len = intel_dp_source_rates(intel_dp, &source_rates);
0336400e
VS		 1378 snprintf_int_array(str, sizeof(str), source_rates, source_len);
1379 DRM_DEBUG_KMS("source rates: %s\n", str);
1380
1381 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1382 snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1383 DRM_DEBUG_KMS("sink rates: %s\n", str);
1384
94ca719e
VS		 1385 common_len = intel_dp_common_rates(intel_dp, common_rates);
1386 snprintf_int_array(str, sizeof(str), common_rates, common_len);
1387 DRM_DEBUG_KMS("common rates: %s\n", str);
0336400e
VS		 1388}
1389
f4896f15 1390static int rate_to_index(int find, const int *rates)
a8f3ef61
SJ		 1391{
1392 int i = 0;
1393
1394 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1395 if (find == rates[i])
1396 break;
1397
1398 return i;
1399}
1400
50fec21a
VS		 1401int
1402intel_dp_max_link_rate(struct intel_dp *intel_dp)
1403{
1404 int rates[DP_MAX_SUPPORTED_RATES] = {};
1405 int len;
1406
94ca719e 1407 len = intel_dp_common_rates(intel_dp, rates);
50fec21a
VS		 1408 if (WARN_ON(len <= 0))
1409 return 162000;
1410
1411 return rates[rate_to_index(0, rates) - 1];
1412}
1413
ed4e9c1d
VS		 1414int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1415{
94ca719e 1416 return rate_to_index(rate, intel_dp->sink_rates);
ed4e9c1d
VS		 1417}
1418
94223d04
ACO		 1419void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1420 uint8_t *link_bw, uint8_t *rate_select)
04a60f9f
VS		 1421{
1422 if (intel_dp->num_sink_rates) {
1423 *link_bw = 0;
1424 *rate_select =
1425 intel_dp_rate_select(intel_dp, port_clock);
1426 } else {
1427 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1428 *rate_select = 0;
1429 }
1430}
1431
00c09d70 1432bool
5bfe2ac0 1433intel_dp_compute_config(struct intel_encoder *encoder,
5cec258b 1434 struct intel_crtc_state *pipe_config)
a4fc5ed6 1435{
5bfe2ac0 1436 struct drm_device *dev = encoder->base.dev;
36008365 1437 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 1438 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5bfe2ac0 1439 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1440 enum port port = dp_to_dig_port(intel_dp)->port;
84556d58 1441 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
dd06f90e 1442 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1443 int lane_count, clock;
56071a20 1444 int min_lane_count = 1;
eeb6324d 1445 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1446 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1447 int min_clock = 0;
a8f3ef61 1448 int max_clock;
083f9560 1449 int bpp, mode_rate;
ff9a6750 1450 int link_avail, link_clock;
94ca719e
VS		 1451 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1452 int common_len;
04a60f9f 1453 uint8_t link_bw, rate_select;
a8f3ef61 1454
94ca719e 1455 common_len = intel_dp_common_rates(intel_dp, common_rates);
a8f3ef61
SJ		 1456
1457 /* No common link rates between source and sink */
94ca719e 1458 WARN_ON(common_len <= 0);
a8f3ef61 1459
94ca719e 1460 max_clock = common_len - 1;
a4fc5ed6 1461
bc7d38a4 1462 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1463 pipe_config->has_pch_encoder = true;
1464
03afc4a2 1465 pipe_config->has_dp_encoder = true;
f769cd24 1466 pipe_config->has_drrs = false;
9fcb1704 1467 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
a4fc5ed6 1468
dd06f90e
JN		 1469 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1470 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1471 adjusted_mode);
a1b2278e
CK		 1472
1473 if (INTEL_INFO(dev)->gen >= 9) {
1474 int ret;
e435d6e5 1475 ret = skl_update_scaler_crtc(pipe_config);
a1b2278e
CK		 1476 if (ret)
1477 return ret;
1478 }
1479
b5667627 1480 if (HAS_GMCH_DISPLAY(dev))
2dd24552
JB		 1481 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1482 intel_connector->panel.fitting_mode);
1483 else
b074cec8
JB		 1484 intel_pch_panel_fitting(intel_crtc, pipe_config,
1485 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1486 }
1487
cb1793ce 1488 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1489 return false;
1490
083f9560 1491 DRM_DEBUG_KMS("DP link computation with max lane count %i "
a8f3ef61 1492 "max bw %d pixel clock %iKHz\n",
94ca719e 1493 max_lane_count, common_rates[max_clock],
241bfc38 1494 adjusted_mode->crtc_clock);
083f9560 1495
36008365
DV		 1496 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1497 * bpc in between. */
3e7ca985 1498 bpp = pipe_config->pipe_bpp;
56071a20 1499 if (is_edp(intel_dp)) {
22ce5628
TS		 1500
1501 /* Get bpp from vbt only for panels that dont have bpp in edid */
1502 if (intel_connector->base.display_info.bpc == 0 &&
1503 (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp)) {
56071a20
JN		 1504 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1505 dev_priv->vbt.edp_bpp);
1506 bpp = dev_priv->vbt.edp_bpp;
1507 }
1508
344c5bbc
JN		 1509 /*
1510 * Use the maximum clock and number of lanes the eDP panel
1511 * advertizes being capable of. The panels are generally
1512 * designed to support only a single clock and lane
1513 * configuration, and typically these values correspond to the
1514 * native resolution of the panel.
1515 */
1516 min_lane_count = max_lane_count;
1517 min_clock = max_clock;
7984211e 1518 }
657445fe 1519
36008365 1520 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1521 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1522 bpp);
36008365 1523
c6930992 1524 for (clock = min_clock; clock <= max_clock; clock++) {
a8f3ef61
SJ		 1525 for (lane_count = min_lane_count;
1526 lane_count <= max_lane_count;
1527 lane_count <<= 1) {
1528
94ca719e 1529 link_clock = common_rates[clock];
36008365
DV		 1530 link_avail = intel_dp_max_data_rate(link_clock,
1531 lane_count);
1532
1533 if (mode_rate <= link_avail) {
1534 goto found;
1535 }
1536 }
1537 }
1538 }
c4867936 1539
36008365 1540 return false;
3685a8f3 1541
36008365 1542found:
55bc60db
VS		 1543 if (intel_dp->color_range_auto) {
1544 /*
1545 * See:
1546 * CEA-861-E - 5.1 Default Encoding Parameters
1547 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1548 */
0f2a2a75
VS		 1549 pipe_config->limited_color_range =
1550 bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1551 } else {
1552 pipe_config->limited_color_range =
1553 intel_dp->limited_color_range;
55bc60db
VS		 1554 }
1555
90a6b7b0 1556 pipe_config->lane_count = lane_count;
a8f3ef61 1557
657445fe 1558 pipe_config->pipe_bpp = bpp;
94ca719e 1559 pipe_config->port_clock = common_rates[clock];
a4fc5ed6 1560
04a60f9f
VS		 1561 intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1562 &link_bw, &rate_select);
1563
1564 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1565 link_bw, rate_select, pipe_config->lane_count,
ff9a6750 1566 pipe_config->port_clock, bpp);
36008365
DV		 1567 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1568 mode_rate, link_avail);
a4fc5ed6 1569
03afc4a2 1570 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1571 adjusted_mode->crtc_clock,
1572 pipe_config->port_clock,
03afc4a2 1573 &pipe_config->dp_m_n);
9d1a455b 1574
439d7ac0 1575 if (intel_connector->panel.downclock_mode != NULL &&
96178eeb 1576 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1577 pipe_config->has_drrs = true;
439d7ac0
PB		 1578 intel_link_compute_m_n(bpp, lane_count,
1579 intel_connector->panel.downclock_mode->clock,
1580 pipe_config->port_clock,
1581 &pipe_config->dp_m2_n2);
1582 }
1583
a3c988ea 1584 if (!HAS_DDI(dev))
840b32b7 1585 intel_dp_set_clock(encoder, pipe_config);
c6bb3538 1586
03afc4a2 1587 return true;
a4fc5ed6
KP		 1588}
1589
901c2daf
VS		 1590void intel_dp_set_link_params(struct intel_dp *intel_dp,
1591 const struct intel_crtc_state *pipe_config)
1592{
1593 intel_dp->link_rate = pipe_config->port_clock;
1594 intel_dp->lane_count = pipe_config->lane_count;
1595}
1596
8ac33ed3 1597static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1598{
b934223d 1599 struct drm_device *dev = encoder->base.dev;
417e822d 1600 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1601 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1602 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d 1603 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
7c5f93b0 1604 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
a4fc5ed6 1605
901c2daf
VS		 1606 intel_dp_set_link_params(intel_dp, crtc->config);
1607
417e822d 1608 /*
1a2eb460 1609 * There are four kinds of DP registers:
417e822d
KP		 1610 *
1611 * IBX PCH
1a2eb460
KP		 1612 * SNB CPU
1613 * IVB CPU
417e822d
KP		 1614 * CPT PCH
1615 *
1616 * IBX PCH and CPU are the same for almost everything,
1617 * except that the CPU DP PLL is configured in this
1618 * register
1619 *
1620 * CPT PCH is quite different, having many bits moved
1621 * to the TRANS_DP_CTL register instead. That
1622 * configuration happens (oddly) in ironlake_pch_enable
1623 */
9c9e7927 1624
417e822d
KP		 1625 /* Preserve the BIOS-computed detected bit. This is
1626 * supposed to be read-only.
1627 */
1628 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1629
417e822d 1630 /* Handle DP bits in common between all three register formats */
417e822d 1631 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
90a6b7b0 1632 intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);
a4fc5ed6 1633
417e822d 1634 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1635
39e5fa88 1636 if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 1637 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1638 intel_dp->DP |= DP_SYNC_HS_HIGH;
1639 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1640 intel_dp->DP |= DP_SYNC_VS_HIGH;
1641 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1642
6aba5b6c 1643 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1644 intel_dp->DP |= DP_ENHANCED_FRAMING;
1645
7c62a164 1646 intel_dp->DP |= crtc->pipe << 29;
39e5fa88 1647 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
e3ef4479
VS		 1648 u32 trans_dp;
1649
39e5fa88 1650 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
e3ef4479
VS		 1651
1652 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1653 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1654 trans_dp |= TRANS_DP_ENH_FRAMING;
1655 else
1656 trans_dp &= ~TRANS_DP_ENH_FRAMING;
1657 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
39e5fa88 1658 } else {
0f2a2a75 1659 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
666a4537 1660 !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range)
0f2a2a75 1661 intel_dp->DP |= DP_COLOR_RANGE_16_235;
417e822d
KP		 1662
1663 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1664 intel_dp->DP |= DP_SYNC_HS_HIGH;
1665 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1666 intel_dp->DP |= DP_SYNC_VS_HIGH;
1667 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1668
6aba5b6c 1669 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1670 intel_dp->DP |= DP_ENHANCED_FRAMING;
1671
39e5fa88 1672 if (IS_CHERRYVIEW(dev))
44f37d1f 1673 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
39e5fa88
VS		 1674 else if (crtc->pipe == PIPE_B)
1675 intel_dp->DP |= DP_PIPEB_SELECT;
32f9d658 1676 }
a4fc5ed6
KP		 1677}
1678
ffd6749d
PZ		 1679#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1680#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1681
1a5ef5b7
PZ		 1682#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1683#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1684
ffd6749d
PZ		 1685#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1686#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1687
4be73780 1688static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1689 u32 mask,
1690 u32 value)
bd943159 1691{
30add22d 1692 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1693 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 1694 i915_reg_t pp_stat_reg, pp_ctrl_reg;
453c5420 1695
e39b999a
VS		 1696 lockdep_assert_held(&dev_priv->pps_mutex);
1697
bf13e81b
JN		 1698 pp_stat_reg = _pp_stat_reg(intel_dp);
1699 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1700
99ea7127 1701 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1702 mask, value,
1703 I915_READ(pp_stat_reg),
1704 I915_READ(pp_ctrl_reg));
32ce697c 1705
3f177625
TU		 1706 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value,
1707 5 * USEC_PER_SEC, 10 * USEC_PER_MSEC))
99ea7127 1708 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1709 I915_READ(pp_stat_reg),
1710 I915_READ(pp_ctrl_reg));
54c136d4
CW		 1711
1712 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1713}
32ce697c 1714
4be73780 1715static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1716{
1717 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1718 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1719}
1720
4be73780 1721static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1722{
1723 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1724 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1725}
1726
4be73780 1727static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127 1728{
d28d4731
AK		 1729 ktime_t panel_power_on_time;
1730 s64 panel_power_off_duration;
1731
99ea7127 1732 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c 1733
d28d4731
AK		 1734 /* take the difference of currrent time and panel power off time
1735 * and then make panel wait for t11_t12 if needed. */
1736 panel_power_on_time = ktime_get_boottime();
1737 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1738
dce56b3c
PZ		 1739 /* When we disable the VDD override bit last we have to do the manual
1740 * wait. */
d28d4731
AK		 1741 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1742 wait_remaining_ms_from_jiffies(jiffies,
1743 intel_dp->panel_power_cycle_delay - panel_power_off_duration);
dce56b3c 1744
4be73780 1745 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1746}
1747
4be73780 1748static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1749{
1750 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1751 intel_dp->backlight_on_delay);
1752}
1753
4be73780 1754static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1755{
1756 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1757 intel_dp->backlight_off_delay);
1758}
99ea7127 1759
832dd3c1
KP		 1760/* Read the current pp_control value, unlocking the register if it
1761 * is locked
1762 */
1763
453c5420 1764static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1765{
453c5420
JB		 1766 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1767 struct drm_i915_private *dev_priv = dev->dev_private;
1768 u32 control;
832dd3c1 1769
e39b999a
VS		 1770 lockdep_assert_held(&dev_priv->pps_mutex);
1771
bf13e81b 1772 control = I915_READ(_pp_ctrl_reg(intel_dp));
b0a08bec
VK		 1773 if (!IS_BROXTON(dev)) {
1774 control &= ~PANEL_UNLOCK_MASK;
1775 control |= PANEL_UNLOCK_REGS;
1776 }
832dd3c1 1777 return control;
bd943159
KP		 1778}
1779
951468f3
VS		 1780/*
1781 * Must be paired with edp_panel_vdd_off().
1782 * Must hold pps_mutex around the whole on/off sequence.
1783 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1784 */
1e0560e0 1785static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1786{
30add22d 1787 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1788 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1789 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1790 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1791 enum intel_display_power_domain power_domain;
5d613501 1792 u32 pp;
f0f59a00 1793 i915_reg_t pp_stat_reg, pp_ctrl_reg;
adddaaf4 1794 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1795
e39b999a
VS		 1796 lockdep_assert_held(&dev_priv->pps_mutex);
1797
97af61f5 1798 if (!is_edp(intel_dp))
adddaaf4 1799 return false;
bd943159 1800
2c623c11 1801 cancel_delayed_work(&intel_dp->panel_vdd_work);
bd943159 1802 intel_dp->want_panel_vdd = true;
99ea7127 1803
4be73780 1804 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1805 return need_to_disable;
b0665d57 1806
25f78f58 1807 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4e6e1a54 1808 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1809
3936fcf4
VS		 1810 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1811 port_name(intel_dig_port->port));
bd943159 1812
4be73780
DV		 1813 if (!edp_have_panel_power(intel_dp))
1814 wait_panel_power_cycle(intel_dp);
99ea7127 1815
453c5420 1816 pp = ironlake_get_pp_control(intel_dp);
5d613501 1817 pp |= EDP_FORCE_VDD;
ebf33b18 1818
bf13e81b
JN		 1819 pp_stat_reg = _pp_stat_reg(intel_dp);
1820 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1821
1822 I915_WRITE(pp_ctrl_reg, pp);
1823 POSTING_READ(pp_ctrl_reg);
1824 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1825 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1826 /*
1827 * If the panel wasn't on, delay before accessing aux channel
1828 */
4be73780 1829 if (!edp_have_panel_power(intel_dp)) {
3936fcf4
VS		 1830 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1831 port_name(intel_dig_port->port));
f01eca2e 1832 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1833 }
adddaaf4
JN		 1834
1835 return need_to_disable;
1836}
1837
951468f3
VS		 1838/*
1839 * Must be paired with intel_edp_panel_vdd_off() or
1840 * intel_edp_panel_off().
1841 * Nested calls to these functions are not allowed since
1842 * we drop the lock. Caller must use some higher level
1843 * locking to prevent nested calls from other threads.
1844 */
b80d6c78 1845void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1846{
c695b6b6 1847 bool vdd;
adddaaf4 1848
c695b6b6
VS		 1849 if (!is_edp(intel_dp))
1850 return;
1851
773538e8 1852 pps_lock(intel_dp);
c695b6b6 1853 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1854 pps_unlock(intel_dp);
c695b6b6 1855
e2c719b7 1856 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
3936fcf4 1857 port_name(dp_to_dig_port(intel_dp)->port));
5d613501
JB		 1858}
1859
4be73780 1860static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1861{
30add22d 1862 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1863 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1864 struct intel_digital_port *intel_dig_port =
1865 dp_to_dig_port(intel_dp);
1866 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1867 enum intel_display_power_domain power_domain;
5d613501 1868 u32 pp;
f0f59a00 1869 i915_reg_t pp_stat_reg, pp_ctrl_reg;
5d613501 1870
e39b999a 1871 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1872
15e899a0 1873 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1874
15e899a0 1875 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1876 return;
b0665d57 1877
3936fcf4
VS		 1878 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1879 port_name(intel_dig_port->port));
bd943159 1880
be2c9196
VS		 1881 pp = ironlake_get_pp_control(intel_dp);
1882 pp &= ~EDP_FORCE_VDD;
453c5420 1883
be2c9196
VS		 1884 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1885 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1886
be2c9196
VS		 1887 I915_WRITE(pp_ctrl_reg, pp);
1888 POSTING_READ(pp_ctrl_reg);
90791a5c 1889
be2c9196
VS		 1890 /* Make sure sequencer is idle before allowing subsequent activity */
1891 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1892 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1893
be2c9196 1894 if ((pp & POWER_TARGET_ON) == 0)
d28d4731 1895 intel_dp->panel_power_off_time = ktime_get_boottime();
e9cb81a2 1896
25f78f58 1897 power_domain = intel_display_port_aux_power_domain(intel_encoder);
be2c9196 1898 intel_display_power_put(dev_priv, power_domain);
bd943159 1899}
5d613501 1900
4be73780 1901static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1902{
1903 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1904 struct intel_dp, panel_vdd_work);
bd943159 1905
773538e8 1906 pps_lock(intel_dp);
15e899a0
VS		 1907 if (!intel_dp->want_panel_vdd)
1908 edp_panel_vdd_off_sync(intel_dp);
773538e8 1909 pps_unlock(intel_dp);
bd943159
KP		 1910}
1911
aba86890
ID		 1912static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1913{
1914 unsigned long delay;
1915
1916 /*
1917 * Queue the timer to fire a long time from now (relative to the power
1918 * down delay) to keep the panel power up across a sequence of
1919 * operations.
1920 */
1921 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1922 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1923}
1924
951468f3
VS		 1925/*
1926 * Must be paired with edp_panel_vdd_on().
1927 * Must hold pps_mutex around the whole on/off sequence.
1928 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1929 */
4be73780 1930static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1931{
e39b999a
VS		 1932 struct drm_i915_private *dev_priv =
1933 intel_dp_to_dev(intel_dp)->dev_private;
1934
1935 lockdep_assert_held(&dev_priv->pps_mutex);
1936
97af61f5
KP		 1937 if (!is_edp(intel_dp))
1938 return;
5d613501 1939
e2c719b7 1940 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
3936fcf4 1941 port_name(dp_to_dig_port(intel_dp)->port));
f2e8b18a 1942
bd943159
KP		 1943 intel_dp->want_panel_vdd = false;
1944
aba86890 1945 if (sync)
4be73780 1946 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1947 else
1948 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1949}
1950
9f0fb5be 1951static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 1952{
30add22d 1953 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1954 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1955 u32 pp;
f0f59a00 1956 i915_reg_t pp_ctrl_reg;
9934c132 1957
9f0fb5be
VS		 1958 lockdep_assert_held(&dev_priv->pps_mutex);
1959
97af61f5 1960 if (!is_edp(intel_dp))
bd943159 1961 return;
99ea7127 1962
3936fcf4
VS		 1963 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1964 port_name(dp_to_dig_port(intel_dp)->port));
e39b999a 1965
e7a89ace
VS		 1966 if (WARN(edp_have_panel_power(intel_dp),
1967 "eDP port %c panel power already on\n",
1968 port_name(dp_to_dig_port(intel_dp)->port)))
9f0fb5be 1969 return;
9934c132 1970
4be73780 1971 wait_panel_power_cycle(intel_dp);
37c6c9b0 1972
bf13e81b 1973 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1974 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1975 if (IS_GEN5(dev)) {
1976 /* ILK workaround: disable reset around power sequence */
1977 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1978 I915_WRITE(pp_ctrl_reg, pp);
1979 POSTING_READ(pp_ctrl_reg);
05ce1a49 1980 }
37c6c9b0 1981
1c0ae80a 1982 pp |= POWER_TARGET_ON;
99ea7127
KP		 1983 if (!IS_GEN5(dev))
1984 pp |= PANEL_POWER_RESET;
1985
453c5420
JB		 1986 I915_WRITE(pp_ctrl_reg, pp);
1987 POSTING_READ(pp_ctrl_reg);
9934c132 1988
4be73780 1989 wait_panel_on(intel_dp);
dce56b3c 1990 intel_dp->last_power_on = jiffies;
9934c132 1991
05ce1a49
KP		 1992 if (IS_GEN5(dev)) {
1993 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1994 I915_WRITE(pp_ctrl_reg, pp);
1995 POSTING_READ(pp_ctrl_reg);
05ce1a49 1996 }
9f0fb5be 1997}
e39b999a 1998
9f0fb5be
VS		 1999void intel_edp_panel_on(struct intel_dp *intel_dp)
2000{
2001 if (!is_edp(intel_dp))
2002 return;
2003
2004 pps_lock(intel_dp);
2005 edp_panel_on(intel_dp);
773538e8 2006 pps_unlock(intel_dp);
9934c132
JB		 2007}
2008
9f0fb5be
VS		 2009
2010static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 2011{
4e6e1a54
ID		 2012 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2013 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 2014 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 2015 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 2016 enum intel_display_power_domain power_domain;
99ea7127 2017 u32 pp;
f0f59a00 2018 i915_reg_t pp_ctrl_reg;
9934c132 2019
9f0fb5be
VS		 2020 lockdep_assert_held(&dev_priv->pps_mutex);
2021
97af61f5
KP		 2022 if (!is_edp(intel_dp))
2023 return;
37c6c9b0 2024
3936fcf4
VS		 2025 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2026 port_name(dp_to_dig_port(intel_dp)->port));
37c6c9b0 2027
3936fcf4
VS		 2028 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2029 port_name(dp_to_dig_port(intel_dp)->port));
24f3e092 2030
453c5420 2031 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 2032 /* We need to switch off panel power _and_ force vdd, for otherwise some
2033 * panels get very unhappy and cease to work. */
b3064154
PJ		 2034 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2035 EDP_BLC_ENABLE);
453c5420 2036
bf13e81b 2037 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 2038
849e39f5
PZ		 2039 intel_dp->want_panel_vdd = false;
2040
453c5420
JB		 2041 I915_WRITE(pp_ctrl_reg, pp);
2042 POSTING_READ(pp_ctrl_reg);
9934c132 2043
d28d4731 2044 intel_dp->panel_power_off_time = ktime_get_boottime();
4be73780 2045 wait_panel_off(intel_dp);
849e39f5
PZ		 2046
2047 /* We got a reference when we enabled the VDD. */
25f78f58 2048 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4e6e1a54 2049 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 2050}
e39b999a 2051
9f0fb5be
VS		 2052void intel_edp_panel_off(struct intel_dp *intel_dp)
2053{
2054 if (!is_edp(intel_dp))
2055 return;
e39b999a 2056
9f0fb5be
VS		 2057 pps_lock(intel_dp);
2058 edp_panel_off(intel_dp);
773538e8 2059 pps_unlock(intel_dp);
9934c132
JB		 2060}
2061
1250d107
JN		 2062/* Enable backlight in the panel power control. */
2063static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 2064{
da63a9f2
PZ		 2065 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2066 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 2067 struct drm_i915_private *dev_priv = dev->dev_private;
2068 u32 pp;
f0f59a00 2069 i915_reg_t pp_ctrl_reg;
32f9d658 2070
01cb9ea6
JB		 2071 /*
2072 * If we enable the backlight right away following a panel power
2073 * on, we may see slight flicker as the panel syncs with the eDP
2074 * link. So delay a bit to make sure the image is solid before
2075 * allowing it to appear.
2076 */
4be73780 2077 wait_backlight_on(intel_dp);
e39b999a 2078
773538e8 2079 pps_lock(intel_dp);
e39b999a 2080
453c5420 2081 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2082 pp |= EDP_BLC_ENABLE;
453c5420 2083
bf13e81b 2084 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2085
2086 I915_WRITE(pp_ctrl_reg, pp);
2087 POSTING_READ(pp_ctrl_reg);
e39b999a 2088
773538e8 2089 pps_unlock(intel_dp);
32f9d658
ZW		 2090}
2091
1250d107
JN		 2092/* Enable backlight PWM and backlight PP control. */
2093void intel_edp_backlight_on(struct intel_dp *intel_dp)
2094{
2095 if (!is_edp(intel_dp))
2096 return;
2097
2098 DRM_DEBUG_KMS("\n");
2099
2100 intel_panel_enable_backlight(intel_dp->attached_connector);
2101 _intel_edp_backlight_on(intel_dp);
2102}
2103
2104/* Disable backlight in the panel power control. */
2105static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 2106{
30add22d 2107 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 2108 struct drm_i915_private *dev_priv = dev->dev_private;
2109 u32 pp;
f0f59a00 2110 i915_reg_t pp_ctrl_reg;
32f9d658 2111
f01eca2e
KP		 2112 if (!is_edp(intel_dp))
2113 return;
2114
773538e8 2115 pps_lock(intel_dp);
e39b999a 2116
453c5420 2117 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2118 pp &= ~EDP_BLC_ENABLE;
453c5420 2119
bf13e81b 2120 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2121
2122 I915_WRITE(pp_ctrl_reg, pp);
2123 POSTING_READ(pp_ctrl_reg);
f7d2323c 2124
773538e8 2125 pps_unlock(intel_dp);
e39b999a
VS		 2126
2127 intel_dp->last_backlight_off = jiffies;
f7d2323c 2128 edp_wait_backlight_off(intel_dp);
1250d107 2129}
f7d2323c 2130
1250d107
JN		 2131/* Disable backlight PP control and backlight PWM. */
2132void intel_edp_backlight_off(struct intel_dp *intel_dp)
2133{
2134 if (!is_edp(intel_dp))
2135 return;
2136
2137 DRM_DEBUG_KMS("\n");
f7d2323c 2138
1250d107 2139 _intel_edp_backlight_off(intel_dp);
f7d2323c 2140 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 2141}
a4fc5ed6 2142
73580fb7
JN		 2143/*
2144 * Hook for controlling the panel power control backlight through the bl_power
2145 * sysfs attribute. Take care to handle multiple calls.
2146 */
2147static void intel_edp_backlight_power(struct intel_connector *connector,
2148 bool enable)
2149{
2150 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 2151 bool is_enabled;
2152
773538e8 2153 pps_lock(intel_dp);
e39b999a 2154 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 2155 pps_unlock(intel_dp);
73580fb7
JN		 2156
2157 if (is_enabled == enable)
2158 return;
2159
23ba9373
JN		 2160 DRM_DEBUG_KMS("panel power control backlight %s\n",
2161 enable ? "enable" : "disable");
73580fb7
JN		 2162
2163 if (enable)
2164 _intel_edp_backlight_on(intel_dp);
2165 else
2166 _intel_edp_backlight_off(intel_dp);
2167}
2168
64e1077a
VS		 2169static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2170{
2171 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2172 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2173 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2174
2175 I915_STATE_WARN(cur_state != state,
2176 "DP port %c state assertion failure (expected %s, current %s)\n",
2177 port_name(dig_port->port),
87ad3212 2178 onoff(state), onoff(cur_state));
64e1077a
VS		 2179}
2180#define assert_dp_port_disabled(d) assert_dp_port((d), false)
2181
2182static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2183{
2184 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2185
2186 I915_STATE_WARN(cur_state != state,
2187 "eDP PLL state assertion failure (expected %s, current %s)\n",
87ad3212 2188 onoff(state), onoff(cur_state));
64e1077a
VS		 2189}
2190#define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2191#define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2192
2bd2ad64 2193static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 2194{
da63a9f2 2195 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
64e1077a
VS		 2196 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2197 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
d240f20f 2198
64e1077a
VS		 2199 assert_pipe_disabled(dev_priv, crtc->pipe);
2200 assert_dp_port_disabled(intel_dp);
2201 assert_edp_pll_disabled(dev_priv);
2bd2ad64 2202
abfce949
VS		 2203 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2204 crtc->config->port_clock);
2205
2206 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2207
2208 if (crtc->config->port_clock == 162000)
2209 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2210 else
2211 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2212
2213 I915_WRITE(DP_A, intel_dp->DP);
2214 POSTING_READ(DP_A);
2215 udelay(500);
2216
0767935e 2217 intel_dp->DP |= DP_PLL_ENABLE;
6fec7662 2218
0767935e 2219 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 2220 POSTING_READ(DP_A);
2221 udelay(200);
d240f20f
JB		 2222}
2223
2bd2ad64 2224static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 2225{
da63a9f2 2226 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
64e1077a
VS		 2227 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2228 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
d240f20f 2229
64e1077a
VS		 2230 assert_pipe_disabled(dev_priv, crtc->pipe);
2231 assert_dp_port_disabled(intel_dp);
2232 assert_edp_pll_enabled(dev_priv);
2bd2ad64 2233
abfce949
VS		 2234 DRM_DEBUG_KMS("disabling eDP PLL\n");
2235
6fec7662 2236 intel_dp->DP &= ~DP_PLL_ENABLE;
0767935e 2237
6fec7662 2238 I915_WRITE(DP_A, intel_dp->DP);
1af5fa1b 2239 POSTING_READ(DP_A);
d240f20f
JB		 2240 udelay(200);
2241}
2242
c7ad3810 2243/* If the sink supports it, try to set the power state appropriately */
c19b0669 2244void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 2245{
2246 int ret, i;
2247
2248 /* Should have a valid DPCD by this point */
2249 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2250 return;
2251
2252 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 2253 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2254 DP_SET_POWER_D3);
c7ad3810
JB		 2255 } else {
2256 /*
2257 * When turning on, we need to retry for 1ms to give the sink
2258 * time to wake up.
2259 */
2260 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2261 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2262 DP_SET_POWER_D0);
c7ad3810
JB		 2263 if (ret == 1)
2264 break;
2265 msleep(1);
2266 }
2267 }
f9cac721
JN		 2268
2269 if (ret != 1)
2270 DRM_DEBUG_KMS("failed to %s sink power state\n",
2271 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 2272}
2273
19d8fe15
DV		 2274static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2275 enum pipe *pipe)
d240f20f 2276{
19d8fe15 2277 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2278 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 2279 struct drm_device *dev = encoder->base.dev;
2280 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 2281 enum intel_display_power_domain power_domain;
2282 u32 tmp;
6fa9a5ec 2283 bool ret;
6d129bea
ID		 2284
2285 power_domain = intel_display_port_power_domain(encoder);
6fa9a5ec 2286 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
6d129bea
ID		 2287 return false;
2288
6fa9a5ec
ID		 2289 ret = false;
2290
6d129bea 2291 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 2292
2293 if (!(tmp & DP_PORT_EN))
6fa9a5ec 2294 goto out;
19d8fe15 2295
39e5fa88 2296 if (IS_GEN7(dev) && port == PORT_A) {
19d8fe15 2297 *pipe = PORT_TO_PIPE_CPT(tmp);
39e5fa88 2298 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
adc289d7 2299 enum pipe p;
19d8fe15 2300
adc289d7
VS		 2301 for_each_pipe(dev_priv, p) {
2302 u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2303 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2304 *pipe = p;
6fa9a5ec
ID		 2305 ret = true;
2306
2307 goto out;
19d8fe15
DV		 2308 }
2309 }
19d8fe15 2310
4a0833ec 2311 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
f0f59a00 2312 i915_mmio_reg_offset(intel_dp->output_reg));
39e5fa88
VS		 2313 } else if (IS_CHERRYVIEW(dev)) {
2314 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2315 } else {
2316 *pipe = PORT_TO_PIPE(tmp);
4a0833ec 2317 }
d240f20f 2318
6fa9a5ec
ID		 2319 ret = true;
2320
2321out:
2322 intel_display_power_put(dev_priv, power_domain);
2323
2324 return ret;
19d8fe15 2325}
d240f20f 2326
045ac3b5 2327static void intel_dp_get_config(struct intel_encoder *encoder,
5cec258b 2328 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2329{
2330 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 2331 u32 tmp, flags = 0;
63000ef6
XZ		 2332 struct drm_device *dev = encoder->base.dev;
2333 struct drm_i915_private *dev_priv = dev->dev_private;
2334 enum port port = dp_to_dig_port(intel_dp)->port;
2335 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
045ac3b5 2336
9ed109a7 2337 tmp = I915_READ(intel_dp->output_reg);
9fcb1704
JN		 2338
2339 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
9ed109a7 2340
39e5fa88 2341 if (HAS_PCH_CPT(dev) && port != PORT_A) {
b81e34c2
VS		 2342 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2343
2344 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2345 flags |= DRM_MODE_FLAG_PHSYNC;
2346 else
2347 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2348
b81e34c2 2349 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2350 flags |= DRM_MODE_FLAG_PVSYNC;
2351 else
2352 flags |= DRM_MODE_FLAG_NVSYNC;
2353 } else {
39e5fa88 2354 if (tmp & DP_SYNC_HS_HIGH)
63000ef6
XZ		 2355 flags |= DRM_MODE_FLAG_PHSYNC;
2356 else
2357 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2358
39e5fa88 2359 if (tmp & DP_SYNC_VS_HIGH)
63000ef6
XZ		 2360 flags |= DRM_MODE_FLAG_PVSYNC;
2361 else
2362 flags |= DRM_MODE_FLAG_NVSYNC;
2363 }
045ac3b5 2364
2d112de7 2365 pipe_config->base.adjusted_mode.flags |= flags;
f1f644dc 2366
8c875fca 2367 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
666a4537 2368 !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
8c875fca
VS		 2369 pipe_config->limited_color_range = true;
2370
eb14cb74
VS		 2371 pipe_config->has_dp_encoder = true;
2372
90a6b7b0
VS		 2373 pipe_config->lane_count =
2374 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2375
eb14cb74
VS		 2376 intel_dp_get_m_n(crtc, pipe_config);
2377
18442d08 2378 if (port == PORT_A) {
b377e0df 2379 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
f1f644dc
JB		 2380 pipe_config->port_clock = 162000;
2381 else
2382 pipe_config->port_clock = 270000;
2383 }
18442d08 2384
e3b247da
VS		 2385 pipe_config->base.adjusted_mode.crtc_clock =
2386 intel_dotclock_calculate(pipe_config->port_clock,
2387 &pipe_config->dp_m_n);
7f16e5c1 2388
c6cd2ee2
JN		 2389 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2390 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2391 /*
2392 * This is a big fat ugly hack.
2393 *
2394 * Some machines in UEFI boot mode provide us a VBT that has 18
2395 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2396 * unknown we fail to light up. Yet the same BIOS boots up with
2397 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2398 * max, not what it tells us to use.
2399 *
2400 * Note: This will still be broken if the eDP panel is not lit
2401 * up by the BIOS, and thus we can't get the mode at module
2402 * load.
2403 */
2404 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2405 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2406 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2407 }
045ac3b5
JB		 2408}
2409
e8cb4558 2410static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2411{
e8cb4558 2412 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2413 struct drm_device *dev = encoder->base.dev;
495a5bb8
JN		 2414 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2415
6e3c9717 2416 if (crtc->config->has_audio)
495a5bb8 2417 intel_audio_codec_disable(encoder);
6cb49835 2418
b32c6f48
RV		 2419 if (HAS_PSR(dev) && !HAS_DDI(dev))
2420 intel_psr_disable(intel_dp);
2421
6cb49835
DV		 2422 /* Make sure the panel is off before trying to change the mode. But also
2423 * ensure that we have vdd while we switch off the panel. */
24f3e092 2424 intel_edp_panel_vdd_on(intel_dp);
4be73780 2425 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2426 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2427 intel_edp_panel_off(intel_dp);
3739850b 2428
08aff3fe
VS		 2429 /* disable the port before the pipe on g4x */
2430 if (INTEL_INFO(dev)->gen < 5)
3739850b 2431 intel_dp_link_down(intel_dp);
d240f20f
JB		 2432}
2433
08aff3fe 2434static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2435{
2bd2ad64 2436 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2437 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2438
49277c31 2439 intel_dp_link_down(intel_dp);
abfce949
VS		 2440
2441 /* Only ilk+ has port A */
08aff3fe
VS		 2442 if (port == PORT_A)
2443 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2444}
2445
2446static void vlv_post_disable_dp(struct intel_encoder *encoder)
2447{
2448 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2449
2450 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2451}
2452
a8f327fb
VS		 2453static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
2454 bool reset)
580d3811 2455{
a8f327fb
VS		 2456 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2457 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
2458 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2459 enum pipe pipe = crtc->pipe;
2460 uint32_t val;
580d3811 2461
a8f327fb
VS		 2462 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2463 if (reset)
2464 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2465 else
2466 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
2467 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
580d3811 2468
a8f327fb
VS		 2469 if (crtc->config->lane_count > 2) {
2470 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2471 if (reset)
2472 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2473 else
2474 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
2475 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2476 }
580d3811 2477
97fd4d5c 2478 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2479 val |= CHV_PCS_REQ_SOFTRESET_EN;
a8f327fb
VS		 2480 if (reset)
2481 val &= ~DPIO_PCS_CLK_SOFT_RESET;
2482 else
2483 val |= DPIO_PCS_CLK_SOFT_RESET;
97fd4d5c 2484 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2485
a8f327fb 2486 if (crtc->config->lane_count > 2) {
e0fce78f
VS		 2487 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2488 val |= CHV_PCS_REQ_SOFTRESET_EN;
a8f327fb
VS		 2489 if (reset)
2490 val &= ~DPIO_PCS_CLK_SOFT_RESET;
2491 else
2492 val |= DPIO_PCS_CLK_SOFT_RESET;
e0fce78f
VS		 2493 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2494 }
a8f327fb 2495}
97fd4d5c 2496
a8f327fb
VS		 2497static void chv_post_disable_dp(struct intel_encoder *encoder)
2498{
2499 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2500 struct drm_device *dev = encoder->base.dev;
2501 struct drm_i915_private *dev_priv = dev->dev_private;
97fd4d5c 2502
a8f327fb
VS		 2503 intel_dp_link_down(intel_dp);
2504
2505 mutex_lock(&dev_priv->sb_lock);
2506
2507 /* Assert data lane reset */
2508 chv_data_lane_soft_reset(encoder, true);
580d3811 2509
a580516d 2510 mutex_unlock(&dev_priv->sb_lock);
580d3811
VS		 2511}
2512
7b13b58a
VS		 2513static void
2514_intel_dp_set_link_train(struct intel_dp *intel_dp,
2515 uint32_t *DP,
2516 uint8_t dp_train_pat)
2517{
2518 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2519 struct drm_device *dev = intel_dig_port->base.base.dev;
2520 struct drm_i915_private *dev_priv = dev->dev_private;
2521 enum port port = intel_dig_port->port;
2522
2523 if (HAS_DDI(dev)) {
2524 uint32_t temp = I915_READ(DP_TP_CTL(port));
2525
2526 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2527 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2528 else
2529 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2530
2531 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2532 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2533 case DP_TRAINING_PATTERN_DISABLE:
2534 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2535
2536 break;
2537 case DP_TRAINING_PATTERN_1:
2538 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2539 break;
2540 case DP_TRAINING_PATTERN_2:
2541 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2542 break;
2543 case DP_TRAINING_PATTERN_3:
2544 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2545 break;
2546 }
2547 I915_WRITE(DP_TP_CTL(port), temp);
2548
39e5fa88
VS		 2549 } else if ((IS_GEN7(dev) && port == PORT_A) ||
2550 (HAS_PCH_CPT(dev) && port != PORT_A)) {
7b13b58a
VS		 2551 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2552
2553 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2554 case DP_TRAINING_PATTERN_DISABLE:
2555 *DP |= DP_LINK_TRAIN_OFF_CPT;
2556 break;
2557 case DP_TRAINING_PATTERN_1:
2558 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2559 break;
2560 case DP_TRAINING_PATTERN_2:
2561 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2562 break;
2563 case DP_TRAINING_PATTERN_3:
2564 DRM_ERROR("DP training pattern 3 not supported\n");
2565 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2566 break;
2567 }
2568
2569 } else {
2570 if (IS_CHERRYVIEW(dev))
2571 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2572 else
2573 *DP &= ~DP_LINK_TRAIN_MASK;
2574
2575 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2576 case DP_TRAINING_PATTERN_DISABLE:
2577 *DP |= DP_LINK_TRAIN_OFF;
2578 break;
2579 case DP_TRAINING_PATTERN_1:
2580 *DP |= DP_LINK_TRAIN_PAT_1;
2581 break;
2582 case DP_TRAINING_PATTERN_2:
2583 *DP |= DP_LINK_TRAIN_PAT_2;
2584 break;
2585 case DP_TRAINING_PATTERN_3:
2586 if (IS_CHERRYVIEW(dev)) {
2587 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2588 } else {
2589 DRM_ERROR("DP training pattern 3 not supported\n");
2590 *DP |= DP_LINK_TRAIN_PAT_2;
2591 }
2592 break;
2593 }
2594 }
2595}
2596
2597static void intel_dp_enable_port(struct intel_dp *intel_dp)
2598{
2599 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2600 struct drm_i915_private *dev_priv = dev->dev_private;
6fec7662
VS		 2601 struct intel_crtc *crtc =
2602 to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
7b13b58a 2603
7b13b58a
VS		 2604 /* enable with pattern 1 (as per spec) */
2605 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2606 DP_TRAINING_PATTERN_1);
2607
2608 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2609 POSTING_READ(intel_dp->output_reg);
7b713f50
VS		 2610
2611 /*
2612 * Magic for VLV/CHV. We _must_ first set up the register
2613 * without actually enabling the port, and then do another
2614 * write to enable the port. Otherwise link training will
2615 * fail when the power sequencer is freshly used for this port.
2616 */
2617 intel_dp->DP |= DP_PORT_EN;
6fec7662
VS		 2618 if (crtc->config->has_audio)
2619 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
7b713f50
VS		 2620
2621 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2622 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2623}
2624
e8cb4558 2625static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2626{
e8cb4558
DV		 2627 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2628 struct drm_device *dev = encoder->base.dev;
2629 struct drm_i915_private *dev_priv = dev->dev_private;
c1dec79a 2630 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
e8cb4558 2631 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
d6fbdd15
VS		 2632 enum port port = dp_to_dig_port(intel_dp)->port;
2633 enum pipe pipe = crtc->pipe;
5d613501 2634
0c33d8d7
DV		 2635 if (WARN_ON(dp_reg & DP_PORT_EN))
2636 return;
5d613501 2637
093e3f13
VS		 2638 pps_lock(intel_dp);
2639
666a4537 2640 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
093e3f13
VS		 2641 vlv_init_panel_power_sequencer(intel_dp);
2642
7864578a
VS		 2643 /*
2644 * We get an occasional spurious underrun between the port
2645 * enable and vdd enable, when enabling port A eDP.
2646 *
2647 * FIXME: Not sure if this applies to (PCH) port D eDP as well
2648 */
2649 if (port == PORT_A)
2650 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
2651
7b13b58a 2652 intel_dp_enable_port(intel_dp);
093e3f13 2653
d6fbdd15
VS		 2654 if (port == PORT_A && IS_GEN5(dev_priv)) {
2655 /*
2656 * Underrun reporting for the other pipe was disabled in
2657 * g4x_pre_enable_dp(). The eDP PLL and port have now been
2658 * enabled, so it's now safe to re-enable underrun reporting.
2659 */
2660 intel_wait_for_vblank_if_active(dev_priv->dev, !pipe);
2661 intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, true);
2662 intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, true);
2663 }
2664
093e3f13
VS		 2665 edp_panel_vdd_on(intel_dp);
2666 edp_panel_on(intel_dp);
2667 edp_panel_vdd_off(intel_dp, true);
2668
7864578a
VS		 2669 if (port == PORT_A)
2670 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2671
093e3f13
VS		 2672 pps_unlock(intel_dp);
2673
666a4537 2674 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e0fce78f
VS		 2675 unsigned int lane_mask = 0x0;
2676
2677 if (IS_CHERRYVIEW(dev))
2678 lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count);
2679
9b6de0a1
VS		 2680 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2681 lane_mask);
e0fce78f 2682 }
61234fa5 2683
f01eca2e 2684 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2685 intel_dp_start_link_train(intel_dp);
3ab9c637 2686 intel_dp_stop_link_train(intel_dp);
c1dec79a 2687
6e3c9717 2688 if (crtc->config->has_audio) {
c1dec79a 2689 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
d6fbdd15 2690 pipe_name(pipe));
c1dec79a
JN		 2691 intel_audio_codec_enable(encoder);
2692 }
ab1f90f9 2693}
89b667f8 2694
ecff4f3b
JN		 2695static void g4x_enable_dp(struct intel_encoder *encoder)
2696{
828f5c6e
JN		 2697 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2698
ecff4f3b 2699 intel_enable_dp(encoder);
4be73780 2700 intel_edp_backlight_on(intel_dp);
ab1f90f9 2701}
89b667f8 2702
ab1f90f9
JN		 2703static void vlv_enable_dp(struct intel_encoder *encoder)
2704{
828f5c6e
JN		 2705 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2706
4be73780 2707 intel_edp_backlight_on(intel_dp);
b32c6f48 2708 intel_psr_enable(intel_dp);
d240f20f
JB		 2709}
2710
ecff4f3b 2711static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9 2712{
d6fbdd15 2713 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
ab1f90f9 2714 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
d6fbdd15
VS		 2715 enum port port = dp_to_dig_port(intel_dp)->port;
2716 enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
ab1f90f9 2717
8ac33ed3
DV		 2718 intel_dp_prepare(encoder);
2719
d6fbdd15
VS		 2720 if (port == PORT_A && IS_GEN5(dev_priv)) {
2721 /*
2722 * We get FIFO underruns on the other pipe when
2723 * enabling the CPU eDP PLL, and when enabling CPU
2724 * eDP port. We could potentially avoid the PLL
2725 * underrun with a vblank wait just prior to enabling
2726 * the PLL, but that doesn't appear to help the port
2727 * enable case. Just sweep it all under the rug.
2728 */
2729 intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, false);
2730 intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, false);
2731 }
2732
d41f1efb 2733 /* Only ilk+ has port A */
abfce949 2734 if (port == PORT_A)
ab1f90f9
JN		 2735 ironlake_edp_pll_on(intel_dp);
2736}
2737
83b84597
VS		 2738static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2739{
2740 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2741 struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2742 enum pipe pipe = intel_dp->pps_pipe;
f0f59a00 2743 i915_reg_t pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
83b84597
VS		 2744
2745 edp_panel_vdd_off_sync(intel_dp);
2746
2747 /*
2748 * VLV seems to get confused when multiple power seqeuencers
2749 * have the same port selected (even if only one has power/vdd
2750 * enabled). The failure manifests as vlv_wait_port_ready() failing
2751 * CHV on the other hand doesn't seem to mind having the same port
2752 * selected in multiple power seqeuencers, but let's clear the
2753 * port select always when logically disconnecting a power sequencer
2754 * from a port.
2755 */
2756 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2757 pipe_name(pipe), port_name(intel_dig_port->port));
2758 I915_WRITE(pp_on_reg, 0);
2759 POSTING_READ(pp_on_reg);
2760
2761 intel_dp->pps_pipe = INVALID_PIPE;
2762}
2763
a4a5d2f8
VS		 2764static void vlv_steal_power_sequencer(struct drm_device *dev,
2765 enum pipe pipe)
2766{
2767 struct drm_i915_private *dev_priv = dev->dev_private;
2768 struct intel_encoder *encoder;
2769
2770 lockdep_assert_held(&dev_priv->pps_mutex);
2771
ac3c12e4
VS		 2772 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2773 return;
2774
19c8054c 2775 for_each_intel_encoder(dev, encoder) {
a4a5d2f8 2776 struct intel_dp *intel_dp;
773538e8 2777 enum port port;
a4a5d2f8
VS		 2778
2779 if (encoder->type != INTEL_OUTPUT_EDP)
2780 continue;
2781
2782 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2783 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2784
2785 if (intel_dp->pps_pipe != pipe)
2786 continue;
2787
2788 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2789 pipe_name(pipe), port_name(port));
a4a5d2f8 2790
e02f9a06 2791 WARN(encoder->base.crtc,
034e43c6
VS		 2792 "stealing pipe %c power sequencer from active eDP port %c\n",
2793 pipe_name(pipe), port_name(port));
a4a5d2f8 2794
a4a5d2f8 2795 /* make sure vdd is off before we steal it */
83b84597 2796 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2797 }
2798}
2799
2800static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2801{
2802 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2803 struct intel_encoder *encoder = &intel_dig_port->base;
2804 struct drm_device *dev = encoder->base.dev;
2805 struct drm_i915_private *dev_priv = dev->dev_private;
2806 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2807
2808 lockdep_assert_held(&dev_priv->pps_mutex);
2809
093e3f13
VS		 2810 if (!is_edp(intel_dp))
2811 return;
2812
a4a5d2f8
VS		 2813 if (intel_dp->pps_pipe == crtc->pipe)
2814 return;
2815
2816 /*
2817 * If another power sequencer was being used on this
2818 * port previously make sure to turn off vdd there while
2819 * we still have control of it.
2820 */
2821 if (intel_dp->pps_pipe != INVALID_PIPE)
83b84597 2822 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2823
2824 /*
2825 * We may be stealing the power
2826 * sequencer from another port.
2827 */
2828 vlv_steal_power_sequencer(dev, crtc->pipe);
2829
2830 /* now it's all ours */
2831 intel_dp->pps_pipe = crtc->pipe;
2832
2833 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2834 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2835
2836 /* init power sequencer on this pipe and port */
36b5f425
VS		 2837 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2838 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2839}
2840
ab1f90f9 2841static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2842{
2bd2ad64 2843 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2844 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2845 struct drm_device *dev = encoder->base.dev;
89b667f8 2846 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2847 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2848 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2849 int pipe = intel_crtc->pipe;
2850 u32 val;
a4fc5ed6 2851
a580516d 2852 mutex_lock(&dev_priv->sb_lock);
89b667f8 2853
ab3c759a 2854 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2855 val = 0;
2856 if (pipe)
2857 val |= (1<<21);
2858 else
2859 val &= ~(1<<21);
2860 val |= 0x001000c4;
ab3c759a
CML		 2861 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2862 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2863 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2864
a580516d 2865 mutex_unlock(&dev_priv->sb_lock);
ab1f90f9
JN		 2866
2867 intel_enable_dp(encoder);
89b667f8
JB		 2868}
2869
ecff4f3b 2870static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2871{
2872 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2873 struct drm_device *dev = encoder->base.dev;
2874 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2875 struct intel_crtc *intel_crtc =
2876 to_intel_crtc(encoder->base.crtc);
e4607fcf 2877 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2878 int pipe = intel_crtc->pipe;
89b667f8 2879
8ac33ed3
DV		 2880 intel_dp_prepare(encoder);
2881
89b667f8 2882 /* Program Tx lane resets to default */
a580516d 2883 mutex_lock(&dev_priv->sb_lock);
ab3c759a 2884 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2885 DPIO_PCS_TX_LANE2_RESET |
2886 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2887 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2888 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2889 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2890 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2891 DPIO_PCS_CLK_SOFT_RESET);
2892
2893 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2894 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2895 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2896 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
a580516d 2897 mutex_unlock(&dev_priv->sb_lock);
a4fc5ed6
KP		 2898}
2899
e4a1d846
CML		 2900static void chv_pre_enable_dp(struct intel_encoder *encoder)
2901{
2902 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2903 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2904 struct drm_device *dev = encoder->base.dev;
2905 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2906 struct intel_crtc *intel_crtc =
2907 to_intel_crtc(encoder->base.crtc);
2908 enum dpio_channel ch = vlv_dport_to_channel(dport);
2909 int pipe = intel_crtc->pipe;
2e523e98 2910 int data, i, stagger;
949c1d43 2911 u32 val;
e4a1d846 2912
a580516d 2913 mutex_lock(&dev_priv->sb_lock);
949c1d43 2914
570e2a74
VS		 2915 /* allow hardware to manage TX FIFO reset source */
2916 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2917 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2918 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2919
e0fce78f
VS		 2920 if (intel_crtc->config->lane_count > 2) {
2921 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2922 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2923 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2924 }
570e2a74 2925
949c1d43 2926 /* Program Tx lane latency optimal setting*/
e0fce78f 2927 for (i = 0; i < intel_crtc->config->lane_count; i++) {
e4a1d846 2928 /* Set the upar bit */
e0fce78f
VS		 2929 if (intel_crtc->config->lane_count == 1)
2930 data = 0x0;
2931 else
2932 data = (i == 1) ? 0x0 : 0x1;
e4a1d846
CML		 2933 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2934 data << DPIO_UPAR_SHIFT);
2935 }
2936
2937 /* Data lane stagger programming */
2e523e98
VS		 2938 if (intel_crtc->config->port_clock > 270000)
2939 stagger = 0x18;
2940 else if (intel_crtc->config->port_clock > 135000)
2941 stagger = 0xd;
2942 else if (intel_crtc->config->port_clock > 67500)
2943 stagger = 0x7;
2944 else if (intel_crtc->config->port_clock > 33750)
2945 stagger = 0x4;
2946 else
2947 stagger = 0x2;
2948
2949 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2950 val |= DPIO_TX2_STAGGER_MASK(0x1f);
2951 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2952
e0fce78f
VS		 2953 if (intel_crtc->config->lane_count > 2) {
2954 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2955 val |= DPIO_TX2_STAGGER_MASK(0x1f);
2956 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2957 }
2e523e98
VS		 2958
2959 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
2960 DPIO_LANESTAGGER_STRAP(stagger) |
2961 DPIO_LANESTAGGER_STRAP_OVRD |
2962 DPIO_TX1_STAGGER_MASK(0x1f) |
2963 DPIO_TX1_STAGGER_MULT(6) |
2964 DPIO_TX2_STAGGER_MULT(0));
2965
e0fce78f
VS		 2966 if (intel_crtc->config->lane_count > 2) {
2967 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
2968 DPIO_LANESTAGGER_STRAP(stagger) |
2969 DPIO_LANESTAGGER_STRAP_OVRD |
2970 DPIO_TX1_STAGGER_MASK(0x1f) |
2971 DPIO_TX1_STAGGER_MULT(7) |
2972 DPIO_TX2_STAGGER_MULT(5));
2973 }
e4a1d846 2974
a8f327fb
VS		 2975 /* Deassert data lane reset */
2976 chv_data_lane_soft_reset(encoder, false);
2977
a580516d 2978 mutex_unlock(&dev_priv->sb_lock);
e4a1d846 2979
e4a1d846 2980 intel_enable_dp(encoder);
b0b33846
VS		 2981
2982 /* Second common lane will stay alive on its own now */
2983 if (dport->release_cl2_override) {
2984 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
2985 dport->release_cl2_override = false;
2986 }
e4a1d846
CML		 2987}
2988
9197c88b
VS		 2989static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2990{
2991 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2992 struct drm_device *dev = encoder->base.dev;
2993 struct drm_i915_private *dev_priv = dev->dev_private;
2994 struct intel_crtc *intel_crtc =
2995 to_intel_crtc(encoder->base.crtc);
2996 enum dpio_channel ch = vlv_dport_to_channel(dport);
2997 enum pipe pipe = intel_crtc->pipe;
e0fce78f
VS		 2998 unsigned int lane_mask =
2999 intel_dp_unused_lane_mask(intel_crtc->config->lane_count);
9197c88b
VS		 3000 u32 val;
3001
625695f8
VS		 3002 intel_dp_prepare(encoder);
3003
b0b33846
VS		 3004 /*
3005 * Must trick the second common lane into life.
3006 * Otherwise we can't even access the PLL.
3007 */
3008 if (ch == DPIO_CH0 && pipe == PIPE_B)
3009 dport->release_cl2_override =
3010 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
3011
e0fce78f
VS		 3012 chv_phy_powergate_lanes(encoder, true, lane_mask);
3013
a580516d 3014 mutex_lock(&dev_priv->sb_lock);
9197c88b 3015
a8f327fb
VS		 3016 /* Assert data lane reset */
3017 chv_data_lane_soft_reset(encoder, true);
3018
b9e5ac3c
VS		 3019 /* program left/right clock distribution */
3020 if (pipe != PIPE_B) {
3021 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
3022 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
3023 if (ch == DPIO_CH0)
3024 val |= CHV_BUFLEFTENA1_FORCE;
3025 if (ch == DPIO_CH1)
3026 val |= CHV_BUFRIGHTENA1_FORCE;
3027 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
3028 } else {
3029 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
3030 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
3031 if (ch == DPIO_CH0)
3032 val |= CHV_BUFLEFTENA2_FORCE;
3033 if (ch == DPIO_CH1)
3034 val |= CHV_BUFRIGHTENA2_FORCE;
3035 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
3036 }
3037
9197c88b
VS		 3038 /* program clock channel usage */
3039 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
3040 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
3041 if (pipe != PIPE_B)
3042 val &= ~CHV_PCS_USEDCLKCHANNEL;
3043 else
3044 val |= CHV_PCS_USEDCLKCHANNEL;
3045 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
3046
e0fce78f
VS		 3047 if (intel_crtc->config->lane_count > 2) {
3048 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
3049 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
3050 if (pipe != PIPE_B)
3051 val &= ~CHV_PCS_USEDCLKCHANNEL;
3052 else
3053 val |= CHV_PCS_USEDCLKCHANNEL;
3054 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
3055 }
9197c88b
VS		 3056
3057 /*
3058 * This a a bit weird since generally CL
3059 * matches the pipe, but here we need to
3060 * pick the CL based on the port.
3061 */
3062 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
3063 if (pipe != PIPE_B)
3064 val &= ~CHV_CMN_USEDCLKCHANNEL;
3065 else
3066 val |= CHV_CMN_USEDCLKCHANNEL;
3067 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
3068
a580516d 3069 mutex_unlock(&dev_priv->sb_lock);
9197c88b
VS		 3070}
3071
d6db995f
VS		 3072static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
3073{
3074 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3075 enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
3076 u32 val;
3077
3078 mutex_lock(&dev_priv->sb_lock);
3079
3080 /* disable left/right clock distribution */
3081 if (pipe != PIPE_B) {
3082 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
3083 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
3084 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
3085 } else {
3086 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
3087 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
3088 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
3089 }
3090
3091 mutex_unlock(&dev_priv->sb_lock);
e0fce78f 3092
b0b33846
VS		 3093 /*
3094 * Leave the power down bit cleared for at least one
3095 * lane so that chv_powergate_phy_ch() will power
3096 * on something when the channel is otherwise unused.
3097 * When the port is off and the override is removed
3098 * the lanes power down anyway, so otherwise it doesn't
3099 * really matter what the state of power down bits is
3100 * after this.
3101 */
e0fce78f 3102 chv_phy_powergate_lanes(encoder, false, 0x0);
d6db995f
VS		 3103}
3104
a4fc5ed6 3105/*
df0c237d
JB		 3106 * Native read with retry for link status and receiver capability reads for
3107 * cases where the sink may still be asleep.
9d1a1031
JN		 3108 *
3109 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
3110 * supposed to retry 3 times per the spec.
a4fc5ed6 3111 */
9d1a1031
JN		 3112static ssize_t
3113intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
3114 void *buffer, size_t size)
a4fc5ed6 3115{
9d1a1031
JN		 3116 ssize_t ret;
3117 int i;
61da5fab 3118
f6a19066
VS		 3119 /*
3120 * Sometime we just get the same incorrect byte repeated
3121 * over the entire buffer. Doing just one throw away read
3122 * initially seems to "solve" it.
3123 */
3124 drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
3125
61da5fab 3126 for (i = 0; i < 3; i++) {
9d1a1031
JN		 3127 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
3128 if (ret == size)
3129 return ret;
61da5fab
JB		 3130 msleep(1);
3131 }
a4fc5ed6 3132
9d1a1031 3133 return ret;
a4fc5ed6
KP		 3134}
3135
3136/*
3137 * Fetch AUX CH registers 0x202 - 0x207 which contain
3138 * link status information
3139 */
94223d04 3140bool
93f62dad 3141intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 3142{
9d1a1031
JN		 3143 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3144 DP_LANE0_1_STATUS,
3145 link_status,
3146 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 3147}
3148
1100244e 3149/* These are source-specific values. */
94223d04 3150uint8_t
1a2eb460 3151intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 3152{
30add22d 3153 struct drm_device *dev = intel_dp_to_dev(intel_dp);
7ad14a29 3154 struct drm_i915_private *dev_priv = dev->dev_private;
bc7d38a4 3155 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 3156
9314726b
VK		 3157 if (IS_BROXTON(dev))
3158 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3159 else if (INTEL_INFO(dev)->gen >= 9) {
9e458034 3160 if (dev_priv->edp_low_vswing && port == PORT_A)
7ad14a29 3161 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
5a9d1f1a 3162 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
666a4537 3163 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
bd60018a 3164 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 3165 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 3166 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 3167 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 3168 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 3169 else
bd60018a 3170 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 3171}
3172
94223d04 3173uint8_t
1a2eb460
KP		 3174intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3175{
30add22d 3176 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 3177 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 3178
5a9d1f1a
DL		 3179 if (INTEL_INFO(dev)->gen >= 9) {
3180 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3181 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3182 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3183 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3184 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3185 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3186 return DP_TRAIN_PRE_EMPH_LEVEL_1;
7ad14a29
SJ		 3187 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3188 return DP_TRAIN_PRE_EMPH_LEVEL_0;
5a9d1f1a
DL		 3189 default:
3190 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3191 }
3192 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 3193 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3194 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3195 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3196 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3197 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3198 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3199 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3200 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 3201 default:
bd60018a 3202 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 3203 }
666a4537 3204 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e2fa6fba 3205 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3206 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3207 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3208 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3209 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3210 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3211 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3212 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 3213 default:
bd60018a 3214 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 3215 }
bc7d38a4 3216 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 3217 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3218 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3219 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3220 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3221 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3222 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 3223 default:
bd60018a 3224 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 3225 }
3226 } else {
3227 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3228 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3229 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3230 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3231 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3232 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3233 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3234 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 3235 default:
bd60018a 3236 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 3237 }
a4fc5ed6
KP		 3238 }
3239}
3240
5829975c 3241static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
e2fa6fba
P		 3242{
3243 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3244 struct drm_i915_private *dev_priv = dev->dev_private;
3245 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 3246 struct intel_crtc *intel_crtc =
3247 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 3248 unsigned long demph_reg_value, preemph_reg_value,
3249 uniqtranscale_reg_value;
3250 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 3251 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 3252 int pipe = intel_crtc->pipe;
e2fa6fba
P		 3253
3254 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3255 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 3256 preemph_reg_value = 0x0004000;
3257 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3258 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3259 demph_reg_value = 0x2B405555;
3260 uniqtranscale_reg_value = 0x552AB83A;
3261 break;
bd60018a 3262 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3263 demph_reg_value = 0x2B404040;
3264 uniqtranscale_reg_value = 0x5548B83A;
3265 break;
bd60018a 3266 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3267 demph_reg_value = 0x2B245555;
3268 uniqtranscale_reg_value = 0x5560B83A;
3269 break;
bd60018a 3270 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 3271 demph_reg_value = 0x2B405555;
3272 uniqtranscale_reg_value = 0x5598DA3A;
3273 break;
3274 default:
3275 return 0;
3276 }
3277 break;
bd60018a 3278 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 3279 preemph_reg_value = 0x0002000;
3280 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3281 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3282 demph_reg_value = 0x2B404040;
3283 uniqtranscale_reg_value = 0x5552B83A;
3284 break;
bd60018a 3285 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3286 demph_reg_value = 0x2B404848;
3287 uniqtranscale_reg_value = 0x5580B83A;
3288 break;
bd60018a 3289 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3290 demph_reg_value = 0x2B404040;
3291 uniqtranscale_reg_value = 0x55ADDA3A;
3292 break;
3293 default:
3294 return 0;
3295 }
3296 break;
bd60018a 3297 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 3298 preemph_reg_value = 0x0000000;
3299 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3300 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3301 demph_reg_value = 0x2B305555;
3302 uniqtranscale_reg_value = 0x5570B83A;
3303 break;
bd60018a 3304 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3305 demph_reg_value = 0x2B2B4040;
3306 uniqtranscale_reg_value = 0x55ADDA3A;
3307 break;
3308 default:
3309 return 0;
3310 }
3311 break;
bd60018a 3312 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3313 preemph_reg_value = 0x0006000;
3314 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3315 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3316 demph_reg_value = 0x1B405555;
3317 uniqtranscale_reg_value = 0x55ADDA3A;
3318 break;
3319 default:
3320 return 0;
3321 }
3322 break;
3323 default:
3324 return 0;
3325 }
3326
a580516d 3327 mutex_lock(&dev_priv->sb_lock);
ab3c759a
CML		 3328 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3329 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3330 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 3331 uniqtranscale_reg_value);
ab3c759a
CML		 3332 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3333 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3334 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3335 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
a580516d 3336 mutex_unlock(&dev_priv->sb_lock);
e2fa6fba
P		 3337
3338 return 0;
3339}
3340
67fa24b4
VS		 3341static bool chv_need_uniq_trans_scale(uint8_t train_set)
3342{
3343 return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) == DP_TRAIN_PRE_EMPH_LEVEL_0 &&
3344 (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3345}
3346
5829975c 3347static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
e4a1d846
CML		 3348{
3349 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3350 struct drm_i915_private *dev_priv = dev->dev_private;
3351 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3352 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 3353 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 3354 uint8_t train_set = intel_dp->train_set[0];
3355 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 3356 enum pipe pipe = intel_crtc->pipe;
3357 int i;
e4a1d846
CML		 3358
3359 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3360 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3361 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3362 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3363 deemph_reg_value = 128;
3364 margin_reg_value = 52;
3365 break;
bd60018a 3366 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3367 deemph_reg_value = 128;
3368 margin_reg_value = 77;
3369 break;
bd60018a 3370 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3371 deemph_reg_value = 128;
3372 margin_reg_value = 102;
3373 break;
bd60018a 3374 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3375 deemph_reg_value = 128;
3376 margin_reg_value = 154;
3377 /* FIXME extra to set for 1200 */
3378 break;
3379 default:
3380 return 0;
3381 }
3382 break;
bd60018a 3383 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3384 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3385 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3386 deemph_reg_value = 85;
3387 margin_reg_value = 78;
3388 break;
bd60018a 3389 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3390 deemph_reg_value = 85;
3391 margin_reg_value = 116;
3392 break;
bd60018a 3393 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3394 deemph_reg_value = 85;
3395 margin_reg_value = 154;
3396 break;
3397 default:
3398 return 0;
3399 }
3400 break;
bd60018a 3401 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3402 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3403 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3404 deemph_reg_value = 64;
3405 margin_reg_value = 104;
3406 break;
bd60018a 3407 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3408 deemph_reg_value = 64;
3409 margin_reg_value = 154;
3410 break;
3411 default:
3412 return 0;
3413 }
3414 break;
bd60018a 3415 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3416 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3417 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3418 deemph_reg_value = 43;
3419 margin_reg_value = 154;
3420 break;
3421 default:
3422 return 0;
3423 }
3424 break;
3425 default:
3426 return 0;
3427 }
3428
a580516d 3429 mutex_lock(&dev_priv->sb_lock);
e4a1d846
CML		 3430
3431 /* Clear calc init */
1966e59e
VS		 3432 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3433 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3434 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3435 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e
VS		 3436 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3437
e0fce78f
VS		 3438 if (intel_crtc->config->lane_count > 2) {
3439 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3440 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3441 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3442 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3443 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3444 }
e4a1d846 3445
a02ef3c7
VS		 3446 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3447 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3448 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3449 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3450
e0fce78f
VS		 3451 if (intel_crtc->config->lane_count > 2) {
3452 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3453 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3454 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3455 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3456 }
a02ef3c7 3457
e4a1d846 3458 /* Program swing deemph */
e0fce78f 3459 for (i = 0; i < intel_crtc->config->lane_count; i++) {
f72df8db
VS		 3460 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3461 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3462 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3463 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3464 }
e4a1d846
CML		 3465
3466 /* Program swing margin */
e0fce78f 3467 for (i = 0; i < intel_crtc->config->lane_count; i++) {
f72df8db 3468 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
67fa24b4 3469
1fb44505
VS		 3470 val &= ~DPIO_SWING_MARGIN000_MASK;
3471 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
67fa24b4
VS		 3472
3473 /*
3474 * Supposedly this value shouldn't matter when unique transition
3475 * scale is disabled, but in fact it does matter. Let's just
3476 * always program the same value and hope it's OK.
3477 */
3478 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3479 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
3480
f72df8db
VS		 3481 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3482 }
e4a1d846 3483
67fa24b4
VS		 3484 /*
3485 * The document said it needs to set bit 27 for ch0 and bit 26
3486 * for ch1. Might be a typo in the doc.
3487 * For now, for this unique transition scale selection, set bit
3488 * 27 for ch0 and ch1.
3489 */
e0fce78f 3490 for (i = 0; i < intel_crtc->config->lane_count; i++) {
f72df8db 3491 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
67fa24b4 3492 if (chv_need_uniq_trans_scale(train_set))
f72df8db 3493 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
67fa24b4
VS		 3494 else
3495 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3496 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
e4a1d846
CML		 3497 }
3498
3499 /* Start swing calculation */
1966e59e
VS		 3500 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3501 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3502 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3503
e0fce78f
VS		 3504 if (intel_crtc->config->lane_count > 2) {
3505 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3506 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3507 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3508 }
e4a1d846 3509
a580516d 3510 mutex_unlock(&dev_priv->sb_lock);
e4a1d846
CML		 3511
3512 return 0;
3513}
3514
a4fc5ed6 3515static uint32_t
5829975c 3516gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3517{
3cf2efb1 3518 uint32_t signal_levels = 0;
a4fc5ed6 3519
3cf2efb1 3520 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3521 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3522 default:
3523 signal_levels |= DP_VOLTAGE_0_4;
3524 break;
bd60018a 3525 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3526 signal_levels |= DP_VOLTAGE_0_6;
3527 break;
bd60018a 3528 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3529 signal_levels |= DP_VOLTAGE_0_8;
3530 break;
bd60018a 3531 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3532 signal_levels |= DP_VOLTAGE_1_2;
3533 break;
3534 }
3cf2efb1 3535 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3536 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3537 default:
3538 signal_levels |= DP_PRE_EMPHASIS_0;
3539 break;
bd60018a 3540 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3541 signal_levels |= DP_PRE_EMPHASIS_3_5;
3542 break;
bd60018a 3543 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3544 signal_levels |= DP_PRE_EMPHASIS_6;
3545 break;
bd60018a 3546 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3547 signal_levels |= DP_PRE_EMPHASIS_9_5;
3548 break;
3549 }
3550 return signal_levels;
3551}
3552
e3421a18
ZW		 3553/* Gen6's DP voltage swing and pre-emphasis control */
3554static uint32_t
5829975c 3555gen6_edp_signal_levels(uint8_t train_set)
e3421a18 3556{
3c5a62b5
YL		 3557 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3558 DP_TRAIN_PRE_EMPHASIS_MASK);
3559 switch (signal_levels) {
bd60018a
SJ		 3560 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3561 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3562 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3563 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3564 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3565 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3566 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3567 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3568 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3569 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3570 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3571 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3572 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3573 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3574 default:
3c5a62b5
YL		 3575 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3576 "0x%x\n", signal_levels);
3577 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3578 }
3579}
3580
1a2eb460
KP		 3581/* Gen7's DP voltage swing and pre-emphasis control */
3582static uint32_t
5829975c 3583gen7_edp_signal_levels(uint8_t train_set)
1a2eb460
KP		 3584{
3585 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3586 DP_TRAIN_PRE_EMPHASIS_MASK);
3587 switch (signal_levels) {
bd60018a 3588 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3589 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3590 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3591 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3592 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3593 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3594
bd60018a 3595 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3596 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3597 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3598 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3599
bd60018a 3600 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3601 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3602 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3603 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3604
3605 default:
3606 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3607 "0x%x\n", signal_levels);
3608 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3609 }
3610}
3611
94223d04 3612void
f4eb692e 3613intel_dp_set_signal_levels(struct intel_dp *intel_dp)
f0a3424e
PZ		 3614{
3615 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3616 enum port port = intel_dig_port->port;
f0a3424e 3617 struct drm_device *dev = intel_dig_port->base.base.dev;
b905a915 3618 struct drm_i915_private *dev_priv = to_i915(dev);
f8896f5d 3619 uint32_t signal_levels, mask = 0;
f0a3424e
PZ		 3620 uint8_t train_set = intel_dp->train_set[0];
3621
f8896f5d
DW		 3622 if (HAS_DDI(dev)) {
3623 signal_levels = ddi_signal_levels(intel_dp);
3624
3625 if (IS_BROXTON(dev))
3626 signal_levels = 0;
3627 else
3628 mask = DDI_BUF_EMP_MASK;
e4a1d846 3629 } else if (IS_CHERRYVIEW(dev)) {
5829975c 3630 signal_levels = chv_signal_levels(intel_dp);
e2fa6fba 3631 } else if (IS_VALLEYVIEW(dev)) {
5829975c 3632 signal_levels = vlv_signal_levels(intel_dp);
bc7d38a4 3633 } else if (IS_GEN7(dev) && port == PORT_A) {
5829975c 3634 signal_levels = gen7_edp_signal_levels(train_set);
f0a3424e 3635 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3636 } else if (IS_GEN6(dev) && port == PORT_A) {
5829975c 3637 signal_levels = gen6_edp_signal_levels(train_set);
f0a3424e
PZ		 3638 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3639 } else {
5829975c 3640 signal_levels = gen4_signal_levels(train_set);
f0a3424e
PZ		 3641 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3642 }
3643
96fb9f9b
VK		 3644 if (mask)
3645 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3646
3647 DRM_DEBUG_KMS("Using vswing level %d\n",
3648 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3649 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3650 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3651 DP_TRAIN_PRE_EMPHASIS_SHIFT);
f0a3424e 3652
f4eb692e 3653 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
b905a915
ACO		 3654
3655 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3656 POSTING_READ(intel_dp->output_reg);
f0a3424e
PZ		 3657}
3658
94223d04 3659void
e9c176d5
ACO		 3660intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3661 uint8_t dp_train_pat)
a4fc5ed6 3662{
174edf1f 3663 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
90a6b7b0
VS		 3664 struct drm_i915_private *dev_priv =
3665 to_i915(intel_dig_port->base.base.dev);
a4fc5ed6 3666
f4eb692e 3667 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
47ea7542 3668
f4eb692e 3669 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
ea5b213a 3670 POSTING_READ(intel_dp->output_reg);
e9c176d5
ACO		 3671}
3672
94223d04 3673void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3ab9c637
ID		 3674{
3675 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3676 struct drm_device *dev = intel_dig_port->base.base.dev;
3677 struct drm_i915_private *dev_priv = dev->dev_private;
3678 enum port port = intel_dig_port->port;
3679 uint32_t val;
3680
3681 if (!HAS_DDI(dev))
3682 return;
3683
3684 val = I915_READ(DP_TP_CTL(port));
3685 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3686 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3687 I915_WRITE(DP_TP_CTL(port), val);
3688
3689 /*
3690 * On PORT_A we can have only eDP in SST mode. There the only reason
3691 * we need to set idle transmission mode is to work around a HW issue
3692 * where we enable the pipe while not in idle link-training mode.
3693 * In this case there is requirement to wait for a minimum number of
3694 * idle patterns to be sent.
3695 */
3696 if (port == PORT_A)
3697 return;
3698
3699 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3700 1))
3701 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3702}
3703
a4fc5ed6 3704static void
ea5b213a 3705intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3706{
da63a9f2 3707 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1612c8bd 3708 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
bc7d38a4 3709 enum port port = intel_dig_port->port;
da63a9f2 3710 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3711 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 3712 uint32_t DP = intel_dp->DP;
a4fc5ed6 3713
bc76e320 3714 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3715 return;
3716
0c33d8d7 3717 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3718 return;
3719
28c97730 3720 DRM_DEBUG_KMS("\n");
32f9d658 3721
39e5fa88
VS		 3722 if ((IS_GEN7(dev) && port == PORT_A) ||
3723 (HAS_PCH_CPT(dev) && port != PORT_A)) {
e3421a18 3724 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1612c8bd 3725 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
e3421a18 3726 } else {
aad3d14d
VS		 3727 if (IS_CHERRYVIEW(dev))
3728 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3729 else
3730 DP &= ~DP_LINK_TRAIN_MASK;
1612c8bd 3731 DP |= DP_LINK_TRAIN_PAT_IDLE;
e3421a18 3732 }
1612c8bd 3733 I915_WRITE(intel_dp->output_reg, DP);
fe255d00 3734 POSTING_READ(intel_dp->output_reg);
5eb08b69 3735
1612c8bd
VS		 3736 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3737 I915_WRITE(intel_dp->output_reg, DP);
3738 POSTING_READ(intel_dp->output_reg);
3739
3740 /*
3741 * HW workaround for IBX, we need to move the port
3742 * to transcoder A after disabling it to allow the
3743 * matching HDMI port to be enabled on transcoder A.
3744 */
3745 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
0c241d5b
VS		 3746 /*
3747 * We get CPU/PCH FIFO underruns on the other pipe when
3748 * doing the workaround. Sweep them under the rug.
3749 */
3750 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3751 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3752
1612c8bd
VS		 3753 /* always enable with pattern 1 (as per spec) */
3754 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3755 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3756 I915_WRITE(intel_dp->output_reg, DP);
3757 POSTING_READ(intel_dp->output_reg);
3758
3759 DP &= ~DP_PORT_EN;
5bddd17f 3760 I915_WRITE(intel_dp->output_reg, DP);
0ca09685 3761 POSTING_READ(intel_dp->output_reg);
0c241d5b
VS		 3762
3763 intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
3764 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3765 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
5bddd17f
EA		 3766 }
3767
f01eca2e 3768 msleep(intel_dp->panel_power_down_delay);
6fec7662
VS		 3769
3770 intel_dp->DP = DP;
a4fc5ed6
KP		 3771}
3772
26d61aad
KP		 3773static bool
3774intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3775{
a031d709
RV		 3776 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3777 struct drm_device *dev = dig_port->base.base.dev;
3778 struct drm_i915_private *dev_priv = dev->dev_private;
fc0f8e25 3779 uint8_t rev;
a031d709 3780
9d1a1031
JN		 3781 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3782 sizeof(intel_dp->dpcd)) < 0)
edb39244 3783 return false; /* aux transfer failed */
92fd8fd1 3784
a8e98153 3785 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3786
edb39244
AJ		 3787 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3788 return false; /* DPCD not present */
3789
2293bb5c
SK		 3790 /* Check if the panel supports PSR */
3791 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3792 if (is_edp(intel_dp)) {
9d1a1031
JN		 3793 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3794 intel_dp->psr_dpcd,
3795 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3796 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3797 dev_priv->psr.sink_support = true;
50003939 3798 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3799 }
474d1ec4
SJ		 3800
3801 if (INTEL_INFO(dev)->gen >= 9 &&
3802 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3803 uint8_t frame_sync_cap;
3804
3805 dev_priv->psr.sink_support = true;
3806 intel_dp_dpcd_read_wake(&intel_dp->aux,
3807 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3808 &frame_sync_cap, 1);
3809 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3810 /* PSR2 needs frame sync as well */
3811 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3812 DRM_DEBUG_KMS("PSR2 %s on sink",
3813 dev_priv->psr.psr2_support ? "supported" : "not supported");
3814 }
50003939
JN		 3815 }
3816
bc5133d5 3817 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
e588fa18 3818 yesno(intel_dp_source_supports_hbr2(intel_dp)),
742f491d 3819 yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
06ea66b6 3820
fc0f8e25
SJ		 3821 /* Intermediate frequency support */
3822 if (is_edp(intel_dp) &&
3823 (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3824 (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
3825 (rev >= 0x03)) { /* eDp v1.4 or higher */
94ca719e 3826 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
ea2d8a42
VS		 3827 int i;
3828
fc0f8e25
SJ		 3829 intel_dp_dpcd_read_wake(&intel_dp->aux,
3830 DP_SUPPORTED_LINK_RATES,
94ca719e
VS		 3831 sink_rates,
3832 sizeof(sink_rates));
ea2d8a42 3833
94ca719e
VS		 3834 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3835 int val = le16_to_cpu(sink_rates[i]);
ea2d8a42
VS		 3836
3837 if (val == 0)
3838 break;
3839
af77b974
SJ		 3840 /* Value read is in kHz while drm clock is saved in deca-kHz */
3841 intel_dp->sink_rates[i] = (val * 200) / 10;
ea2d8a42 3842 }
94ca719e 3843 intel_dp->num_sink_rates = i;
fc0f8e25 3844 }
0336400e
VS		 3845
3846 intel_dp_print_rates(intel_dp);
3847
edb39244
AJ		 3848 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3849 DP_DWN_STRM_PORT_PRESENT))
3850 return true; /* native DP sink */
3851
3852 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3853 return true; /* no per-port downstream info */
3854
9d1a1031
JN		 3855 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3856 intel_dp->downstream_ports,
3857 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3858 return false; /* downstream port status fetch failed */
3859
3860 return true;
92fd8fd1
KP		 3861}
3862
0d198328
AJ		 3863static void
3864intel_dp_probe_oui(struct intel_dp *intel_dp)
3865{
3866 u8 buf[3];
3867
3868 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3869 return;
3870
9d1a1031 3871 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3872 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3873 buf[0], buf[1], buf[2]);
3874
9d1a1031 3875 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3876 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3877 buf[0], buf[1], buf[2]);
3878}
3879
0e32b39c
DA		 3880static bool
3881intel_dp_probe_mst(struct intel_dp *intel_dp)
3882{
3883 u8 buf[1];
3884
7cc96139
NS		 3885 if (!i915.enable_dp_mst)
3886 return false;
3887
0e32b39c
DA		 3888 if (!intel_dp->can_mst)
3889 return false;
3890
3891 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3892 return false;
3893
0e32b39c
DA		 3894 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3895 if (buf[0] & DP_MST_CAP) {
3896 DRM_DEBUG_KMS("Sink is MST capable\n");
3897 intel_dp->is_mst = true;
3898 } else {
3899 DRM_DEBUG_KMS("Sink is not MST capable\n");
3900 intel_dp->is_mst = false;
3901 }
3902 }
0e32b39c
DA		 3903
3904 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3905 return intel_dp->is_mst;
3906}
3907
e5a1cab5 3908static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
d2e216d0 3909{
082dcc7c 3910 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
d72f9d91 3911 struct drm_device *dev = dig_port->base.base.dev;
082dcc7c 3912 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
ad9dc91b 3913 u8 buf;
e5a1cab5 3914 int ret = 0;
c6297843
RV		 3915 int count = 0;
3916 int attempts = 10;
d2e216d0 3917
082dcc7c
RV		 3918 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3919 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
e5a1cab5
RV		 3920 ret = -EIO;
3921 goto out;
4373f0f2
PZ		 3922 }
3923
082dcc7c 3924 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
e5a1cab5 3925 buf & ~DP_TEST_SINK_START) < 0) {
082dcc7c 3926 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
e5a1cab5
RV		 3927 ret = -EIO;
3928 goto out;
3929 }
d2e216d0 3930
c6297843
RV		 3931 do {
3932 intel_wait_for_vblank(dev, intel_crtc->pipe);
3933
3934 if (drm_dp_dpcd_readb(&intel_dp->aux,
3935 DP_TEST_SINK_MISC, &buf) < 0) {
3936 ret = -EIO;
3937 goto out;
3938 }
3939 count = buf & DP_TEST_COUNT_MASK;
3940 } while (--attempts && count);
3941
3942 if (attempts == 0) {
dc5a9037 3943 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
c6297843
RV		 3944 ret = -ETIMEDOUT;
3945 }
3946
e5a1cab5 3947 out:
082dcc7c 3948 hsw_enable_ips(intel_crtc);
e5a1cab5 3949 return ret;
082dcc7c
RV		 3950}
3951
3952static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3953{
3954 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
d72f9d91 3955 struct drm_device *dev = dig_port->base.base.dev;
082dcc7c
RV		 3956 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3957 u8 buf;
e5a1cab5
RV		 3958 int ret;
3959
082dcc7c
RV		 3960 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3961 return -EIO;
3962
3963 if (!(buf & DP_TEST_CRC_SUPPORTED))
3964 return -ENOTTY;
3965
3966 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3967 return -EIO;
3968
6d8175da
RV		 3969 if (buf & DP_TEST_SINK_START) {
3970 ret = intel_dp_sink_crc_stop(intel_dp);
3971 if (ret)
3972 return ret;
3973 }
3974
082dcc7c 3975 hsw_disable_ips(intel_crtc);
1dda5f93 3976
9d1a1031 3977 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
082dcc7c
RV		 3978 buf | DP_TEST_SINK_START) < 0) {
3979 hsw_enable_ips(intel_crtc);
3980 return -EIO;
4373f0f2
PZ		 3981 }
3982
d72f9d91 3983 intel_wait_for_vblank(dev, intel_crtc->pipe);
082dcc7c
RV		 3984 return 0;
3985}
3986
3987int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3988{
3989 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3990 struct drm_device *dev = dig_port->base.base.dev;
3991 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3992 u8 buf;
621d4c76 3993 int count, ret;
082dcc7c 3994 int attempts = 6;
082dcc7c
RV		 3995
3996 ret = intel_dp_sink_crc_start(intel_dp);
3997 if (ret)
3998 return ret;
3999
ad9dc91b 4000 do {
621d4c76
RV		 4001 intel_wait_for_vblank(dev, intel_crtc->pipe);
4002
1dda5f93 4003 if (drm_dp_dpcd_readb(&intel_dp->aux,
4373f0f2
PZ		 4004 DP_TEST_SINK_MISC, &buf) < 0) {
4005 ret = -EIO;
afe0d67e 4006 goto stop;
4373f0f2 4007 }
621d4c76 4008 count = buf & DP_TEST_COUNT_MASK;
aabc95dc 4009
7e38eeff 4010 } while (--attempts && count == 0);
ad9dc91b
RV		 4011
4012 if (attempts == 0) {
7e38eeff
RV		 4013 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
4014 ret = -ETIMEDOUT;
4015 goto stop;
4016 }
4017
4018 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
4019 ret = -EIO;
4020 goto stop;
ad9dc91b 4021 }
d2e216d0 4022
afe0d67e 4023stop:
082dcc7c 4024 intel_dp_sink_crc_stop(intel_dp);
4373f0f2 4025 return ret;
d2e216d0
RV		 4026}
4027
a60f0e38
JB		 4028static bool
4029intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4030{
9d1a1031
JN		 4031 return intel_dp_dpcd_read_wake(&intel_dp->aux,
4032 DP_DEVICE_SERVICE_IRQ_VECTOR,
4033 sink_irq_vector, 1) == 1;
a60f0e38
JB		 4034}
4035
0e32b39c
DA		 4036static bool
4037intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4038{
4039 int ret;
4040
4041 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
4042 DP_SINK_COUNT_ESI,
4043 sink_irq_vector, 14);
4044 if (ret != 14)
4045 return false;
4046
4047 return true;
4048}
4049
c5d5ab7a
TP		 4050static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4051{
4052 uint8_t test_result = DP_TEST_ACK;
4053 return test_result;
4054}
4055
4056static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4057{
4058 uint8_t test_result = DP_TEST_NAK;
4059 return test_result;
4060}
4061
4062static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
a60f0e38 4063{
c5d5ab7a 4064 uint8_t test_result = DP_TEST_NAK;
559be30c
TP		 4065 struct intel_connector *intel_connector = intel_dp->attached_connector;
4066 struct drm_connector *connector = &intel_connector->base;
4067
4068 if (intel_connector->detect_edid == NULL ||
ac6f2e29 4069 connector->edid_corrupt ||
559be30c
TP		 4070 intel_dp->aux.i2c_defer_count > 6) {
4071 /* Check EDID read for NACKs, DEFERs and corruption
4072 * (DP CTS 1.2 Core r1.1)
4073 * 4.2.2.4 : Failed EDID read, I2C_NAK
4074 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4075 * 4.2.2.6 : EDID corruption detected
4076 * Use failsafe mode for all cases
4077 */
4078 if (intel_dp->aux.i2c_nack_count > 0 ||
4079 intel_dp->aux.i2c_defer_count > 0)
4080 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4081 intel_dp->aux.i2c_nack_count,
4082 intel_dp->aux.i2c_defer_count);
4083 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
4084 } else {
f79b468e
TS		 4085 struct edid *block = intel_connector->detect_edid;
4086
4087 /* We have to write the checksum
4088 * of the last block read
4089 */
4090 block += intel_connector->detect_edid->extensions;
4091
559be30c
TP		 4092 if (!drm_dp_dpcd_write(&intel_dp->aux,
4093 DP_TEST_EDID_CHECKSUM,
f79b468e 4094 &block->checksum,
5a1cc655 4095 1))
559be30c
TP		 4096 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4097
4098 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4099 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
4100 }
4101
4102 /* Set test active flag here so userspace doesn't interrupt things */
4103 intel_dp->compliance_test_active = 1;
4104
c5d5ab7a
TP		 4105 return test_result;
4106}
4107
4108static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
a60f0e38 4109{
c5d5ab7a
TP		 4110 uint8_t test_result = DP_TEST_NAK;
4111 return test_result;
4112}
4113
4114static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4115{
4116 uint8_t response = DP_TEST_NAK;
4117 uint8_t rxdata = 0;
4118 int status = 0;
4119
c5d5ab7a
TP		 4120 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
4121 if (status <= 0) {
4122 DRM_DEBUG_KMS("Could not read test request from sink\n");
4123 goto update_status;
4124 }
4125
4126 switch (rxdata) {
4127 case DP_TEST_LINK_TRAINING:
4128 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4129 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
4130 response = intel_dp_autotest_link_training(intel_dp);
4131 break;
4132 case DP_TEST_LINK_VIDEO_PATTERN:
4133 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4134 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
4135 response = intel_dp_autotest_video_pattern(intel_dp);
4136 break;
4137 case DP_TEST_LINK_EDID_READ:
4138 DRM_DEBUG_KMS("EDID test requested\n");
4139 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
4140 response = intel_dp_autotest_edid(intel_dp);
4141 break;
4142 case DP_TEST_LINK_PHY_TEST_PATTERN:
4143 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4144 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
4145 response = intel_dp_autotest_phy_pattern(intel_dp);
4146 break;
4147 default:
4148 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
4149 break;
4150 }
4151
4152update_status:
4153 status = drm_dp_dpcd_write(&intel_dp->aux,
4154 DP_TEST_RESPONSE,
4155 &response, 1);
4156 if (status <= 0)
4157 DRM_DEBUG_KMS("Could not write test response to sink\n");
a60f0e38
JB		 4158}
4159
0e32b39c
DA		 4160static int
4161intel_dp_check_mst_status(struct intel_dp *intel_dp)
4162{
4163 bool bret;
4164
4165 if (intel_dp->is_mst) {
4166 u8 esi[16] = { 0 };
4167 int ret = 0;
4168 int retry;
4169 bool handled;
4170 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4171go_again:
4172 if (bret == true) {
4173
4174 /* check link status - esi[10] = 0x200c */
90a6b7b0 4175 if (intel_dp->active_mst_links &&
901c2daf 4176 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
0e32b39c
DA		 4177 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4178 intel_dp_start_link_train(intel_dp);
0e32b39c
DA		 4179 intel_dp_stop_link_train(intel_dp);
4180 }
4181
6f34cc39 4182 DRM_DEBUG_KMS("got esi %3ph\n", esi);
0e32b39c
DA		 4183 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4184
4185 if (handled) {
4186 for (retry = 0; retry < 3; retry++) {
4187 int wret;
4188 wret = drm_dp_dpcd_write(&intel_dp->aux,
4189 DP_SINK_COUNT_ESI+1,
4190 &esi[1], 3);
4191 if (wret == 3) {
4192 break;
4193 }
4194 }
4195
4196 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4197 if (bret == true) {
6f34cc39 4198 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
0e32b39c
DA		 4199 goto go_again;
4200 }
4201 } else
4202 ret = 0;
4203
4204 return ret;
4205 } else {
4206 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4207 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4208 intel_dp->is_mst = false;
4209 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4210 /* send a hotplug event */
4211 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4212 }
4213 }
4214 return -EINVAL;
4215}
4216
a4fc5ed6
KP		 4217/*
4218 * According to DP spec
4219 * 5.1.2:
4220 * 1. Read DPCD
4221 * 2. Configure link according to Receiver Capabilities
4222 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4223 * 4. Check link status on receipt of hot-plug interrupt
4224 */
a5146200 4225static void
ea5b213a 4226intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 4227{
5b215bcf 4228 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 4229 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 4230 u8 sink_irq_vector;
93f62dad 4231 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 4232
5b215bcf
DA		 4233 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4234
4df6960e
SS		 4235 /*
4236 * Clearing compliance test variables to allow capturing
4237 * of values for next automated test request.
4238 */
4239 intel_dp->compliance_test_active = 0;
4240 intel_dp->compliance_test_type = 0;
4241 intel_dp->compliance_test_data = 0;
4242
e02f9a06 4243 if (!intel_encoder->base.crtc)
a4fc5ed6
KP		 4244 return;
4245
1a125d8a
ID		 4246 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4247 return;
4248
92fd8fd1 4249 /* Try to read receiver status if the link appears to be up */
93f62dad 4250 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 4251 return;
4252 }
4253
92fd8fd1 4254 /* Now read the DPCD to see if it's actually running */
26d61aad 4255 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 4256 return;
4257 }
4258
a60f0e38
JB		 4259 /* Try to read the source of the interrupt */
4260 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4261 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4262 /* Clear interrupt source */
9d1a1031
JN		 4263 drm_dp_dpcd_writeb(&intel_dp->aux,
4264 DP_DEVICE_SERVICE_IRQ_VECTOR,
4265 sink_irq_vector);
a60f0e38
JB		 4266
4267 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
09b1eb13 4268 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
a60f0e38
JB		 4269 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4270 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4271 }
4272
14631e9d
SS		 4273 /* if link training is requested we should perform it always */
4274 if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
4275 (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
92fd8fd1 4276 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 4277 intel_encoder->base.name);
33a34e4e 4278 intel_dp_start_link_train(intel_dp);
3ab9c637 4279 intel_dp_stop_link_train(intel_dp);
33a34e4e 4280 }
a4fc5ed6 4281}
a4fc5ed6 4282
caf9ab24 4283/* XXX this is probably wrong for multiple downstream ports */
71ba9000 4284static enum drm_connector_status
26d61aad 4285intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 4286{
caf9ab24 4287 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 4288 uint8_t type;
4289
4290 if (!intel_dp_get_dpcd(intel_dp))
4291 return connector_status_disconnected;
4292
4293 /* if there's no downstream port, we're done */
4294 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 4295 return connector_status_connected;
caf9ab24
AJ		 4296
4297 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 4298 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4299 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 4300 uint8_t reg;
9d1a1031
JN		 4301
4302 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4303 &reg, 1) < 0)
caf9ab24 4304 return connector_status_unknown;
9d1a1031 4305
23235177
AJ		 4306 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4307 : connector_status_disconnected;
caf9ab24
AJ		 4308 }
4309
4310 /* If no HPD, poke DDC gently */
0b99836f 4311 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4312 return connector_status_connected;
caf9ab24
AJ		 4313
4314 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4315 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4316 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4317 if (type == DP_DS_PORT_TYPE_VGA ||
4318 type == DP_DS_PORT_TYPE_NON_EDID)
4319 return connector_status_unknown;
4320 } else {
4321 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4322 DP_DWN_STRM_PORT_TYPE_MASK;
4323 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4324 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4325 return connector_status_unknown;
4326 }
caf9ab24
AJ		 4327
4328 /* Anything else is out of spec, warn and ignore */
4329 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4330 return connector_status_disconnected;
71ba9000
AJ		 4331}
4332
d410b56d
CW		 4333static enum drm_connector_status
4334edp_detect(struct intel_dp *intel_dp)
4335{
4336 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4337 enum drm_connector_status status;
4338
4339 status = intel_panel_detect(dev);
4340 if (status == connector_status_unknown)
4341 status = connector_status_connected;
4342
4343 return status;
4344}
4345
b93433cc
JN		 4346static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4347 struct intel_digital_port *port)
5eb08b69 4348{
b93433cc 4349 u32 bit;
01cb9ea6 4350
0df53b77
JN		 4351 switch (port->port) {
4352 case PORT_A:
4353 return true;
4354 case PORT_B:
4355 bit = SDE_PORTB_HOTPLUG;
4356 break;
4357 case PORT_C:
4358 bit = SDE_PORTC_HOTPLUG;
4359 break;
4360 case PORT_D:
4361 bit = SDE_PORTD_HOTPLUG;
4362 break;
4363 default:
4364 MISSING_CASE(port->port);
4365 return false;
4366 }
4367
4368 return I915_READ(SDEISR) & bit;
4369}
4370
4371static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4372 struct intel_digital_port *port)
4373{
4374 u32 bit;
4375
4376 switch (port->port) {
4377 case PORT_A:
4378 return true;
4379 case PORT_B:
4380 bit = SDE_PORTB_HOTPLUG_CPT;
4381 break;
4382 case PORT_C:
4383 bit = SDE_PORTC_HOTPLUG_CPT;
4384 break;
4385 case PORT_D:
4386 bit = SDE_PORTD_HOTPLUG_CPT;
4387 break;
a78695d3
JN		 4388 case PORT_E:
4389 bit = SDE_PORTE_HOTPLUG_SPT;
4390 break;
0df53b77
JN		 4391 default:
4392 MISSING_CASE(port->port);
4393 return false;
b93433cc 4394 }
1b469639 4395
b93433cc 4396 return I915_READ(SDEISR) & bit;
5eb08b69
ZW		 4397}
4398
7e66bcf2 4399static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
1d245987 4400 struct intel_digital_port *port)
a4fc5ed6 4401{
9642c81c 4402 u32 bit;
5eb08b69 4403
9642c81c
JN		 4404 switch (port->port) {
4405 case PORT_B:
4406 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4407 break;
4408 case PORT_C:
4409 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4410 break;
4411 case PORT_D:
4412 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4413 break;
4414 default:
4415 MISSING_CASE(port->port);
4416 return false;
4417 }
4418
4419 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4420}
4421
0780cd36
VS		 4422static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4423 struct intel_digital_port *port)
9642c81c
JN		 4424{
4425 u32 bit;
4426
4427 switch (port->port) {
4428 case PORT_B:
0780cd36 4429 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4430 break;
4431 case PORT_C:
0780cd36 4432 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4433 break;
4434 case PORT_D:
0780cd36 4435 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4436 break;
4437 default:
4438 MISSING_CASE(port->port);
4439 return false;
a4fc5ed6
KP		 4440 }
4441
1d245987 4442 return I915_READ(PORT_HOTPLUG_STAT) & bit;
2a592bec
DA		 4443}
4444
e464bfde 4445static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
e2ec35a5 4446 struct intel_digital_port *intel_dig_port)
e464bfde 4447{
e2ec35a5
SJ		 4448 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4449 enum port port;
e464bfde
JN		 4450 u32 bit;
4451
e2ec35a5
SJ		 4452 intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4453 switch (port) {
e464bfde
JN		 4454 case PORT_A:
4455 bit = BXT_DE_PORT_HP_DDIA;
4456 break;
4457 case PORT_B:
4458 bit = BXT_DE_PORT_HP_DDIB;
4459 break;
4460 case PORT_C:
4461 bit = BXT_DE_PORT_HP_DDIC;
4462 break;
4463 default:
e2ec35a5 4464 MISSING_CASE(port);
e464bfde
JN		 4465 return false;
4466 }
4467
4468 return I915_READ(GEN8_DE_PORT_ISR) & bit;
4469}
4470
7e66bcf2
JN		 4471/*
4472 * intel_digital_port_connected - is the specified port connected?
4473 * @dev_priv: i915 private structure
4474 * @port: the port to test
4475 *
4476 * Return %true if @port is connected, %false otherwise.
4477 */
237ed86c 4478bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
7e66bcf2
JN		 4479 struct intel_digital_port *port)
4480{
0df53b77 4481 if (HAS_PCH_IBX(dev_priv))
7e66bcf2 4482 return ibx_digital_port_connected(dev_priv, port);
22824fac 4483 else if (HAS_PCH_SPLIT(dev_priv))
0df53b77 4484 return cpt_digital_port_connected(dev_priv, port);
e464bfde
JN		 4485 else if (IS_BROXTON(dev_priv))
4486 return bxt_digital_port_connected(dev_priv, port);
0780cd36
VS		 4487 else if (IS_GM45(dev_priv))
4488 return gm45_digital_port_connected(dev_priv, port);
7e66bcf2
JN		 4489 else
4490 return g4x_digital_port_connected(dev_priv, port);
4491}
4492
8c241fef 4493static struct edid *
beb60608 4494intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4495{
beb60608 4496 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4497
9cd300e0
JN		 4498 /* use cached edid if we have one */
4499 if (intel_connector->edid) {
9cd300e0
JN		 4500 /* invalid edid */
4501 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4502 return NULL;
4503
55e9edeb 4504 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4505 } else
4506 return drm_get_edid(&intel_connector->base,
4507 &intel_dp->aux.ddc);
4508}
8c241fef 4509
beb60608
CW		 4510static void
4511intel_dp_set_edid(struct intel_dp *intel_dp)
4512{
4513 struct intel_connector *intel_connector = intel_dp->attached_connector;
4514 struct edid *edid;
8c241fef 4515
beb60608
CW		 4516 edid = intel_dp_get_edid(intel_dp);
4517 intel_connector->detect_edid = edid;
4518
4519 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4520 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4521 else
4522 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4523}
4524
beb60608
CW		 4525static void
4526intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4527{
beb60608 4528 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4529
beb60608
CW		 4530 kfree(intel_connector->detect_edid);
4531 intel_connector->detect_edid = NULL;
9cd300e0 4532
beb60608
CW		 4533 intel_dp->has_audio = false;
4534}
d6f24d0f 4535
a9756bb5
ZW		 4536static enum drm_connector_status
4537intel_dp_detect(struct drm_connector *connector, bool force)
4538{
4539 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4540 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4541 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4542 struct drm_device *dev = connector->dev;
a9756bb5 4543 enum drm_connector_status status;
671dedd2 4544 enum intel_display_power_domain power_domain;
0e32b39c 4545 bool ret;
09b1eb13 4546 u8 sink_irq_vector;
a9756bb5 4547
164c8598 4548 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4549 connector->base.id, connector->name);
beb60608 4550 intel_dp_unset_edid(intel_dp);
164c8598 4551
0e32b39c
DA		 4552 if (intel_dp->is_mst) {
4553 /* MST devices are disconnected from a monitor POV */
4554 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4555 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4556 return connector_status_disconnected;
0e32b39c
DA		 4557 }
4558
25f78f58
VS		 4559 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4560 intel_display_power_get(to_i915(dev), power_domain);
a9756bb5 4561
d410b56d
CW		 4562 /* Can't disconnect eDP, but you can close the lid... */
4563 if (is_edp(intel_dp))
4564 status = edp_detect(intel_dp);
c555a81d
ACO		 4565 else if (intel_digital_port_connected(to_i915(dev),
4566 dp_to_dig_port(intel_dp)))
4567 status = intel_dp_detect_dpcd(intel_dp);
a9756bb5 4568 else
c555a81d
ACO		 4569 status = connector_status_disconnected;
4570
4df6960e
SS		 4571 if (status != connector_status_connected) {
4572 intel_dp->compliance_test_active = 0;
4573 intel_dp->compliance_test_type = 0;
4574 intel_dp->compliance_test_data = 0;
4575
c8c8fb33 4576 goto out;
4df6960e 4577 }
a9756bb5 4578
0d198328
AJ		 4579 intel_dp_probe_oui(intel_dp);
4580
0e32b39c
DA		 4581 ret = intel_dp_probe_mst(intel_dp);
4582 if (ret) {
4583 /* if we are in MST mode then this connector
4584 won't appear connected or have anything with EDID on it */
4585 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4586 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4587 status = connector_status_disconnected;
4588 goto out;
4589 }
4590
4df6960e
SS		 4591 /*
4592 * Clearing NACK and defer counts to get their exact values
4593 * while reading EDID which are required by Compliance tests
4594 * 4.2.2.4 and 4.2.2.5
4595 */
4596 intel_dp->aux.i2c_nack_count = 0;
4597 intel_dp->aux.i2c_defer_count = 0;
4598
beb60608 4599 intel_dp_set_edid(intel_dp);
a9756bb5 4600
d63885da
PZ		 4601 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4602 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4603 status = connector_status_connected;
4604
09b1eb13
TP		 4605 /* Try to read the source of the interrupt */
4606 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4607 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4608 /* Clear interrupt source */
4609 drm_dp_dpcd_writeb(&intel_dp->aux,
4610 DP_DEVICE_SERVICE_IRQ_VECTOR,
4611 sink_irq_vector);
4612
4613 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4614 intel_dp_handle_test_request(intel_dp);
4615 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4616 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4617 }
4618
c8c8fb33 4619out:
25f78f58 4620 intel_display_power_put(to_i915(dev), power_domain);
c8c8fb33 4621 return status;
a4fc5ed6
KP		 4622}
4623
beb60608
CW		 4624static void
4625intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4626{
df0e9248 4627 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4628 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
25f78f58 4629 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
671dedd2 4630 enum intel_display_power_domain power_domain;
a4fc5ed6 4631
beb60608
CW		 4632 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4633 connector->base.id, connector->name);
4634 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4635
beb60608
CW		 4636 if (connector->status != connector_status_connected)
4637 return;
671dedd2 4638
25f78f58
VS		 4639 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4640 intel_display_power_get(dev_priv, power_domain);
beb60608
CW		 4641
4642 intel_dp_set_edid(intel_dp);
4643
25f78f58 4644 intel_display_power_put(dev_priv, power_domain);
beb60608
CW		 4645
4646 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4647 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4648}
4649
4650static int intel_dp_get_modes(struct drm_connector *connector)
4651{
4652 struct intel_connector *intel_connector = to_intel_connector(connector);
4653 struct edid *edid;
4654
4655 edid = intel_connector->detect_edid;
4656 if (edid) {
4657 int ret = intel_connector_update_modes(connector, edid);
4658 if (ret)
4659 return ret;
4660 }
32f9d658 4661
f8779fda 4662 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4663 if (is_edp(intel_attached_dp(connector)) &&
4664 intel_connector->panel.fixed_mode) {
f8779fda 4665 struct drm_display_mode *mode;
beb60608
CW		 4666
4667 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4668 intel_connector->panel.fixed_mode);
f8779fda 4669 if (mode) {
32f9d658
ZW		 4670 drm_mode_probed_add(connector, mode);
4671 return 1;
4672 }
4673 }
beb60608 4674
32f9d658 4675 return 0;
a4fc5ed6
KP		 4676}
4677
1aad7ac0
CW		 4678static bool
4679intel_dp_detect_audio(struct drm_connector *connector)
4680{
1aad7ac0 4681 bool has_audio = false;
beb60608 4682 struct edid *edid;
1aad7ac0 4683
beb60608
CW		 4684 edid = to_intel_connector(connector)->detect_edid;
4685 if (edid)
1aad7ac0 4686 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4687
1aad7ac0
CW		 4688 return has_audio;
4689}
4690
f684960e
CW		 4691static int
4692intel_dp_set_property(struct drm_connector *connector,
4693 struct drm_property *property,
4694 uint64_t val)
4695{
e953fd7b 4696 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4697 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4698 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4699 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4700 int ret;
4701
662595df 4702 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4703 if (ret)
4704 return ret;
4705
3f43c48d 4706 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4707 int i = val;
4708 bool has_audio;
4709
4710 if (i == intel_dp->force_audio)
f684960e
CW		 4711 return 0;
4712
1aad7ac0 4713 intel_dp->force_audio = i;
f684960e 4714
c3e5f67b 4715 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4716 has_audio = intel_dp_detect_audio(connector);
4717 else
c3e5f67b 4718 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4719
4720 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4721 return 0;
4722
1aad7ac0 4723 intel_dp->has_audio = has_audio;
f684960e
CW		 4724 goto done;
4725 }
4726
e953fd7b 4727 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80 4728 bool old_auto = intel_dp->color_range_auto;
0f2a2a75 4729 bool old_range = intel_dp->limited_color_range;
ae4edb80 4730
55bc60db
VS		 4731 switch (val) {
4732 case INTEL_BROADCAST_RGB_AUTO:
4733 intel_dp->color_range_auto = true;
4734 break;
4735 case INTEL_BROADCAST_RGB_FULL:
4736 intel_dp->color_range_auto = false;
0f2a2a75 4737 intel_dp->limited_color_range = false;
55bc60db
VS		 4738 break;
4739 case INTEL_BROADCAST_RGB_LIMITED:
4740 intel_dp->color_range_auto = false;
0f2a2a75 4741 intel_dp->limited_color_range = true;
55bc60db
VS		 4742 break;
4743 default:
4744 return -EINVAL;
4745 }
ae4edb80
DV		 4746
4747 if (old_auto == intel_dp->color_range_auto &&
0f2a2a75 4748 old_range == intel_dp->limited_color_range)
ae4edb80
DV		 4749 return 0;
4750
e953fd7b
CW		 4751 goto done;
4752 }
4753
53b41837
YN		 4754 if (is_edp(intel_dp) &&
4755 property == connector->dev->mode_config.scaling_mode_property) {
4756 if (val == DRM_MODE_SCALE_NONE) {
4757 DRM_DEBUG_KMS("no scaling not supported\n");
4758 return -EINVAL;
4759 }
4760
4761 if (intel_connector->panel.fitting_mode == val) {
4762 /* the eDP scaling property is not changed */
4763 return 0;
4764 }
4765 intel_connector->panel.fitting_mode = val;
4766
4767 goto done;
4768 }
4769
f684960e
CW		 4770 return -EINVAL;
4771
4772done:
c0c36b94
CW		 4773 if (intel_encoder->base.crtc)
4774 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4775
4776 return 0;
4777}
4778
a4fc5ed6 4779static void
73845adf 4780intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4781{
1d508706 4782 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4783
10e972d3 4784 kfree(intel_connector->detect_edid);
beb60608 4785
9cd300e0
JN		 4786 if (!IS_ERR_OR_NULL(intel_connector->edid))
4787 kfree(intel_connector->edid);
4788
acd8db10
PZ		 4789 /* Can't call is_edp() since the encoder may have been destroyed
4790 * already. */
4791 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4792 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4793
a4fc5ed6 4794 drm_connector_cleanup(connector);
55f78c43 4795 kfree(connector);
a4fc5ed6
KP		 4796}
4797
00c09d70 4798void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4799{
da63a9f2
PZ		 4800 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4801 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4802
0e32b39c 4803 intel_dp_mst_encoder_cleanup(intel_dig_port);
bd943159
KP		 4804 if (is_edp(intel_dp)) {
4805 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4806 /*
4807 * vdd might still be enabled do to the delayed vdd off.
4808 * Make sure vdd is actually turned off here.
4809 */
773538e8 4810 pps_lock(intel_dp);
4be73780 4811 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4812 pps_unlock(intel_dp);
4813
01527b31
CT		 4814 if (intel_dp->edp_notifier.notifier_call) {
4815 unregister_reboot_notifier(&intel_dp->edp_notifier);
4816 intel_dp->edp_notifier.notifier_call = NULL;
4817 }
bd943159 4818 }
c8bd0e49 4819 drm_encoder_cleanup(encoder);
da63a9f2 4820 kfree(intel_dig_port);
24d05927
DV		 4821}
4822
07f9cd0b
ID		 4823static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4824{
4825 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4826
4827 if (!is_edp(intel_dp))
4828 return;
4829
951468f3
VS		 4830 /*
4831 * vdd might still be enabled do to the delayed vdd off.
4832 * Make sure vdd is actually turned off here.
4833 */
afa4e53a 4834 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
773538e8 4835 pps_lock(intel_dp);
07f9cd0b 4836 edp_panel_vdd_off_sync(intel_dp);
773538e8 4837 pps_unlock(intel_dp);
07f9cd0b
ID		 4838}
4839
49e6bc51
VS		 4840static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4841{
4842 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4843 struct drm_device *dev = intel_dig_port->base.base.dev;
4844 struct drm_i915_private *dev_priv = dev->dev_private;
4845 enum intel_display_power_domain power_domain;
4846
4847 lockdep_assert_held(&dev_priv->pps_mutex);
4848
4849 if (!edp_have_panel_vdd(intel_dp))
4850 return;
4851
4852 /*
4853 * The VDD bit needs a power domain reference, so if the bit is
4854 * already enabled when we boot or resume, grab this reference and
4855 * schedule a vdd off, so we don't hold on to the reference
4856 * indefinitely.
4857 */
4858 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
25f78f58 4859 power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
49e6bc51
VS		 4860 intel_display_power_get(dev_priv, power_domain);
4861
4862 edp_panel_vdd_schedule_off(intel_dp);
4863}
4864
6d93c0c4
ID		 4865static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4866{
49e6bc51
VS		 4867 struct intel_dp *intel_dp;
4868
4869 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4870 return;
4871
4872 intel_dp = enc_to_intel_dp(encoder);
4873
4874 pps_lock(intel_dp);
4875
4876 /*
4877 * Read out the current power sequencer assignment,
4878 * in case the BIOS did something with it.
4879 */
666a4537 4880 if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev))
49e6bc51
VS		 4881 vlv_initial_power_sequencer_setup(intel_dp);
4882
4883 intel_edp_panel_vdd_sanitize(intel_dp);
4884
4885 pps_unlock(intel_dp);
6d93c0c4
ID		 4886}
4887
a4fc5ed6 4888static const struct drm_connector_funcs intel_dp_connector_funcs = {
4d688a2a 4889 .dpms = drm_atomic_helper_connector_dpms,
a4fc5ed6 4890 .detect = intel_dp_detect,
beb60608 4891 .force = intel_dp_force,
a4fc5ed6 4892 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4893 .set_property = intel_dp_set_property,
2545e4a6 4894 .atomic_get_property = intel_connector_atomic_get_property,
73845adf 4895 .destroy = intel_dp_connector_destroy,
c6f95f27 4896 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
98969725 4897 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
a4fc5ed6
KP		 4898};
4899
4900static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4901 .get_modes = intel_dp_get_modes,
4902 .mode_valid = intel_dp_mode_valid,
df0e9248 4903 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4904};
4905
a4fc5ed6 4906static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4907 .reset = intel_dp_encoder_reset,
24d05927 4908 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4909};
4910
b2c5c181 4911enum irqreturn
13cf5504
DA		 4912intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4913{
4914 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4915 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4916 struct drm_device *dev = intel_dig_port->base.base.dev;
4917 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33 4918 enum intel_display_power_domain power_domain;
b2c5c181 4919 enum irqreturn ret = IRQ_NONE;
1c767b33 4920
2540058f
TI		 4921 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
4922 intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
0e32b39c 4923 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4924
7a7f84cc
VS		 4925 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4926 /*
4927 * vdd off can generate a long pulse on eDP which
4928 * would require vdd on to handle it, and thus we
4929 * would end up in an endless cycle of
4930 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4931 */
4932 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4933 port_name(intel_dig_port->port));
a8b3d52f 4934 return IRQ_HANDLED;
7a7f84cc
VS		 4935 }
4936
26fbb774
VS		 4937 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4938 port_name(intel_dig_port->port),
0e32b39c 4939 long_hpd ? "long" : "short");
13cf5504 4940
25f78f58 4941 power_domain = intel_display_port_aux_power_domain(intel_encoder);
1c767b33
ID		 4942 intel_display_power_get(dev_priv, power_domain);
4943
0e32b39c 4944 if (long_hpd) {
5fa836a9
MK		 4945 /* indicate that we need to restart link training */
4946 intel_dp->train_set_valid = false;
2a592bec 4947
7e66bcf2
JN		 4948 if (!intel_digital_port_connected(dev_priv, intel_dig_port))
4949 goto mst_fail;
0e32b39c
DA		 4950
4951 if (!intel_dp_get_dpcd(intel_dp)) {
4952 goto mst_fail;
4953 }
4954
4955 intel_dp_probe_oui(intel_dp);
4956
d14e7b6d
VS		 4957 if (!intel_dp_probe_mst(intel_dp)) {
4958 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4959 intel_dp_check_link_status(intel_dp);
4960 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c 4961 goto mst_fail;
d14e7b6d 4962 }
0e32b39c
DA		 4963 } else {
4964 if (intel_dp->is_mst) {
1c767b33 4965 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4966 goto mst_fail;
4967 }
4968
4969 if (!intel_dp->is_mst) {
5b215bcf 4970 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4971 intel_dp_check_link_status(intel_dp);
5b215bcf 4972 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4973 }
4974 }
b2c5c181
DV		 4975
4976 ret = IRQ_HANDLED;
4977
1c767b33 4978 goto put_power;
0e32b39c
DA		 4979mst_fail:
4980 /* if we were in MST mode, and device is not there get out of MST mode */
4981 if (intel_dp->is_mst) {
4982 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4983 intel_dp->is_mst = false;
4984 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4985 }
1c767b33
ID		 4986put_power:
4987 intel_display_power_put(dev_priv, power_domain);
4988
4989 return ret;
13cf5504
DA		 4990}
4991
477ec328 4992/* check the VBT to see whether the eDP is on another port */
5d8a7752 4993bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4994{
4995 struct drm_i915_private *dev_priv = dev->dev_private;
36e83a18 4996
53ce81a7
VS		 4997 /*
4998 * eDP not supported on g4x. so bail out early just
4999 * for a bit extra safety in case the VBT is bonkers.
5000 */
5001 if (INTEL_INFO(dev)->gen < 5)
5002 return false;
5003
3b32a35b
VS		 5004 if (port == PORT_A)
5005 return true;
5006
951d9efe 5007 return intel_bios_is_port_edp(dev_priv, port);
36e83a18
ZY		 5008}
5009
0e32b39c 5010void
f684960e
CW		 5011intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5012{
53b41837
YN		 5013 struct intel_connector *intel_connector = to_intel_connector(connector);
5014
3f43c48d 5015 intel_attach_force_audio_property(connector);
e953fd7b 5016 intel_attach_broadcast_rgb_property(connector);
55bc60db 5017 intel_dp->color_range_auto = true;
53b41837
YN		 5018
5019 if (is_edp(intel_dp)) {
5020 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 5021 drm_object_attach_property(
5022 &connector->base,
53b41837 5023 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 5024 DRM_MODE_SCALE_ASPECT);
5025 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 5026 }
f684960e
CW		 5027}
5028
dada1a9f
ID		 5029static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5030{
d28d4731 5031 intel_dp->panel_power_off_time = ktime_get_boottime();
dada1a9f
ID		 5032 intel_dp->last_power_on = jiffies;
5033 intel_dp->last_backlight_off = jiffies;
5034}
5035
67a54566
DV		 5036static void
5037intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 5038 struct intel_dp *intel_dp)
67a54566
DV		 5039{
5040 struct drm_i915_private *dev_priv = dev->dev_private;
36b5f425
VS		 5041 struct edp_power_seq cur, vbt, spec,
5042 *final = &intel_dp->pps_delays;
b0a08bec 5043 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
f0f59a00 5044 i915_reg_t pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 5045
e39b999a
VS		 5046 lockdep_assert_held(&dev_priv->pps_mutex);
5047
81ddbc69
VS		 5048 /* already initialized? */
5049 if (final->t11_t12 != 0)
5050 return;
5051
b0a08bec
VK		 5052 if (IS_BROXTON(dev)) {
5053 /*
5054 * TODO: BXT has 2 sets of PPS registers.
5055 * Correct Register for Broxton need to be identified
5056 * using VBT. hardcoding for now
5057 */
5058 pp_ctrl_reg = BXT_PP_CONTROL(0);
5059 pp_on_reg = BXT_PP_ON_DELAYS(0);
5060 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5061 } else if (HAS_PCH_SPLIT(dev)) {
bf13e81b 5062 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 5063 pp_on_reg = PCH_PP_ON_DELAYS;
5064 pp_off_reg = PCH_PP_OFF_DELAYS;
5065 pp_div_reg = PCH_PP_DIVISOR;
5066 } else {
bf13e81b
JN		 5067 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5068
5069 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
5070 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5071 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5072 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 5073 }
67a54566
DV		 5074
5075 /* Workaround: Need to write PP_CONTROL with the unlock key as
5076 * the very first thing. */
b0a08bec 5077 pp_ctl = ironlake_get_pp_control(intel_dp);
67a54566 5078
453c5420
JB		 5079 pp_on = I915_READ(pp_on_reg);
5080 pp_off = I915_READ(pp_off_reg);
b0a08bec
VK		 5081 if (!IS_BROXTON(dev)) {
5082 I915_WRITE(pp_ctrl_reg, pp_ctl);
5083 pp_div = I915_READ(pp_div_reg);
5084 }
67a54566
DV		 5085
5086 /* Pull timing values out of registers */
5087 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5088 PANEL_POWER_UP_DELAY_SHIFT;
5089
5090 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5091 PANEL_LIGHT_ON_DELAY_SHIFT;
5092
5093 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5094 PANEL_LIGHT_OFF_DELAY_SHIFT;
5095
5096 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5097 PANEL_POWER_DOWN_DELAY_SHIFT;
5098
b0a08bec
VK		 5099 if (IS_BROXTON(dev)) {
5100 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5101 BXT_POWER_CYCLE_DELAY_SHIFT;
5102 if (tmp > 0)
5103 cur.t11_t12 = (tmp - 1) * 1000;
5104 else
5105 cur.t11_t12 = 0;
5106 } else {
5107 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
67a54566 5108 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
b0a08bec 5109 }
67a54566
DV		 5110
5111 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5112 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
5113
41aa3448 5114 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 5115
5116 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5117 * our hw here, which are all in 100usec. */
5118 spec.t1_t3 = 210 * 10;
5119 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5120 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5121 spec.t10 = 500 * 10;
5122 /* This one is special and actually in units of 100ms, but zero
5123 * based in the hw (so we need to add 100 ms). But the sw vbt
5124 * table multiplies it with 1000 to make it in units of 100usec,
5125 * too. */
5126 spec.t11_t12 = (510 + 100) * 10;
5127
5128 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5129 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
5130
5131 /* Use the max of the register settings and vbt. If both are
5132 * unset, fall back to the spec limits. */
36b5f425 5133#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 5134 spec.field : \
5135 max(cur.field, vbt.field))
5136 assign_final(t1_t3);
5137 assign_final(t8);
5138 assign_final(t9);
5139 assign_final(t10);
5140 assign_final(t11_t12);
5141#undef assign_final
5142
36b5f425 5143#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 5144 intel_dp->panel_power_up_delay = get_delay(t1_t3);
5145 intel_dp->backlight_on_delay = get_delay(t8);
5146 intel_dp->backlight_off_delay = get_delay(t9);
5147 intel_dp->panel_power_down_delay = get_delay(t10);
5148 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5149#undef get_delay
5150
f30d26e4
JN		 5151 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5152 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5153 intel_dp->panel_power_cycle_delay);
5154
5155 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5156 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
f30d26e4
JN		 5157}
5158
5159static void
5160intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 5161 struct intel_dp *intel_dp)
f30d26e4
JN		 5162{
5163 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 5164 u32 pp_on, pp_off, pp_div, port_sel = 0;
e7dc33f3 5165 int div = dev_priv->rawclk_freq / 1000;
f0f59a00 5166 i915_reg_t pp_on_reg, pp_off_reg, pp_div_reg, pp_ctrl_reg;
ad933b56 5167 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 5168 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 5169
e39b999a 5170 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420 5171
b0a08bec
VK		 5172 if (IS_BROXTON(dev)) {
5173 /*
5174 * TODO: BXT has 2 sets of PPS registers.
5175 * Correct Register for Broxton need to be identified
5176 * using VBT. hardcoding for now
5177 */
5178 pp_ctrl_reg = BXT_PP_CONTROL(0);
5179 pp_on_reg = BXT_PP_ON_DELAYS(0);
5180 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5181
5182 } else if (HAS_PCH_SPLIT(dev)) {
453c5420
JB		 5183 pp_on_reg = PCH_PP_ON_DELAYS;
5184 pp_off_reg = PCH_PP_OFF_DELAYS;
5185 pp_div_reg = PCH_PP_DIVISOR;
5186 } else {
bf13e81b
JN		 5187 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5188
5189 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5190 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5191 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 5192 }
5193
b2f19d1a
PZ		 5194 /*
5195 * And finally store the new values in the power sequencer. The
5196 * backlight delays are set to 1 because we do manual waits on them. For
5197 * T8, even BSpec recommends doing it. For T9, if we don't do this,
5198 * we'll end up waiting for the backlight off delay twice: once when we
5199 * do the manual sleep, and once when we disable the panel and wait for
5200 * the PP_STATUS bit to become zero.
5201 */
f30d26e4 5202 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 5203 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
5204 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 5205 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 5206 /* Compute the divisor for the pp clock, simply match the Bspec
5207 * formula. */
b0a08bec
VK		 5208 if (IS_BROXTON(dev)) {
5209 pp_div = I915_READ(pp_ctrl_reg);
5210 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5211 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5212 << BXT_POWER_CYCLE_DELAY_SHIFT);
5213 } else {
5214 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5215 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5216 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5217 }
67a54566
DV		 5218
5219 /* Haswell doesn't have any port selection bits for the panel
5220 * power sequencer any more. */
666a4537 5221 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
ad933b56 5222 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 5223 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 5224 if (port == PORT_A)
a24c144c 5225 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 5226 else
a24c144c 5227 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 5228 }
5229
453c5420
JB		 5230 pp_on |= port_sel;
5231
5232 I915_WRITE(pp_on_reg, pp_on);
5233 I915_WRITE(pp_off_reg, pp_off);
b0a08bec
VK		 5234 if (IS_BROXTON(dev))
5235 I915_WRITE(pp_ctrl_reg, pp_div);
5236 else
5237 I915_WRITE(pp_div_reg, pp_div);
67a54566 5238
67a54566 5239 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 5240 I915_READ(pp_on_reg),
5241 I915_READ(pp_off_reg),
b0a08bec
VK		 5242 IS_BROXTON(dev) ?
5243 (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) :
453c5420 5244 I915_READ(pp_div_reg));
f684960e
CW		 5245}
5246
b33a2815
VK		 5247/**
5248 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5249 * @dev: DRM device
5250 * @refresh_rate: RR to be programmed
5251 *
5252 * This function gets called when refresh rate (RR) has to be changed from
5253 * one frequency to another. Switches can be between high and low RR
5254 * supported by the panel or to any other RR based on media playback (in
5255 * this case, RR value needs to be passed from user space).
5256 *
5257 * The caller of this function needs to take a lock on dev_priv->drrs.
5258 */
96178eeb 5259static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
439d7ac0
PB		 5260{
5261 struct drm_i915_private *dev_priv = dev->dev_private;
5262 struct intel_encoder *encoder;
96178eeb
VK		 5263 struct intel_digital_port *dig_port = NULL;
5264 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5cec258b 5265 struct intel_crtc_state *config = NULL;
439d7ac0 5266 struct intel_crtc *intel_crtc = NULL;
96178eeb 5267 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
439d7ac0
PB		 5268
5269 if (refresh_rate <= 0) {
5270 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5271 return;
5272 }
5273
96178eeb
VK		 5274 if (intel_dp == NULL) {
5275 DRM_DEBUG_KMS("DRRS not supported.\n");
439d7ac0
PB		 5276 return;
5277 }
5278
1fcc9d1c 5279 /*
e4d59f6b
RV		 5280 * FIXME: This needs proper synchronization with psr state for some
5281 * platforms that cannot have PSR and DRRS enabled at the same time.
1fcc9d1c 5282 */
439d7ac0 5283
96178eeb
VK		 5284 dig_port = dp_to_dig_port(intel_dp);
5285 encoder = &dig_port->base;
723f9aab 5286 intel_crtc = to_intel_crtc(encoder->base.crtc);
439d7ac0
PB		 5287
5288 if (!intel_crtc) {
5289 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5290 return;
5291 }
5292
6e3c9717 5293 config = intel_crtc->config;
439d7ac0 5294
96178eeb 5295 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
439d7ac0
PB		 5296 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5297 return;
5298 }
5299
96178eeb
VK		 5300 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5301 refresh_rate)
439d7ac0
PB		 5302 index = DRRS_LOW_RR;
5303
96178eeb 5304 if (index == dev_priv->drrs.refresh_rate_type) {
439d7ac0
PB		 5305 DRM_DEBUG_KMS(
5306 "DRRS requested for previously set RR...ignoring\n");
5307 return;
5308 }
5309
5310 if (!intel_crtc->active) {
5311 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5312 return;
5313 }
5314
44395bfe 5315 if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
a4c30b1d
VK		 5316 switch (index) {
5317 case DRRS_HIGH_RR:
5318 intel_dp_set_m_n(intel_crtc, M1_N1);
5319 break;
5320 case DRRS_LOW_RR:
5321 intel_dp_set_m_n(intel_crtc, M2_N2);
5322 break;
5323 case DRRS_MAX_RR:
5324 default:
5325 DRM_ERROR("Unsupported refreshrate type\n");
5326 }
5327 } else if (INTEL_INFO(dev)->gen > 6) {
f0f59a00 5328 i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder);
649636ef 5329 u32 val;
a4c30b1d 5330
649636ef 5331 val = I915_READ(reg);
439d7ac0 5332 if (index > DRRS_HIGH_RR) {
666a4537 5333 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
6fa7aec1
VK		 5334 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5335 else
5336 val |= PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0 5337 } else {
666a4537 5338 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
6fa7aec1
VK		 5339 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5340 else
5341 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0
PB		 5342 }
5343 I915_WRITE(reg, val);
5344 }
5345
4e9ac947
VK		 5346 dev_priv->drrs.refresh_rate_type = index;
5347
5348 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5349}
5350
b33a2815
VK		 5351/**
5352 * intel_edp_drrs_enable - init drrs struct if supported
5353 * @intel_dp: DP struct
5354 *
5355 * Initializes frontbuffer_bits and drrs.dp
5356 */
c395578e
VK		 5357void intel_edp_drrs_enable(struct intel_dp *intel_dp)
5358{
5359 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5360 struct drm_i915_private *dev_priv = dev->dev_private;
5361 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5362 struct drm_crtc *crtc = dig_port->base.base.crtc;
5363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5364
5365 if (!intel_crtc->config->has_drrs) {
5366 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5367 return;
5368 }
5369
5370 mutex_lock(&dev_priv->drrs.mutex);
5371 if (WARN_ON(dev_priv->drrs.dp)) {
5372 DRM_ERROR("DRRS already enabled\n");
5373 goto unlock;
5374 }
5375
5376 dev_priv->drrs.busy_frontbuffer_bits = 0;
5377
5378 dev_priv->drrs.dp = intel_dp;
5379
5380unlock:
5381 mutex_unlock(&dev_priv->drrs.mutex);
5382}
5383
b33a2815
VK		 5384/**
5385 * intel_edp_drrs_disable - Disable DRRS
5386 * @intel_dp: DP struct
5387 *
5388 */
c395578e
VK		 5389void intel_edp_drrs_disable(struct intel_dp *intel_dp)
5390{
5391 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5392 struct drm_i915_private *dev_priv = dev->dev_private;
5393 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5394 struct drm_crtc *crtc = dig_port->base.base.crtc;
5395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5396
5397 if (!intel_crtc->config->has_drrs)
5398 return;
5399
5400 mutex_lock(&dev_priv->drrs.mutex);
5401 if (!dev_priv->drrs.dp) {
5402 mutex_unlock(&dev_priv->drrs.mutex);
5403 return;
5404 }
5405
5406 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5407 intel_dp_set_drrs_state(dev_priv->dev,
5408 intel_dp->attached_connector->panel.
5409 fixed_mode->vrefresh);
5410
5411 dev_priv->drrs.dp = NULL;
5412 mutex_unlock(&dev_priv->drrs.mutex);
5413
5414 cancel_delayed_work_sync(&dev_priv->drrs.work);
5415}
5416
4e9ac947
VK		 5417static void intel_edp_drrs_downclock_work(struct work_struct *work)
5418{
5419 struct drm_i915_private *dev_priv =
5420 container_of(work, typeof(*dev_priv), drrs.work.work);
5421 struct intel_dp *intel_dp;
5422
5423 mutex_lock(&dev_priv->drrs.mutex);
5424
5425 intel_dp = dev_priv->drrs.dp;
5426
5427 if (!intel_dp)
5428 goto unlock;
5429
439d7ac0 5430 /*
4e9ac947
VK		 5431 * The delayed work can race with an invalidate hence we need to
5432 * recheck.
439d7ac0
PB		 5433 */
5434
4e9ac947
VK		 5435 if (dev_priv->drrs.busy_frontbuffer_bits)
5436 goto unlock;
439d7ac0 5437
4e9ac947
VK		 5438 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
5439 intel_dp_set_drrs_state(dev_priv->dev,
5440 intel_dp->attached_connector->panel.
5441 downclock_mode->vrefresh);
439d7ac0 5442
4e9ac947 5443unlock:
4e9ac947 5444 mutex_unlock(&dev_priv->drrs.mutex);
439d7ac0
PB		 5445}
5446
b33a2815 5447/**
0ddfd203 5448 * intel_edp_drrs_invalidate - Disable Idleness DRRS
b33a2815
VK		 5449 * @dev: DRM device
5450 * @frontbuffer_bits: frontbuffer plane tracking bits
5451 *
0ddfd203
R		 5452 * This function gets called everytime rendering on the given planes start.
5453 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
b33a2815
VK		 5454 *
5455 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5456 */
a93fad0f
VK		 5457void intel_edp_drrs_invalidate(struct drm_device *dev,
5458 unsigned frontbuffer_bits)
5459{
5460 struct drm_i915_private *dev_priv = dev->dev_private;
5461 struct drm_crtc *crtc;
5462 enum pipe pipe;
5463
9da7d693 5464 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5465 return;
5466
88f933a8 5467 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5468
a93fad0f 5469 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5470 if (!dev_priv->drrs.dp) {
5471 mutex_unlock(&dev_priv->drrs.mutex);
5472 return;
5473 }
5474
a93fad0f
VK		 5475 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5476 pipe = to_intel_crtc(crtc)->pipe;
5477
c1d038c6
DV		 5478 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5479 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5480
0ddfd203 5481 /* invalidate means busy screen hence upclock */
c1d038c6 5482 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
a93fad0f
VK		 5483 intel_dp_set_drrs_state(dev_priv->dev,
5484 dev_priv->drrs.dp->attached_connector->panel.
5485 fixed_mode->vrefresh);
a93fad0f 5486
a93fad0f
VK		 5487 mutex_unlock(&dev_priv->drrs.mutex);
5488}
5489
b33a2815 5490/**
0ddfd203 5491 * intel_edp_drrs_flush - Restart Idleness DRRS
b33a2815
VK		 5492 * @dev: DRM device
5493 * @frontbuffer_bits: frontbuffer plane tracking bits
5494 *
0ddfd203
R		 5495 * This function gets called every time rendering on the given planes has
5496 * completed or flip on a crtc is completed. So DRRS should be upclocked
5497 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5498 * if no other planes are dirty.
b33a2815
VK		 5499 *
5500 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5501 */
a93fad0f
VK		 5502void intel_edp_drrs_flush(struct drm_device *dev,
5503 unsigned frontbuffer_bits)
5504{
5505 struct drm_i915_private *dev_priv = dev->dev_private;
5506 struct drm_crtc *crtc;
5507 enum pipe pipe;
5508
9da7d693 5509 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5510 return;
5511
88f933a8 5512 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5513
a93fad0f 5514 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5515 if (!dev_priv->drrs.dp) {
5516 mutex_unlock(&dev_priv->drrs.mutex);
5517 return;
5518 }
5519
a93fad0f
VK		 5520 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5521 pipe = to_intel_crtc(crtc)->pipe;
c1d038c6
DV		 5522
5523 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
a93fad0f
VK		 5524 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5525
0ddfd203 5526 /* flush means busy screen hence upclock */
c1d038c6 5527 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
0ddfd203
R		 5528 intel_dp_set_drrs_state(dev_priv->dev,
5529 dev_priv->drrs.dp->attached_connector->panel.
5530 fixed_mode->vrefresh);
5531
5532 /*
5533 * flush also means no more activity hence schedule downclock, if all
5534 * other fbs are quiescent too
5535 */
5536 if (!dev_priv->drrs.busy_frontbuffer_bits)
a93fad0f
VK		 5537 schedule_delayed_work(&dev_priv->drrs.work,
5538 msecs_to_jiffies(1000));
5539 mutex_unlock(&dev_priv->drrs.mutex);
5540}
5541
b33a2815
VK		 5542/**
5543 * DOC: Display Refresh Rate Switching (DRRS)
5544 *
5545 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5546 * which enables swtching between low and high refresh rates,
5547 * dynamically, based on the usage scenario. This feature is applicable
5548 * for internal panels.
5549 *
5550 * Indication that the panel supports DRRS is given by the panel EDID, which
5551 * would list multiple refresh rates for one resolution.
5552 *
5553 * DRRS is of 2 types - static and seamless.
5554 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5555 * (may appear as a blink on screen) and is used in dock-undock scenario.
5556 * Seamless DRRS involves changing RR without any visual effect to the user
5557 * and can be used during normal system usage. This is done by programming
5558 * certain registers.
5559 *
5560 * Support for static/seamless DRRS may be indicated in the VBT based on
5561 * inputs from the panel spec.
5562 *
5563 * DRRS saves power by switching to low RR based on usage scenarios.
5564 *
5565 * eDP DRRS:-
5566 * The implementation is based on frontbuffer tracking implementation.
5567 * When there is a disturbance on the screen triggered by user activity or a
5568 * periodic system activity, DRRS is disabled (RR is changed to high RR).
5569 * When there is no movement on screen, after a timeout of 1 second, a switch
5570 * to low RR is made.
5571 * For integration with frontbuffer tracking code,
5572 * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5573 *
5574 * DRRS can be further extended to support other internal panels and also
5575 * the scenario of video playback wherein RR is set based on the rate
5576 * requested by userspace.
5577 */
5578
5579/**
5580 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5581 * @intel_connector: eDP connector
5582 * @fixed_mode: preferred mode of panel
5583 *
5584 * This function is called only once at driver load to initialize basic
5585 * DRRS stuff.
5586 *
5587 * Returns:
5588 * Downclock mode if panel supports it, else return NULL.
5589 * DRRS support is determined by the presence of downclock mode (apart
5590 * from VBT setting).
5591 */
4f9db5b5 5592static struct drm_display_mode *
96178eeb
VK		 5593intel_dp_drrs_init(struct intel_connector *intel_connector,
5594 struct drm_display_mode *fixed_mode)
4f9db5b5
PB		 5595{
5596 struct drm_connector *connector = &intel_connector->base;
96178eeb 5597 struct drm_device *dev = connector->dev;
4f9db5b5
PB		 5598 struct drm_i915_private *dev_priv = dev->dev_private;
5599 struct drm_display_mode *downclock_mode = NULL;
5600
9da7d693
DV		 5601 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5602 mutex_init(&dev_priv->drrs.mutex);
5603
4f9db5b5
PB		 5604 if (INTEL_INFO(dev)->gen <= 6) {
5605 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5606 return NULL;
5607 }
5608
5609 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 5610 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 5611 return NULL;
5612 }
5613
5614 downclock_mode = intel_find_panel_downclock
5615 (dev, fixed_mode, connector);
5616
5617 if (!downclock_mode) {
a1d26342 5618 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
4f9db5b5
PB		 5619 return NULL;
5620 }
5621
96178eeb 5622 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
4f9db5b5 5623
96178eeb 5624 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 5625 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 5626 return downclock_mode;
5627}
5628
ed92f0b2 5629static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 5630 struct intel_connector *intel_connector)
ed92f0b2
PZ		 5631{
5632 struct drm_connector *connector = &intel_connector->base;
5633 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5634 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5635 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 5636 struct drm_i915_private *dev_priv = dev->dev_private;
5637 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5638 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5639 bool has_dpcd;
5640 struct drm_display_mode *scan;
5641 struct edid *edid;
6517d273 5642 enum pipe pipe = INVALID_PIPE;
ed92f0b2
PZ		 5643
5644 if (!is_edp(intel_dp))
5645 return true;
5646
49e6bc51
VS		 5647 pps_lock(intel_dp);
5648 intel_edp_panel_vdd_sanitize(intel_dp);
5649 pps_unlock(intel_dp);
63635217 5650
ed92f0b2 5651 /* Cache DPCD and EDID for edp. */
ed92f0b2 5652 has_dpcd = intel_dp_get_dpcd(intel_dp);
ed92f0b2
PZ		 5653
5654 if (has_dpcd) {
5655 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5656 dev_priv->no_aux_handshake =
5657 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5658 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5659 } else {
5660 /* if this fails, presume the device is a ghost */
5661 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 5662 return false;
5663 }
5664
5665 /* We now know it's not a ghost, init power sequence regs. */
773538e8 5666 pps_lock(intel_dp);
36b5f425 5667 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
773538e8 5668 pps_unlock(intel_dp);
ed92f0b2 5669
060c8778 5670 mutex_lock(&dev->mode_config.mutex);
0b99836f 5671 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5672 if (edid) {
5673 if (drm_add_edid_modes(connector, edid)) {
5674 drm_mode_connector_update_edid_property(connector,
5675 edid);
5676 drm_edid_to_eld(connector, edid);
5677 } else {
5678 kfree(edid);
5679 edid = ERR_PTR(-EINVAL);
5680 }
5681 } else {
5682 edid = ERR_PTR(-ENOENT);
5683 }
5684 intel_connector->edid = edid;
5685
5686 /* prefer fixed mode from EDID if available */
5687 list_for_each_entry(scan, &connector->probed_modes, head) {
5688 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5689 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5 5690 downclock_mode = intel_dp_drrs_init(
4f9db5b5 5691 intel_connector, fixed_mode);
ed92f0b2
PZ		 5692 break;
5693 }
5694 }
5695
5696 /* fallback to VBT if available for eDP */
5697 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5698 fixed_mode = drm_mode_duplicate(dev,
5699 dev_priv->vbt.lfp_lvds_vbt_mode);
5700 if (fixed_mode)
5701 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5702 }
060c8778 5703 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5704
666a4537 5705 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
01527b31
CT		 5706 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5707 register_reboot_notifier(&intel_dp->edp_notifier);
6517d273
VS		 5708
5709 /*
5710 * Figure out the current pipe for the initial backlight setup.
5711 * If the current pipe isn't valid, try the PPS pipe, and if that
5712 * fails just assume pipe A.
5713 */
5714 if (IS_CHERRYVIEW(dev))
5715 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5716 else
5717 pipe = PORT_TO_PIPE(intel_dp->DP);
5718
5719 if (pipe != PIPE_A && pipe != PIPE_B)
5720 pipe = intel_dp->pps_pipe;
5721
5722 if (pipe != PIPE_A && pipe != PIPE_B)
5723 pipe = PIPE_A;
5724
5725 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5726 pipe_name(pipe));
01527b31
CT		 5727 }
5728
4f9db5b5 5729 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5507faeb 5730 intel_connector->panel.backlight.power = intel_edp_backlight_power;
6517d273 5731 intel_panel_setup_backlight(connector, pipe);
ed92f0b2
PZ		 5732
5733 return true;
5734}
5735
16c25533 5736bool
f0fec3f2
PZ		 5737intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5738 struct intel_connector *intel_connector)
a4fc5ed6 5739{
f0fec3f2
PZ		 5740 struct drm_connector *connector = &intel_connector->base;
5741 struct intel_dp *intel_dp = &intel_dig_port->dp;
5742 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5743 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5744 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5745 enum port port = intel_dig_port->port;
a121f4e5 5746 int type, ret;
a4fc5ed6 5747
ccb1a831
VS		 5748 if (WARN(intel_dig_port->max_lanes < 1,
5749 "Not enough lanes (%d) for DP on port %c\n",
5750 intel_dig_port->max_lanes, port_name(port)))
5751 return false;
5752
a4a5d2f8
VS		 5753 intel_dp->pps_pipe = INVALID_PIPE;
5754
ec5b01dd 5755 /* intel_dp vfuncs */
b6b5e383
DL		 5756 if (INTEL_INFO(dev)->gen >= 9)
5757 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
ec5b01dd
DL		 5758 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5759 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5760 else if (HAS_PCH_SPLIT(dev))
5761 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5762 else
6ffb1be7 5763 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
ec5b01dd 5764
b9ca5fad
DL		 5765 if (INTEL_INFO(dev)->gen >= 9)
5766 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5767 else
6ffb1be7 5768 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
153b1100 5769
ad64217b
ACO		 5770 if (HAS_DDI(dev))
5771 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5772
0767935e
DV		 5773 /* Preserve the current hw state. */
5774 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5775 intel_dp->attached_connector = intel_connector;
3d3dc149 5776
3b32a35b 5777 if (intel_dp_is_edp(dev, port))
b329530c 5778 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5779 else
5780 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5781
f7d24902
ID		 5782 /*
5783 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5784 * for DP the encoder type can be set by the caller to
5785 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5786 */
5787 if (type == DRM_MODE_CONNECTOR_eDP)
5788 intel_encoder->type = INTEL_OUTPUT_EDP;
5789
c17ed5b5 5790 /* eDP only on port B and/or C on vlv/chv */
666a4537
WB		 5791 if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
5792 is_edp(intel_dp) && port != PORT_B && port != PORT_C))
c17ed5b5
VS		 5793 return false;
5794
e7281eab
ID		 5795 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5796 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5797 port_name(port));
5798
b329530c 5799 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5800 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5801
a4fc5ed6
KP		 5802 connector->interlace_allowed = true;
5803 connector->doublescan_allowed = 0;
5804
f0fec3f2 5805 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5806 edp_panel_vdd_work);
a4fc5ed6 5807
df0e9248 5808 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5809 drm_connector_register(connector);
a4fc5ed6 5810
affa9354 5811 if (HAS_DDI(dev))
bcbc889b
PZ		 5812 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5813 else
5814 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5815 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5816
0b99836f 5817 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5818 switch (port) {
5819 case PORT_A:
1d843f9d 5820 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5821 break;
5822 case PORT_B:
1d843f9d 5823 intel_encoder->hpd_pin = HPD_PORT_B;
e87a005d 5824 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
cf1d5883 5825 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5826 break;
5827 case PORT_C:
1d843f9d 5828 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5829 break;
5830 case PORT_D:
1d843f9d 5831 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30 5832 break;
26951caf
XZ		 5833 case PORT_E:
5834 intel_encoder->hpd_pin = HPD_PORT_E;
5835 break;
ab9d7c30 5836 default:
ad1c0b19 5837 BUG();
5eb08b69
ZW		 5838 }
5839
dada1a9f 5840 if (is_edp(intel_dp)) {
773538e8 5841 pps_lock(intel_dp);
1e74a324 5842 intel_dp_init_panel_power_timestamps(intel_dp);
666a4537 5843 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
a4a5d2f8 5844 vlv_initial_power_sequencer_setup(intel_dp);
1e74a324 5845 else
36b5f425 5846 intel_dp_init_panel_power_sequencer(dev, intel_dp);
773538e8 5847 pps_unlock(intel_dp);
dada1a9f 5848 }
0095e6dc 5849
a121f4e5
VS		 5850 ret = intel_dp_aux_init(intel_dp, intel_connector);
5851 if (ret)
5852 goto fail;
c1f05264 5853
0e32b39c 5854 /* init MST on ports that can support it */
0c9b3715
JN		 5855 if (HAS_DP_MST(dev) &&
5856 (port == PORT_B || port == PORT_C || port == PORT_D))
5857 intel_dp_mst_encoder_init(intel_dig_port,
5858 intel_connector->base.base.id);
0e32b39c 5859
36b5f425 5860 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
a121f4e5
VS		 5861 intel_dp_aux_fini(intel_dp);
5862 intel_dp_mst_encoder_cleanup(intel_dig_port);
5863 goto fail;
b2f246a8 5864 }
32f9d658 5865
f684960e
CW		 5866 intel_dp_add_properties(intel_dp, connector);
5867
a4fc5ed6
KP		 5868 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5869 * 0xd. Failure to do so will result in spurious interrupts being
5870 * generated on the port when a cable is not attached.
5871 */
5872 if (IS_G4X(dev) && !IS_GM45(dev)) {
5873 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5874 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5875 }
16c25533 5876
aa7471d2
JN		 5877 i915_debugfs_connector_add(connector);
5878
16c25533 5879 return true;
a121f4e5
VS		 5880
5881fail:
5882 if (is_edp(intel_dp)) {
5883 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5884 /*
5885 * vdd might still be enabled do to the delayed vdd off.
5886 * Make sure vdd is actually turned off here.
5887 */
5888 pps_lock(intel_dp);
5889 edp_panel_vdd_off_sync(intel_dp);
5890 pps_unlock(intel_dp);
5891 }
5892 drm_connector_unregister(connector);
5893 drm_connector_cleanup(connector);
5894
5895 return false;
a4fc5ed6 5896}
f0fec3f2
PZ		 5897
5898void
f0f59a00
VS		 5899intel_dp_init(struct drm_device *dev,
5900 i915_reg_t output_reg, enum port port)
f0fec3f2 5901{
13cf5504 5902 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5903 struct intel_digital_port *intel_dig_port;
5904 struct intel_encoder *intel_encoder;
5905 struct drm_encoder *encoder;
5906 struct intel_connector *intel_connector;
5907
b14c5679 5908 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5909 if (!intel_dig_port)
5910 return;
5911
08d9bc92 5912 intel_connector = intel_connector_alloc();
11aee0f6
SM		 5913 if (!intel_connector)
5914 goto err_connector_alloc;
f0fec3f2
PZ		 5915
5916 intel_encoder = &intel_dig_port->base;
5917 encoder = &intel_encoder->base;
5918
893da0c9 5919 if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
ade1ba73 5920 DRM_MODE_ENCODER_TMDS, NULL))
893da0c9 5921 goto err_encoder_init;
f0fec3f2 5922
5bfe2ac0 5923 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5924 intel_encoder->disable = intel_disable_dp;
00c09d70 5925 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5926 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5927 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5928 if (IS_CHERRYVIEW(dev)) {
9197c88b 5929 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5930 intel_encoder->pre_enable = chv_pre_enable_dp;
5931 intel_encoder->enable = vlv_enable_dp;
580d3811 5932 intel_encoder->post_disable = chv_post_disable_dp;
d6db995f 5933 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
e4a1d846 5934 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5935 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5936 intel_encoder->pre_enable = vlv_pre_enable_dp;
5937 intel_encoder->enable = vlv_enable_dp;
49277c31 5938 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5939 } else {
ecff4f3b
JN		 5940 intel_encoder->pre_enable = g4x_pre_enable_dp;
5941 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5942 if (INTEL_INFO(dev)->gen >= 5)
5943 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5944 }
f0fec3f2 5945
174edf1f 5946 intel_dig_port->port = port;
f0fec3f2 5947 intel_dig_port->dp.output_reg = output_reg;
ccb1a831 5948 intel_dig_port->max_lanes = 4;
f0fec3f2 5949
00c09d70 5950 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5951 if (IS_CHERRYVIEW(dev)) {
5952 if (port == PORT_D)
5953 intel_encoder->crtc_mask = 1 << 2;
5954 else
5955 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5956 } else {
5957 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5958 }
bc079e8b 5959 intel_encoder->cloneable = 0;
f0fec3f2 5960
13cf5504 5961 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5fcece80 5962 dev_priv->hotplug.irq_port[port] = intel_dig_port;
13cf5504 5963
11aee0f6
SM		 5964 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
5965 goto err_init_connector;
5966
5967 return;
5968
5969err_init_connector:
5970 drm_encoder_cleanup(encoder);
893da0c9 5971err_encoder_init:
11aee0f6
SM		 5972 kfree(intel_connector);
5973err_connector_alloc:
5974 kfree(intel_dig_port);
5975
5976 return;
f0fec3f2 5977}
0e32b39c
DA		 5978
5979void intel_dp_mst_suspend(struct drm_device *dev)
5980{
5981 struct drm_i915_private *dev_priv = dev->dev_private;
5982 int i;
5983
5984 /* disable MST */
5985 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 5986 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
0e32b39c
DA		 5987 if (!intel_dig_port)
5988 continue;
5989
5990 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5991 if (!intel_dig_port->dp.can_mst)
5992 continue;
5993 if (intel_dig_port->dp.is_mst)
5994 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5995 }
5996 }
5997}
5998
5999void intel_dp_mst_resume(struct drm_device *dev)
6000{
6001 struct drm_i915_private *dev_priv = dev->dev_private;
6002 int i;
6003
6004 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 6005 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
0e32b39c
DA		 6006 if (!intel_dig_port)
6007 continue;
6008 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
6009 int ret;
6010
6011 if (!intel_dig_port->dp.can_mst)
6012 continue;
6013
6014 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6015 if (ret != 0) {
6016 intel_dp_check_mst_status(&intel_dig_port->dp);
6017 }
6018 }
6019 }
6020}
Linux kernel - Deliverables
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