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drm/i915: add basic Haswell DP link train bits
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
a4fc5ed6
KP		 31#include "drmP.h"
32#include "drm.h"
33#include "drm_crtc.h"
34#include "drm_crtc_helper.h"
d6f24d0f 35#include "drm_edid.h"
a4fc5ed6
KP		 36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
a4fc5ed6 39
b091cd92 40#define DP_RECEIVER_CAP_SIZE 0xf
a4fc5ed6
KP		 41#define DP_LINK_STATUS_SIZE 6
42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
cfcb0fc9
JB		 44/**
45 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
46 * @intel_dp: DP struct
47 *
48 * If a CPU or PCH DP output is attached to an eDP panel, this function
49 * will return true, and false otherwise.
50 */
51static bool is_edp(struct intel_dp *intel_dp)
52{
53 return intel_dp->base.type == INTEL_OUTPUT_EDP;
54}
55
56/**
57 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
58 * @intel_dp: DP struct
59 *
60 * Returns true if the given DP struct corresponds to a PCH DP port attached
61 * to an eDP panel, false otherwise. Helpful for determining whether we
62 * may need FDI resources for a given DP output or not.
63 */
64static bool is_pch_edp(struct intel_dp *intel_dp)
65{
66 return intel_dp->is_pch_edp;
67}
68
1c95822a
AJ		 69/**
70 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
71 * @intel_dp: DP struct
72 *
73 * Returns true if the given DP struct corresponds to a CPU eDP port.
74 */
75static bool is_cpu_edp(struct intel_dp *intel_dp)
76{
77 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
78}
79
df0e9248
CW		 80static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
81{
82 return container_of(intel_attached_encoder(connector),
83 struct intel_dp, base);
84}
85
814948ad
JB		 86/**
87 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
88 * @encoder: DRM encoder
89 *
90 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
91 * by intel_display.c.
92 */
93bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
94{
95 struct intel_dp *intel_dp;
96
97 if (!encoder)
98 return false;
99
100 intel_dp = enc_to_intel_dp(encoder);
101
102 return is_pch_edp(intel_dp);
103}
104
33a34e4e
JB		 105static void intel_dp_start_link_train(struct intel_dp *intel_dp);
106static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
ea5b213a 107static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 108
32f9d658 109void
0206e353 110intel_edp_link_config(struct intel_encoder *intel_encoder,
ea5b213a 111 int *lane_num, int *link_bw)
32f9d658 112{
ea5b213a 113 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
32f9d658 114
ea5b213a
CW		 115 *lane_num = intel_dp->lane_count;
116 if (intel_dp->link_bw == DP_LINK_BW_1_62)
32f9d658 117 *link_bw = 162000;
ea5b213a 118 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
32f9d658
ZW		 119 *link_bw = 270000;
120}
121
94bf2ced
DV		 122int
123intel_edp_target_clock(struct intel_encoder *intel_encoder,
124 struct drm_display_mode *mode)
125{
126 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
127
128 if (intel_dp->panel_fixed_mode)
129 return intel_dp->panel_fixed_mode->clock;
130 else
131 return mode->clock;
132}
133
a4fc5ed6 134static int
ea5b213a 135intel_dp_max_lane_count(struct intel_dp *intel_dp)
a4fc5ed6 136{
9a10f401
KP		 137 int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
138 switch (max_lane_count) {
139 case 1: case 2: case 4:
140 break;
141 default:
142 max_lane_count = 4;
a4fc5ed6
KP		 143 }
144 return max_lane_count;
145}
146
147static int
ea5b213a 148intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 149{
7183dc29 150 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 151
152 switch (max_link_bw) {
153 case DP_LINK_BW_1_62:
154 case DP_LINK_BW_2_7:
155 break;
156 default:
157 max_link_bw = DP_LINK_BW_1_62;
158 break;
159 }
160 return max_link_bw;
161}
162
163static int
164intel_dp_link_clock(uint8_t link_bw)
165{
166 if (link_bw == DP_LINK_BW_2_7)
167 return 270000;
168 else
169 return 162000;
170}
171
cd9dde44
AJ		 172/*
173 * The units on the numbers in the next two are... bizarre. Examples will
174 * make it clearer; this one parallels an example in the eDP spec.
175 *
176 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
177 *
178 * 270000 * 1 * 8 / 10 == 216000
179 *
180 * The actual data capacity of that configuration is 2.16Gbit/s, so the
181 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
182 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
183 * 119000. At 18bpp that's 2142000 kilobits per second.
184 *
185 * Thus the strange-looking division by 10 in intel_dp_link_required, to
186 * get the result in decakilobits instead of kilobits.
187 */
188
a4fc5ed6 189static int
c898261c 190intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 191{
cd9dde44 192 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 193}
194
fe27d53e
DA		 195static int
196intel_dp_max_data_rate(int max_link_clock, int max_lanes)
197{
198 return (max_link_clock * max_lanes * 8) / 10;
199}
200
c4867936
DV		 201static bool
202intel_dp_adjust_dithering(struct intel_dp *intel_dp,
203 struct drm_display_mode *mode,
cb1793ce 204 bool adjust_mode)
c4867936
DV		 205{
206 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
207 int max_lanes = intel_dp_max_lane_count(intel_dp);
208 int max_rate, mode_rate;
209
210 mode_rate = intel_dp_link_required(mode->clock, 24);
211 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
212
213 if (mode_rate > max_rate) {
214 mode_rate = intel_dp_link_required(mode->clock, 18);
215 if (mode_rate > max_rate)
216 return false;
217
cb1793ce
DV		 218 if (adjust_mode)
219 mode->private_flags
c4867936
DV		 220 |= INTEL_MODE_DP_FORCE_6BPC;
221
222 return true;
223 }
224
225 return true;
226}
227
a4fc5ed6
KP		 228static int
229intel_dp_mode_valid(struct drm_connector *connector,
230 struct drm_display_mode *mode)
231{
df0e9248 232 struct intel_dp *intel_dp = intel_attached_dp(connector);
a4fc5ed6 233
d15456de
KP		 234 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
235 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
7de56f43
ZY		 236 return MODE_PANEL;
237
d15456de 238 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
7de56f43
ZY		 239 return MODE_PANEL;
240 }
241
cb1793ce 242 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
c4867936 243 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 244
245 if (mode->clock < 10000)
246 return MODE_CLOCK_LOW;
247
0af78a2b
DV		 248 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
249 return MODE_H_ILLEGAL;
250
a4fc5ed6
KP		 251 return MODE_OK;
252}
253
254static uint32_t
255pack_aux(uint8_t *src, int src_bytes)
256{
257 int i;
258 uint32_t v = 0;
259
260 if (src_bytes > 4)
261 src_bytes = 4;
262 for (i = 0; i < src_bytes; i++)
263 v |= ((uint32_t) src[i]) << ((3-i) * 8);
264 return v;
265}
266
267static void
268unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
269{
270 int i;
271 if (dst_bytes > 4)
272 dst_bytes = 4;
273 for (i = 0; i < dst_bytes; i++)
274 dst[i] = src >> ((3-i) * 8);
275}
276
fb0f8fbf
KP		 277/* hrawclock is 1/4 the FSB frequency */
278static int
279intel_hrawclk(struct drm_device *dev)
280{
281 struct drm_i915_private *dev_priv = dev->dev_private;
282 uint32_t clkcfg;
283
9473c8f4
VP		 284 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
285 if (IS_VALLEYVIEW(dev))
286 return 200;
287
fb0f8fbf
KP		 288 clkcfg = I915_READ(CLKCFG);
289 switch (clkcfg & CLKCFG_FSB_MASK) {
290 case CLKCFG_FSB_400:
291 return 100;
292 case CLKCFG_FSB_533:
293 return 133;
294 case CLKCFG_FSB_667:
295 return 166;
296 case CLKCFG_FSB_800:
297 return 200;
298 case CLKCFG_FSB_1067:
299 return 266;
300 case CLKCFG_FSB_1333:
301 return 333;
302 /* these two are just a guess; one of them might be right */
303 case CLKCFG_FSB_1600:
304 case CLKCFG_FSB_1600_ALT:
305 return 400;
306 default:
307 return 133;
308 }
309}
310
ebf33b18
KP		 311static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
312{
313 struct drm_device *dev = intel_dp->base.base.dev;
314 struct drm_i915_private *dev_priv = dev->dev_private;
315
316 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
317}
318
319static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
320{
321 struct drm_device *dev = intel_dp->base.base.dev;
322 struct drm_i915_private *dev_priv = dev->dev_private;
323
324 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
325}
326
9b984dae
KP		 327static void
328intel_dp_check_edp(struct intel_dp *intel_dp)
329{
330 struct drm_device *dev = intel_dp->base.base.dev;
331 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 332
9b984dae
KP		 333 if (!is_edp(intel_dp))
334 return;
ebf33b18 335 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 336 WARN(1, "eDP powered off while attempting aux channel communication.\n");
337 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
ebf33b18 338 I915_READ(PCH_PP_STATUS),
9b984dae
KP		 339 I915_READ(PCH_PP_CONTROL));
340 }
341}
342
a4fc5ed6 343static int
ea5b213a 344intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 345 uint8_t *send, int send_bytes,
346 uint8_t *recv, int recv_size)
347{
ea5b213a 348 uint32_t output_reg = intel_dp->output_reg;
4ef69c7a 349 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6
KP		 350 struct drm_i915_private *dev_priv = dev->dev_private;
351 uint32_t ch_ctl = output_reg + 0x10;
352 uint32_t ch_data = ch_ctl + 4;
353 int i;
354 int recv_bytes;
a4fc5ed6 355 uint32_t status;
fb0f8fbf 356 uint32_t aux_clock_divider;
6b4e0a93 357 int try, precharge;
a4fc5ed6 358
9b984dae 359 intel_dp_check_edp(intel_dp);
a4fc5ed6 360 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 361 * and would like to run at 2MHz. So, take the
362 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 363 *
364 * Note that PCH attached eDP panels should use a 125MHz input
365 * clock divider.
a4fc5ed6 366 */
1c95822a 367 if (is_cpu_edp(intel_dp)) {
9473c8f4
VP		 368 if (IS_VALLEYVIEW(dev))
369 aux_clock_divider = 100;
370 else if (IS_GEN6(dev) || IS_GEN7(dev))
1a2eb460 371 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 372 else
373 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
374 } else if (HAS_PCH_SPLIT(dev))
6919132e 375 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
5eb08b69
ZW		 376 else
377 aux_clock_divider = intel_hrawclk(dev) / 2;
378
6b4e0a93
DV		 379 if (IS_GEN6(dev))
380 precharge = 3;
381 else
382 precharge = 5;
383
11bee43e
JB		 384 /* Try to wait for any previous AUX channel activity */
385 for (try = 0; try < 3; try++) {
386 status = I915_READ(ch_ctl);
387 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
388 break;
389 msleep(1);
390 }
391
392 if (try == 3) {
393 WARN(1, "dp_aux_ch not started status 0x%08x\n",
394 I915_READ(ch_ctl));
4f7f7b7e
CW		 395 return -EBUSY;
396 }
397
fb0f8fbf
KP		 398 /* Must try at least 3 times according to DP spec */
399 for (try = 0; try < 5; try++) {
400 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 401 for (i = 0; i < send_bytes; i += 4)
402 I915_WRITE(ch_data + i,
403 pack_aux(send + i, send_bytes - i));
0206e353 404
fb0f8fbf 405 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 406 I915_WRITE(ch_ctl,
407 DP_AUX_CH_CTL_SEND_BUSY |
408 DP_AUX_CH_CTL_TIME_OUT_400us |
409 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
410 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
411 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
412 DP_AUX_CH_CTL_DONE |
413 DP_AUX_CH_CTL_TIME_OUT_ERROR |
414 DP_AUX_CH_CTL_RECEIVE_ERROR);
fb0f8fbf 415 for (;;) {
fb0f8fbf
KP		 416 status = I915_READ(ch_ctl);
417 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
418 break;
4f7f7b7e 419 udelay(100);
fb0f8fbf 420 }
0206e353 421
fb0f8fbf 422 /* Clear done status and any errors */
4f7f7b7e
CW		 423 I915_WRITE(ch_ctl,
424 status |
425 DP_AUX_CH_CTL_DONE |
426 DP_AUX_CH_CTL_TIME_OUT_ERROR |
427 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 428
429 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
430 DP_AUX_CH_CTL_RECEIVE_ERROR))
431 continue;
4f7f7b7e 432 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 433 break;
434 }
435
a4fc5ed6 436 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 437 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
a5b3da54 438 return -EBUSY;
a4fc5ed6
KP		 439 }
440
441 /* Check for timeout or receive error.
442 * Timeouts occur when the sink is not connected
443 */
a5b3da54 444 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 445 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
a5b3da54
KP		 446 return -EIO;
447 }
1ae8c0a5
KP		 448
449 /* Timeouts occur when the device isn't connected, so they're
450 * "normal" -- don't fill the kernel log with these */
a5b3da54 451 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 452 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
a5b3da54 453 return -ETIMEDOUT;
a4fc5ed6
KP		 454 }
455
456 /* Unload any bytes sent back from the other side */
457 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
458 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 459 if (recv_bytes > recv_size)
460 recv_bytes = recv_size;
0206e353 461
4f7f7b7e
CW		 462 for (i = 0; i < recv_bytes; i += 4)
463 unpack_aux(I915_READ(ch_data + i),
464 recv + i, recv_bytes - i);
a4fc5ed6
KP		 465
466 return recv_bytes;
467}
468
469/* Write data to the aux channel in native mode */
470static int
ea5b213a 471intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 472 uint16_t address, uint8_t *send, int send_bytes)
473{
474 int ret;
475 uint8_t msg[20];
476 int msg_bytes;
477 uint8_t ack;
478
9b984dae 479 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 480 if (send_bytes > 16)
481 return -1;
482 msg[0] = AUX_NATIVE_WRITE << 4;
483 msg[1] = address >> 8;
eebc863e 484 msg[2] = address & 0xff;
a4fc5ed6
KP		 485 msg[3] = send_bytes - 1;
486 memcpy(&msg[4], send, send_bytes);
487 msg_bytes = send_bytes + 4;
488 for (;;) {
ea5b213a 489 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 490 if (ret < 0)
491 return ret;
492 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
493 break;
494 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
495 udelay(100);
496 else
a5b3da54 497 return -EIO;
a4fc5ed6
KP		 498 }
499 return send_bytes;
500}
501
502/* Write a single byte to the aux channel in native mode */
503static int
ea5b213a 504intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 505 uint16_t address, uint8_t byte)
506{
ea5b213a 507 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 508}
509
510/* read bytes from a native aux channel */
511static int
ea5b213a 512intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 513 uint16_t address, uint8_t *recv, int recv_bytes)
514{
515 uint8_t msg[4];
516 int msg_bytes;
517 uint8_t reply[20];
518 int reply_bytes;
519 uint8_t ack;
520 int ret;
521
9b984dae 522 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 523 msg[0] = AUX_NATIVE_READ << 4;
524 msg[1] = address >> 8;
525 msg[2] = address & 0xff;
526 msg[3] = recv_bytes - 1;
527
528 msg_bytes = 4;
529 reply_bytes = recv_bytes + 1;
530
531 for (;;) {
ea5b213a 532 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 533 reply, reply_bytes);
a5b3da54
KP		 534 if (ret == 0)
535 return -EPROTO;
536 if (ret < 0)
a4fc5ed6
KP		 537 return ret;
538 ack = reply[0];
539 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
540 memcpy(recv, reply + 1, ret - 1);
541 return ret - 1;
542 }
543 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
544 udelay(100);
545 else
a5b3da54 546 return -EIO;
a4fc5ed6
KP		 547 }
548}
549
550static int
ab2c0672
DA		 551intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
552 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 553{
ab2c0672 554 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 555 struct intel_dp *intel_dp = container_of(adapter,
556 struct intel_dp,
557 adapter);
ab2c0672
DA		 558 uint16_t address = algo_data->address;
559 uint8_t msg[5];
560 uint8_t reply[2];
8316f337 561 unsigned retry;
ab2c0672
DA		 562 int msg_bytes;
563 int reply_bytes;
564 int ret;
565
9b984dae 566 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 567 /* Set up the command byte */
568 if (mode & MODE_I2C_READ)
569 msg[0] = AUX_I2C_READ << 4;
570 else
571 msg[0] = AUX_I2C_WRITE << 4;
572
573 if (!(mode & MODE_I2C_STOP))
574 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 575
ab2c0672
DA		 576 msg[1] = address >> 8;
577 msg[2] = address;
578
579 switch (mode) {
580 case MODE_I2C_WRITE:
581 msg[3] = 0;
582 msg[4] = write_byte;
583 msg_bytes = 5;
584 reply_bytes = 1;
585 break;
586 case MODE_I2C_READ:
587 msg[3] = 0;
588 msg_bytes = 4;
589 reply_bytes = 2;
590 break;
591 default:
592 msg_bytes = 3;
593 reply_bytes = 1;
594 break;
595 }
596
8316f337
DF		 597 for (retry = 0; retry < 5; retry++) {
598 ret = intel_dp_aux_ch(intel_dp,
599 msg, msg_bytes,
600 reply, reply_bytes);
ab2c0672 601 if (ret < 0) {
3ff99164 602 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 603 return ret;
604 }
8316f337
DF		 605
606 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
607 case AUX_NATIVE_REPLY_ACK:
608 /* I2C-over-AUX Reply field is only valid
609 * when paired with AUX ACK.
610 */
611 break;
612 case AUX_NATIVE_REPLY_NACK:
613 DRM_DEBUG_KMS("aux_ch native nack\n");
614 return -EREMOTEIO;
615 case AUX_NATIVE_REPLY_DEFER:
616 udelay(100);
617 continue;
618 default:
619 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
620 reply[0]);
621 return -EREMOTEIO;
622 }
623
ab2c0672
DA		 624 switch (reply[0] & AUX_I2C_REPLY_MASK) {
625 case AUX_I2C_REPLY_ACK:
626 if (mode == MODE_I2C_READ) {
627 *read_byte = reply[1];
628 }
629 return reply_bytes - 1;
630 case AUX_I2C_REPLY_NACK:
8316f337 631 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 632 return -EREMOTEIO;
633 case AUX_I2C_REPLY_DEFER:
8316f337 634 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 635 udelay(100);
636 break;
637 default:
8316f337 638 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 639 return -EREMOTEIO;
640 }
641 }
8316f337
DF		 642
643 DRM_ERROR("too many retries, giving up\n");
644 return -EREMOTEIO;
a4fc5ed6
KP		 645}
646
0b5c541b 647static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
bd943159 648static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
0b5c541b 649
a4fc5ed6 650static int
ea5b213a 651intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 652 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 653{
0b5c541b
KP		 654 int ret;
655
d54e9d28 656 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 657 intel_dp->algo.running = false;
658 intel_dp->algo.address = 0;
659 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
660
0206e353 661 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 662 intel_dp->adapter.owner = THIS_MODULE;
663 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 664 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 665 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
666 intel_dp->adapter.algo_data = &intel_dp->algo;
667 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
668
0b5c541b
KP		 669 ironlake_edp_panel_vdd_on(intel_dp);
670 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 671 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 672 return ret;
a4fc5ed6
KP		 673}
674
675static bool
e811f5ae
LP		 676intel_dp_mode_fixup(struct drm_encoder *encoder,
677 const struct drm_display_mode *mode,
a4fc5ed6
KP		 678 struct drm_display_mode *adjusted_mode)
679{
0d3a1bee 680 struct drm_device *dev = encoder->dev;
ea5b213a 681 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
a4fc5ed6 682 int lane_count, clock;
ea5b213a
CW		 683 int max_lane_count = intel_dp_max_lane_count(intel_dp);
684 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 685 int bpp, mode_rate;
a4fc5ed6
KP		 686 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
687
d15456de
KP		 688 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
689 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
1d8e1c75
CW		 690 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
691 mode, adjusted_mode);
0d3a1bee
ZY		 692 }
693
cb1793ce 694 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 695 return false;
696
083f9560
DV		 697 DRM_DEBUG_KMS("DP link computation with max lane count %i "
698 "max bw %02x pixel clock %iKHz\n",
71244653 699 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 700
cb1793ce 701 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
c4867936
DV		 702 return false;
703
704 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
71244653 705 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
c4867936 706
2514bc51
JB		 707 for (clock = 0; clock <= max_clock; clock++) {
708 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
fe27d53e 709 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
a4fc5ed6 710
083f9560 711 if (mode_rate <= link_avail) {
ea5b213a
CW		 712 intel_dp->link_bw = bws[clock];
713 intel_dp->lane_count = lane_count;
714 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
083f9560
DV		 715 DRM_DEBUG_KMS("DP link bw %02x lane "
716 "count %d clock %d bpp %d\n",
ea5b213a 717 intel_dp->link_bw, intel_dp->lane_count,
083f9560
DV		 718 adjusted_mode->clock, bpp);
719 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
720 mode_rate, link_avail);
a4fc5ed6
KP		 721 return true;
722 }
723 }
724 }
fe27d53e 725
a4fc5ed6
KP		 726 return false;
727}
728
729struct intel_dp_m_n {
730 uint32_t tu;
731 uint32_t gmch_m;
732 uint32_t gmch_n;
733 uint32_t link_m;
734 uint32_t link_n;
735};
736
737static void
738intel_reduce_ratio(uint32_t *num, uint32_t *den)
739{
740 while (*num > 0xffffff || *den > 0xffffff) {
741 *num >>= 1;
742 *den >>= 1;
743 }
744}
745
746static void
36e83a18 747intel_dp_compute_m_n(int bpp,
a4fc5ed6
KP		 748 int nlanes,
749 int pixel_clock,
750 int link_clock,
751 struct intel_dp_m_n *m_n)
752{
753 m_n->tu = 64;
36e83a18 754 m_n->gmch_m = (pixel_clock * bpp) >> 3;
a4fc5ed6
KP		 755 m_n->gmch_n = link_clock * nlanes;
756 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
757 m_n->link_m = pixel_clock;
758 m_n->link_n = link_clock;
759 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
760}
761
762void
763intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
764 struct drm_display_mode *adjusted_mode)
765{
766 struct drm_device *dev = crtc->dev;
6c2b7c12 767 struct intel_encoder *encoder;
a4fc5ed6
KP		 768 struct drm_i915_private *dev_priv = dev->dev_private;
769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
858fa035 770 int lane_count = 4;
a4fc5ed6 771 struct intel_dp_m_n m_n;
9db4a9c7 772 int pipe = intel_crtc->pipe;
a4fc5ed6
KP		 773
774 /*
21d40d37 775 * Find the lane count in the intel_encoder private
a4fc5ed6 776 */
6c2b7c12
DV		 777 for_each_encoder_on_crtc(dev, crtc, encoder) {
778 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
a4fc5ed6 779
9a10f401
KP		 780 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
781 intel_dp->base.type == INTEL_OUTPUT_EDP)
782 {
ea5b213a 783 lane_count = intel_dp->lane_count;
51190667 784 break;
a4fc5ed6
KP		 785 }
786 }
787
788 /*
789 * Compute the GMCH and Link ratios. The '3' here is
790 * the number of bytes_per_pixel post-LUT, which we always
791 * set up for 8-bits of R/G/B, or 3 bytes total.
792 */
858fa035 793 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
a4fc5ed6
KP		 794 mode->clock, adjusted_mode->clock, &m_n);
795
c619eed4 796 if (HAS_PCH_SPLIT(dev)) {
9db4a9c7
JB		 797 I915_WRITE(TRANSDATA_M1(pipe),
798 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
799 m_n.gmch_m);
800 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
801 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
802 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
74a4dd2e
VP		 803 } else if (IS_VALLEYVIEW(dev)) {
804 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
805 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
806 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
807 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
a4fc5ed6 808 } else {
9db4a9c7
JB		 809 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
810 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
811 m_n.gmch_m);
812 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
813 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
814 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
a4fc5ed6
KP		 815 }
816}
817
818static void
819intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
820 struct drm_display_mode *adjusted_mode)
821{
e3421a18 822 struct drm_device *dev = encoder->dev;
417e822d 823 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 824 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4ef69c7a 825 struct drm_crtc *crtc = intel_dp->base.base.crtc;
a4fc5ed6
KP		 826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
827
417e822d 828 /*
1a2eb460 829 * There are four kinds of DP registers:
417e822d
KP		 830 *
831 * IBX PCH
1a2eb460
KP		 832 * SNB CPU
833 * IVB CPU
417e822d
KP		 834 * CPT PCH
835 *
836 * IBX PCH and CPU are the same for almost everything,
837 * except that the CPU DP PLL is configured in this
838 * register
839 *
840 * CPT PCH is quite different, having many bits moved
841 * to the TRANS_DP_CTL register instead. That
842 * configuration happens (oddly) in ironlake_pch_enable
843 */
9c9e7927 844
417e822d
KP		 845 /* Preserve the BIOS-computed detected bit. This is
846 * supposed to be read-only.
847 */
848 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 849
417e822d 850 /* Handle DP bits in common between all three register formats */
417e822d 851 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 852
ea5b213a 853 switch (intel_dp->lane_count) {
a4fc5ed6 854 case 1:
ea5b213a 855 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 856 break;
857 case 2:
ea5b213a 858 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 859 break;
860 case 4:
ea5b213a 861 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 862 break;
863 }
e0dac65e
WF		 864 if (intel_dp->has_audio) {
865 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
866 pipe_name(intel_crtc->pipe));
ea5b213a 867 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 868 intel_write_eld(encoder, adjusted_mode);
869 }
ea5b213a
CW		 870 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
871 intel_dp->link_configuration[0] = intel_dp->link_bw;
872 intel_dp->link_configuration[1] = intel_dp->lane_count;
a2cab1b2 873 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
a4fc5ed6 874 /*
9962c925 875 * Check for DPCD version > 1.1 and enhanced framing support
a4fc5ed6 876 */
7183dc29
JB		 877 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
878 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
ea5b213a 879 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
a4fc5ed6
KP		 880 }
881
417e822d 882 /* Split out the IBX/CPU vs CPT settings */
32f9d658 883
19c03924 884 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 885 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
886 intel_dp->DP |= DP_SYNC_HS_HIGH;
887 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
888 intel_dp->DP |= DP_SYNC_VS_HIGH;
889 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
890
891 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
892 intel_dp->DP |= DP_ENHANCED_FRAMING;
893
894 intel_dp->DP |= intel_crtc->pipe << 29;
895
896 /* don't miss out required setting for eDP */
1a2eb460
KP		 897 if (adjusted_mode->clock < 200000)
898 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
899 else
900 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
901 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
417e822d
KP		 902 intel_dp->DP |= intel_dp->color_range;
903
904 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
905 intel_dp->DP |= DP_SYNC_HS_HIGH;
906 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
907 intel_dp->DP |= DP_SYNC_VS_HIGH;
908 intel_dp->DP |= DP_LINK_TRAIN_OFF;
909
910 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
911 intel_dp->DP |= DP_ENHANCED_FRAMING;
912
913 if (intel_crtc->pipe == 1)
914 intel_dp->DP |= DP_PIPEB_SELECT;
915
916 if (is_cpu_edp(intel_dp)) {
917 /* don't miss out required setting for eDP */
417e822d
KP		 918 if (adjusted_mode->clock < 200000)
919 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
920 else
921 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
922 }
923 } else {
924 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 925 }
a4fc5ed6
KP		 926}
927
99ea7127
KP		 928#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
929#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
930
931#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
932#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
933
934#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
935#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
936
937static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
938 u32 mask,
939 u32 value)
bd943159 940{
99ea7127
KP		 941 struct drm_device *dev = intel_dp->base.base.dev;
942 struct drm_i915_private *dev_priv = dev->dev_private;
32ce697c 943
99ea7127
KP		 944 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
945 mask, value,
946 I915_READ(PCH_PP_STATUS),
947 I915_READ(PCH_PP_CONTROL));
32ce697c 948
99ea7127
KP		 949 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
950 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
951 I915_READ(PCH_PP_STATUS),
952 I915_READ(PCH_PP_CONTROL));
32ce697c 953 }
99ea7127 954}
32ce697c 955
99ea7127
KP		 956static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
957{
958 DRM_DEBUG_KMS("Wait for panel power on\n");
959 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 960}
961
99ea7127
KP		 962static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
963{
964 DRM_DEBUG_KMS("Wait for panel power off time\n");
965 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
966}
967
968static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
969{
970 DRM_DEBUG_KMS("Wait for panel power cycle\n");
971 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
972}
973
974
832dd3c1
KP		 975/* Read the current pp_control value, unlocking the register if it
976 * is locked
977 */
978
979static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
980{
981 u32 control = I915_READ(PCH_PP_CONTROL);
982
983 control &= ~PANEL_UNLOCK_MASK;
984 control |= PANEL_UNLOCK_REGS;
985 return control;
bd943159
KP		 986}
987
5d613501
JB		 988static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
989{
990 struct drm_device *dev = intel_dp->base.base.dev;
991 struct drm_i915_private *dev_priv = dev->dev_private;
992 u32 pp;
993
97af61f5
KP		 994 if (!is_edp(intel_dp))
995 return;
f01eca2e 996 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 997
bd943159
KP		 998 WARN(intel_dp->want_panel_vdd,
999 "eDP VDD already requested on\n");
1000
1001 intel_dp->want_panel_vdd = true;
99ea7127 1002
bd943159
KP		 1003 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1004 DRM_DEBUG_KMS("eDP VDD already on\n");
1005 return;
1006 }
1007
99ea7127
KP		 1008 if (!ironlake_edp_have_panel_power(intel_dp))
1009 ironlake_wait_panel_power_cycle(intel_dp);
1010
832dd3c1 1011 pp = ironlake_get_pp_control(dev_priv);
5d613501
JB		 1012 pp |= EDP_FORCE_VDD;
1013 I915_WRITE(PCH_PP_CONTROL, pp);
1014 POSTING_READ(PCH_PP_CONTROL);
f01eca2e
KP		 1015 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1016 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
ebf33b18
KP		 1017
1018 /*
1019 * If the panel wasn't on, delay before accessing aux channel
1020 */
1021 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1022 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1023 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1024 }
5d613501
JB		 1025}
1026
bd943159 1027static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501
JB		 1028{
1029 struct drm_device *dev = intel_dp->base.base.dev;
1030 struct drm_i915_private *dev_priv = dev->dev_private;
1031 u32 pp;
1032
bd943159 1033 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
832dd3c1 1034 pp = ironlake_get_pp_control(dev_priv);
bd943159
KP		 1035 pp &= ~EDP_FORCE_VDD;
1036 I915_WRITE(PCH_PP_CONTROL, pp);
1037 POSTING_READ(PCH_PP_CONTROL);
1038
1039 /* Make sure sequencer is idle before allowing subsequent activity */
1040 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1041 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
99ea7127
KP		 1042
1043 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1044 }
1045}
5d613501 1046
bd943159
KP		 1047static void ironlake_panel_vdd_work(struct work_struct *__work)
1048{
1049 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1050 struct intel_dp, panel_vdd_work);
1051 struct drm_device *dev = intel_dp->base.base.dev;
1052
627f7675 1053 mutex_lock(&dev->mode_config.mutex);
bd943159 1054 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1055 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1056}
1057
1058static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1059{
97af61f5
KP		 1060 if (!is_edp(intel_dp))
1061 return;
5d613501 1062
bd943159
KP		 1063 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1064 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1065
bd943159
KP		 1066 intel_dp->want_panel_vdd = false;
1067
1068 if (sync) {
1069 ironlake_panel_vdd_off_sync(intel_dp);
1070 } else {
1071 /*
1072 * Queue the timer to fire a long
1073 * time from now (relative to the power down delay)
1074 * to keep the panel power up across a sequence of operations
1075 */
1076 schedule_delayed_work(&intel_dp->panel_vdd_work,
1077 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1078 }
5d613501
JB		 1079}
1080
86a3073e 1081static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1082{
01cb9ea6 1083 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1084 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1085 u32 pp;
9934c132 1086
97af61f5 1087 if (!is_edp(intel_dp))
bd943159 1088 return;
99ea7127
KP		 1089
1090 DRM_DEBUG_KMS("Turn eDP power on\n");
1091
1092 if (ironlake_edp_have_panel_power(intel_dp)) {
1093 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1094 return;
99ea7127 1095 }
9934c132 1096
99ea7127 1097 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1098
99ea7127 1099 pp = ironlake_get_pp_control(dev_priv);
05ce1a49
KP		 1100 if (IS_GEN5(dev)) {
1101 /* ILK workaround: disable reset around power sequence */
1102 pp &= ~PANEL_POWER_RESET;
1103 I915_WRITE(PCH_PP_CONTROL, pp);
1104 POSTING_READ(PCH_PP_CONTROL);
1105 }
37c6c9b0 1106
1c0ae80a 1107 pp |= POWER_TARGET_ON;
99ea7127
KP		 1108 if (!IS_GEN5(dev))
1109 pp |= PANEL_POWER_RESET;
1110
9934c132 1111 I915_WRITE(PCH_PP_CONTROL, pp);
01cb9ea6 1112 POSTING_READ(PCH_PP_CONTROL);
9934c132 1113
99ea7127 1114 ironlake_wait_panel_on(intel_dp);
9934c132 1115
05ce1a49
KP		 1116 if (IS_GEN5(dev)) {
1117 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1118 I915_WRITE(PCH_PP_CONTROL, pp);
1119 POSTING_READ(PCH_PP_CONTROL);
1120 }
9934c132
JB		 1121}
1122
99ea7127 1123static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1124{
99ea7127 1125 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1126 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1127 u32 pp;
9934c132 1128
97af61f5
KP		 1129 if (!is_edp(intel_dp))
1130 return;
37c6c9b0 1131
99ea7127 1132 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1133
6cb49835 1134 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1135
99ea7127 1136 pp = ironlake_get_pp_control(dev_priv);
35a38556
DV		 1137 /* We need to switch off panel power _and_ force vdd, for otherwise some
1138 * panels get very unhappy and cease to work. */
1139 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
99ea7127
KP		 1140 I915_WRITE(PCH_PP_CONTROL, pp);
1141 POSTING_READ(PCH_PP_CONTROL);
9934c132 1142
35a38556
DV		 1143 intel_dp->want_panel_vdd = false;
1144
99ea7127 1145 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1146}
1147
86a3073e 1148static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1149{
f01eca2e 1150 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1151 struct drm_i915_private *dev_priv = dev->dev_private;
1152 u32 pp;
1153
f01eca2e
KP		 1154 if (!is_edp(intel_dp))
1155 return;
1156
28c97730 1157 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1158 /*
1159 * If we enable the backlight right away following a panel power
1160 * on, we may see slight flicker as the panel syncs with the eDP
1161 * link. So delay a bit to make sure the image is solid before
1162 * allowing it to appear.
1163 */
f01eca2e 1164 msleep(intel_dp->backlight_on_delay);
832dd3c1 1165 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1166 pp |= EDP_BLC_ENABLE;
1167 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e 1168 POSTING_READ(PCH_PP_CONTROL);
32f9d658
ZW		 1169}
1170
86a3073e 1171static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1172{
f01eca2e 1173 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1174 struct drm_i915_private *dev_priv = dev->dev_private;
1175 u32 pp;
1176
f01eca2e
KP		 1177 if (!is_edp(intel_dp))
1178 return;
1179
28c97730 1180 DRM_DEBUG_KMS("\n");
832dd3c1 1181 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1182 pp &= ~EDP_BLC_ENABLE;
1183 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e
KP		 1184 POSTING_READ(PCH_PP_CONTROL);
1185 msleep(intel_dp->backlight_off_delay);
32f9d658 1186}
a4fc5ed6 1187
2bd2ad64 1188static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1189{
2bd2ad64
DV		 1190 struct drm_device *dev = intel_dp->base.base.dev;
1191 struct drm_crtc *crtc = intel_dp->base.base.crtc;
d240f20f
JB		 1192 struct drm_i915_private *dev_priv = dev->dev_private;
1193 u32 dpa_ctl;
1194
2bd2ad64
DV		 1195 assert_pipe_disabled(dev_priv,
1196 to_intel_crtc(crtc)->pipe);
1197
d240f20f
JB		 1198 DRM_DEBUG_KMS("\n");
1199 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1200 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1201 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1202
1203 /* We don't adjust intel_dp->DP while tearing down the link, to
1204 * facilitate link retraining (e.g. after hotplug). Hence clear all
1205 * enable bits here to ensure that we don't enable too much. */
1206 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1207 intel_dp->DP |= DP_PLL_ENABLE;
1208 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1209 POSTING_READ(DP_A);
1210 udelay(200);
d240f20f
JB		 1211}
1212
2bd2ad64 1213static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1214{
2bd2ad64
DV		 1215 struct drm_device *dev = intel_dp->base.base.dev;
1216 struct drm_crtc *crtc = intel_dp->base.base.crtc;
d240f20f
JB		 1217 struct drm_i915_private *dev_priv = dev->dev_private;
1218 u32 dpa_ctl;
1219
2bd2ad64
DV		 1220 assert_pipe_disabled(dev_priv,
1221 to_intel_crtc(crtc)->pipe);
1222
d240f20f 1223 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1224 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1225 "dp pll off, should be on\n");
1226 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1227
1228 /* We can't rely on the value tracked for the DP register in
1229 * intel_dp->DP because link_down must not change that (otherwise link
1230 * re-training will fail. */
298b0b39 1231 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1232 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1233 POSTING_READ(DP_A);
d240f20f
JB		 1234 udelay(200);
1235}
1236
c7ad3810
JB		 1237/* If the sink supports it, try to set the power state appropriately */
1238static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1239{
1240 int ret, i;
1241
1242 /* Should have a valid DPCD by this point */
1243 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1244 return;
1245
1246 if (mode != DRM_MODE_DPMS_ON) {
1247 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1248 DP_SET_POWER_D3);
1249 if (ret != 1)
1250 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1251 } else {
1252 /*
1253 * When turning on, we need to retry for 1ms to give the sink
1254 * time to wake up.
1255 */
1256 for (i = 0; i < 3; i++) {
1257 ret = intel_dp_aux_native_write_1(intel_dp,
1258 DP_SET_POWER,
1259 DP_SET_POWER_D0);
1260 if (ret == 1)
1261 break;
1262 msleep(1);
1263 }
1264 }
1265}
1266
19d8fe15
DV		 1267static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1268 enum pipe *pipe)
d240f20f 1269{
19d8fe15
DV		 1270 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1271 struct drm_device *dev = encoder->base.dev;
1272 struct drm_i915_private *dev_priv = dev->dev_private;
1273 u32 tmp = I915_READ(intel_dp->output_reg);
1274
1275 if (!(tmp & DP_PORT_EN))
1276 return false;
1277
1278 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1279 *pipe = PORT_TO_PIPE_CPT(tmp);
1280 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1281 *pipe = PORT_TO_PIPE(tmp);
1282 } else {
1283 u32 trans_sel;
1284 u32 trans_dp;
1285 int i;
1286
1287 switch (intel_dp->output_reg) {
1288 case PCH_DP_B:
1289 trans_sel = TRANS_DP_PORT_SEL_B;
1290 break;
1291 case PCH_DP_C:
1292 trans_sel = TRANS_DP_PORT_SEL_C;
1293 break;
1294 case PCH_DP_D:
1295 trans_sel = TRANS_DP_PORT_SEL_D;
1296 break;
1297 default:
1298 return true;
1299 }
1300
1301 for_each_pipe(i) {
1302 trans_dp = I915_READ(TRANS_DP_CTL(i));
1303 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1304 *pipe = i;
1305 return true;
1306 }
1307 }
1308 }
1309
1310 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp->output_reg);
d240f20f 1311
19d8fe15
DV		 1312 return true;
1313}
1314
e8cb4558 1315static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1316{
e8cb4558 1317 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
6cb49835
DV		 1318
1319 /* Make sure the panel is off before trying to change the mode. But also
1320 * ensure that we have vdd while we switch off the panel. */
1321 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1322 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1323 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1324 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1325
1326 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1327 if (!is_cpu_edp(intel_dp))
1328 intel_dp_link_down(intel_dp);
d240f20f
JB		 1329}
1330
2bd2ad64
DV		 1331static void intel_post_disable_dp(struct intel_encoder *encoder)
1332{
1333 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1334
3739850b
DV		 1335 if (is_cpu_edp(intel_dp)) {
1336 intel_dp_link_down(intel_dp);
2bd2ad64 1337 ironlake_edp_pll_off(intel_dp);
3739850b 1338 }
2bd2ad64
DV		 1339}
1340
e8cb4558 1341static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1342{
e8cb4558
DV		 1343 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1344 struct drm_device *dev = encoder->base.dev;
1345 struct drm_i915_private *dev_priv = dev->dev_private;
1346 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1347
0c33d8d7
DV		 1348 if (WARN_ON(dp_reg & DP_PORT_EN))
1349 return;
1350
97af61f5 1351 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1352 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
0c33d8d7
DV		 1353 intel_dp_start_link_train(intel_dp);
1354 ironlake_edp_panel_on(intel_dp);
1355 ironlake_edp_panel_vdd_off(intel_dp, true);
1356 intel_dp_complete_link_train(intel_dp);
f01eca2e 1357 ironlake_edp_backlight_on(intel_dp);
d240f20f
JB		 1358}
1359
2bd2ad64 1360static void intel_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1361{
2bd2ad64 1362 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
0a91ca29 1363
2bd2ad64
DV		 1364 if (is_cpu_edp(intel_dp))
1365 ironlake_edp_pll_on(intel_dp);
a4fc5ed6
KP		 1366}
1367
1368/*
df0c237d
JB		 1369 * Native read with retry for link status and receiver capability reads for
1370 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1371 */
1372static bool
df0c237d
JB		 1373intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1374 uint8_t *recv, int recv_bytes)
a4fc5ed6 1375{
61da5fab
JB		 1376 int ret, i;
1377
df0c237d
JB		 1378 /*
1379 * Sinks are *supposed* to come up within 1ms from an off state,
1380 * but we're also supposed to retry 3 times per the spec.
1381 */
61da5fab 1382 for (i = 0; i < 3; i++) {
df0c237d
JB		 1383 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1384 recv_bytes);
1385 if (ret == recv_bytes)
61da5fab
JB		 1386 return true;
1387 msleep(1);
1388 }
a4fc5ed6 1389
61da5fab 1390 return false;
a4fc5ed6
KP		 1391}
1392
1393/*
1394 * Fetch AUX CH registers 0x202 - 0x207 which contain
1395 * link status information
1396 */
1397static bool
93f62dad 1398intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1399{
df0c237d
JB		 1400 return intel_dp_aux_native_read_retry(intel_dp,
1401 DP_LANE0_1_STATUS,
93f62dad 1402 link_status,
df0c237d 1403 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1404}
1405
1406static uint8_t
1407intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1408 int r)
1409{
1410 return link_status[r - DP_LANE0_1_STATUS];
1411}
1412
a4fc5ed6 1413static uint8_t
93f62dad 1414intel_get_adjust_request_voltage(uint8_t adjust_request[2],
a4fc5ed6
KP		 1415 int lane)
1416{
a4fc5ed6
KP		 1417 int s = ((lane & 1) ?
1418 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1419 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
93f62dad 1420 uint8_t l = adjust_request[lane>>1];
a4fc5ed6
KP		 1421
1422 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1423}
1424
1425static uint8_t
93f62dad 1426intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
a4fc5ed6
KP		 1427 int lane)
1428{
a4fc5ed6
KP		 1429 int s = ((lane & 1) ?
1430 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1431 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
93f62dad 1432 uint8_t l = adjust_request[lane>>1];
a4fc5ed6
KP		 1433
1434 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1435}
1436
1437
1438#if 0
1439static char *voltage_names[] = {
1440 "0.4V", "0.6V", "0.8V", "1.2V"
1441};
1442static char *pre_emph_names[] = {
1443 "0dB", "3.5dB", "6dB", "9.5dB"
1444};
1445static char *link_train_names[] = {
1446 "pattern 1", "pattern 2", "idle", "off"
1447};
1448#endif
1449
1450/*
1451 * These are source-specific values; current Intel hardware supports
1452 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1453 */
a4fc5ed6
KP		 1454
1455static uint8_t
1a2eb460 1456intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1457{
1a2eb460
KP		 1458 struct drm_device *dev = intel_dp->base.base.dev;
1459
1460 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1461 return DP_TRAIN_VOLTAGE_SWING_800;
1462 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1463 return DP_TRAIN_VOLTAGE_SWING_1200;
1464 else
1465 return DP_TRAIN_VOLTAGE_SWING_800;
1466}
1467
1468static uint8_t
1469intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1470{
1471 struct drm_device *dev = intel_dp->base.base.dev;
1472
d6c0d722
PZ		 1473 if (IS_HASWELL(dev)) {
1474 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1475 case DP_TRAIN_VOLTAGE_SWING_400:
1476 return DP_TRAIN_PRE_EMPHASIS_9_5;
1477 case DP_TRAIN_VOLTAGE_SWING_600:
1478 return DP_TRAIN_PRE_EMPHASIS_6;
1479 case DP_TRAIN_VOLTAGE_SWING_800:
1480 return DP_TRAIN_PRE_EMPHASIS_3_5;
1481 case DP_TRAIN_VOLTAGE_SWING_1200:
1482 default:
1483 return DP_TRAIN_PRE_EMPHASIS_0;
1484 }
1485 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1486 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1487 case DP_TRAIN_VOLTAGE_SWING_400:
1488 return DP_TRAIN_PRE_EMPHASIS_6;
1489 case DP_TRAIN_VOLTAGE_SWING_600:
1490 case DP_TRAIN_VOLTAGE_SWING_800:
1491 return DP_TRAIN_PRE_EMPHASIS_3_5;
1492 default:
1493 return DP_TRAIN_PRE_EMPHASIS_0;
1494 }
1495 } else {
1496 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1497 case DP_TRAIN_VOLTAGE_SWING_400:
1498 return DP_TRAIN_PRE_EMPHASIS_6;
1499 case DP_TRAIN_VOLTAGE_SWING_600:
1500 return DP_TRAIN_PRE_EMPHASIS_6;
1501 case DP_TRAIN_VOLTAGE_SWING_800:
1502 return DP_TRAIN_PRE_EMPHASIS_3_5;
1503 case DP_TRAIN_VOLTAGE_SWING_1200:
1504 default:
1505 return DP_TRAIN_PRE_EMPHASIS_0;
1506 }
a4fc5ed6
KP		 1507 }
1508}
1509
1510static void
93f62dad 1511intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1512{
1513 uint8_t v = 0;
1514 uint8_t p = 0;
1515 int lane;
93f62dad 1516 uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1a2eb460
KP		 1517 uint8_t voltage_max;
1518 uint8_t preemph_max;
a4fc5ed6 1519
33a34e4e 1520 for (lane = 0; lane < intel_dp->lane_count; lane++) {
93f62dad
KP		 1521 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1522 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
a4fc5ed6
KP		 1523
1524 if (this_v > v)
1525 v = this_v;
1526 if (this_p > p)
1527 p = this_p;
1528 }
1529
1a2eb460 1530 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1531 if (v >= voltage_max)
1532 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1533
1a2eb460
KP		 1534 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1535 if (p >= preemph_max)
1536 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1537
1538 for (lane = 0; lane < 4; lane++)
33a34e4e 1539 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1540}
1541
1542static uint32_t
93f62dad 1543intel_dp_signal_levels(uint8_t train_set)
a4fc5ed6 1544{
3cf2efb1 1545 uint32_t signal_levels = 0;
a4fc5ed6 1546
3cf2efb1 1547 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1548 case DP_TRAIN_VOLTAGE_SWING_400:
1549 default:
1550 signal_levels |= DP_VOLTAGE_0_4;
1551 break;
1552 case DP_TRAIN_VOLTAGE_SWING_600:
1553 signal_levels |= DP_VOLTAGE_0_6;
1554 break;
1555 case DP_TRAIN_VOLTAGE_SWING_800:
1556 signal_levels |= DP_VOLTAGE_0_8;
1557 break;
1558 case DP_TRAIN_VOLTAGE_SWING_1200:
1559 signal_levels |= DP_VOLTAGE_1_2;
1560 break;
1561 }
3cf2efb1 1562 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1563 case DP_TRAIN_PRE_EMPHASIS_0:
1564 default:
1565 signal_levels |= DP_PRE_EMPHASIS_0;
1566 break;
1567 case DP_TRAIN_PRE_EMPHASIS_3_5:
1568 signal_levels |= DP_PRE_EMPHASIS_3_5;
1569 break;
1570 case DP_TRAIN_PRE_EMPHASIS_6:
1571 signal_levels |= DP_PRE_EMPHASIS_6;
1572 break;
1573 case DP_TRAIN_PRE_EMPHASIS_9_5:
1574 signal_levels |= DP_PRE_EMPHASIS_9_5;
1575 break;
1576 }
1577 return signal_levels;
1578}
1579
e3421a18
ZW		 1580/* Gen6's DP voltage swing and pre-emphasis control */
1581static uint32_t
1582intel_gen6_edp_signal_levels(uint8_t train_set)
1583{
3c5a62b5
YL		 1584 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1585 DP_TRAIN_PRE_EMPHASIS_MASK);
1586 switch (signal_levels) {
e3421a18 1587 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1588 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1589 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1590 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1591 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1592 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1593 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1594 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1595 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1596 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1597 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1598 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1599 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1600 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1601 default:
3c5a62b5
YL		 1602 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1603 "0x%x\n", signal_levels);
1604 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1605 }
1606}
1607
1a2eb460
KP		 1608/* Gen7's DP voltage swing and pre-emphasis control */
1609static uint32_t
1610intel_gen7_edp_signal_levels(uint8_t train_set)
1611{
1612 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1613 DP_TRAIN_PRE_EMPHASIS_MASK);
1614 switch (signal_levels) {
1615 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1616 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1617 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1618 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1619 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1620 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1621
1622 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1623 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1624 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1625 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1626
1627 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1628 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1629 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1630 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1631
1632 default:
1633 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1634 "0x%x\n", signal_levels);
1635 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1636 }
1637}
1638
d6c0d722
PZ		 1639/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1640static uint32_t
1641intel_dp_signal_levels_hsw(uint8_t train_set)
1642{
1643 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1644 DP_TRAIN_PRE_EMPHASIS_MASK);
1645 switch (signal_levels) {
1646 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1647 return DDI_BUF_EMP_400MV_0DB_HSW;
1648 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1649 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1650 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1651 return DDI_BUF_EMP_400MV_6DB_HSW;
1652 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1653 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1654
1655 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1656 return DDI_BUF_EMP_600MV_0DB_HSW;
1657 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1658 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1659 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1660 return DDI_BUF_EMP_600MV_6DB_HSW;
1661
1662 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1663 return DDI_BUF_EMP_800MV_0DB_HSW;
1664 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1665 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1666 default:
1667 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1668 "0x%x\n", signal_levels);
1669 return DDI_BUF_EMP_400MV_0DB_HSW;
1670 }
1671}
1672
a4fc5ed6
KP		 1673static uint8_t
1674intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1675 int lane)
1676{
a4fc5ed6 1677 int s = (lane & 1) * 4;
93f62dad 1678 uint8_t l = link_status[lane>>1];
a4fc5ed6
KP		 1679
1680 return (l >> s) & 0xf;
1681}
1682
1683/* Check for clock recovery is done on all channels */
1684static bool
1685intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1686{
1687 int lane;
1688 uint8_t lane_status;
1689
1690 for (lane = 0; lane < lane_count; lane++) {
1691 lane_status = intel_get_lane_status(link_status, lane);
1692 if ((lane_status & DP_LANE_CR_DONE) == 0)
1693 return false;
1694 }
1695 return true;
1696}
1697
1698/* Check to see if channel eq is done on all channels */
1699#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1700 DP_LANE_CHANNEL_EQ_DONE|\
1701 DP_LANE_SYMBOL_LOCKED)
1702static bool
93f62dad 1703intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1704{
1705 uint8_t lane_align;
1706 uint8_t lane_status;
1707 int lane;
1708
93f62dad 1709 lane_align = intel_dp_link_status(link_status,
a4fc5ed6
KP		 1710 DP_LANE_ALIGN_STATUS_UPDATED);
1711 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1712 return false;
33a34e4e 1713 for (lane = 0; lane < intel_dp->lane_count; lane++) {
93f62dad 1714 lane_status = intel_get_lane_status(link_status, lane);
a4fc5ed6
KP		 1715 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1716 return false;
1717 }
1718 return true;
1719}
1720
1721static bool
ea5b213a 1722intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1723 uint32_t dp_reg_value,
58e10eb9 1724 uint8_t dp_train_pat)
a4fc5ed6 1725{
4ef69c7a 1726 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1727 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6 1728 int ret;
d6c0d722 1729 uint32_t temp;
a4fc5ed6 1730
d6c0d722
PZ		 1731 if (IS_HASWELL(dev)) {
1732 temp = I915_READ(DP_TP_CTL(intel_dp->port));
1733
1734 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1735 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1736 else
1737 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1738
1739 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1740 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1741 case DP_TRAINING_PATTERN_DISABLE:
1742 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1743 I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1744
1745 if (wait_for((I915_READ(DP_TP_STATUS(intel_dp->port)) &
1746 DP_TP_STATUS_IDLE_DONE), 1))
1747 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1748
1749 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1750 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1751
1752 break;
1753 case DP_TRAINING_PATTERN_1:
1754 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1755 break;
1756 case DP_TRAINING_PATTERN_2:
1757 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1758 break;
1759 case DP_TRAINING_PATTERN_3:
1760 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1761 break;
1762 }
1763 I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1764
1765 } else if (HAS_PCH_CPT(dev) &&
1766 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
47ea7542
PZ		 1767 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1768
1769 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1770 case DP_TRAINING_PATTERN_DISABLE:
1771 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1772 break;
1773 case DP_TRAINING_PATTERN_1:
1774 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1775 break;
1776 case DP_TRAINING_PATTERN_2:
1777 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1778 break;
1779 case DP_TRAINING_PATTERN_3:
1780 DRM_ERROR("DP training pattern 3 not supported\n");
1781 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1782 break;
1783 }
1784
1785 } else {
1786 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1787
1788 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1789 case DP_TRAINING_PATTERN_DISABLE:
1790 dp_reg_value |= DP_LINK_TRAIN_OFF;
1791 break;
1792 case DP_TRAINING_PATTERN_1:
1793 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1794 break;
1795 case DP_TRAINING_PATTERN_2:
1796 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1797 break;
1798 case DP_TRAINING_PATTERN_3:
1799 DRM_ERROR("DP training pattern 3 not supported\n");
1800 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1801 break;
1802 }
1803 }
1804
ea5b213a
CW		 1805 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1806 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1807
ea5b213a 1808 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1809 DP_TRAINING_PATTERN_SET,
1810 dp_train_pat);
1811
47ea7542
PZ		 1812 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1813 DP_TRAINING_PATTERN_DISABLE) {
1814 ret = intel_dp_aux_native_write(intel_dp,
1815 DP_TRAINING_LANE0_SET,
1816 intel_dp->train_set,
1817 intel_dp->lane_count);
1818 if (ret != intel_dp->lane_count)
1819 return false;
1820 }
a4fc5ed6
KP		 1821
1822 return true;
1823}
1824
33a34e4e 1825/* Enable corresponding port and start training pattern 1 */
a4fc5ed6 1826static void
33a34e4e 1827intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1828{
4ef69c7a 1829 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6
KP		 1830 int i;
1831 uint8_t voltage;
1832 bool clock_recovery = false;
cdb0e95b 1833 int voltage_tries, loop_tries;
ea5b213a 1834 uint32_t DP = intel_dp->DP;
a4fc5ed6 1835
3cf2efb1
CW		 1836 /* Write the link configuration data */
1837 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1838 intel_dp->link_configuration,
1839 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1840
1841 DP |= DP_PORT_EN;
1a2eb460 1842
33a34e4e 1843 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 1844 voltage = 0xff;
cdb0e95b
KP		 1845 voltage_tries = 0;
1846 loop_tries = 0;
a4fc5ed6
KP		 1847 clock_recovery = false;
1848 for (;;) {
33a34e4e 1849 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 1850 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1851 uint32_t signal_levels;
417e822d 1852
d6c0d722
PZ		 1853 if (IS_HASWELL(dev)) {
1854 signal_levels = intel_dp_signal_levels_hsw(
1855 intel_dp->train_set[0]);
1856 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1857 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1858 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1859 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1860 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1861 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1862 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1863 } else {
93f62dad 1864 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1865 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1866 }
d6c0d722
PZ		 1867 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
1868 signal_levels);
a4fc5ed6 1869
47ea7542 1870 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1871 DP_TRAINING_PATTERN_1 |
1872 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 1873 break;
a4fc5ed6
KP		 1874 /* Set training pattern 1 */
1875
3cf2efb1 1876 udelay(100);
93f62dad
KP		 1877 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1878 DRM_ERROR("failed to get link status\n");
a4fc5ed6 1879 break;
93f62dad 1880 }
a4fc5ed6 1881
93f62dad
KP		 1882 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1883 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 1884 clock_recovery = true;
1885 break;
1886 }
1887
1888 /* Check to see if we've tried the max voltage */
1889 for (i = 0; i < intel_dp->lane_count; i++)
1890 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 1891 break;
0d710688 1892 if (i == intel_dp->lane_count && voltage_tries == 5) {
cdb0e95b
KP		 1893 ++loop_tries;
1894 if (loop_tries == 5) {
1895 DRM_DEBUG_KMS("too many full retries, give up\n");
1896 break;
1897 }
1898 memset(intel_dp->train_set, 0, 4);
1899 voltage_tries = 0;
1900 continue;
1901 }
a4fc5ed6 1902
3cf2efb1
CW		 1903 /* Check to see if we've tried the same voltage 5 times */
1904 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
cdb0e95b
KP		 1905 ++voltage_tries;
1906 if (voltage_tries == 5) {
1907 DRM_DEBUG_KMS("too many voltage retries, give up\n");
a4fc5ed6 1908 break;
cdb0e95b 1909 }
3cf2efb1 1910 } else
cdb0e95b 1911 voltage_tries = 0;
3cf2efb1 1912 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 1913
3cf2efb1 1914 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1915 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 1916 }
1917
33a34e4e
JB		 1918 intel_dp->DP = DP;
1919}
1920
1921static void
1922intel_dp_complete_link_train(struct intel_dp *intel_dp)
1923{
4ef69c7a 1924 struct drm_device *dev = intel_dp->base.base.dev;
33a34e4e 1925 bool channel_eq = false;
37f80975 1926 int tries, cr_tries;
33a34e4e
JB		 1927 uint32_t DP = intel_dp->DP;
1928
a4fc5ed6
KP		 1929 /* channel equalization */
1930 tries = 0;
37f80975 1931 cr_tries = 0;
a4fc5ed6
KP		 1932 channel_eq = false;
1933 for (;;) {
33a34e4e 1934 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
e3421a18 1935 uint32_t signal_levels;
93f62dad 1936 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1937
37f80975
JB		 1938 if (cr_tries > 5) {
1939 DRM_ERROR("failed to train DP, aborting\n");
1940 intel_dp_link_down(intel_dp);
1941 break;
1942 }
1943
d6c0d722
PZ		 1944 if (IS_HASWELL(dev)) {
1945 signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]);
1946 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1947 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1948 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1949 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1950 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1951 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1952 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1953 } else {
93f62dad 1954 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1955 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1956 }
1957
a4fc5ed6 1958 /* channel eq pattern */
47ea7542 1959 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1960 DP_TRAINING_PATTERN_2 |
1961 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 1962 break;
1963
3cf2efb1 1964 udelay(400);
93f62dad 1965 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 1966 break;
a4fc5ed6 1967
37f80975 1968 /* Make sure clock is still ok */
93f62dad 1969 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 1970 intel_dp_start_link_train(intel_dp);
1971 cr_tries++;
1972 continue;
1973 }
1974
93f62dad 1975 if (intel_channel_eq_ok(intel_dp, link_status)) {
3cf2efb1
CW		 1976 channel_eq = true;
1977 break;
1978 }
a4fc5ed6 1979
37f80975
JB		 1980 /* Try 5 times, then try clock recovery if that fails */
1981 if (tries > 5) {
1982 intel_dp_link_down(intel_dp);
1983 intel_dp_start_link_train(intel_dp);
1984 tries = 0;
1985 cr_tries++;
1986 continue;
1987 }
a4fc5ed6 1988
3cf2efb1 1989 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1990 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 1991 ++tries;
869184a6 1992 }
3cf2efb1 1993
d6c0d722
PZ		 1994 if (channel_eq)
1995 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
1996
47ea7542 1997 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 1998}
1999
2000static void
ea5b213a 2001intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2002{
4ef69c7a 2003 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 2004 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 2005 uint32_t DP = intel_dp->DP;
a4fc5ed6 2006
0c33d8d7 2007 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2008 return;
2009
28c97730 2010 DRM_DEBUG_KMS("\n");
32f9d658 2011
1a2eb460 2012 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 2013 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2014 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2015 } else {
2016 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2017 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2018 }
fe255d00 2019 POSTING_READ(intel_dp->output_reg);
5eb08b69 2020
fe255d00 2021 msleep(17);
5eb08b69 2022
493a7081 2023 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2024 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
31acbcc4
CW		 2025 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2026
5bddd17f
EA		 2027 /* Hardware workaround: leaving our transcoder select
2028 * set to transcoder B while it's off will prevent the
2029 * corresponding HDMI output on transcoder A.
2030 *
2031 * Combine this with another hardware workaround:
2032 * transcoder select bit can only be cleared while the
2033 * port is enabled.
2034 */
2035 DP &= ~DP_PIPEB_SELECT;
2036 I915_WRITE(intel_dp->output_reg, DP);
2037
2038 /* Changes to enable or select take place the vblank
2039 * after being written.
2040 */
31acbcc4
CW		 2041 if (crtc == NULL) {
2042 /* We can arrive here never having been attached
2043 * to a CRTC, for instance, due to inheriting
2044 * random state from the BIOS.
2045 *
2046 * If the pipe is not running, play safe and
2047 * wait for the clocks to stabilise before
2048 * continuing.
2049 */
2050 POSTING_READ(intel_dp->output_reg);
2051 msleep(50);
2052 } else
2053 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
5bddd17f
EA		 2054 }
2055
832afda6 2056 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2057 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2058 POSTING_READ(intel_dp->output_reg);
f01eca2e 2059 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2060}
2061
26d61aad
KP		 2062static bool
2063intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2064{
92fd8fd1 2065 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
b091cd92
AJ		 2066 sizeof(intel_dp->dpcd)) == 0)
2067 return false; /* aux transfer failed */
92fd8fd1 2068
b091cd92
AJ		 2069 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2070 return false; /* DPCD not present */
2071
2072 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2073 DP_DWN_STRM_PORT_PRESENT))
2074 return true; /* native DP sink */
2075
2076 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2077 return true; /* no per-port downstream info */
2078
2079 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2080 intel_dp->downstream_ports,
2081 DP_MAX_DOWNSTREAM_PORTS) == 0)
2082 return false; /* downstream port status fetch failed */
2083
2084 return true;
92fd8fd1
KP		 2085}
2086
0d198328
AJ		 2087static void
2088intel_dp_probe_oui(struct intel_dp *intel_dp)
2089{
2090 u8 buf[3];
2091
2092 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2093 return;
2094
351cfc34
DV		 2095 ironlake_edp_panel_vdd_on(intel_dp);
2096
0d198328
AJ		 2097 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2098 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2099 buf[0], buf[1], buf[2]);
2100
2101 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2102 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2103 buf[0], buf[1], buf[2]);
351cfc34
DV		 2104
2105 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2106}
2107
a60f0e38
JB		 2108static bool
2109intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2110{
2111 int ret;
2112
2113 ret = intel_dp_aux_native_read_retry(intel_dp,
2114 DP_DEVICE_SERVICE_IRQ_VECTOR,
2115 sink_irq_vector, 1);
2116 if (!ret)
2117 return false;
2118
2119 return true;
2120}
2121
2122static void
2123intel_dp_handle_test_request(struct intel_dp *intel_dp)
2124{
2125 /* NAK by default */
2126 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
2127}
2128
a4fc5ed6
KP		 2129/*
2130 * According to DP spec
2131 * 5.1.2:
2132 * 1. Read DPCD
2133 * 2. Configure link according to Receiver Capabilities
2134 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2135 * 4. Check link status on receipt of hot-plug interrupt
2136 */
2137
2138static void
ea5b213a 2139intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2140{
a60f0e38 2141 u8 sink_irq_vector;
93f62dad 2142 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2143
24e804ba 2144 if (!intel_dp->base.connectors_active)
d2b996ac 2145 return;
59cd09e1 2146
24e804ba 2147 if (WARN_ON(!intel_dp->base.base.crtc))
a4fc5ed6
KP		 2148 return;
2149
92fd8fd1 2150 /* Try to read receiver status if the link appears to be up */
93f62dad 2151 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2152 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2153 return;
2154 }
2155
92fd8fd1 2156 /* Now read the DPCD to see if it's actually running */
26d61aad 2157 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2158 intel_dp_link_down(intel_dp);
2159 return;
2160 }
2161
a60f0e38
JB		 2162 /* Try to read the source of the interrupt */
2163 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2164 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2165 /* Clear interrupt source */
2166 intel_dp_aux_native_write_1(intel_dp,
2167 DP_DEVICE_SERVICE_IRQ_VECTOR,
2168 sink_irq_vector);
2169
2170 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2171 intel_dp_handle_test_request(intel_dp);
2172 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2173 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2174 }
2175
93f62dad 2176 if (!intel_channel_eq_ok(intel_dp, link_status)) {
92fd8fd1
KP		 2177 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2178 drm_get_encoder_name(&intel_dp->base.base));
33a34e4e
JB		 2179 intel_dp_start_link_train(intel_dp);
2180 intel_dp_complete_link_train(intel_dp);
2181 }
a4fc5ed6 2182}
a4fc5ed6 2183
07d3dc18 2184/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2185static enum drm_connector_status
26d61aad 2186intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2187{
07d3dc18
AJ		 2188 uint8_t *dpcd = intel_dp->dpcd;
2189 bool hpd;
2190 uint8_t type;
2191
2192 if (!intel_dp_get_dpcd(intel_dp))
2193 return connector_status_disconnected;
2194
2195 /* if there's no downstream port, we're done */
2196 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2197 return connector_status_connected;
2198
2199 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2200 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2201 if (hpd) {
da131a46 2202 uint8_t reg;
07d3dc18 2203 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
da131a46 2204 &reg, 1))
07d3dc18 2205 return connector_status_unknown;
da131a46
AJ		 2206 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2207 : connector_status_disconnected;
07d3dc18
AJ		 2208 }
2209
2210 /* If no HPD, poke DDC gently */
2211 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2212 return connector_status_connected;
07d3dc18
AJ		 2213
2214 /* Well we tried, say unknown for unreliable port types */
2215 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2216 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2217 return connector_status_unknown;
2218
2219 /* Anything else is out of spec, warn and ignore */
2220 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2221 return connector_status_disconnected;
71ba9000
AJ		 2222}
2223
5eb08b69 2224static enum drm_connector_status
a9756bb5 2225ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2226{
5eb08b69
ZW		 2227 enum drm_connector_status status;
2228
fe16d949
CW		 2229 /* Can't disconnect eDP, but you can close the lid... */
2230 if (is_edp(intel_dp)) {
2231 status = intel_panel_detect(intel_dp->base.base.dev);
2232 if (status == connector_status_unknown)
2233 status = connector_status_connected;
2234 return status;
2235 }
01cb9ea6 2236
26d61aad 2237 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2238}
2239
a4fc5ed6 2240static enum drm_connector_status
a9756bb5 2241g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2242{
4ef69c7a 2243 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 2244 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 2245 uint32_t bit;
5eb08b69 2246
ea5b213a 2247 switch (intel_dp->output_reg) {
a4fc5ed6 2248 case DP_B:
10f76a38 2249 bit = DPB_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2250 break;
2251 case DP_C:
10f76a38 2252 bit = DPC_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2253 break;
2254 case DP_D:
10f76a38 2255 bit = DPD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2256 break;
2257 default:
2258 return connector_status_unknown;
2259 }
2260
10f76a38 2261 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2262 return connector_status_disconnected;
2263
26d61aad 2264 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2265}
2266
8c241fef
KP		 2267static struct edid *
2268intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2269{
2270 struct intel_dp *intel_dp = intel_attached_dp(connector);
2271 struct edid *edid;
d6f24d0f
JB		 2272 int size;
2273
2274 if (is_edp(intel_dp)) {
2275 if (!intel_dp->edid)
2276 return NULL;
2277
2278 size = (intel_dp->edid->extensions + 1) * EDID_LENGTH;
2279 edid = kmalloc(size, GFP_KERNEL);
2280 if (!edid)
2281 return NULL;
2282
2283 memcpy(edid, intel_dp->edid, size);
2284 return edid;
2285 }
8c241fef 2286
8c241fef 2287 edid = drm_get_edid(connector, adapter);
8c241fef
KP		 2288 return edid;
2289}
2290
2291static int
2292intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2293{
2294 struct intel_dp *intel_dp = intel_attached_dp(connector);
2295 int ret;
2296
d6f24d0f
JB		 2297 if (is_edp(intel_dp)) {
2298 drm_mode_connector_update_edid_property(connector,
2299 intel_dp->edid);
2300 ret = drm_add_edid_modes(connector, intel_dp->edid);
2301 drm_edid_to_eld(connector,
2302 intel_dp->edid);
d6f24d0f
JB		 2303 return intel_dp->edid_mode_count;
2304 }
2305
8c241fef 2306 ret = intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2307 return ret;
2308}
2309
2310
a9756bb5
ZW		 2311/**
2312 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2313 *
2314 * \return true if DP port is connected.
2315 * \return false if DP port is disconnected.
2316 */
2317static enum drm_connector_status
2318intel_dp_detect(struct drm_connector *connector, bool force)
2319{
2320 struct intel_dp *intel_dp = intel_attached_dp(connector);
2321 struct drm_device *dev = intel_dp->base.base.dev;
2322 enum drm_connector_status status;
2323 struct edid *edid = NULL;
2324
2325 intel_dp->has_audio = false;
2326
2327 if (HAS_PCH_SPLIT(dev))
2328 status = ironlake_dp_detect(intel_dp);
2329 else
2330 status = g4x_dp_detect(intel_dp);
1b9be9d0 2331
ac66ae83
AJ		 2332 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2333 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2334 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2335 intel_dp->dpcd[6], intel_dp->dpcd[7]);
1b9be9d0 2336
a9756bb5
ZW		 2337 if (status != connector_status_connected)
2338 return status;
2339
0d198328
AJ		 2340 intel_dp_probe_oui(intel_dp);
2341
c3e5f67b
DV		 2342 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2343 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2344 } else {
8c241fef 2345 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2346 if (edid) {
2347 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2348 kfree(edid);
2349 }
a9756bb5
ZW		 2350 }
2351
2352 return connector_status_connected;
a4fc5ed6
KP		 2353}
2354
2355static int intel_dp_get_modes(struct drm_connector *connector)
2356{
df0e9248 2357 struct intel_dp *intel_dp = intel_attached_dp(connector);
4ef69c7a 2358 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 2359 struct drm_i915_private *dev_priv = dev->dev_private;
2360 int ret;
a4fc5ed6
KP		 2361
2362 /* We should parse the EDID data and find out if it has an audio sink
2363 */
2364
8c241fef 2365 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
b9efc480 2366 if (ret) {
d15456de 2367 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
b9efc480
ZY		 2368 struct drm_display_mode *newmode;
2369 list_for_each_entry(newmode, &connector->probed_modes,
2370 head) {
d15456de
KP		 2371 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2372 intel_dp->panel_fixed_mode =
b9efc480
ZY		 2373 drm_mode_duplicate(dev, newmode);
2374 break;
2375 }
2376 }
2377 }
32f9d658 2378 return ret;
b9efc480 2379 }
32f9d658
ZW		 2380
2381 /* if eDP has no EDID, try to use fixed panel mode from VBT */
4d926461 2382 if (is_edp(intel_dp)) {
47f0eb22 2383 /* initialize panel mode from VBT if available for eDP */
d15456de
KP		 2384 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2385 intel_dp->panel_fixed_mode =
47f0eb22 2386 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
d15456de
KP		 2387 if (intel_dp->panel_fixed_mode) {
2388 intel_dp->panel_fixed_mode->type |=
47f0eb22
KP		 2389 DRM_MODE_TYPE_PREFERRED;
2390 }
2391 }
d15456de 2392 if (intel_dp->panel_fixed_mode) {
32f9d658 2393 struct drm_display_mode *mode;
d15456de 2394 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
32f9d658
ZW		 2395 drm_mode_probed_add(connector, mode);
2396 return 1;
2397 }
2398 }
2399 return 0;
a4fc5ed6
KP		 2400}
2401
1aad7ac0
CW		 2402static bool
2403intel_dp_detect_audio(struct drm_connector *connector)
2404{
2405 struct intel_dp *intel_dp = intel_attached_dp(connector);
2406 struct edid *edid;
2407 bool has_audio = false;
2408
8c241fef 2409 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2410 if (edid) {
2411 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2412 kfree(edid);
2413 }
2414
2415 return has_audio;
2416}
2417
f684960e
CW		 2418static int
2419intel_dp_set_property(struct drm_connector *connector,
2420 struct drm_property *property,
2421 uint64_t val)
2422{
e953fd7b 2423 struct drm_i915_private *dev_priv = connector->dev->dev_private;
f684960e
CW		 2424 struct intel_dp *intel_dp = intel_attached_dp(connector);
2425 int ret;
2426
2427 ret = drm_connector_property_set_value(connector, property, val);
2428 if (ret)
2429 return ret;
2430
3f43c48d 2431 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2432 int i = val;
2433 bool has_audio;
2434
2435 if (i == intel_dp->force_audio)
f684960e
CW		 2436 return 0;
2437
1aad7ac0 2438 intel_dp->force_audio = i;
f684960e 2439
c3e5f67b 2440 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2441 has_audio = intel_dp_detect_audio(connector);
2442 else
c3e5f67b 2443 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2444
2445 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2446 return 0;
2447
1aad7ac0 2448 intel_dp->has_audio = has_audio;
f684960e
CW		 2449 goto done;
2450 }
2451
e953fd7b
CW		 2452 if (property == dev_priv->broadcast_rgb_property) {
2453 if (val == !!intel_dp->color_range)
2454 return 0;
2455
2456 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2457 goto done;
2458 }
2459
f684960e
CW		 2460 return -EINVAL;
2461
2462done:
2463 if (intel_dp->base.base.crtc) {
2464 struct drm_crtc *crtc = intel_dp->base.base.crtc;
a6778b3c
DV		 2465 intel_set_mode(crtc, &crtc->mode,
2466 crtc->x, crtc->y, crtc->fb);
f684960e
CW		 2467 }
2468
2469 return 0;
2470}
2471
a4fc5ed6 2472static void
0206e353 2473intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2474{
aaa6fd2a
MG		 2475 struct drm_device *dev = connector->dev;
2476
2477 if (intel_dpd_is_edp(dev))
2478 intel_panel_destroy_backlight(dev);
2479
a4fc5ed6
KP		 2480 drm_sysfs_connector_remove(connector);
2481 drm_connector_cleanup(connector);
55f78c43 2482 kfree(connector);
a4fc5ed6
KP		 2483}
2484
24d05927
DV		 2485static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2486{
2487 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2488
2489 i2c_del_adapter(&intel_dp->adapter);
2490 drm_encoder_cleanup(encoder);
bd943159 2491 if (is_edp(intel_dp)) {
d6f24d0f 2492 kfree(intel_dp->edid);
bd943159
KP		 2493 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2494 ironlake_panel_vdd_off_sync(intel_dp);
2495 }
24d05927
DV		 2496 kfree(intel_dp);
2497}
2498
a4fc5ed6 2499static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 2500 .mode_fixup = intel_dp_mode_fixup,
a4fc5ed6 2501 .mode_set = intel_dp_mode_set,
1f703855 2502 .disable = intel_encoder_noop,
a4fc5ed6
KP		 2503};
2504
2505static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 2506 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 2507 .detect = intel_dp_detect,
2508 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2509 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2510 .destroy = intel_dp_destroy,
2511};
2512
2513static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2514 .get_modes = intel_dp_get_modes,
2515 .mode_valid = intel_dp_mode_valid,
df0e9248 2516 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2517};
2518
a4fc5ed6 2519static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2520 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2521};
2522
995b6762 2523static void
21d40d37 2524intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2525{
ea5b213a 2526 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
c8110e52 2527
885a5014 2528 intel_dp_check_link_status(intel_dp);
c8110e52 2529}
6207937d 2530
e3421a18
ZW		 2531/* Return which DP Port should be selected for Transcoder DP control */
2532int
0206e353 2533intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2534{
2535 struct drm_device *dev = crtc->dev;
6c2b7c12 2536 struct intel_encoder *encoder;
e3421a18 2537
6c2b7c12
DV		 2538 for_each_encoder_on_crtc(dev, crtc, encoder) {
2539 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
e3421a18 2540
417e822d
KP		 2541 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2542 intel_dp->base.type == INTEL_OUTPUT_EDP)
ea5b213a 2543 return intel_dp->output_reg;
e3421a18 2544 }
ea5b213a 2545
e3421a18
ZW		 2546 return -1;
2547}
2548
36e83a18 2549/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2550bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2551{
2552 struct drm_i915_private *dev_priv = dev->dev_private;
2553 struct child_device_config *p_child;
2554 int i;
2555
2556 if (!dev_priv->child_dev_num)
2557 return false;
2558
2559 for (i = 0; i < dev_priv->child_dev_num; i++) {
2560 p_child = dev_priv->child_dev + i;
2561
2562 if (p_child->dvo_port == PORT_IDPD &&
2563 p_child->device_type == DEVICE_TYPE_eDP)
2564 return true;
2565 }
2566 return false;
2567}
2568
f684960e
CW		 2569static void
2570intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2571{
3f43c48d 2572 intel_attach_force_audio_property(connector);
e953fd7b 2573 intel_attach_broadcast_rgb_property(connector);
f684960e
CW		 2574}
2575
a4fc5ed6 2576void
ab9d7c30 2577intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
a4fc5ed6
KP		 2578{
2579 struct drm_i915_private *dev_priv = dev->dev_private;
2580 struct drm_connector *connector;
ea5b213a 2581 struct intel_dp *intel_dp;
21d40d37 2582 struct intel_encoder *intel_encoder;
55f78c43 2583 struct intel_connector *intel_connector;
5eb08b69 2584 const char *name = NULL;
b329530c 2585 int type;
a4fc5ed6 2586
ea5b213a
CW		 2587 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2588 if (!intel_dp)
a4fc5ed6
KP		 2589 return;
2590
3d3dc149 2591 intel_dp->output_reg = output_reg;
ab9d7c30 2592 intel_dp->port = port;
0767935e
DV		 2593 /* Preserve the current hw state. */
2594 intel_dp->DP = I915_READ(intel_dp->output_reg);
3d3dc149 2595
55f78c43
ZW		 2596 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2597 if (!intel_connector) {
ea5b213a 2598 kfree(intel_dp);
55f78c43
ZW		 2599 return;
2600 }
ea5b213a 2601 intel_encoder = &intel_dp->base;
55f78c43 2602
ea5b213a 2603 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
b329530c 2604 if (intel_dpd_is_edp(dev))
ea5b213a 2605 intel_dp->is_pch_edp = true;
b329530c 2606
19c03924
GB		 2607 /*
2608 * FIXME : We need to initialize built-in panels before external panels.
2609 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2610 */
2611 if (IS_VALLEYVIEW(dev) && output_reg == DP_C) {
2612 type = DRM_MODE_CONNECTOR_eDP;
2613 intel_encoder->type = INTEL_OUTPUT_EDP;
2614 } else if (output_reg == DP_A || is_pch_edp(intel_dp)) {
b329530c
AJ		 2615 type = DRM_MODE_CONNECTOR_eDP;
2616 intel_encoder->type = INTEL_OUTPUT_EDP;
2617 } else {
2618 type = DRM_MODE_CONNECTOR_DisplayPort;
2619 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2620 }
2621
55f78c43 2622 connector = &intel_connector->base;
b329530c 2623 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 2624 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2625
eb1f8e4f
DA		 2626 connector->polled = DRM_CONNECTOR_POLL_HPD;
2627
66a9278e 2628 intel_encoder->cloneable = false;
f8aed700 2629
66a9278e
DV		 2630 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2631 ironlake_panel_vdd_work);
6251ec0a 2632
27f8227b 2633 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
ee7b9f93 2634
a4fc5ed6
KP		 2635 connector->interlace_allowed = true;
2636 connector->doublescan_allowed = 0;
2637
4ef69c7a 2638 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
a4fc5ed6 2639 DRM_MODE_ENCODER_TMDS);
4ef69c7a 2640 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
a4fc5ed6 2641
df0e9248 2642 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 2643 drm_sysfs_connector_add(connector);
2644
e8cb4558 2645 intel_encoder->enable = intel_enable_dp;
2bd2ad64 2646 intel_encoder->pre_enable = intel_pre_enable_dp;
e8cb4558 2647 intel_encoder->disable = intel_disable_dp;
2bd2ad64 2648 intel_encoder->post_disable = intel_post_disable_dp;
19d8fe15
DV		 2649 intel_encoder->get_hw_state = intel_dp_get_hw_state;
2650 intel_connector->get_hw_state = intel_connector_get_hw_state;
e8cb4558 2651
a4fc5ed6 2652 /* Set up the DDC bus. */
ab9d7c30
PZ		 2653 switch (port) {
2654 case PORT_A:
2655 name = "DPDDC-A";
2656 break;
2657 case PORT_B:
2658 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2659 name = "DPDDC-B";
2660 break;
2661 case PORT_C:
2662 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2663 name = "DPDDC-C";
2664 break;
2665 case PORT_D:
2666 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2667 name = "DPDDC-D";
2668 break;
2669 default:
2670 WARN(1, "Invalid port %c\n", port_name(port));
2671 break;
5eb08b69
ZW		 2672 }
2673
89667383
JB		 2674 /* Cache some DPCD data in the eDP case */
2675 if (is_edp(intel_dp)) {
f01eca2e
KP		 2676 struct edp_power_seq cur, vbt;
2677 u32 pp_on, pp_off, pp_div;
5d613501
JB		 2678
2679 pp_on = I915_READ(PCH_PP_ON_DELAYS);
f01eca2e 2680 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
5d613501 2681 pp_div = I915_READ(PCH_PP_DIVISOR);
89667383 2682
bfa3384a
JB		 2683 if (!pp_on || !pp_off || !pp_div) {
2684 DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2685 intel_dp_encoder_destroy(&intel_dp->base.base);
2686 intel_dp_destroy(&intel_connector->base);
2687 return;
2688 }
2689
f01eca2e
KP		 2690 /* Pull timing values out of registers */
2691 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2692 PANEL_POWER_UP_DELAY_SHIFT;
2693
2694 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2695 PANEL_LIGHT_ON_DELAY_SHIFT;
f2e8b18a 2696
f01eca2e
KP		 2697 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2698 PANEL_LIGHT_OFF_DELAY_SHIFT;
2699
2700 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2701 PANEL_POWER_DOWN_DELAY_SHIFT;
2702
2703 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2704 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2705
2706 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2707 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2708
2709 vbt = dev_priv->edp.pps;
2710
2711 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2712 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2713
2714#define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2715
2716 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2717 intel_dp->backlight_on_delay = get_delay(t8);
2718 intel_dp->backlight_off_delay = get_delay(t9);
2719 intel_dp->panel_power_down_delay = get_delay(t10);
2720 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2721
2722 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2723 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2724 intel_dp->panel_power_cycle_delay);
2725
2726 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2727 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
c1f05264
DA		 2728 }
2729
2730 intel_dp_i2c_init(intel_dp, intel_connector, name);
2731
2732 if (is_edp(intel_dp)) {
2733 bool ret;
2734 struct edid *edid;
5d613501
JB		 2735
2736 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 2737 ret = intel_dp_get_dpcd(intel_dp);
bd943159 2738 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 2739
59f3e272 2740 if (ret) {
7183dc29
JB		 2741 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2742 dev_priv->no_aux_handshake =
2743 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 2744 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2745 } else {
3d3dc149 2746 /* if this fails, presume the device is a ghost */
48898b03 2747 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3d3dc149 2748 intel_dp_encoder_destroy(&intel_dp->base.base);
48898b03 2749 intel_dp_destroy(&intel_connector->base);
3d3dc149 2750 return;
89667383 2751 }
89667383 2752
d6f24d0f
JB		 2753 ironlake_edp_panel_vdd_on(intel_dp);
2754 edid = drm_get_edid(connector, &intel_dp->adapter);
2755 if (edid) {
2756 drm_mode_connector_update_edid_property(connector,
2757 edid);
2758 intel_dp->edid_mode_count =
2759 drm_add_edid_modes(connector, edid);
2760 drm_edid_to_eld(connector, edid);
2761 intel_dp->edid = edid;
2762 }
2763 ironlake_edp_panel_vdd_off(intel_dp, false);
2764 }
552fb0b7 2765
21d40d37 2766 intel_encoder->hot_plug = intel_dp_hot_plug;
a4fc5ed6 2767
4d926461 2768 if (is_edp(intel_dp)) {
aaa6fd2a
MG		 2769 dev_priv->int_edp_connector = connector;
2770 intel_panel_setup_backlight(dev);
32f9d658
ZW		 2771 }
2772
f684960e
CW		 2773 intel_dp_add_properties(intel_dp, connector);
2774
a4fc5ed6
KP		 2775 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2776 * 0xd. Failure to do so will result in spurious interrupts being
2777 * generated on the port when a cable is not attached.
2778 */
2779 if (IS_G4X(dev) && !IS_GM45(dev)) {
2780 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2781 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2782 }
2783}
Linux kernel - Deliverables
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