[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp_link_training.c

/*
 * Copyright © 2008-2015 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 */

#include "intel_drv.h"

static void
intel_get_adjust_train(struct intel_dp *intel_dp,
		       const uint8_t link_status[DP_LINK_STATUS_SIZE])
{
	uint8_t v = 0;
	uint8_t p = 0;
	int lane;
	uint8_t voltage_max;
	uint8_t preemph_max;

	for (lane = 0; lane < intel_dp->lane_count; lane++) {
		uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
		uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);

		if (this_v > v)
			v = this_v;
		if (this_p > p)
			p = this_p;
	}

	voltage_max = intel_dp_voltage_max(intel_dp);
	if (v >= voltage_max)
		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;

	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
	if (p >= preemph_max)
		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;

	for (lane = 0; lane < 4; lane++)
		intel_dp->train_set[lane] = v | p;
}

static bool
intel_dp_set_link_train(struct intel_dp *intel_dp,
			uint8_t dp_train_pat)
{
	uint8_t buf[sizeof(intel_dp->train_set) + 1];
	int ret, len;

	intel_dp_program_link_training_pattern(intel_dp, dp_train_pat);

	buf[0] = dp_train_pat;
	if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
	    DP_TRAINING_PATTERN_DISABLE) {
		/* don't write DP_TRAINING_LANEx_SET on disable */
		len = 1;
	} else {
		/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
		memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
		len = intel_dp->lane_count + 1;
	}

	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
				buf, len);

	return ret == len;
}

static bool
intel_dp_reset_link_train(struct intel_dp *intel_dp,
			uint8_t dp_train_pat)
{
	if (!intel_dp->train_set_valid)
		memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
	intel_dp_set_signal_levels(intel_dp);
	return intel_dp_set_link_train(intel_dp, dp_train_pat);
}

static bool
intel_dp_update_link_train(struct intel_dp *intel_dp)
{
	int ret;

	intel_dp_set_signal_levels(intel_dp);

	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
				intel_dp->train_set, intel_dp->lane_count);

	return ret == intel_dp->lane_count;
}

/* Enable corresponding port and start training pattern 1 */
static void
intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
{
	struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
	struct drm_device *dev = encoder->dev;
	int i;
	uint8_t voltage;
	int voltage_tries, loop_tries;
	uint8_t link_config[2];
	uint8_t link_bw, rate_select;

	if (HAS_DDI(dev))
		intel_ddi_prepare_link_retrain(encoder);

	intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
			      &link_bw, &rate_select);

	/* Write the link configuration data */
	link_config[0] = link_bw;
	link_config[1] = intel_dp->lane_count;
	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
	if (intel_dp->num_sink_rates)
		drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
				  &rate_select, 1);

	link_config[0] = 0;
	link_config[1] = DP_SET_ANSI_8B10B;
	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);

	intel_dp->DP |= DP_PORT_EN;

	/* clock recovery */
	if (!intel_dp_reset_link_train(intel_dp,
				       DP_TRAINING_PATTERN_1 |
				       DP_LINK_SCRAMBLING_DISABLE)) {
		DRM_ERROR("failed to enable link training\n");
		return;
	}

	voltage = 0xff;
	voltage_tries = 0;
	loop_tries = 0;
	for (;;) {
		uint8_t link_status[DP_LINK_STATUS_SIZE];

		drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
		if (!intel_dp_get_link_status(intel_dp, link_status)) {
			DRM_ERROR("failed to get link status\n");
			break;
		}

		if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
			DRM_DEBUG_KMS("clock recovery OK\n");
			break;
		}

		/*
		 * if we used previously trained voltage and pre-emphasis values
		 * and we don't get clock recovery, reset link training values
		 */
		if (intel_dp->train_set_valid) {
			DRM_DEBUG_KMS("clock recovery not ok, reset");
			/* clear the flag as we are not reusing train set */
			intel_dp->train_set_valid = false;
			if (!intel_dp_reset_link_train(intel_dp,
						       DP_TRAINING_PATTERN_1 |
						       DP_LINK_SCRAMBLING_DISABLE)) {
				DRM_ERROR("failed to enable link training\n");
				return;
			}
			continue;
		}

		/* Check to see if we've tried the max voltage */
		for (i = 0; i < intel_dp->lane_count; i++)
			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
				break;
		if (i == intel_dp->lane_count) {
			++loop_tries;
			if (loop_tries == 5) {
				DRM_ERROR("too many full retries, give up\n");
				break;
			}
			intel_dp_reset_link_train(intel_dp,
						  DP_TRAINING_PATTERN_1 |
						  DP_LINK_SCRAMBLING_DISABLE);
			voltage_tries = 0;
			continue;
		}

		/* Check to see if we've tried the same voltage 5 times */
		if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
			++voltage_tries;
			if (voltage_tries == 5) {
				DRM_ERROR("too many voltage retries, give up\n");
				break;
			}
		} else
			voltage_tries = 0;
		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;

		/* Update training set as requested by target */
		intel_get_adjust_train(intel_dp, link_status);
		if (!intel_dp_update_link_train(intel_dp)) {
			DRM_ERROR("failed to update link training\n");
			break;
		}
	}
}

static void
intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	bool channel_eq = false;
	int tries, cr_tries;
	uint32_t training_pattern = DP_TRAINING_PATTERN_2;

	/*
	 * Training Pattern 3 for HBR2 or 1.2 devices that support it.
	 *
	 * Intel platforms that support HBR2 also support TPS3. TPS3 support is
	 * also mandatory for downstream devices that support HBR2.
	 *
	 * Due to WaDisableHBR2 SKL < B0 is the only exception where TPS3 is
	 * supported but still not enabled.
	 */
	if (intel_dp_source_supports_hbr2(dev) &&
	    drm_dp_tps3_supported(intel_dp->dpcd))
		training_pattern = DP_TRAINING_PATTERN_3;
	else if (intel_dp->link_rate == 540000)
		DRM_ERROR("5.4 Gbps link rate without HBR2/TPS3 support\n");

	/* channel equalization */
	if (!intel_dp_set_link_train(intel_dp,
				     training_pattern |
				     DP_LINK_SCRAMBLING_DISABLE)) {
		DRM_ERROR("failed to start channel equalization\n");
		return;
	}

	tries = 0;
	cr_tries = 0;
	channel_eq = false;
	for (;;) {
		uint8_t link_status[DP_LINK_STATUS_SIZE];

		if (cr_tries > 5) {
			DRM_ERROR("failed to train DP, aborting\n");
			break;
		}

		drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
		if (!intel_dp_get_link_status(intel_dp, link_status)) {
			DRM_ERROR("failed to get link status\n");
			break;
		}

		/* Make sure clock is still ok */
		if (!drm_dp_clock_recovery_ok(link_status,
					      intel_dp->lane_count)) {
			intel_dp->train_set_valid = false;
			intel_dp_link_training_clock_recovery(intel_dp);
			intel_dp_set_link_train(intel_dp,
						training_pattern |
						DP_LINK_SCRAMBLING_DISABLE);
			cr_tries++;
			continue;
		}

		if (drm_dp_channel_eq_ok(link_status,
					 intel_dp->lane_count)) {
			channel_eq = true;
			break;
		}

		/* Try 5 times, then try clock recovery if that fails */
		if (tries > 5) {
			intel_dp->train_set_valid = false;
			intel_dp_link_training_clock_recovery(intel_dp);
			intel_dp_set_link_train(intel_dp,
						training_pattern |
						DP_LINK_SCRAMBLING_DISABLE);
			tries = 0;
			cr_tries++;
			continue;
		}

		/* Update training set as requested by target */
		intel_get_adjust_train(intel_dp, link_status);
		if (!intel_dp_update_link_train(intel_dp)) {
			DRM_ERROR("failed to update link training\n");
			break;
		}
		++tries;
	}

	intel_dp_set_idle_link_train(intel_dp);

	if (channel_eq) {
		intel_dp->train_set_valid = true;
		DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
	}
}

void intel_dp_stop_link_train(struct intel_dp *intel_dp)
{
	intel_dp_set_link_train(intel_dp,
				DP_TRAINING_PATTERN_DISABLE);
}

void
intel_dp_start_link_train(struct intel_dp *intel_dp)
{
	intel_dp_link_training_clock_recovery(intel_dp);
	intel_dp_link_training_channel_equalization(intel_dp);
}
Commit	Line	Data
94223d04 ACO	1	/*
	2	* Copyright © 2008-2015 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*/
	23
	24	#include "intel_drv.h"
	25
	26	static void
	27	intel_get_adjust_train(struct intel_dp *intel_dp,
	28	const uint8_t link_status[DP_LINK_STATUS_SIZE])
	29	{
	30	uint8_t v = 0;
	31	uint8_t p = 0;
	32	int lane;
	33	uint8_t voltage_max;
	34	uint8_t preemph_max;
	35
	36	for (lane = 0; lane < intel_dp->lane_count; lane++) {
	37	uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
	38	uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
	39
	40	if (this_v > v)
	41	v = this_v;
	42	if (this_p > p)
	43	p = this_p;
	44	}
	45
	46	voltage_max = intel_dp_voltage_max(intel_dp);
	47	if (v >= voltage_max)
	48	v = voltage_max \| DP_TRAIN_MAX_SWING_REACHED;
	49
	50	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
	51	if (p >= preemph_max)
	52	p = preemph_max \| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
	53
	54	for (lane = 0; lane < 4; lane++)
	55	intel_dp->train_set[lane] = v \| p;
	56	}
	57
	58	static bool
	59	intel_dp_set_link_train(struct intel_dp *intel_dp,
	60	uint8_t dp_train_pat)
	61	{
	62	uint8_t buf[sizeof(intel_dp->train_set) + 1];
	63	int ret, len;
	64
65	intel_dp_program_link_training_pattern(intel_dp, dp_train_pat);
66
67	buf[0] = dp_train_pat;
68	if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
69	DP_TRAINING_PATTERN_DISABLE) {
70	/* don't write DP_TRAINING_LANEx_SET on disable */
71	len = 1;
72	} else {
73	/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
74	memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
75	len = intel_dp->lane_count + 1;
76	}
77
78	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
79	buf, len);
80
81	return ret == len;
82	}
83
84	static bool
85	intel_dp_reset_link_train(struct intel_dp *intel_dp,
86	uint8_t dp_train_pat)
87	{
88	if (!intel_dp->train_set_valid)
89	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
90	intel_dp_set_signal_levels(intel_dp);
91	return intel_dp_set_link_train(intel_dp, dp_train_pat);
92	}
93
94	static bool
95	intel_dp_update_link_train(struct intel_dp *intel_dp)
96	{
97	int ret;
98
99	intel_dp_set_signal_levels(intel_dp);
100
101	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
102	intel_dp->train_set, intel_dp->lane_count);
103
104	return ret == intel_dp->lane_count;
105	}
106
107	/* Enable corresponding port and start training pattern 1 */
108	static void
109	intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
110	{
111	struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
112	struct drm_device *dev = encoder->dev;
113	int i;
114	uint8_t voltage;
115	int voltage_tries, loop_tries;
116	uint8_t link_config[2];
117	uint8_t link_bw, rate_select;
118
119	if (HAS_DDI(dev))
120	intel_ddi_prepare_link_retrain(encoder);
121
122	intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
123	&link_bw, &rate_select);
124
125	/* Write the link configuration data */
126	link_config[0] = link_bw;
127	link_config[1] = intel_dp->lane_count;
128	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
129	link_config[1] \|= DP_LANE_COUNT_ENHANCED_FRAME_EN;
130	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
131	if (intel_dp->num_sink_rates)
132	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
133	&rate_select, 1);
134
135	link_config[0] = 0;
136	link_config[1] = DP_SET_ANSI_8B10B;
137	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
138
139	intel_dp->DP \|= DP_PORT_EN;
140
141	/* clock recovery */
142	if (!intel_dp_reset_link_train(intel_dp,
143	DP_TRAINING_PATTERN_1 \|
144	DP_LINK_SCRAMBLING_DISABLE)) {
145	DRM_ERROR("failed to enable link training\n");
146	return;
147	}
148
149	voltage = 0xff;
150	voltage_tries = 0;
151	loop_tries = 0;
152	for (;;) {
153	uint8_t link_status[DP_LINK_STATUS_SIZE];
154
155	drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
156	if (!intel_dp_get_link_status(intel_dp, link_status)) {
157	DRM_ERROR("failed to get link status\n");
158	break;
159	}
160
161	if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
162	DRM_DEBUG_KMS("clock recovery OK\n");
163	break;
164	}
165
166	/*
167	* if we used previously trained voltage and pre-emphasis values
168	* and we don't get clock recovery, reset link training values
169	*/
170	if (intel_dp->train_set_valid) {
171	DRM_DEBUG_KMS("clock recovery not ok, reset");
172	/* clear the flag as we are not reusing train set */
173	intel_dp->train_set_valid = false;
174	if (!intel_dp_reset_link_train(intel_dp,
175	DP_TRAINING_PATTERN_1 \|
176	DP_LINK_SCRAMBLING_DISABLE)) {
177	DRM_ERROR("failed to enable link training\n");
178	return;
179	}
180	continue;
181	}
182
183	/* Check to see if we've tried the max voltage */
184	for (i = 0; i < intel_dp->lane_count; i++)
185	if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
186	break;
187	if (i == intel_dp->lane_count) {
188	++loop_tries;
189	if (loop_tries == 5) {
190	DRM_ERROR("too many full retries, give up\n");
191	break;
192	}
193	intel_dp_reset_link_train(intel_dp,
194	DP_TRAINING_PATTERN_1 \|
195	DP_LINK_SCRAMBLING_DISABLE);
196	voltage_tries = 0;
197	continue;
198	}
199
200	/* Check to see if we've tried the same voltage 5 times */
201	if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
202	++voltage_tries;
203	if (voltage_tries == 5) {
204	DRM_ERROR("too many voltage retries, give up\n");
205	break;
206	}
207	} else
208	voltage_tries = 0;
209	voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
210
211	/* Update training set as requested by target */
212	intel_get_adjust_train(intel_dp, link_status);
213	if (!intel_dp_update_link_train(intel_dp)) {
214	DRM_ERROR("failed to update link training\n");
215	break;
216	}
217	}
218	}
219
220	static void
221	intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
222	{
223	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
224	struct drm_device *dev = dig_port->base.base.dev;
225	bool channel_eq = false;
226	int tries, cr_tries;
227	uint32_t training_pattern = DP_TRAINING_PATTERN_2;
228
229	/*
230	* Training Pattern 3 for HBR2 or 1.2 devices that support it.
231	*
232	* Intel platforms that support HBR2 also support TPS3. TPS3 support is
233	* also mandatory for downstream devices that support HBR2.
234	*
235	* Due to WaDisableHBR2 SKL < B0 is the only exception where TPS3 is
236	* supported but still not enabled.
237	*/
238	if (intel_dp_source_supports_hbr2(dev) &&
239	drm_dp_tps3_supported(intel_dp->dpcd))
240	training_pattern = DP_TRAINING_PATTERN_3;
241	else if (intel_dp->link_rate == 540000)
242	DRM_ERROR("5.4 Gbps link rate without HBR2/TPS3 support\n");
243
244	/* channel equalization */
245	if (!intel_dp_set_link_train(intel_dp,
246	training_pattern \|
247	DP_LINK_SCRAMBLING_DISABLE)) {
248	DRM_ERROR("failed to start channel equalization\n");
249	return;
250	}
251
252	tries = 0;
253	cr_tries = 0;
254	channel_eq = false;
255	for (;;) {
256	uint8_t link_status[DP_LINK_STATUS_SIZE];
257
258	if (cr_tries > 5) {
259	DRM_ERROR("failed to train DP, aborting\n");
260	break;
261	}
262
263	drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
264	if (!intel_dp_get_link_status(intel_dp, link_status)) {
265	DRM_ERROR("failed to get link status\n");
266	break;
267	}
268
269	/* Make sure clock is still ok */
270	if (!drm_dp_clock_recovery_ok(link_status,
271	intel_dp->lane_count)) {
272	intel_dp->train_set_valid = false;
273	intel_dp_link_training_clock_recovery(intel_dp);
274	intel_dp_set_link_train(intel_dp,
275	training_pattern \|
276	DP_LINK_SCRAMBLING_DISABLE);
277	cr_tries++;
278	continue;
279	}
280
281	if (drm_dp_channel_eq_ok(link_status,
282	intel_dp->lane_count)) {
283	channel_eq = true;
284	break;
285	}
286
287	/* Try 5 times, then try clock recovery if that fails */
288	if (tries > 5) {
289	intel_dp->train_set_valid = false;
290	intel_dp_link_training_clock_recovery(intel_dp);
291	intel_dp_set_link_train(intel_dp,
292	training_pattern \|
293	DP_LINK_SCRAMBLING_DISABLE);
294	tries = 0;
295	cr_tries++;
296	continue;
297	}
298
299	/* Update training set as requested by target */
300	intel_get_adjust_train(intel_dp, link_status);
301	if (!intel_dp_update_link_train(intel_dp)) {
302	DRM_ERROR("failed to update link training\n");
303	break;
304	}
305	++tries;
306	}
307
308	intel_dp_set_idle_link_train(intel_dp);
309
310	if (channel_eq) {
311	intel_dp->train_set_valid = true;
312	DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
313	}
314	}
315
316	void intel_dp_stop_link_train(struct intel_dp *intel_dp)
317	{
318	intel_dp_set_link_train(intel_dp,
319	DP_TRAINING_PATTERN_DISABLE);
320	}
321
322	void
323	intel_dp_start_link_train(struct intel_dp *intel_dp)
324	{
325	intel_dp_link_training_clock_recovery(intel_dp);
326	intel_dp_link_training_channel_equalization(intel_dp);
327	}