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drm/i915: Move pll power state to crtc power domains.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dpll_mgr.c
CommitLineData
7abd4b35
ACO		 1/*
2 * Copyright © 2006-2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include "intel_drv.h"
25
26struct intel_shared_dpll *
8106ddbd
ACO		 27intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
28 enum intel_dpll_id id)
7abd4b35 29{
8106ddbd
ACO		 30 return &dev_priv->shared_dplls[id];
31}
7abd4b35 32
8106ddbd
ACO		 33enum intel_dpll_id
34intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
35 struct intel_shared_dpll *pll)
36{
37 if (WARN_ON(pll < dev_priv->shared_dplls||
38 pll > &dev_priv->shared_dplls[dev_priv->num_shared_dpll]))
39 return -1;
40
41 return (enum intel_dpll_id) (pll - dev_priv->shared_dplls);
42}
43
44void
45intel_shared_dpll_config_get(struct intel_shared_dpll_config *config,
46 struct intel_shared_dpll *pll,
47 struct intel_crtc *crtc)
48{
49 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
50 enum intel_dpll_id id = intel_get_shared_dpll_id(dev_priv, pll);
51
52 config[id].crtc_mask |= 1 << crtc->pipe;
53}
54
55void
56intel_shared_dpll_config_put(struct intel_shared_dpll_config *config,
57 struct intel_shared_dpll *pll,
58 struct intel_crtc *crtc)
59{
60 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
61 enum intel_dpll_id id = intel_get_shared_dpll_id(dev_priv, pll);
7abd4b35 62
8106ddbd 63 config[id].crtc_mask &= ~(1 << crtc->pipe);
7abd4b35
ACO		 64}
65
66/* For ILK+ */
67void assert_shared_dpll(struct drm_i915_private *dev_priv,
68 struct intel_shared_dpll *pll,
69 bool state)
70{
71 bool cur_state;
72 struct intel_dpll_hw_state hw_state;
73
74 if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state)))
75 return;
76
2edd6443 77 cur_state = pll->funcs.get_hw_state(dev_priv, pll, &hw_state);
7abd4b35
ACO		 78 I915_STATE_WARN(cur_state != state,
79 "%s assertion failure (expected %s, current %s)\n",
80 pll->name, onoff(state), onoff(cur_state));
81}
82
83void intel_prepare_shared_dpll(struct intel_crtc *crtc)
84{
85 struct drm_device *dev = crtc->base.dev;
86 struct drm_i915_private *dev_priv = dev->dev_private;
8106ddbd 87 struct intel_shared_dpll *pll = crtc->config->shared_dpll;
7abd4b35
ACO		 88
89 if (WARN_ON(pll == NULL))
90 return;
91
92 WARN_ON(!pll->config.crtc_mask);
2dd66ebd 93 if (pll->active_mask == 0) {
7abd4b35
ACO		 94 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
95 WARN_ON(pll->on);
96 assert_shared_dpll_disabled(dev_priv, pll);
97
2edd6443 98 pll->funcs.mode_set(dev_priv, pll);
7abd4b35
ACO		 99 }
100}
101
102/**
103 * intel_enable_shared_dpll - enable PCH PLL
104 * @dev_priv: i915 private structure
105 * @pipe: pipe PLL to enable
106 *
107 * The PCH PLL needs to be enabled before the PCH transcoder, since it
108 * drives the transcoder clock.
109 */
110void intel_enable_shared_dpll(struct intel_crtc *crtc)
111{
112 struct drm_device *dev = crtc->base.dev;
113 struct drm_i915_private *dev_priv = dev->dev_private;
8106ddbd 114 struct intel_shared_dpll *pll = crtc->config->shared_dpll;
2dd66ebd
ML		 115 unsigned crtc_mask = 1 << drm_crtc_index(&crtc->base);
116 unsigned old_mask = pll->active_mask;
7abd4b35
ACO		 117
118 if (WARN_ON(pll == NULL))
119 return;
120
2dd66ebd
ML		 121 if (WARN_ON(!(pll->config.crtc_mask & crtc_mask)) ||
122 WARN_ON(pll->active_mask & crtc_mask))
7abd4b35
ACO		 123 return;
124
2dd66ebd
ML		 125 pll->active_mask |= crtc_mask;
126
127 DRM_DEBUG_KMS("enable %s (active %x, on? %d) for crtc %d\n",
128 pll->name, pll->active_mask, pll->on,
7abd4b35
ACO		 129 crtc->base.base.id);
130
2dd66ebd 131 if (old_mask) {
7abd4b35
ACO		 132 WARN_ON(!pll->on);
133 assert_shared_dpll_enabled(dev_priv, pll);
134 return;
135 }
136 WARN_ON(pll->on);
137
7abd4b35 138 DRM_DEBUG_KMS("enabling %s\n", pll->name);
2edd6443 139 pll->funcs.enable(dev_priv, pll);
7abd4b35
ACO		 140 pll->on = true;
141}
142
143void intel_disable_shared_dpll(struct intel_crtc *crtc)
144{
145 struct drm_device *dev = crtc->base.dev;
146 struct drm_i915_private *dev_priv = dev->dev_private;
8106ddbd 147 struct intel_shared_dpll *pll = crtc->config->shared_dpll;
2dd66ebd 148 unsigned crtc_mask = 1 << drm_crtc_index(&crtc->base);
7abd4b35
ACO		 149
150 /* PCH only available on ILK+ */
151 if (INTEL_INFO(dev)->gen < 5)
152 return;
153
154 if (pll == NULL)
155 return;
156
a1475e77 157 if (WARN_ON(!(pll->active_mask & crtc_mask)))
7abd4b35
ACO		 158 return;
159
2dd66ebd
ML		 160 DRM_DEBUG_KMS("disable %s (active %x, on? %d) for crtc %d\n",
161 pll->name, pll->active_mask, pll->on,
7abd4b35
ACO		 162 crtc->base.base.id);
163
7abd4b35
ACO		 164 assert_shared_dpll_enabled(dev_priv, pll);
165 WARN_ON(!pll->on);
2dd66ebd
ML		 166
167 pll->active_mask &= ~crtc_mask;
168 if (pll->active_mask)
7abd4b35
ACO		 169 return;
170
171 DRM_DEBUG_KMS("disabling %s\n", pll->name);
2edd6443 172 pll->funcs.disable(dev_priv, pll);
7abd4b35 173 pll->on = false;
7abd4b35
ACO		 174}
175
f9476a6c 176static struct intel_shared_dpll *
a4780b77 177intel_find_shared_dpll(struct intel_crtc *crtc,
f9476a6c
ACO		 178 struct intel_crtc_state *crtc_state,
179 enum intel_dpll_id range_min,
180 enum intel_dpll_id range_max)
a4780b77
ACO		 181{
182 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
183 struct intel_shared_dpll *pll;
184 struct intel_shared_dpll_config *shared_dpll;
185 enum intel_dpll_id i;
7abd4b35 186
a4780b77
ACO		 187 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
188
f9476a6c 189 for (i = range_min; i <= range_max; i++) {
7abd4b35
ACO		 190 pll = &dev_priv->shared_dplls[i];
191
192 /* Only want to check enabled timings first */
193 if (shared_dpll[i].crtc_mask == 0)
194 continue;
195
196 if (memcmp(&crtc_state->dpll_hw_state,
197 &shared_dpll[i].hw_state,
198 sizeof(crtc_state->dpll_hw_state)) == 0) {
2dd66ebd 199 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, active %x)\n",
7abd4b35
ACO		 200 crtc->base.base.id, pll->name,
201 shared_dpll[i].crtc_mask,
2dd66ebd 202 pll->active_mask);
f9476a6c 203 return pll;
7abd4b35
ACO		 204 }
205 }
206
207 /* Ok no matching timings, maybe there's a free one? */
f9476a6c 208 for (i = range_min; i <= range_max; i++) {
7abd4b35
ACO		 209 pll = &dev_priv->shared_dplls[i];
210 if (shared_dpll[i].crtc_mask == 0) {
211 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
212 crtc->base.base.id, pll->name);
f9476a6c 213 return pll;
7abd4b35
ACO		 214 }
215 }
216
f9476a6c 217 return NULL;
a4780b77
ACO		 218}
219
f9476a6c
ACO		 220static void
221intel_reference_shared_dpll(struct intel_shared_dpll *pll,
222 struct intel_crtc_state *crtc_state)
a4780b77 223{
a4780b77 224 struct intel_shared_dpll_config *shared_dpll;
f9476a6c
ACO		 225 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
226 enum intel_dpll_id i = pll->id;
a4780b77
ACO		 227
228 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
229
7abd4b35
ACO		 230 if (shared_dpll[i].crtc_mask == 0)
231 shared_dpll[i].hw_state =
232 crtc_state->dpll_hw_state;
233
8106ddbd 234 crtc_state->shared_dpll = pll;
7abd4b35
ACO		 235 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
236 pipe_name(crtc->pipe));
237
8106ddbd 238 intel_shared_dpll_config_get(shared_dpll, pll, crtc);
7abd4b35
ACO		 239}
240
241void intel_shared_dpll_commit(struct drm_atomic_state *state)
242{
243 struct drm_i915_private *dev_priv = to_i915(state->dev);
244 struct intel_shared_dpll_config *shared_dpll;
245 struct intel_shared_dpll *pll;
246 enum intel_dpll_id i;
247
248 if (!to_intel_atomic_state(state)->dpll_set)
249 return;
250
251 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
252 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
253 pll = &dev_priv->shared_dplls[i];
254 pll->config = shared_dpll[i];
255 }
256}
257
258static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
259 struct intel_shared_dpll *pll,
260 struct intel_dpll_hw_state *hw_state)
261{
262 uint32_t val;
263
264 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
265 return false;
266
267 val = I915_READ(PCH_DPLL(pll->id));
268 hw_state->dpll = val;
269 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
270 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
271
272 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
273
274 return val & DPLL_VCO_ENABLE;
275}
276
277static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
278 struct intel_shared_dpll *pll)
279{
280 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
281 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
282}
283
284static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
285{
286 u32 val;
287 bool enabled;
288
289 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
290
291 val = I915_READ(PCH_DREF_CONTROL);
292 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
293 DREF_SUPERSPREAD_SOURCE_MASK));
294 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
295}
296
297static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
298 struct intel_shared_dpll *pll)
299{
300 /* PCH refclock must be enabled first */
301 ibx_assert_pch_refclk_enabled(dev_priv);
302
303 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
304
305 /* Wait for the clocks to stabilize. */
306 POSTING_READ(PCH_DPLL(pll->id));
307 udelay(150);
308
309 /* The pixel multiplier can only be updated once the
310 * DPLL is enabled and the clocks are stable.
311 *
312 * So write it again.
313 */
314 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
315 POSTING_READ(PCH_DPLL(pll->id));
316 udelay(200);
317}
318
319static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
320 struct intel_shared_dpll *pll)
321{
322 struct drm_device *dev = dev_priv->dev;
323 struct intel_crtc *crtc;
324
325 /* Make sure no transcoder isn't still depending on us. */
326 for_each_intel_crtc(dev, crtc) {
8106ddbd 327 if (crtc->config->shared_dpll == pll)
7abd4b35
ACO		 328 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
329 }
330
331 I915_WRITE(PCH_DPLL(pll->id), 0);
332 POSTING_READ(PCH_DPLL(pll->id));
333 udelay(200);
334}
335
f9476a6c 336static struct intel_shared_dpll *
daedf20a
ACO		 337ibx_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
338 struct intel_encoder *encoder)
f9476a6c
ACO		 339{
340 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
341 struct intel_shared_dpll *pll;
342 enum intel_dpll_id i;
343
344 if (HAS_PCH_IBX(dev_priv)) {
345 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
346 i = (enum intel_dpll_id) crtc->pipe;
347 pll = &dev_priv->shared_dplls[i];
348
349 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
350 crtc->base.base.id, pll->name);
351 } else {
352 pll = intel_find_shared_dpll(crtc, crtc_state,
353 DPLL_ID_PCH_PLL_A,
354 DPLL_ID_PCH_PLL_B);
355 }
356
357 /* reference the pll */
358 intel_reference_shared_dpll(pll, crtc_state);
359
360 return pll;
361}
362
2edd6443
ACO		 363static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = {
364 .mode_set = ibx_pch_dpll_mode_set,
365 .enable = ibx_pch_dpll_enable,
366 .disable = ibx_pch_dpll_disable,
367 .get_hw_state = ibx_pch_dpll_get_hw_state,
7abd4b35
ACO		 368};
369
55be2f08
ACO		 370static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
371 struct intel_shared_dpll *pll)
372{
373 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
374 POSTING_READ(WRPLL_CTL(pll->id));
375 udelay(20);
376}
377
378static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv,
379 struct intel_shared_dpll *pll)
380{
381 I915_WRITE(SPLL_CTL, pll->config.hw_state.spll);
382 POSTING_READ(SPLL_CTL);
383 udelay(20);
384}
385
386static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
387 struct intel_shared_dpll *pll)
388{
389 uint32_t val;
390
391 val = I915_READ(WRPLL_CTL(pll->id));
392 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
393 POSTING_READ(WRPLL_CTL(pll->id));
394}
395
396static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
397 struct intel_shared_dpll *pll)
398{
399 uint32_t val;
400
401 val = I915_READ(SPLL_CTL);
402 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
403 POSTING_READ(SPLL_CTL);
404}
405
406static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
407 struct intel_shared_dpll *pll,
408 struct intel_dpll_hw_state *hw_state)
409{
410 uint32_t val;
411
412 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
413 return false;
414
415 val = I915_READ(WRPLL_CTL(pll->id));
416 hw_state->wrpll = val;
417
418 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
419
420 return val & WRPLL_PLL_ENABLE;
421}
422
423static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv,
424 struct intel_shared_dpll *pll,
425 struct intel_dpll_hw_state *hw_state)
426{
427 uint32_t val;
428
429 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
430 return false;
431
432 val = I915_READ(SPLL_CTL);
433 hw_state->spll = val;
434
435 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
436
437 return val & SPLL_PLL_ENABLE;
438}
439
daedf20a
ACO		 440static uint32_t hsw_pll_to_ddi_pll_sel(struct intel_shared_dpll *pll)
441{
442 switch (pll->id) {
443 case DPLL_ID_WRPLL1:
444 return PORT_CLK_SEL_WRPLL1;
445 case DPLL_ID_WRPLL2:
446 return PORT_CLK_SEL_WRPLL2;
447 case DPLL_ID_SPLL:
448 return PORT_CLK_SEL_SPLL;
9d16da65
ACO		 449 case DPLL_ID_LCPLL_810:
450 return PORT_CLK_SEL_LCPLL_810;
451 case DPLL_ID_LCPLL_1350:
452 return PORT_CLK_SEL_LCPLL_1350;
453 case DPLL_ID_LCPLL_2700:
454 return PORT_CLK_SEL_LCPLL_2700;
daedf20a
ACO		 455 default:
456 return PORT_CLK_SEL_NONE;
457 }
458}
459
460#define LC_FREQ 2700
461#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
462
463#define P_MIN 2
464#define P_MAX 64
465#define P_INC 2
466
467/* Constraints for PLL good behavior */
468#define REF_MIN 48
469#define REF_MAX 400
470#define VCO_MIN 2400
471#define VCO_MAX 4800
472
473struct hsw_wrpll_rnp {
474 unsigned p, n2, r2;
475};
476
477static unsigned hsw_wrpll_get_budget_for_freq(int clock)
478{
479 unsigned budget;
480
481 switch (clock) {
482 case 25175000:
483 case 25200000:
484 case 27000000:
485 case 27027000:
486 case 37762500:
487 case 37800000:
488 case 40500000:
489 case 40541000:
490 case 54000000:
491 case 54054000:
492 case 59341000:
493 case 59400000:
494 case 72000000:
495 case 74176000:
496 case 74250000:
497 case 81000000:
498 case 81081000:
499 case 89012000:
500 case 89100000:
501 case 108000000:
502 case 108108000:
503 case 111264000:
504 case 111375000:
505 case 148352000:
506 case 148500000:
507 case 162000000:
508 case 162162000:
509 case 222525000:
510 case 222750000:
511 case 296703000:
512 case 297000000:
513 budget = 0;
514 break;
515 case 233500000:
516 case 245250000:
517 case 247750000:
518 case 253250000:
519 case 298000000:
520 budget = 1500;
521 break;
522 case 169128000:
523 case 169500000:
524 case 179500000:
525 case 202000000:
526 budget = 2000;
527 break;
528 case 256250000:
529 case 262500000:
530 case 270000000:
531 case 272500000:
532 case 273750000:
533 case 280750000:
534 case 281250000:
535 case 286000000:
536 case 291750000:
537 budget = 4000;
538 break;
539 case 267250000:
540 case 268500000:
541 budget = 5000;
542 break;
543 default:
544 budget = 1000;
545 break;
546 }
547
548 return budget;
549}
550
551static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
552 unsigned r2, unsigned n2, unsigned p,
553 struct hsw_wrpll_rnp *best)
554{
555 uint64_t a, b, c, d, diff, diff_best;
556
557 /* No best (r,n,p) yet */
558 if (best->p == 0) {
559 best->p = p;
560 best->n2 = n2;
561 best->r2 = r2;
562 return;
563 }
564
565 /*
566 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
567 * freq2k.
568 *
569 * delta = 1e6 *
570 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
571 * freq2k;
572 *
573 * and we would like delta <= budget.
574 *
575 * If the discrepancy is above the PPM-based budget, always prefer to
576 * improve upon the previous solution. However, if you're within the
577 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
578 */
579 a = freq2k * budget * p * r2;
580 b = freq2k * budget * best->p * best->r2;
581 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
582 diff_best = abs_diff(freq2k * best->p * best->r2,
583 LC_FREQ_2K * best->n2);
584 c = 1000000 * diff;
585 d = 1000000 * diff_best;
586
587 if (a < c && b < d) {
588 /* If both are above the budget, pick the closer */
589 if (best->p * best->r2 * diff < p * r2 * diff_best) {
590 best->p = p;
591 best->n2 = n2;
592 best->r2 = r2;
593 }
594 } else if (a >= c && b < d) {
595 /* If A is below the threshold but B is above it? Update. */
596 best->p = p;
597 best->n2 = n2;
598 best->r2 = r2;
599 } else if (a >= c && b >= d) {
600 /* Both are below the limit, so pick the higher n2/(r2*r2) */
601 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
602 best->p = p;
603 best->n2 = n2;
604 best->r2 = r2;
605 }
606 }
607 /* Otherwise a < c && b >= d, do nothing */
608}
609
610static void
611hsw_ddi_calculate_wrpll(int clock /* in Hz */,
612 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
613{
614 uint64_t freq2k;
615 unsigned p, n2, r2;
616 struct hsw_wrpll_rnp best = { 0, 0, 0 };
617 unsigned budget;
618
619 freq2k = clock / 100;
620
621 budget = hsw_wrpll_get_budget_for_freq(clock);
622
623 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
624 * and directly pass the LC PLL to it. */
625 if (freq2k == 5400000) {
626 *n2_out = 2;
627 *p_out = 1;
628 *r2_out = 2;
629 return;
630 }
631
632 /*
633 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
634 * the WR PLL.
635 *
636 * We want R so that REF_MIN <= Ref <= REF_MAX.
637 * Injecting R2 = 2 * R gives:
638 * REF_MAX * r2 > LC_FREQ * 2 and
639 * REF_MIN * r2 < LC_FREQ * 2
640 *
641 * Which means the desired boundaries for r2 are:
642 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
643 *
644 */
645 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
646 r2 <= LC_FREQ * 2 / REF_MIN;
647 r2++) {
648
649 /*
650 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
651 *
652 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
653 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
654 * VCO_MAX * r2 > n2 * LC_FREQ and
655 * VCO_MIN * r2 < n2 * LC_FREQ)
656 *
657 * Which means the desired boundaries for n2 are:
658 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
659 */
660 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
661 n2 <= VCO_MAX * r2 / LC_FREQ;
662 n2++) {
663
664 for (p = P_MIN; p <= P_MAX; p += P_INC)
665 hsw_wrpll_update_rnp(freq2k, budget,
666 r2, n2, p, &best);
667 }
668 }
669
670 *n2_out = best.n2;
671 *p_out = best.p;
672 *r2_out = best.r2;
673}
674
f9476a6c 675static struct intel_shared_dpll *
daedf20a
ACO		 676hsw_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
677 struct intel_encoder *encoder)
f9476a6c 678{
9d16da65 679 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
f9476a6c 680 struct intel_shared_dpll *pll;
daedf20a 681 int clock = crtc_state->port_clock;
f9476a6c 682
9d16da65
ACO		 683 memset(&crtc_state->dpll_hw_state, 0,
684 sizeof(crtc_state->dpll_hw_state));
685
daedf20a
ACO		 686 if (encoder->type == INTEL_OUTPUT_HDMI) {
687 uint32_t val;
688 unsigned p, n2, r2;
689
690 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
691
692 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
693 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
694 WRPLL_DIVIDER_POST(p);
695
daedf20a
ACO		 696 crtc_state->dpll_hw_state.wrpll = val;
697
698 pll = intel_find_shared_dpll(crtc, crtc_state,
699 DPLL_ID_WRPLL1, DPLL_ID_WRPLL2);
700
9d16da65
ACO		 701 } else if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
702 encoder->type == INTEL_OUTPUT_DP_MST ||
703 encoder->type == INTEL_OUTPUT_EDP) {
704 enum intel_dpll_id pll_id;
705
706 switch (clock / 2) {
707 case 81000:
708 pll_id = DPLL_ID_LCPLL_810;
709 break;
710 case 135000:
711 pll_id = DPLL_ID_LCPLL_1350;
712 break;
713 case 270000:
714 pll_id = DPLL_ID_LCPLL_2700;
715 break;
716 default:
717 DRM_DEBUG_KMS("Invalid clock for DP: %d\n", clock);
718 return NULL;
719 }
720
721 pll = intel_get_shared_dpll_by_id(dev_priv, pll_id);
722
daedf20a
ACO		 723 } else if (encoder->type == INTEL_OUTPUT_ANALOG) {
724 if (WARN_ON(crtc_state->port_clock / 2 != 135000))
725 return NULL;
726
daedf20a
ACO		 727 crtc_state->dpll_hw_state.spll =
728 SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
729
730 pll = intel_find_shared_dpll(crtc, crtc_state,
731 DPLL_ID_SPLL, DPLL_ID_SPLL);
732 } else {
733 return NULL;
734 }
735
736 if (!pll)
737 return NULL;
738
739 crtc_state->ddi_pll_sel = hsw_pll_to_ddi_pll_sel(pll);
740
741 intel_reference_shared_dpll(pll, crtc_state);
f9476a6c
ACO		 742
743 return pll;
744}
745
55be2f08 746
2edd6443
ACO		 747static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = {
748 .enable = hsw_ddi_wrpll_enable,
749 .disable = hsw_ddi_wrpll_disable,
750 .get_hw_state = hsw_ddi_wrpll_get_hw_state,
55be2f08
ACO		 751};
752
2edd6443
ACO		 753static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = {
754 .enable = hsw_ddi_spll_enable,
755 .disable = hsw_ddi_spll_disable,
756 .get_hw_state = hsw_ddi_spll_get_hw_state,
55be2f08
ACO		 757};
758
9d16da65
ACO		 759static void hsw_ddi_lcpll_enable(struct drm_i915_private *dev_priv,
760 struct intel_shared_dpll *pll)
761{
762}
763
764static void hsw_ddi_lcpll_disable(struct drm_i915_private *dev_priv,
765 struct intel_shared_dpll *pll)
766{
767}
768
769static bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_private *dev_priv,
770 struct intel_shared_dpll *pll,
771 struct intel_dpll_hw_state *hw_state)
772{
773 return true;
774}
775
776static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = {
777 .enable = hsw_ddi_lcpll_enable,
778 .disable = hsw_ddi_lcpll_disable,
779 .get_hw_state = hsw_ddi_lcpll_get_hw_state,
780};
781
55be2f08
ACO		 782struct skl_dpll_regs {
783 i915_reg_t ctl, cfgcr1, cfgcr2;
784};
785
786/* this array is indexed by the *shared* pll id */
a3c988ea
ACO		 787static const struct skl_dpll_regs skl_dpll_regs[4] = {
788 {
789 /* DPLL 0 */
790 .ctl = LCPLL1_CTL,
791 /* DPLL 0 doesn't support HDMI mode */
792 },
55be2f08
ACO		 793 {
794 /* DPLL 1 */
795 .ctl = LCPLL2_CTL,
796 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
797 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
798 },
799 {
800 /* DPLL 2 */
801 .ctl = WRPLL_CTL(0),
802 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
803 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
804 },
805 {
806 /* DPLL 3 */
807 .ctl = WRPLL_CTL(1),
808 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
809 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
810 },
811};
812
a3c988ea
ACO		 813static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *dev_priv,
814 struct intel_shared_dpll *pll)
55be2f08
ACO		 815{
816 uint32_t val;
55be2f08
ACO		 817
818 val = I915_READ(DPLL_CTRL1);
819
a3c988ea
ACO		 820 val &= ~(DPLL_CTRL1_HDMI_MODE(pll->id) | DPLL_CTRL1_SSC(pll->id) |
821 DPLL_CTRL1_LINK_RATE_MASK(pll->id));
822 val |= pll->config.hw_state.ctrl1 << (pll->id * 6);
55be2f08
ACO		 823
824 I915_WRITE(DPLL_CTRL1, val);
825 POSTING_READ(DPLL_CTRL1);
a3c988ea
ACO		 826}
827
828static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
829 struct intel_shared_dpll *pll)
830{
831 const struct skl_dpll_regs *regs = skl_dpll_regs;
832
833 skl_ddi_pll_write_ctrl1(dev_priv, pll);
55be2f08
ACO		 834
835 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
836 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
837 POSTING_READ(regs[pll->id].cfgcr1);
838 POSTING_READ(regs[pll->id].cfgcr2);
839
840 /* the enable bit is always bit 31 */
841 I915_WRITE(regs[pll->id].ctl,
842 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
843
a3c988ea
ACO		 844 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(pll->id), 5))
845 DRM_ERROR("DPLL %d not locked\n", pll->id);
846}
847
848static void skl_ddi_dpll0_enable(struct drm_i915_private *dev_priv,
849 struct intel_shared_dpll *pll)
850{
851 skl_ddi_pll_write_ctrl1(dev_priv, pll);
55be2f08
ACO		 852}
853
854static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
855 struct intel_shared_dpll *pll)
856{
857 const struct skl_dpll_regs *regs = skl_dpll_regs;
858
859 /* the enable bit is always bit 31 */
860 I915_WRITE(regs[pll->id].ctl,
861 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
862 POSTING_READ(regs[pll->id].ctl);
863}
864
a3c988ea
ACO		 865static void skl_ddi_dpll0_disable(struct drm_i915_private *dev_priv,
866 struct intel_shared_dpll *pll)
867{
868}
869
55be2f08
ACO		 870static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
871 struct intel_shared_dpll *pll,
872 struct intel_dpll_hw_state *hw_state)
873{
874 uint32_t val;
55be2f08
ACO		 875 const struct skl_dpll_regs *regs = skl_dpll_regs;
876 bool ret;
877
878 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
879 return false;
880
881 ret = false;
882
55be2f08
ACO		 883 val = I915_READ(regs[pll->id].ctl);
884 if (!(val & LCPLL_PLL_ENABLE))
885 goto out;
886
887 val = I915_READ(DPLL_CTRL1);
a3c988ea 888 hw_state->ctrl1 = (val >> (pll->id * 6)) & 0x3f;
55be2f08
ACO		 889
890 /* avoid reading back stale values if HDMI mode is not enabled */
a3c988ea 891 if (val & DPLL_CTRL1_HDMI_MODE(pll->id)) {
55be2f08
ACO		 892 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
893 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
894 }
895 ret = true;
896
897out:
898 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
899
900 return ret;
901}
902
a3c988ea
ACO		 903static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv,
904 struct intel_shared_dpll *pll,
905 struct intel_dpll_hw_state *hw_state)
906{
907 uint32_t val;
908 const struct skl_dpll_regs *regs = skl_dpll_regs;
909 bool ret;
910
911 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
912 return false;
913
914 ret = false;
915
916 /* DPLL0 is always enabled since it drives CDCLK */
917 val = I915_READ(regs[pll->id].ctl);
918 if (WARN_ON(!(val & LCPLL_PLL_ENABLE)))
919 goto out;
920
921 val = I915_READ(DPLL_CTRL1);
922 hw_state->ctrl1 = (val >> (pll->id * 6)) & 0x3f;
923
924 ret = true;
925
926out:
927 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
928
929 return ret;
930}
931
304b65cb
ACO		 932struct skl_wrpll_context {
933 uint64_t min_deviation; /* current minimal deviation */
934 uint64_t central_freq; /* chosen central freq */
935 uint64_t dco_freq; /* chosen dco freq */
936 unsigned int p; /* chosen divider */
937};
938
939static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
940{
941 memset(ctx, 0, sizeof(*ctx));
942
943 ctx->min_deviation = U64_MAX;
944}
945
946/* DCO freq must be within +1%/-6% of the DCO central freq */
947#define SKL_DCO_MAX_PDEVIATION 100
948#define SKL_DCO_MAX_NDEVIATION 600
949
950static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
951 uint64_t central_freq,
952 uint64_t dco_freq,
953 unsigned int divider)
954{
955 uint64_t deviation;
956
957 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
958 central_freq);
959
960 /* positive deviation */
961 if (dco_freq >= central_freq) {
962 if (deviation < SKL_DCO_MAX_PDEVIATION &&
963 deviation < ctx->min_deviation) {
964 ctx->min_deviation = deviation;
965 ctx->central_freq = central_freq;
966 ctx->dco_freq = dco_freq;
967 ctx->p = divider;
968 }
969 /* negative deviation */
970 } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
971 deviation < ctx->min_deviation) {
972 ctx->min_deviation = deviation;
973 ctx->central_freq = central_freq;
974 ctx->dco_freq = dco_freq;
975 ctx->p = divider;
976 }
977}
978
979static void skl_wrpll_get_multipliers(unsigned int p,
980 unsigned int *p0 /* out */,
981 unsigned int *p1 /* out */,
982 unsigned int *p2 /* out */)
983{
984 /* even dividers */
985 if (p % 2 == 0) {
986 unsigned int half = p / 2;
987
988 if (half == 1 || half == 2 || half == 3 || half == 5) {
989 *p0 = 2;
990 *p1 = 1;
991 *p2 = half;
992 } else if (half % 2 == 0) {
993 *p0 = 2;
994 *p1 = half / 2;
995 *p2 = 2;
996 } else if (half % 3 == 0) {
997 *p0 = 3;
998 *p1 = half / 3;
999 *p2 = 2;
1000 } else if (half % 7 == 0) {
1001 *p0 = 7;
1002 *p1 = half / 7;
1003 *p2 = 2;
1004 }
1005 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1006 *p0 = 3;
1007 *p1 = 1;
1008 *p2 = p / 3;
1009 } else if (p == 5 || p == 7) {
1010 *p0 = p;
1011 *p1 = 1;
1012 *p2 = 1;
1013 } else if (p == 15) {
1014 *p0 = 3;
1015 *p1 = 1;
1016 *p2 = 5;
1017 } else if (p == 21) {
1018 *p0 = 7;
1019 *p1 = 1;
1020 *p2 = 3;
1021 } else if (p == 35) {
1022 *p0 = 7;
1023 *p1 = 1;
1024 *p2 = 5;
1025 }
1026}
1027
1028struct skl_wrpll_params {
1029 uint32_t dco_fraction;
1030 uint32_t dco_integer;
1031 uint32_t qdiv_ratio;
1032 uint32_t qdiv_mode;
1033 uint32_t kdiv;
1034 uint32_t pdiv;
1035 uint32_t central_freq;
1036};
1037
1038static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1039 uint64_t afe_clock,
1040 uint64_t central_freq,
1041 uint32_t p0, uint32_t p1, uint32_t p2)
1042{
1043 uint64_t dco_freq;
1044
1045 switch (central_freq) {
1046 case 9600000000ULL:
1047 params->central_freq = 0;
1048 break;
1049 case 9000000000ULL:
1050 params->central_freq = 1;
1051 break;
1052 case 8400000000ULL:
1053 params->central_freq = 3;
1054 }
1055
1056 switch (p0) {
1057 case 1:
1058 params->pdiv = 0;
1059 break;
1060 case 2:
1061 params->pdiv = 1;
1062 break;
1063 case 3:
1064 params->pdiv = 2;
1065 break;
1066 case 7:
1067 params->pdiv = 4;
1068 break;
1069 default:
1070 WARN(1, "Incorrect PDiv\n");
1071 }
1072
1073 switch (p2) {
1074 case 5:
1075 params->kdiv = 0;
1076 break;
1077 case 2:
1078 params->kdiv = 1;
1079 break;
1080 case 3:
1081 params->kdiv = 2;
1082 break;
1083 case 1:
1084 params->kdiv = 3;
1085 break;
1086 default:
1087 WARN(1, "Incorrect KDiv\n");
1088 }
1089
1090 params->qdiv_ratio = p1;
1091 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1092
1093 dco_freq = p0 * p1 * p2 * afe_clock;
1094
1095 /*
1096 * Intermediate values are in Hz.
1097 * Divide by MHz to match bsepc
1098 */
1099 params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
1100 params->dco_fraction =
1101 div_u64((div_u64(dco_freq, 24) -
1102 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
1103}
1104
1105static bool
1106skl_ddi_calculate_wrpll(int clock /* in Hz */,
1107 struct skl_wrpll_params *wrpll_params)
1108{
1109 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
1110 uint64_t dco_central_freq[3] = {8400000000ULL,
1111 9000000000ULL,
1112 9600000000ULL};
1113 static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1114 24, 28, 30, 32, 36, 40, 42, 44,
1115 48, 52, 54, 56, 60, 64, 66, 68,
1116 70, 72, 76, 78, 80, 84, 88, 90,
1117 92, 96, 98 };
1118 static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1119 static const struct {
1120 const int *list;
1121 int n_dividers;
1122 } dividers[] = {
1123 { even_dividers, ARRAY_SIZE(even_dividers) },
1124 { odd_dividers, ARRAY_SIZE(odd_dividers) },
1125 };
1126 struct skl_wrpll_context ctx;
1127 unsigned int dco, d, i;
1128 unsigned int p0, p1, p2;
1129
1130 skl_wrpll_context_init(&ctx);
1131
1132 for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1133 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1134 for (i = 0; i < dividers[d].n_dividers; i++) {
1135 unsigned int p = dividers[d].list[i];
1136 uint64_t dco_freq = p * afe_clock;
1137
1138 skl_wrpll_try_divider(&ctx,
1139 dco_central_freq[dco],
1140 dco_freq,
1141 p);
1142 /*
1143 * Skip the remaining dividers if we're sure to
1144 * have found the definitive divider, we can't
1145 * improve a 0 deviation.
1146 */
1147 if (ctx.min_deviation == 0)
1148 goto skip_remaining_dividers;
1149 }
1150 }
1151
1152skip_remaining_dividers:
1153 /*
1154 * If a solution is found with an even divider, prefer
1155 * this one.
1156 */
1157 if (d == 0 && ctx.p)
1158 break;
1159 }
1160
1161 if (!ctx.p) {
1162 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
1163 return false;
1164 }
1165
1166 /*
1167 * gcc incorrectly analyses that these can be used without being
1168 * initialized. To be fair, it's hard to guess.
1169 */
1170 p0 = p1 = p2 = 0;
1171 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1172 skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
1173 p0, p1, p2);
1174
1175 return true;
1176}
1177
f9476a6c 1178static struct intel_shared_dpll *
daedf20a
ACO		 1179skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
1180 struct intel_encoder *encoder)
f9476a6c
ACO		 1181{
1182 struct intel_shared_dpll *pll;
304b65cb
ACO		 1183 uint32_t ctrl1, cfgcr1, cfgcr2;
1184 int clock = crtc_state->port_clock;
1185
1186 /*
1187 * See comment in intel_dpll_hw_state to understand why we always use 0
1188 * as the DPLL id in this function.
1189 */
1190
1191 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1192
1193 if (encoder->type == INTEL_OUTPUT_HDMI) {
1194 struct skl_wrpll_params wrpll_params = { 0, };
1195
1196 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1197
1198 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
1199 return false;
1200
1201 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1202 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1203 wrpll_params.dco_integer;
1204
1205 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1206 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1207 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1208 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1209 wrpll_params.central_freq;
1210 } else if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
a3c988ea
ACO		 1211 encoder->type == INTEL_OUTPUT_DP_MST ||
1212 encoder->type == INTEL_OUTPUT_EDP) {
304b65cb
ACO		 1213 switch (crtc_state->port_clock / 2) {
1214 case 81000:
1215 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
1216 break;
1217 case 135000:
1218 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
1219 break;
1220 case 270000:
1221 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
1222 break;
a3c988ea
ACO		 1223 /* eDP 1.4 rates */
1224 case 162000:
1225 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, 0);
1226 break;
1227 /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
1228 results in CDCLK change. Need to handle the change of CDCLK by
1229 disabling pipes and re-enabling them */
1230 case 108000:
1231 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0);
1232 break;
1233 case 216000:
1234 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0);
1235 break;
304b65cb
ACO		 1236 }
1237
1238 cfgcr1 = cfgcr2 = 0;
1239 } else {
1240 return NULL;
1241 }
1242
1243 memset(&crtc_state->dpll_hw_state, 0,
1244 sizeof(crtc_state->dpll_hw_state));
1245
1246 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1247 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1248 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
f9476a6c 1249
a3c988ea
ACO		 1250 if (encoder->type == INTEL_OUTPUT_EDP)
1251 pll = intel_find_shared_dpll(crtc, crtc_state,
1252 DPLL_ID_SKL_DPLL0,
1253 DPLL_ID_SKL_DPLL0);
1254 else
1255 pll = intel_find_shared_dpll(crtc, crtc_state,
1256 DPLL_ID_SKL_DPLL1,
1257 DPLL_ID_SKL_DPLL3);
304b65cb
ACO		 1258 if (!pll)
1259 return NULL;
1260
a3c988ea 1261 crtc_state->ddi_pll_sel = pll->id;
304b65cb
ACO		 1262
1263 intel_reference_shared_dpll(pll, crtc_state);
f9476a6c
ACO		 1264
1265 return pll;
1266}
1267
2edd6443
ACO		 1268static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = {
1269 .enable = skl_ddi_pll_enable,
1270 .disable = skl_ddi_pll_disable,
1271 .get_hw_state = skl_ddi_pll_get_hw_state,
55be2f08
ACO		 1272};
1273
a3c988ea
ACO		 1274static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = {
1275 .enable = skl_ddi_dpll0_enable,
1276 .disable = skl_ddi_dpll0_disable,
1277 .get_hw_state = skl_ddi_dpll0_get_hw_state,
1278};
1279
55be2f08
ACO		 1280static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
1281 struct intel_shared_dpll *pll)
1282{
1283 uint32_t temp;
1284 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
1285
1286 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1287 temp &= ~PORT_PLL_REF_SEL;
1288 /* Non-SSC reference */
1289 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1290
1291 /* Disable 10 bit clock */
1292 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
1293 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
1294 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
1295
1296 /* Write P1 & P2 */
1297 temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
1298 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
1299 temp |= pll->config.hw_state.ebb0;
1300 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
1301
1302 /* Write M2 integer */
1303 temp = I915_READ(BXT_PORT_PLL(port, 0));
1304 temp &= ~PORT_PLL_M2_MASK;
1305 temp |= pll->config.hw_state.pll0;
1306 I915_WRITE(BXT_PORT_PLL(port, 0), temp);
1307
1308 /* Write N */
1309 temp = I915_READ(BXT_PORT_PLL(port, 1));
1310 temp &= ~PORT_PLL_N_MASK;
1311 temp |= pll->config.hw_state.pll1;
1312 I915_WRITE(BXT_PORT_PLL(port, 1), temp);
1313
1314 /* Write M2 fraction */
1315 temp = I915_READ(BXT_PORT_PLL(port, 2));
1316 temp &= ~PORT_PLL_M2_FRAC_MASK;
1317 temp |= pll->config.hw_state.pll2;
1318 I915_WRITE(BXT_PORT_PLL(port, 2), temp);
1319
1320 /* Write M2 fraction enable */
1321 temp = I915_READ(BXT_PORT_PLL(port, 3));
1322 temp &= ~PORT_PLL_M2_FRAC_ENABLE;
1323 temp |= pll->config.hw_state.pll3;
1324 I915_WRITE(BXT_PORT_PLL(port, 3), temp);
1325
1326 /* Write coeff */
1327 temp = I915_READ(BXT_PORT_PLL(port, 6));
1328 temp &= ~PORT_PLL_PROP_COEFF_MASK;
1329 temp &= ~PORT_PLL_INT_COEFF_MASK;
1330 temp &= ~PORT_PLL_GAIN_CTL_MASK;
1331 temp |= pll->config.hw_state.pll6;
1332 I915_WRITE(BXT_PORT_PLL(port, 6), temp);
1333
1334 /* Write calibration val */
1335 temp = I915_READ(BXT_PORT_PLL(port, 8));
1336 temp &= ~PORT_PLL_TARGET_CNT_MASK;
1337 temp |= pll->config.hw_state.pll8;
1338 I915_WRITE(BXT_PORT_PLL(port, 8), temp);
1339
1340 temp = I915_READ(BXT_PORT_PLL(port, 9));
1341 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
1342 temp |= pll->config.hw_state.pll9;
1343 I915_WRITE(BXT_PORT_PLL(port, 9), temp);
1344
1345 temp = I915_READ(BXT_PORT_PLL(port, 10));
1346 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
1347 temp &= ~PORT_PLL_DCO_AMP_MASK;
1348 temp |= pll->config.hw_state.pll10;
1349 I915_WRITE(BXT_PORT_PLL(port, 10), temp);
1350
1351 /* Recalibrate with new settings */
1352 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
1353 temp |= PORT_PLL_RECALIBRATE;
1354 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
1355 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
1356 temp |= pll->config.hw_state.ebb4;
1357 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
1358
1359 /* Enable PLL */
1360 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1361 temp |= PORT_PLL_ENABLE;
1362 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1363 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
1364
1365 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
1366 PORT_PLL_LOCK), 200))
1367 DRM_ERROR("PLL %d not locked\n", port);
1368
1369 /*
1370 * While we write to the group register to program all lanes at once we
1371 * can read only lane registers and we pick lanes 0/1 for that.
1372 */
1373 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
1374 temp &= ~LANE_STAGGER_MASK;
1375 temp &= ~LANESTAGGER_STRAP_OVRD;
1376 temp |= pll->config.hw_state.pcsdw12;
1377 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
1378}
1379
1380static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
1381 struct intel_shared_dpll *pll)
1382{
1383 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
1384 uint32_t temp;
1385
1386 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1387 temp &= ~PORT_PLL_ENABLE;
1388 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1389 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
1390}
1391
1392static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1393 struct intel_shared_dpll *pll,
1394 struct intel_dpll_hw_state *hw_state)
1395{
1396 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
1397 uint32_t val;
1398 bool ret;
1399
1400 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
1401 return false;
1402
1403 ret = false;
1404
1405 val = I915_READ(BXT_PORT_PLL_ENABLE(port));
1406 if (!(val & PORT_PLL_ENABLE))
1407 goto out;
1408
1409 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
1410 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
1411
1412 hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port));
1413 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
1414
1415 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
1416 hw_state->pll0 &= PORT_PLL_M2_MASK;
1417
1418 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
1419 hw_state->pll1 &= PORT_PLL_N_MASK;
1420
1421 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
1422 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
1423
1424 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
1425 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
1426
1427 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
1428 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
1429 PORT_PLL_INT_COEFF_MASK |
1430 PORT_PLL_GAIN_CTL_MASK;
1431
1432 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
1433 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
1434
1435 hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9));
1436 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
1437
1438 hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
1439 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
1440 PORT_PLL_DCO_AMP_MASK;
1441
1442 /*
1443 * While we write to the group register to program all lanes at once we
1444 * can read only lane registers. We configure all lanes the same way, so
1445 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
1446 */
1447 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
1448 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12)
1449 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
1450 hw_state->pcsdw12,
1451 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
1452 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
1453
1454 ret = true;
1455
1456out:
1457 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1458
1459 return ret;
1460}
1461
34177c24
ACO		 1462/* bxt clock parameters */
1463struct bxt_clk_div {
1464 int clock;
1465 uint32_t p1;
1466 uint32_t p2;
1467 uint32_t m2_int;
1468 uint32_t m2_frac;
1469 bool m2_frac_en;
1470 uint32_t n;
1471};
1472
1473/* pre-calculated values for DP linkrates */
1474static const struct bxt_clk_div bxt_dp_clk_val[] = {
1475 {162000, 4, 2, 32, 1677722, 1, 1},
1476 {270000, 4, 1, 27, 0, 0, 1},
1477 {540000, 2, 1, 27, 0, 0, 1},
1478 {216000, 3, 2, 32, 1677722, 1, 1},
1479 {243000, 4, 1, 24, 1258291, 1, 1},
1480 {324000, 4, 1, 32, 1677722, 1, 1},
1481 {432000, 3, 1, 32, 1677722, 1, 1}
1482};
1483
f9476a6c 1484static struct intel_shared_dpll *
daedf20a
ACO		 1485bxt_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
1486 struct intel_encoder *encoder)
f9476a6c
ACO		 1487{
1488 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
f9476a6c
ACO		 1489 struct intel_shared_dpll *pll;
1490 enum intel_dpll_id i;
34177c24
ACO		 1491 struct intel_digital_port *intel_dig_port;
1492 struct bxt_clk_div clk_div = {0};
1493 int vco = 0;
1494 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
1495 uint32_t lanestagger;
1496 int clock = crtc_state->port_clock;
f9476a6c 1497
34177c24
ACO		 1498 if (encoder->type == INTEL_OUTPUT_HDMI) {
1499 intel_clock_t best_clock;
1500
1501 /* Calculate HDMI div */
1502 /*
1503 * FIXME: tie the following calculation into
1504 * i9xx_crtc_compute_clock
1505 */
1506 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1507 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1508 clock, pipe_name(crtc->pipe));
1509 return NULL;
1510 }
1511
1512 clk_div.p1 = best_clock.p1;
1513 clk_div.p2 = best_clock.p2;
1514 WARN_ON(best_clock.m1 != 2);
1515 clk_div.n = best_clock.n;
1516 clk_div.m2_int = best_clock.m2 >> 22;
1517 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
1518 clk_div.m2_frac_en = clk_div.m2_frac != 0;
1519
1520 vco = best_clock.vco;
1521 } else if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1522 encoder->type == INTEL_OUTPUT_EDP) {
1523 int i;
1524
1525 clk_div = bxt_dp_clk_val[0];
1526 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
1527 if (bxt_dp_clk_val[i].clock == clock) {
1528 clk_div = bxt_dp_clk_val[i];
1529 break;
1530 }
1531 }
1532 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
1533 }
1534
1535 if (vco >= 6200000 && vco <= 6700000) {
1536 prop_coef = 4;
1537 int_coef = 9;
1538 gain_ctl = 3;
1539 targ_cnt = 8;
1540 } else if ((vco > 5400000 && vco < 6200000) ||
1541 (vco >= 4800000 && vco < 5400000)) {
1542 prop_coef = 5;
1543 int_coef = 11;
1544 gain_ctl = 3;
1545 targ_cnt = 9;
1546 } else if (vco == 5400000) {
1547 prop_coef = 3;
1548 int_coef = 8;
1549 gain_ctl = 1;
1550 targ_cnt = 9;
1551 } else {
1552 DRM_ERROR("Invalid VCO\n");
f9476a6c 1553 return NULL;
34177c24
ACO		 1554 }
1555
1556 memset(&crtc_state->dpll_hw_state, 0,
1557 sizeof(crtc_state->dpll_hw_state));
1558
1559 if (clock > 270000)
1560 lanestagger = 0x18;
1561 else if (clock > 135000)
1562 lanestagger = 0x0d;
1563 else if (clock > 67000)
1564 lanestagger = 0x07;
1565 else if (clock > 33000)
1566 lanestagger = 0x04;
1567 else
1568 lanestagger = 0x02;
1569
1570 crtc_state->dpll_hw_state.ebb0 =
1571 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
1572 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
1573 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
1574 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
1575
1576 if (clk_div.m2_frac_en)
1577 crtc_state->dpll_hw_state.pll3 =
1578 PORT_PLL_M2_FRAC_ENABLE;
1579
1580 crtc_state->dpll_hw_state.pll6 =
1581 prop_coef | PORT_PLL_INT_COEFF(int_coef);
1582 crtc_state->dpll_hw_state.pll6 |=
1583 PORT_PLL_GAIN_CTL(gain_ctl);
1584
1585 crtc_state->dpll_hw_state.pll8 = targ_cnt;
1586
1587 crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
1588
1589 crtc_state->dpll_hw_state.pll10 =
1590 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
1591 | PORT_PLL_DCO_AMP_OVR_EN_H;
1592
1593 crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
1594
1595 crtc_state->dpll_hw_state.pcsdw12 =
1596 LANESTAGGER_STRAP_OVRD | lanestagger;
f9476a6c
ACO		 1597
1598 intel_dig_port = enc_to_dig_port(&encoder->base);
34177c24 1599
f9476a6c 1600 /* 1:1 mapping between ports and PLLs */
34177c24
ACO		 1601 i = (enum intel_dpll_id) intel_dig_port->port;
1602 pll = intel_get_shared_dpll_by_id(dev_priv, i);
1603
f9476a6c
ACO		 1604 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
1605 crtc->base.base.id, pll->name);
1606
1607 intel_reference_shared_dpll(pll, crtc_state);
1608
34177c24
ACO		 1609 /* shared DPLL id 0 is DPLL A */
1610 crtc_state->ddi_pll_sel = pll->id;
1611
f9476a6c
ACO		 1612 return pll;
1613}
1614
2edd6443
ACO		 1615static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
1616 .enable = bxt_ddi_pll_enable,
1617 .disable = bxt_ddi_pll_disable,
1618 .get_hw_state = bxt_ddi_pll_get_hw_state,
1619};
55be2f08
ACO		 1620
1621static void intel_ddi_pll_init(struct drm_device *dev)
1622{
1623 struct drm_i915_private *dev_priv = dev->dev_private;
1624 uint32_t val = I915_READ(LCPLL_CTL);
1625
55be2f08
ACO		 1626 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1627 int cdclk_freq;
1628
1629 cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
1630 dev_priv->skl_boot_cdclk = cdclk_freq;
1631 if (skl_sanitize_cdclk(dev_priv))
1632 DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
1633 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
1634 DRM_ERROR("LCPLL1 is disabled\n");
1635 } else if (IS_BROXTON(dev)) {
1636 broxton_init_cdclk(dev);
1637 broxton_ddi_phy_init(dev);
1638 } else {
1639 /*
1640 * The LCPLL register should be turned on by the BIOS. For now
1641 * let's just check its state and print errors in case
1642 * something is wrong. Don't even try to turn it on.
1643 */
1644
1645 if (val & LCPLL_CD_SOURCE_FCLK)
1646 DRM_ERROR("CDCLK source is not LCPLL\n");
1647
1648 if (val & LCPLL_PLL_DISABLE)
1649 DRM_ERROR("LCPLL is disabled\n");
1650 }
1651}
1652
2edd6443
ACO		 1653struct dpll_info {
1654 const char *name;
1655 const int id;
1656 const struct intel_shared_dpll_funcs *funcs;
9d16da65 1657 uint32_t flags;
2edd6443
ACO		 1658};
1659
f9476a6c
ACO		 1660struct intel_dpll_mgr {
1661 const struct dpll_info *dpll_info;
1662
1663 struct intel_shared_dpll *(*get_dpll)(struct intel_crtc *crtc,
daedf20a
ACO		 1664 struct intel_crtc_state *crtc_state,
1665 struct intel_encoder *encoder);
f9476a6c
ACO		 1666};
1667
2edd6443 1668static const struct dpll_info pch_plls[] = {
9d16da65
ACO		 1669 { "PCH DPLL A", DPLL_ID_PCH_PLL_A, &ibx_pch_dpll_funcs, 0 },
1670 { "PCH DPLL B", DPLL_ID_PCH_PLL_B, &ibx_pch_dpll_funcs, 0 },
1671 { NULL, -1, NULL, 0 },
2edd6443
ACO		 1672};
1673
f9476a6c
ACO		 1674static const struct intel_dpll_mgr pch_pll_mgr = {
1675 .dpll_info = pch_plls,
1676 .get_dpll = ibx_get_dpll,
1677};
1678
2edd6443 1679static const struct dpll_info hsw_plls[] = {
9d16da65
ACO		 1680 { "WRPLL 1", DPLL_ID_WRPLL1, &hsw_ddi_wrpll_funcs, 0 },
1681 { "WRPLL 2", DPLL_ID_WRPLL2, &hsw_ddi_wrpll_funcs, 0 },
1682 { "SPLL", DPLL_ID_SPLL, &hsw_ddi_spll_funcs, 0 },
1683 { "LCPLL 810", DPLL_ID_LCPLL_810, &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON },
1684 { "LCPLL 1350", DPLL_ID_LCPLL_1350, &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON },
1685 { "LCPLL 2700", DPLL_ID_LCPLL_2700, &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON },
2edd6443
ACO		 1686 { NULL, -1, NULL, },
1687};
1688
f9476a6c
ACO		 1689static const struct intel_dpll_mgr hsw_pll_mgr = {
1690 .dpll_info = hsw_plls,
1691 .get_dpll = hsw_get_dpll,
1692};
1693
2edd6443 1694static const struct dpll_info skl_plls[] = {
a3c988ea
ACO		 1695 { "DPLL 0", DPLL_ID_SKL_DPLL0, &skl_ddi_dpll0_funcs, INTEL_DPLL_ALWAYS_ON },
1696 { "DPPL 1", DPLL_ID_SKL_DPLL1, &skl_ddi_pll_funcs, 0 },
1697 { "DPPL 2", DPLL_ID_SKL_DPLL2, &skl_ddi_pll_funcs, 0 },
1698 { "DPPL 3", DPLL_ID_SKL_DPLL3, &skl_ddi_pll_funcs, 0 },
2edd6443
ACO		 1699 { NULL, -1, NULL, },
1700};
1701
f9476a6c
ACO		 1702static const struct intel_dpll_mgr skl_pll_mgr = {
1703 .dpll_info = skl_plls,
1704 .get_dpll = skl_get_dpll,
1705};
1706
2edd6443 1707static const struct dpll_info bxt_plls[] = {
08250c4b
ID		 1708 { "PORT PLL A", DPLL_ID_SKL_DPLL0, &bxt_ddi_pll_funcs, 0 },
1709 { "PORT PLL B", DPLL_ID_SKL_DPLL1, &bxt_ddi_pll_funcs, 0 },
1710 { "PORT PLL C", DPLL_ID_SKL_DPLL2, &bxt_ddi_pll_funcs, 0 },
2edd6443
ACO		 1711 { NULL, -1, NULL, },
1712};
1713
f9476a6c
ACO		 1714static const struct intel_dpll_mgr bxt_pll_mgr = {
1715 .dpll_info = bxt_plls,
1716 .get_dpll = bxt_get_dpll,
1717};
1718
7abd4b35
ACO		 1719void intel_shared_dpll_init(struct drm_device *dev)
1720{
1721 struct drm_i915_private *dev_priv = dev->dev_private;
f9476a6c
ACO		 1722 const struct intel_dpll_mgr *dpll_mgr = NULL;
1723 const struct dpll_info *dpll_info;
2edd6443 1724 int i;
7abd4b35 1725
2edd6443 1726 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
f9476a6c 1727 dpll_mgr = &skl_pll_mgr;
08250c4b 1728 else if (IS_BROXTON(dev))
f9476a6c 1729 dpll_mgr = &bxt_pll_mgr;
2edd6443 1730 else if (HAS_DDI(dev))
f9476a6c 1731 dpll_mgr = &hsw_pll_mgr;
7abd4b35 1732 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
f9476a6c 1733 dpll_mgr = &pch_pll_mgr;
2edd6443 1734
f9476a6c 1735 if (!dpll_mgr) {
7abd4b35 1736 dev_priv->num_shared_dpll = 0;
2edd6443
ACO		 1737 return;
1738 }
1739
f9476a6c
ACO		 1740 dpll_info = dpll_mgr->dpll_info;
1741
2edd6443
ACO		 1742 for (i = 0; dpll_info[i].id >= 0; i++) {
1743 WARN_ON(i != dpll_info[i].id);
1744
1745 dev_priv->shared_dplls[i].id = dpll_info[i].id;
1746 dev_priv->shared_dplls[i].name = dpll_info[i].name;
1747 dev_priv->shared_dplls[i].funcs = *dpll_info[i].funcs;
9d16da65 1748 dev_priv->shared_dplls[i].flags = dpll_info[i].flags;
2edd6443
ACO		 1749 }
1750
f9476a6c 1751 dev_priv->dpll_mgr = dpll_mgr;
2edd6443 1752 dev_priv->num_shared_dpll = i;
7abd4b35
ACO		 1753
1754 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
2edd6443
ACO		 1755
1756 /* FIXME: Move this to a more suitable place */
1757 if (HAS_DDI(dev))
1758 intel_ddi_pll_init(dev);
7abd4b35 1759}
f9476a6c
ACO		 1760
1761struct intel_shared_dpll *
1762intel_get_shared_dpll(struct intel_crtc *crtc,
daedf20a
ACO		 1763 struct intel_crtc_state *crtc_state,
1764 struct intel_encoder *encoder)
f9476a6c
ACO		 1765{
1766 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1767 const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr;
1768
1769 if (WARN_ON(!dpll_mgr))
1770 return NULL;
1771
daedf20a 1772 return dpll_mgr->get_dpll(crtc, crtc_state, encoder);
f9476a6c 1773}
Linux kernel - Deliverables
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