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7abd4b35 ACO |
1 | /* |
2 | * Copyright © 2006-2016 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | #include "intel_drv.h" | |
25 | ||
26 | struct intel_shared_dpll * | |
8106ddbd ACO |
27 | intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv, |
28 | enum intel_dpll_id id) | |
7abd4b35 | 29 | { |
8106ddbd ACO |
30 | return &dev_priv->shared_dplls[id]; |
31 | } | |
7abd4b35 | 32 | |
8106ddbd ACO |
33 | enum intel_dpll_id |
34 | intel_get_shared_dpll_id(struct drm_i915_private *dev_priv, | |
35 | struct intel_shared_dpll *pll) | |
36 | { | |
37 | if (WARN_ON(pll < dev_priv->shared_dplls|| | |
38 | pll > &dev_priv->shared_dplls[dev_priv->num_shared_dpll])) | |
39 | return -1; | |
40 | ||
41 | return (enum intel_dpll_id) (pll - dev_priv->shared_dplls); | |
42 | } | |
43 | ||
44 | void | |
45 | intel_shared_dpll_config_get(struct intel_shared_dpll_config *config, | |
46 | struct intel_shared_dpll *pll, | |
47 | struct intel_crtc *crtc) | |
48 | { | |
49 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
50 | enum intel_dpll_id id = intel_get_shared_dpll_id(dev_priv, pll); | |
51 | ||
52 | config[id].crtc_mask |= 1 << crtc->pipe; | |
53 | } | |
54 | ||
55 | void | |
56 | intel_shared_dpll_config_put(struct intel_shared_dpll_config *config, | |
57 | struct intel_shared_dpll *pll, | |
58 | struct intel_crtc *crtc) | |
59 | { | |
60 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
61 | enum intel_dpll_id id = intel_get_shared_dpll_id(dev_priv, pll); | |
7abd4b35 | 62 | |
8106ddbd | 63 | config[id].crtc_mask &= ~(1 << crtc->pipe); |
7abd4b35 ACO |
64 | } |
65 | ||
66 | /* For ILK+ */ | |
67 | void assert_shared_dpll(struct drm_i915_private *dev_priv, | |
68 | struct intel_shared_dpll *pll, | |
69 | bool state) | |
70 | { | |
71 | bool cur_state; | |
72 | struct intel_dpll_hw_state hw_state; | |
73 | ||
74 | if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state))) | |
75 | return; | |
76 | ||
2edd6443 | 77 | cur_state = pll->funcs.get_hw_state(dev_priv, pll, &hw_state); |
7abd4b35 ACO |
78 | I915_STATE_WARN(cur_state != state, |
79 | "%s assertion failure (expected %s, current %s)\n", | |
80 | pll->name, onoff(state), onoff(cur_state)); | |
81 | } | |
82 | ||
83 | void intel_prepare_shared_dpll(struct intel_crtc *crtc) | |
84 | { | |
85 | struct drm_device *dev = crtc->base.dev; | |
86 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8106ddbd | 87 | struct intel_shared_dpll *pll = crtc->config->shared_dpll; |
7abd4b35 ACO |
88 | |
89 | if (WARN_ON(pll == NULL)) | |
90 | return; | |
91 | ||
92 | WARN_ON(!pll->config.crtc_mask); | |
93 | if (pll->active == 0) { | |
94 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
95 | WARN_ON(pll->on); | |
96 | assert_shared_dpll_disabled(dev_priv, pll); | |
97 | ||
2edd6443 | 98 | pll->funcs.mode_set(dev_priv, pll); |
7abd4b35 ACO |
99 | } |
100 | } | |
101 | ||
102 | /** | |
103 | * intel_enable_shared_dpll - enable PCH PLL | |
104 | * @dev_priv: i915 private structure | |
105 | * @pipe: pipe PLL to enable | |
106 | * | |
107 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
108 | * drives the transcoder clock. | |
109 | */ | |
110 | void intel_enable_shared_dpll(struct intel_crtc *crtc) | |
111 | { | |
112 | struct drm_device *dev = crtc->base.dev; | |
113 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8106ddbd | 114 | struct intel_shared_dpll *pll = crtc->config->shared_dpll; |
7abd4b35 ACO |
115 | |
116 | if (WARN_ON(pll == NULL)) | |
117 | return; | |
118 | ||
119 | if (WARN_ON(pll->config.crtc_mask == 0)) | |
120 | return; | |
121 | ||
122 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", | |
123 | pll->name, pll->active, pll->on, | |
124 | crtc->base.base.id); | |
125 | ||
126 | if (pll->active++) { | |
127 | WARN_ON(!pll->on); | |
128 | assert_shared_dpll_enabled(dev_priv, pll); | |
129 | return; | |
130 | } | |
131 | WARN_ON(pll->on); | |
132 | ||
133 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
134 | ||
135 | DRM_DEBUG_KMS("enabling %s\n", pll->name); | |
2edd6443 | 136 | pll->funcs.enable(dev_priv, pll); |
7abd4b35 ACO |
137 | pll->on = true; |
138 | } | |
139 | ||
140 | void intel_disable_shared_dpll(struct intel_crtc *crtc) | |
141 | { | |
142 | struct drm_device *dev = crtc->base.dev; | |
143 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8106ddbd | 144 | struct intel_shared_dpll *pll = crtc->config->shared_dpll; |
7abd4b35 ACO |
145 | |
146 | /* PCH only available on ILK+ */ | |
147 | if (INTEL_INFO(dev)->gen < 5) | |
148 | return; | |
149 | ||
150 | if (pll == NULL) | |
151 | return; | |
152 | ||
153 | if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base))))) | |
154 | return; | |
155 | ||
156 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", | |
157 | pll->name, pll->active, pll->on, | |
158 | crtc->base.base.id); | |
159 | ||
160 | if (WARN_ON(pll->active == 0)) { | |
161 | assert_shared_dpll_disabled(dev_priv, pll); | |
162 | return; | |
163 | } | |
164 | ||
165 | assert_shared_dpll_enabled(dev_priv, pll); | |
166 | WARN_ON(!pll->on); | |
167 | if (--pll->active) | |
168 | return; | |
169 | ||
170 | DRM_DEBUG_KMS("disabling %s\n", pll->name); | |
2edd6443 | 171 | pll->funcs.disable(dev_priv, pll); |
7abd4b35 ACO |
172 | pll->on = false; |
173 | ||
174 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
175 | } | |
176 | ||
a4780b77 ACO |
177 | static enum intel_dpll_id |
178 | ibx_get_fixed_dpll(struct intel_crtc *crtc, | |
179 | struct intel_crtc_state *crtc_state) | |
7abd4b35 | 180 | { |
a4780b77 | 181 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
7abd4b35 | 182 | struct intel_shared_dpll *pll; |
7abd4b35 | 183 | enum intel_dpll_id i; |
7abd4b35 | 184 | |
a4780b77 ACO |
185 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ |
186 | i = (enum intel_dpll_id) crtc->pipe; | |
187 | pll = &dev_priv->shared_dplls[i]; | |
7abd4b35 | 188 | |
a4780b77 ACO |
189 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
190 | crtc->base.base.id, pll->name); | |
7abd4b35 | 191 | |
a4780b77 ACO |
192 | return i; |
193 | } | |
7abd4b35 | 194 | |
a4780b77 ACO |
195 | static enum intel_dpll_id |
196 | bxt_get_fixed_dpll(struct intel_crtc *crtc, | |
197 | struct intel_crtc_state *crtc_state) | |
198 | { | |
199 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
200 | struct intel_encoder *encoder; | |
201 | struct intel_digital_port *intel_dig_port; | |
202 | struct intel_shared_dpll *pll; | |
203 | enum intel_dpll_id i; | |
7abd4b35 | 204 | |
a4780b77 ACO |
205 | /* PLL is attached to port in bxt */ |
206 | encoder = intel_ddi_get_crtc_new_encoder(crtc_state); | |
207 | if (WARN_ON(!encoder)) | |
208 | return DPLL_ID_PRIVATE; | |
7abd4b35 | 209 | |
a4780b77 ACO |
210 | intel_dig_port = enc_to_dig_port(&encoder->base); |
211 | /* 1:1 mapping between ports and PLLs */ | |
212 | i = (enum intel_dpll_id)intel_dig_port->port; | |
213 | pll = &dev_priv->shared_dplls[i]; | |
214 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", | |
215 | crtc->base.base.id, pll->name); | |
7abd4b35 | 216 | |
a4780b77 ACO |
217 | return i; |
218 | } | |
7abd4b35 | 219 | |
a4780b77 ACO |
220 | static enum intel_dpll_id |
221 | intel_find_shared_dpll(struct intel_crtc *crtc, | |
222 | struct intel_crtc_state *crtc_state) | |
223 | { | |
224 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
225 | struct intel_shared_dpll *pll; | |
226 | struct intel_shared_dpll_config *shared_dpll; | |
227 | enum intel_dpll_id i; | |
228 | int max = dev_priv->num_shared_dpll; | |
7abd4b35 | 229 | |
a4780b77 | 230 | if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv)) |
7abd4b35 ACO |
231 | /* Do not consider SPLL */ |
232 | max = 2; | |
233 | ||
a4780b77 ACO |
234 | shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); |
235 | ||
7abd4b35 ACO |
236 | for (i = 0; i < max; i++) { |
237 | pll = &dev_priv->shared_dplls[i]; | |
238 | ||
239 | /* Only want to check enabled timings first */ | |
240 | if (shared_dpll[i].crtc_mask == 0) | |
241 | continue; | |
242 | ||
243 | if (memcmp(&crtc_state->dpll_hw_state, | |
244 | &shared_dpll[i].hw_state, | |
245 | sizeof(crtc_state->dpll_hw_state)) == 0) { | |
246 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", | |
247 | crtc->base.base.id, pll->name, | |
248 | shared_dpll[i].crtc_mask, | |
249 | pll->active); | |
a4780b77 | 250 | return i; |
7abd4b35 ACO |
251 | } |
252 | } | |
253 | ||
254 | /* Ok no matching timings, maybe there's a free one? */ | |
255 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
256 | pll = &dev_priv->shared_dplls[i]; | |
257 | if (shared_dpll[i].crtc_mask == 0) { | |
258 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", | |
259 | crtc->base.base.id, pll->name); | |
a4780b77 | 260 | return i; |
7abd4b35 ACO |
261 | } |
262 | } | |
263 | ||
a4780b77 ACO |
264 | return DPLL_ID_PRIVATE; |
265 | } | |
266 | ||
267 | struct intel_shared_dpll * | |
268 | intel_get_shared_dpll(struct intel_crtc *crtc, | |
269 | struct intel_crtc_state *crtc_state) | |
270 | { | |
271 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
272 | struct intel_shared_dpll *pll; | |
273 | struct intel_shared_dpll_config *shared_dpll; | |
274 | enum intel_dpll_id i; | |
275 | ||
276 | shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); | |
277 | ||
278 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
279 | i = ibx_get_fixed_dpll(crtc, crtc_state); | |
280 | WARN_ON(shared_dpll[i].crtc_mask); | |
281 | } else if (IS_BROXTON(dev_priv->dev)) { | |
282 | i = bxt_get_fixed_dpll(crtc, crtc_state); | |
283 | WARN_ON(shared_dpll[i].crtc_mask); | |
284 | } else { | |
285 | i = intel_find_shared_dpll(crtc, crtc_state); | |
286 | } | |
287 | ||
288 | if (i < 0) | |
289 | return NULL; | |
290 | ||
291 | pll = &dev_priv->shared_dplls[i]; | |
7abd4b35 | 292 | |
7abd4b35 ACO |
293 | if (shared_dpll[i].crtc_mask == 0) |
294 | shared_dpll[i].hw_state = | |
295 | crtc_state->dpll_hw_state; | |
296 | ||
8106ddbd | 297 | crtc_state->shared_dpll = pll; |
7abd4b35 ACO |
298 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
299 | pipe_name(crtc->pipe)); | |
300 | ||
8106ddbd | 301 | intel_shared_dpll_config_get(shared_dpll, pll, crtc); |
7abd4b35 ACO |
302 | |
303 | return pll; | |
304 | } | |
305 | ||
306 | void intel_shared_dpll_commit(struct drm_atomic_state *state) | |
307 | { | |
308 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
309 | struct intel_shared_dpll_config *shared_dpll; | |
310 | struct intel_shared_dpll *pll; | |
311 | enum intel_dpll_id i; | |
312 | ||
313 | if (!to_intel_atomic_state(state)->dpll_set) | |
314 | return; | |
315 | ||
316 | shared_dpll = to_intel_atomic_state(state)->shared_dpll; | |
317 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
318 | pll = &dev_priv->shared_dplls[i]; | |
319 | pll->config = shared_dpll[i]; | |
320 | } | |
321 | } | |
322 | ||
323 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, | |
324 | struct intel_shared_dpll *pll, | |
325 | struct intel_dpll_hw_state *hw_state) | |
326 | { | |
327 | uint32_t val; | |
328 | ||
329 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) | |
330 | return false; | |
331 | ||
332 | val = I915_READ(PCH_DPLL(pll->id)); | |
333 | hw_state->dpll = val; | |
334 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
335 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
336 | ||
337 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
338 | ||
339 | return val & DPLL_VCO_ENABLE; | |
340 | } | |
341 | ||
342 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, | |
343 | struct intel_shared_dpll *pll) | |
344 | { | |
345 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); | |
346 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
347 | } | |
348 | ||
349 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) | |
350 | { | |
351 | u32 val; | |
352 | bool enabled; | |
353 | ||
354 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); | |
355 | ||
356 | val = I915_READ(PCH_DREF_CONTROL); | |
357 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
358 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
359 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
360 | } | |
361 | ||
362 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, | |
363 | struct intel_shared_dpll *pll) | |
364 | { | |
365 | /* PCH refclock must be enabled first */ | |
366 | ibx_assert_pch_refclk_enabled(dev_priv); | |
367 | ||
368 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); | |
369 | ||
370 | /* Wait for the clocks to stabilize. */ | |
371 | POSTING_READ(PCH_DPLL(pll->id)); | |
372 | udelay(150); | |
373 | ||
374 | /* The pixel multiplier can only be updated once the | |
375 | * DPLL is enabled and the clocks are stable. | |
376 | * | |
377 | * So write it again. | |
378 | */ | |
379 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); | |
380 | POSTING_READ(PCH_DPLL(pll->id)); | |
381 | udelay(200); | |
382 | } | |
383 | ||
384 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
385 | struct intel_shared_dpll *pll) | |
386 | { | |
387 | struct drm_device *dev = dev_priv->dev; | |
388 | struct intel_crtc *crtc; | |
389 | ||
390 | /* Make sure no transcoder isn't still depending on us. */ | |
391 | for_each_intel_crtc(dev, crtc) { | |
8106ddbd | 392 | if (crtc->config->shared_dpll == pll) |
7abd4b35 ACO |
393 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); |
394 | } | |
395 | ||
396 | I915_WRITE(PCH_DPLL(pll->id), 0); | |
397 | POSTING_READ(PCH_DPLL(pll->id)); | |
398 | udelay(200); | |
399 | } | |
400 | ||
2edd6443 ACO |
401 | static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = { |
402 | .mode_set = ibx_pch_dpll_mode_set, | |
403 | .enable = ibx_pch_dpll_enable, | |
404 | .disable = ibx_pch_dpll_disable, | |
405 | .get_hw_state = ibx_pch_dpll_get_hw_state, | |
7abd4b35 ACO |
406 | }; |
407 | ||
55be2f08 ACO |
408 | static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv, |
409 | struct intel_shared_dpll *pll) | |
410 | { | |
411 | I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll); | |
412 | POSTING_READ(WRPLL_CTL(pll->id)); | |
413 | udelay(20); | |
414 | } | |
415 | ||
416 | static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv, | |
417 | struct intel_shared_dpll *pll) | |
418 | { | |
419 | I915_WRITE(SPLL_CTL, pll->config.hw_state.spll); | |
420 | POSTING_READ(SPLL_CTL); | |
421 | udelay(20); | |
422 | } | |
423 | ||
424 | static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv, | |
425 | struct intel_shared_dpll *pll) | |
426 | { | |
427 | uint32_t val; | |
428 | ||
429 | val = I915_READ(WRPLL_CTL(pll->id)); | |
430 | I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE); | |
431 | POSTING_READ(WRPLL_CTL(pll->id)); | |
432 | } | |
433 | ||
434 | static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv, | |
435 | struct intel_shared_dpll *pll) | |
436 | { | |
437 | uint32_t val; | |
438 | ||
439 | val = I915_READ(SPLL_CTL); | |
440 | I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); | |
441 | POSTING_READ(SPLL_CTL); | |
442 | } | |
443 | ||
444 | static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv, | |
445 | struct intel_shared_dpll *pll, | |
446 | struct intel_dpll_hw_state *hw_state) | |
447 | { | |
448 | uint32_t val; | |
449 | ||
450 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) | |
451 | return false; | |
452 | ||
453 | val = I915_READ(WRPLL_CTL(pll->id)); | |
454 | hw_state->wrpll = val; | |
455 | ||
456 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
457 | ||
458 | return val & WRPLL_PLL_ENABLE; | |
459 | } | |
460 | ||
461 | static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv, | |
462 | struct intel_shared_dpll *pll, | |
463 | struct intel_dpll_hw_state *hw_state) | |
464 | { | |
465 | uint32_t val; | |
466 | ||
467 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) | |
468 | return false; | |
469 | ||
470 | val = I915_READ(SPLL_CTL); | |
471 | hw_state->spll = val; | |
472 | ||
473 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
474 | ||
475 | return val & SPLL_PLL_ENABLE; | |
476 | } | |
477 | ||
478 | ||
2edd6443 ACO |
479 | static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = { |
480 | .enable = hsw_ddi_wrpll_enable, | |
481 | .disable = hsw_ddi_wrpll_disable, | |
482 | .get_hw_state = hsw_ddi_wrpll_get_hw_state, | |
55be2f08 ACO |
483 | }; |
484 | ||
2edd6443 ACO |
485 | static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = { |
486 | .enable = hsw_ddi_spll_enable, | |
487 | .disable = hsw_ddi_spll_disable, | |
488 | .get_hw_state = hsw_ddi_spll_get_hw_state, | |
55be2f08 ACO |
489 | }; |
490 | ||
491 | struct skl_dpll_regs { | |
492 | i915_reg_t ctl, cfgcr1, cfgcr2; | |
493 | }; | |
494 | ||
495 | /* this array is indexed by the *shared* pll id */ | |
496 | static const struct skl_dpll_regs skl_dpll_regs[3] = { | |
497 | { | |
498 | /* DPLL 1 */ | |
499 | .ctl = LCPLL2_CTL, | |
500 | .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1), | |
501 | .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1), | |
502 | }, | |
503 | { | |
504 | /* DPLL 2 */ | |
505 | .ctl = WRPLL_CTL(0), | |
506 | .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2), | |
507 | .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2), | |
508 | }, | |
509 | { | |
510 | /* DPLL 3 */ | |
511 | .ctl = WRPLL_CTL(1), | |
512 | .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3), | |
513 | .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3), | |
514 | }, | |
515 | }; | |
516 | ||
517 | static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv, | |
518 | struct intel_shared_dpll *pll) | |
519 | { | |
520 | uint32_t val; | |
521 | unsigned int dpll; | |
522 | const struct skl_dpll_regs *regs = skl_dpll_regs; | |
523 | ||
524 | /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ | |
525 | dpll = pll->id + 1; | |
526 | ||
527 | val = I915_READ(DPLL_CTRL1); | |
528 | ||
529 | val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) | | |
530 | DPLL_CTRL1_LINK_RATE_MASK(dpll)); | |
531 | val |= pll->config.hw_state.ctrl1 << (dpll * 6); | |
532 | ||
533 | I915_WRITE(DPLL_CTRL1, val); | |
534 | POSTING_READ(DPLL_CTRL1); | |
535 | ||
536 | I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1); | |
537 | I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2); | |
538 | POSTING_READ(regs[pll->id].cfgcr1); | |
539 | POSTING_READ(regs[pll->id].cfgcr2); | |
540 | ||
541 | /* the enable bit is always bit 31 */ | |
542 | I915_WRITE(regs[pll->id].ctl, | |
543 | I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE); | |
544 | ||
545 | if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5)) | |
546 | DRM_ERROR("DPLL %d not locked\n", dpll); | |
547 | } | |
548 | ||
549 | static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv, | |
550 | struct intel_shared_dpll *pll) | |
551 | { | |
552 | const struct skl_dpll_regs *regs = skl_dpll_regs; | |
553 | ||
554 | /* the enable bit is always bit 31 */ | |
555 | I915_WRITE(regs[pll->id].ctl, | |
556 | I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE); | |
557 | POSTING_READ(regs[pll->id].ctl); | |
558 | } | |
559 | ||
560 | static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, | |
561 | struct intel_shared_dpll *pll, | |
562 | struct intel_dpll_hw_state *hw_state) | |
563 | { | |
564 | uint32_t val; | |
565 | unsigned int dpll; | |
566 | const struct skl_dpll_regs *regs = skl_dpll_regs; | |
567 | bool ret; | |
568 | ||
569 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) | |
570 | return false; | |
571 | ||
572 | ret = false; | |
573 | ||
574 | /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ | |
575 | dpll = pll->id + 1; | |
576 | ||
577 | val = I915_READ(regs[pll->id].ctl); | |
578 | if (!(val & LCPLL_PLL_ENABLE)) | |
579 | goto out; | |
580 | ||
581 | val = I915_READ(DPLL_CTRL1); | |
582 | hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f; | |
583 | ||
584 | /* avoid reading back stale values if HDMI mode is not enabled */ | |
585 | if (val & DPLL_CTRL1_HDMI_MODE(dpll)) { | |
586 | hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1); | |
587 | hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2); | |
588 | } | |
589 | ret = true; | |
590 | ||
591 | out: | |
592 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
593 | ||
594 | return ret; | |
595 | } | |
596 | ||
2edd6443 ACO |
597 | static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = { |
598 | .enable = skl_ddi_pll_enable, | |
599 | .disable = skl_ddi_pll_disable, | |
600 | .get_hw_state = skl_ddi_pll_get_hw_state, | |
55be2f08 ACO |
601 | }; |
602 | ||
603 | static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv, | |
604 | struct intel_shared_dpll *pll) | |
605 | { | |
606 | uint32_t temp; | |
607 | enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ | |
608 | ||
609 | temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); | |
610 | temp &= ~PORT_PLL_REF_SEL; | |
611 | /* Non-SSC reference */ | |
612 | I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); | |
613 | ||
614 | /* Disable 10 bit clock */ | |
615 | temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); | |
616 | temp &= ~PORT_PLL_10BIT_CLK_ENABLE; | |
617 | I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); | |
618 | ||
619 | /* Write P1 & P2 */ | |
620 | temp = I915_READ(BXT_PORT_PLL_EBB_0(port)); | |
621 | temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK); | |
622 | temp |= pll->config.hw_state.ebb0; | |
623 | I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp); | |
624 | ||
625 | /* Write M2 integer */ | |
626 | temp = I915_READ(BXT_PORT_PLL(port, 0)); | |
627 | temp &= ~PORT_PLL_M2_MASK; | |
628 | temp |= pll->config.hw_state.pll0; | |
629 | I915_WRITE(BXT_PORT_PLL(port, 0), temp); | |
630 | ||
631 | /* Write N */ | |
632 | temp = I915_READ(BXT_PORT_PLL(port, 1)); | |
633 | temp &= ~PORT_PLL_N_MASK; | |
634 | temp |= pll->config.hw_state.pll1; | |
635 | I915_WRITE(BXT_PORT_PLL(port, 1), temp); | |
636 | ||
637 | /* Write M2 fraction */ | |
638 | temp = I915_READ(BXT_PORT_PLL(port, 2)); | |
639 | temp &= ~PORT_PLL_M2_FRAC_MASK; | |
640 | temp |= pll->config.hw_state.pll2; | |
641 | I915_WRITE(BXT_PORT_PLL(port, 2), temp); | |
642 | ||
643 | /* Write M2 fraction enable */ | |
644 | temp = I915_READ(BXT_PORT_PLL(port, 3)); | |
645 | temp &= ~PORT_PLL_M2_FRAC_ENABLE; | |
646 | temp |= pll->config.hw_state.pll3; | |
647 | I915_WRITE(BXT_PORT_PLL(port, 3), temp); | |
648 | ||
649 | /* Write coeff */ | |
650 | temp = I915_READ(BXT_PORT_PLL(port, 6)); | |
651 | temp &= ~PORT_PLL_PROP_COEFF_MASK; | |
652 | temp &= ~PORT_PLL_INT_COEFF_MASK; | |
653 | temp &= ~PORT_PLL_GAIN_CTL_MASK; | |
654 | temp |= pll->config.hw_state.pll6; | |
655 | I915_WRITE(BXT_PORT_PLL(port, 6), temp); | |
656 | ||
657 | /* Write calibration val */ | |
658 | temp = I915_READ(BXT_PORT_PLL(port, 8)); | |
659 | temp &= ~PORT_PLL_TARGET_CNT_MASK; | |
660 | temp |= pll->config.hw_state.pll8; | |
661 | I915_WRITE(BXT_PORT_PLL(port, 8), temp); | |
662 | ||
663 | temp = I915_READ(BXT_PORT_PLL(port, 9)); | |
664 | temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK; | |
665 | temp |= pll->config.hw_state.pll9; | |
666 | I915_WRITE(BXT_PORT_PLL(port, 9), temp); | |
667 | ||
668 | temp = I915_READ(BXT_PORT_PLL(port, 10)); | |
669 | temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H; | |
670 | temp &= ~PORT_PLL_DCO_AMP_MASK; | |
671 | temp |= pll->config.hw_state.pll10; | |
672 | I915_WRITE(BXT_PORT_PLL(port, 10), temp); | |
673 | ||
674 | /* Recalibrate with new settings */ | |
675 | temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); | |
676 | temp |= PORT_PLL_RECALIBRATE; | |
677 | I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); | |
678 | temp &= ~PORT_PLL_10BIT_CLK_ENABLE; | |
679 | temp |= pll->config.hw_state.ebb4; | |
680 | I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); | |
681 | ||
682 | /* Enable PLL */ | |
683 | temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); | |
684 | temp |= PORT_PLL_ENABLE; | |
685 | I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); | |
686 | POSTING_READ(BXT_PORT_PLL_ENABLE(port)); | |
687 | ||
688 | if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & | |
689 | PORT_PLL_LOCK), 200)) | |
690 | DRM_ERROR("PLL %d not locked\n", port); | |
691 | ||
692 | /* | |
693 | * While we write to the group register to program all lanes at once we | |
694 | * can read only lane registers and we pick lanes 0/1 for that. | |
695 | */ | |
696 | temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); | |
697 | temp &= ~LANE_STAGGER_MASK; | |
698 | temp &= ~LANESTAGGER_STRAP_OVRD; | |
699 | temp |= pll->config.hw_state.pcsdw12; | |
700 | I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp); | |
701 | } | |
702 | ||
703 | static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv, | |
704 | struct intel_shared_dpll *pll) | |
705 | { | |
706 | enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ | |
707 | uint32_t temp; | |
708 | ||
709 | temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); | |
710 | temp &= ~PORT_PLL_ENABLE; | |
711 | I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); | |
712 | POSTING_READ(BXT_PORT_PLL_ENABLE(port)); | |
713 | } | |
714 | ||
715 | static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, | |
716 | struct intel_shared_dpll *pll, | |
717 | struct intel_dpll_hw_state *hw_state) | |
718 | { | |
719 | enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ | |
720 | uint32_t val; | |
721 | bool ret; | |
722 | ||
723 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) | |
724 | return false; | |
725 | ||
726 | ret = false; | |
727 | ||
728 | val = I915_READ(BXT_PORT_PLL_ENABLE(port)); | |
729 | if (!(val & PORT_PLL_ENABLE)) | |
730 | goto out; | |
731 | ||
732 | hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port)); | |
733 | hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK; | |
734 | ||
735 | hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port)); | |
736 | hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE; | |
737 | ||
738 | hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0)); | |
739 | hw_state->pll0 &= PORT_PLL_M2_MASK; | |
740 | ||
741 | hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1)); | |
742 | hw_state->pll1 &= PORT_PLL_N_MASK; | |
743 | ||
744 | hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2)); | |
745 | hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK; | |
746 | ||
747 | hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3)); | |
748 | hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE; | |
749 | ||
750 | hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6)); | |
751 | hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK | | |
752 | PORT_PLL_INT_COEFF_MASK | | |
753 | PORT_PLL_GAIN_CTL_MASK; | |
754 | ||
755 | hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8)); | |
756 | hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK; | |
757 | ||
758 | hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9)); | |
759 | hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK; | |
760 | ||
761 | hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10)); | |
762 | hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H | | |
763 | PORT_PLL_DCO_AMP_MASK; | |
764 | ||
765 | /* | |
766 | * While we write to the group register to program all lanes at once we | |
767 | * can read only lane registers. We configure all lanes the same way, so | |
768 | * here just read out lanes 0/1 and output a note if lanes 2/3 differ. | |
769 | */ | |
770 | hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); | |
771 | if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12) | |
772 | DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n", | |
773 | hw_state->pcsdw12, | |
774 | I915_READ(BXT_PORT_PCS_DW12_LN23(port))); | |
775 | hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD; | |
776 | ||
777 | ret = true; | |
778 | ||
779 | out: | |
780 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
781 | ||
782 | return ret; | |
783 | } | |
784 | ||
2edd6443 ACO |
785 | static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = { |
786 | .enable = bxt_ddi_pll_enable, | |
787 | .disable = bxt_ddi_pll_disable, | |
788 | .get_hw_state = bxt_ddi_pll_get_hw_state, | |
789 | }; | |
55be2f08 ACO |
790 | |
791 | static void intel_ddi_pll_init(struct drm_device *dev) | |
792 | { | |
793 | struct drm_i915_private *dev_priv = dev->dev_private; | |
794 | uint32_t val = I915_READ(LCPLL_CTL); | |
795 | ||
55be2f08 ACO |
796 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
797 | int cdclk_freq; | |
798 | ||
799 | cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
800 | dev_priv->skl_boot_cdclk = cdclk_freq; | |
801 | if (skl_sanitize_cdclk(dev_priv)) | |
802 | DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n"); | |
803 | if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) | |
804 | DRM_ERROR("LCPLL1 is disabled\n"); | |
805 | } else if (IS_BROXTON(dev)) { | |
806 | broxton_init_cdclk(dev); | |
807 | broxton_ddi_phy_init(dev); | |
808 | } else { | |
809 | /* | |
810 | * The LCPLL register should be turned on by the BIOS. For now | |
811 | * let's just check its state and print errors in case | |
812 | * something is wrong. Don't even try to turn it on. | |
813 | */ | |
814 | ||
815 | if (val & LCPLL_CD_SOURCE_FCLK) | |
816 | DRM_ERROR("CDCLK source is not LCPLL\n"); | |
817 | ||
818 | if (val & LCPLL_PLL_DISABLE) | |
819 | DRM_ERROR("LCPLL is disabled\n"); | |
820 | } | |
821 | } | |
822 | ||
2edd6443 ACO |
823 | struct dpll_info { |
824 | const char *name; | |
825 | const int id; | |
826 | const struct intel_shared_dpll_funcs *funcs; | |
827 | }; | |
828 | ||
829 | static const struct dpll_info pch_plls[] = { | |
830 | { "PCH DPLL A", DPLL_ID_PCH_PLL_A, &ibx_pch_dpll_funcs }, | |
831 | { "PCH DPLL B", DPLL_ID_PCH_PLL_B, &ibx_pch_dpll_funcs }, | |
832 | { NULL, -1, NULL }, | |
833 | }; | |
834 | ||
835 | static const struct dpll_info hsw_plls[] = { | |
836 | { "WRPLL 1", DPLL_ID_WRPLL1, &hsw_ddi_wrpll_funcs }, | |
837 | { "WRPLL 2", DPLL_ID_WRPLL2, &hsw_ddi_wrpll_funcs }, | |
838 | { "SPLL", DPLL_ID_SPLL, &hsw_ddi_spll_funcs }, | |
839 | { NULL, -1, NULL, }, | |
840 | }; | |
841 | ||
842 | static const struct dpll_info skl_plls[] = { | |
843 | { "DPPL 1", DPLL_ID_SKL_DPLL1, &skl_ddi_pll_funcs }, | |
844 | { "DPPL 2", DPLL_ID_SKL_DPLL2, &skl_ddi_pll_funcs }, | |
845 | { "DPPL 3", DPLL_ID_SKL_DPLL3, &skl_ddi_pll_funcs }, | |
846 | { NULL, -1, NULL, }, | |
847 | }; | |
848 | ||
849 | static const struct dpll_info bxt_plls[] = { | |
850 | { "PORT PLL A", 0, &bxt_ddi_pll_funcs }, | |
851 | { "PORT PLL B", 1, &bxt_ddi_pll_funcs }, | |
852 | { "PORT PLL C", 2, &bxt_ddi_pll_funcs }, | |
853 | { NULL, -1, NULL, }, | |
854 | }; | |
855 | ||
7abd4b35 ACO |
856 | void intel_shared_dpll_init(struct drm_device *dev) |
857 | { | |
858 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2edd6443 ACO |
859 | const struct dpll_info *dpll_info = NULL; |
860 | int i; | |
7abd4b35 | 861 | |
2edd6443 ACO |
862 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
863 | dpll_info = skl_plls; | |
864 | else if IS_BROXTON(dev) | |
865 | dpll_info = bxt_plls; | |
866 | else if (HAS_DDI(dev)) | |
867 | dpll_info = hsw_plls; | |
7abd4b35 | 868 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
2edd6443 ACO |
869 | dpll_info = pch_plls; |
870 | ||
871 | if (!dpll_info) { | |
7abd4b35 | 872 | dev_priv->num_shared_dpll = 0; |
2edd6443 ACO |
873 | return; |
874 | } | |
875 | ||
876 | for (i = 0; dpll_info[i].id >= 0; i++) { | |
877 | WARN_ON(i != dpll_info[i].id); | |
878 | ||
879 | dev_priv->shared_dplls[i].id = dpll_info[i].id; | |
880 | dev_priv->shared_dplls[i].name = dpll_info[i].name; | |
881 | dev_priv->shared_dplls[i].funcs = *dpll_info[i].funcs; | |
882 | } | |
883 | ||
884 | dev_priv->num_shared_dpll = i; | |
7abd4b35 ACO |
885 | |
886 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
2edd6443 ACO |
887 | |
888 | /* FIXME: Move this to a more suitable place */ | |
889 | if (HAS_DDI(dev)) | |
890 | intel_ddi_pll_init(dev); | |
7abd4b35 | 891 | } |