[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dpll_mgr.h

/*
 * Copyright © 2012-2016 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 */

#ifndef _INTEL_DPLL_MGR_H_
#define _INTEL_DPLL_MGR_H_

/*FIXME: Move this to a more appropriate place. */
#define abs_diff(a, b) ({			\
	typeof(a) __a = (a);			\
	typeof(b) __b = (b);			\
	(void) (&__a == &__b);			\
	__a > __b ? (__a - __b) : (__b - __a); })

struct drm_i915_private;
struct intel_crtc;
struct intel_crtc_state;
struct intel_encoder;

struct intel_shared_dpll;
struct intel_dpll_mgr;

enum intel_dpll_id {
	DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
	/* real shared dpll ids must be >= 0 */
	DPLL_ID_PCH_PLL_A = 0,
	DPLL_ID_PCH_PLL_B = 1,
	/* hsw/bdw */
	DPLL_ID_WRPLL1 = 0,
	DPLL_ID_WRPLL2 = 1,
	DPLL_ID_SPLL = 2,
	DPLL_ID_LCPLL_810 = 3,
	DPLL_ID_LCPLL_1350 = 4,
	DPLL_ID_LCPLL_2700 = 5,

	/* skl */
	DPLL_ID_SKL_DPLL1 = 0,
	DPLL_ID_SKL_DPLL2 = 1,
	DPLL_ID_SKL_DPLL3 = 2,
};
#define I915_NUM_PLLS 6

/** Inform the state checker that the DPLL is kept enabled even if not
 * in use by any crtc.
 */
#define INTEL_DPLL_ALWAYS_ON	(1 << 0)

struct intel_dpll_hw_state {
	/* i9xx, pch plls */
	uint32_t dpll;
	uint32_t dpll_md;
	uint32_t fp0;
	uint32_t fp1;

	/* hsw, bdw */
	uint32_t wrpll;
	uint32_t spll;

	/* skl */
	/*
	 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
	 * lower part of ctrl1 and they get shifted into position when writing
	 * the register.  This allows us to easily compare the state to share
	 * the DPLL.
	 */
	uint32_t ctrl1;
	/* HDMI only, 0 when used for DP */
	uint32_t cfgcr1, cfgcr2;

	/* bxt */
	uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
		 pcsdw12;
};

struct intel_shared_dpll_config {
	unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
	struct intel_dpll_hw_state hw_state;
};

struct intel_shared_dpll_funcs {
	/* The mode_set hook is optional and should be used together with the
	 * intel_prepare_shared_dpll function. */
	void (*mode_set)(struct drm_i915_private *dev_priv,
			 struct intel_shared_dpll *pll);
	void (*enable)(struct drm_i915_private *dev_priv,
		       struct intel_shared_dpll *pll);
	void (*disable)(struct drm_i915_private *dev_priv,
			struct intel_shared_dpll *pll);
	bool (*get_hw_state)(struct drm_i915_private *dev_priv,
			     struct intel_shared_dpll *pll,
			     struct intel_dpll_hw_state *hw_state);
};

struct intel_shared_dpll {
	struct intel_shared_dpll_config config;

	int active; /* count of number of active CRTCs (i.e. DPMS on) */
	bool on; /* is the PLL actually active? Disabled during modeset */
	const char *name;
	/* should match the index in the dev_priv->shared_dplls array */
	enum intel_dpll_id id;

	struct intel_shared_dpll_funcs funcs;

	uint32_t flags;
};

#define SKL_DPLL0 0
#define SKL_DPLL1 1
#define SKL_DPLL2 2
#define SKL_DPLL3 3

/* shared dpll functions */
struct intel_shared_dpll *
intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
			    enum intel_dpll_id id);
enum intel_dpll_id
intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
			 struct intel_shared_dpll *pll);
void
intel_shared_dpll_config_get(struct intel_shared_dpll_config *config,
			     struct intel_shared_dpll *pll,
			     struct intel_crtc *crtc);
void
intel_shared_dpll_config_put(struct intel_shared_dpll_config *config,
			     struct intel_shared_dpll *pll,
			     struct intel_crtc *crtc);
void assert_shared_dpll(struct drm_i915_private *dev_priv,
			struct intel_shared_dpll *pll,
			bool state);
#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
						struct intel_crtc_state *state,
						struct intel_encoder *encoder);
void intel_prepare_shared_dpll(struct intel_crtc *crtc);
void intel_enable_shared_dpll(struct intel_crtc *crtc);
void intel_disable_shared_dpll(struct intel_crtc *crtc);
void intel_shared_dpll_commit(struct drm_atomic_state *state);
void intel_shared_dpll_init(struct drm_device *dev);


#endif /* _INTEL_DPLL_MGR_H_ */
Commit	Line	Data
ac7f11c6 ACO	1	/*
	2	* Copyright © 2012-2016 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	*/
	24
	25	#ifndef _INTEL_DPLL_MGR_H_
	26	#define _INTEL_DPLL_MGR_H_
	27
daedf20a ACO	28	/FIXME: Move this to a more appropriate place. /
	29	#define abs_diff(a, b) ({ \
	30	typeof(a) __a = (a); \
	31	typeof(b) __b = (b); \
	32	(void) (&__a == &__b); \
	33	__a > __b ? (__a - __b) : (__b - __a); })
	34
ac7f11c6	35	struct drm_i915_private;
c2a9fcd6 ACO	36	struct intel_crtc;
c2a9fcd6 ACO	37	struct intel_crtc_state;
daedf20a	38	struct intel_encoder;
ac7f11c6	39
daedf20a	40	struct intel_shared_dpll;
f9476a6c ACO	41	struct intel_dpll_mgr;
f9476a6c ACO	42
ac7f11c6 ACO	43	enum intel_dpll_id {
	44	DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
	45	/* real shared dpll ids must be >= 0 */
	46	DPLL_ID_PCH_PLL_A = 0,
	47	DPLL_ID_PCH_PLL_B = 1,
	48	/* hsw/bdw */
	49	DPLL_ID_WRPLL1 = 0,
	50	DPLL_ID_WRPLL2 = 1,
	51	DPLL_ID_SPLL = 2,
9d16da65 ACO	52	DPLL_ID_LCPLL_810 = 3,
	53	DPLL_ID_LCPLL_1350 = 4,
	54	DPLL_ID_LCPLL_2700 = 5,
ac7f11c6 ACO	55
	56	/* skl */
	57	DPLL_ID_SKL_DPLL1 = 0,
	58	DPLL_ID_SKL_DPLL2 = 1,
	59	DPLL_ID_SKL_DPLL3 = 2,
	60	};
9d16da65 ACO	61	#define I915_NUM_PLLS 6
	62
	63	/** Inform the state checker that the DPLL is kept enabled even if not
	64	* in use by any crtc.
	65	*/
	66	#define INTEL_DPLL_ALWAYS_ON (1 << 0)
ac7f11c6 ACO	67
	68	struct intel_dpll_hw_state {
	69	/* i9xx, pch plls */
	70	uint32_t dpll;
	71	uint32_t dpll_md;
	72	uint32_t fp0;
	73	uint32_t fp1;
	74
	75	/* hsw, bdw */
	76	uint32_t wrpll;
	77	uint32_t spll;
	78
	79	/* skl */
	80	/*
	81	* DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
	82	* lower part of ctrl1 and they get shifted into position when writing
	83	* the register. This allows us to easily compare the state to share
	84	* the DPLL.
	85	*/
	86	uint32_t ctrl1;
	87	/* HDMI only, 0 when used for DP */
	88	uint32_t cfgcr1, cfgcr2;
	89
	90	/* bxt */
	91	uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
	92	pcsdw12;
	93	};
	94
	95	struct intel_shared_dpll_config {
	96	unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
	97	struct intel_dpll_hw_state hw_state;
	98	};
	99
2edd6443	100	struct intel_shared_dpll_funcs {
ac7f11c6 ACO	101	/* The mode_set hook is optional and should be used together with the
	102	* intel_prepare_shared_dpll function. */
	103	void (mode_set)(struct drm_i915_private dev_priv,
	104	struct intel_shared_dpll *pll);
	105	void (enable)(struct drm_i915_private dev_priv,
	106	struct intel_shared_dpll *pll);
	107	void (disable)(struct drm_i915_private dev_priv,
	108	struct intel_shared_dpll *pll);
	109	bool (get_hw_state)(struct drm_i915_private dev_priv,
	110	struct intel_shared_dpll *pll,
	111	struct intel_dpll_hw_state *hw_state);
	112	};
	113
2edd6443 ACO	114	struct intel_shared_dpll {
	115	struct intel_shared_dpll_config config;
	116
	117	int active; /* count of number of active CRTCs (i.e. DPMS on) */
	118	bool on; /* is the PLL actually active? Disabled during modeset */
	119	const char *name;
	120	/* should match the index in the dev_priv->shared_dplls array */
	121	enum intel_dpll_id id;
	122
	123	struct intel_shared_dpll_funcs funcs;
9d16da65 ACO	124
9d16da65 ACO	125	uint32_t flags;
2edd6443 ACO	126	};
2edd6443 ACO	127
ac7f11c6 ACO	128	#define SKL_DPLL0 0
	129	#define SKL_DPLL1 1
	130	#define SKL_DPLL2 2
	131	#define SKL_DPLL3 3
	132
c2a9fcd6 ACO	133	/* shared dpll functions */
	134	struct intel_shared_dpll *
	135	intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
	136	enum intel_dpll_id id);
	137	enum intel_dpll_id
	138	intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
	139	struct intel_shared_dpll *pll);
	140	void
	141	intel_shared_dpll_config_get(struct intel_shared_dpll_config *config,
	142	struct intel_shared_dpll *pll,
	143	struct intel_crtc *crtc);
	144	void
	145	intel_shared_dpll_config_put(struct intel_shared_dpll_config *config,
	146	struct intel_shared_dpll *pll,
	147	struct intel_crtc *crtc);
	148	void assert_shared_dpll(struct drm_i915_private *dev_priv,
	149	struct intel_shared_dpll *pll,
	150	bool state);
	151	#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
	152	#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
	153	struct intel_shared_dpll intel_get_shared_dpll(struct intel_crtc crtc,
daedf20a ACO	154	struct intel_crtc_state *state,
daedf20a ACO	155	struct intel_encoder *encoder);
c2a9fcd6 ACO	156	void intel_prepare_shared_dpll(struct intel_crtc *crtc);
	157	void intel_enable_shared_dpll(struct intel_crtc *crtc);
	158	void intel_disable_shared_dpll(struct intel_crtc *crtc);
	159	void intel_shared_dpll_commit(struct drm_atomic_state *state);
	160	void intel_shared_dpll_init(struct drm_device *dev);
	161
ac7f11c6 ACO	162
ac7f11c6 ACO	163	#endif /* _INTEL_DPLL_MGR_H_ */