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drm/i915: stage modeset output changes
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_drv.h
CommitLineData
79e53945
JB		 1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25#ifndef __INTEL_DRV_H__
26#define __INTEL_DRV_H__
27
28#include <linux/i2c.h>
8ea30864 29#include "i915_drm.h"
80824003 30#include "i915_drv.h"
79e53945 31#include "drm_crtc.h"
79e53945 32#include "drm_crtc_helper.h"
37811fcc 33#include "drm_fb_helper.h"
54d63ca6 34#include "drm_dp_helper.h"
913d8d11 35
481b6af3 36#define _wait_for(COND, MS, W) ({ \
913d8d11
CW		 37 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
38 int ret__ = 0; \
0206e353 39 while (!(COND)) { \
913d8d11
CW		 40 if (time_after(jiffies, timeout__)) { \
41 ret__ = -ETIMEDOUT; \
42 break; \
43 } \
cc1f7194 44 if (W && drm_can_sleep()) msleep(W); \
913d8d11
CW		 45 } \
46 ret__; \
47})
48
57f350b6 49#define wait_for_atomic_us(COND, US) ({ \
bcf9dcc1
CW		 50 unsigned long timeout__ = jiffies + usecs_to_jiffies(US); \
51 int ret__ = 0; \
52 while (!(COND)) { \
53 if (time_after(jiffies, timeout__)) { \
54 ret__ = -ETIMEDOUT; \
55 break; \
56 } \
57 cpu_relax(); \
58 } \
59 ret__; \
57f350b6
JB		 60})
61
481b6af3
CW		 62#define wait_for(COND, MS) _wait_for(COND, MS, 1)
63#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
64
021357ac
CW		 65#define KHz(x) (1000*x)
66#define MHz(x) KHz(1000*x)
67
79e53945
JB		 68/*
69 * Display related stuff
70 */
71
72/* store information about an Ixxx DVO */
73/* The i830->i865 use multiple DVOs with multiple i2cs */
74/* the i915, i945 have a single sDVO i2c bus - which is different */
75#define MAX_OUTPUTS 6
76/* maximum connectors per crtcs in the mode set */
77#define INTELFB_CONN_LIMIT 4
78
79#define INTEL_I2C_BUS_DVO 1
80#define INTEL_I2C_BUS_SDVO 2
81
82/* these are outputs from the chip - integrated only
83 external chips are via DVO or SDVO output */
84#define INTEL_OUTPUT_UNUSED 0
85#define INTEL_OUTPUT_ANALOG 1
86#define INTEL_OUTPUT_DVO 2
87#define INTEL_OUTPUT_SDVO 3
88#define INTEL_OUTPUT_LVDS 4
89#define INTEL_OUTPUT_TVOUT 5
7d57382e 90#define INTEL_OUTPUT_HDMI 6
a4fc5ed6 91#define INTEL_OUTPUT_DISPLAYPORT 7
32f9d658 92#define INTEL_OUTPUT_EDP 8
79e53945
JB		 93
94#define INTEL_DVO_CHIP_NONE 0
95#define INTEL_DVO_CHIP_LVDS 1
96#define INTEL_DVO_CHIP_TMDS 2
97#define INTEL_DVO_CHIP_TVOUT 4
98
6c9547ff
CW		 99/* drm_display_mode->private_flags */
100#define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
101#define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
3b5c78a3 102#define INTEL_MODE_DP_FORCE_6BPC (0x10)
f9bef081
DV		 103/* This flag must be set by the encoder's mode_fixup if it changes the crtc
104 * timings in the mode to prevent the crtc fixup from overwriting them.
105 * Currently only lvds needs that. */
106#define INTEL_MODE_CRTC_TIMINGS_SET (0x20)
6c9547ff
CW		 107
108static inline void
109intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
110 int multiplier)
111{
112 mode->clock *= multiplier;
113 mode->private_flags |= multiplier;
114}
115
116static inline int
117intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode)
118{
119 return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT;
120}
121
79e53945
JB		 122struct intel_framebuffer {
123 struct drm_framebuffer base;
05394f39 124 struct drm_i915_gem_object *obj;
79e53945
JB		 125};
126
37811fcc
CW		 127struct intel_fbdev {
128 struct drm_fb_helper helper;
129 struct intel_framebuffer ifb;
130 struct list_head fbdev_list;
131 struct drm_display_mode *our_mode;
132};
79e53945 133
21d40d37 134struct intel_encoder {
4ef69c7a 135 struct drm_encoder base;
9a935856
DV		 136 /*
137 * The new crtc this encoder will be driven from. Only differs from
138 * base->crtc while a modeset is in progress.
139 */
140 struct intel_crtc *new_crtc;
141
79e53945 142 int type;
e2f0ba97 143 bool needs_tv_clock;
66a9278e
DV		 144 /*
145 * Intel hw has only one MUX where encoders could be clone, hence a
146 * simple flag is enough to compute the possible_clones mask.
147 */
148 bool cloneable;
5ab432ef 149 bool connectors_active;
21d40d37 150 void (*hot_plug)(struct intel_encoder *);
ef9c3aee
DV		 151 void (*enable)(struct intel_encoder *);
152 void (*disable)(struct intel_encoder *);
f0947c37
DV		 153 /* Read out the current hw state of this connector, returning true if
154 * the encoder is active. If the encoder is enabled it also set the pipe
155 * it is connected to in the pipe parameter. */
156 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
f8aed700 157 int crtc_mask;
79e53945
JB		 158};
159
5daa55eb
ZW		 160struct intel_connector {
161 struct drm_connector base;
9a935856
DV		 162 /*
163 * The fixed encoder this connector is connected to.
164 */
df0e9248 165 struct intel_encoder *encoder;
9a935856
DV		 166
167 /*
168 * The new encoder this connector will be driven. Only differs from
169 * encoder while a modeset is in progress.
170 */
171 struct intel_encoder *new_encoder;
172
f0947c37
DV		 173 /* Reads out the current hw, returning true if the connector is enabled
174 * and active (i.e. dpms ON state). */
175 bool (*get_hw_state)(struct intel_connector *);
5daa55eb
ZW		 176};
177
79e53945
JB		 178struct intel_crtc {
179 struct drm_crtc base;
80824003
JB		 180 enum pipe pipe;
181 enum plane plane;
79e53945 182 u8 lut_r[256], lut_g[256], lut_b[256];
08a48469
DV		 183 /*
184 * Whether the crtc and the connected output pipeline is active. Implies
185 * that crtc->enabled is set, i.e. the current mode configuration has
186 * some outputs connected to this crtc.
187 *
188 * Atm crtc->enabled is unconditionally updated _before_ the hw state is
189 * changed, hence we can only check this when enabling the crtc.
190 */
191 bool active;
93314b5b 192 bool primary_disabled; /* is the crtc obscured by a plane? */
652c393a 193 bool lowfreq_avail;
02e792fb 194 struct intel_overlay *overlay;
6b95a207 195 struct intel_unpin_work *unpin_work;
77ffb597 196 int fdi_lanes;
cda4b7d3 197
e506a0c6
DV		 198 /* Display surface base address adjustement for pageflips. Note that on
199 * gen4+ this only adjusts up to a tile, offsets within a tile are
200 * handled in the hw itself (with the TILEOFF register). */
201 unsigned long dspaddr_offset;
202
05394f39 203 struct drm_i915_gem_object *cursor_bo;
cda4b7d3
CW		 204 uint32_t cursor_addr;
205 int16_t cursor_x, cursor_y;
206 int16_t cursor_width, cursor_height;
6b383a7f 207 bool cursor_visible;
5a354204 208 unsigned int bpp;
4b645f14 209
ee7b9f93
JB		 210 /* We can share PLLs across outputs if the timings match */
211 struct intel_pch_pll *pch_pll;
79e53945
JB		 212};
213
b840d907
JB		 214struct intel_plane {
215 struct drm_plane base;
216 enum pipe pipe;
217 struct drm_i915_gem_object *obj;
218 int max_downscale;
219 u32 lut_r[1024], lut_g[1024], lut_b[1024];
220 void (*update_plane)(struct drm_plane *plane,
221 struct drm_framebuffer *fb,
222 struct drm_i915_gem_object *obj,
223 int crtc_x, int crtc_y,
224 unsigned int crtc_w, unsigned int crtc_h,
225 uint32_t x, uint32_t y,
226 uint32_t src_w, uint32_t src_h);
227 void (*disable_plane)(struct drm_plane *plane);
8ea30864
JB		 228 int (*update_colorkey)(struct drm_plane *plane,
229 struct drm_intel_sprite_colorkey *key);
230 void (*get_colorkey)(struct drm_plane *plane,
231 struct drm_intel_sprite_colorkey *key);
b840d907
JB		 232};
233
b445e3b0
ED		 234struct intel_watermark_params {
235 unsigned long fifo_size;
236 unsigned long max_wm;
237 unsigned long default_wm;
238 unsigned long guard_size;
239 unsigned long cacheline_size;
240};
241
242struct cxsr_latency {
243 int is_desktop;
244 int is_ddr3;
245 unsigned long fsb_freq;
246 unsigned long mem_freq;
247 unsigned long display_sr;
248 unsigned long display_hpll_disable;
249 unsigned long cursor_sr;
250 unsigned long cursor_hpll_disable;
251};
252
79e53945 253#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
5daa55eb 254#define to_intel_connector(x) container_of(x, struct intel_connector, base)
4ef69c7a 255#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
79e53945 256#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
b840d907 257#define to_intel_plane(x) container_of(x, struct intel_plane, base)
79e53945 258
45187ace
JB		 259#define DIP_HEADER_SIZE 5
260
3c17fe4b
DH		 261#define DIP_TYPE_AVI 0x82
262#define DIP_VERSION_AVI 0x2
263#define DIP_LEN_AVI 13
c846b619
PZ		 264#define DIP_AVI_PR_1 0
265#define DIP_AVI_PR_2 1
3c17fe4b 266
26005210 267#define DIP_TYPE_SPD 0x83
c0864cb3
JB		 268#define DIP_VERSION_SPD 0x1
269#define DIP_LEN_SPD 25
270#define DIP_SPD_UNKNOWN 0
271#define DIP_SPD_DSTB 0x1
272#define DIP_SPD_DVDP 0x2
273#define DIP_SPD_DVHS 0x3
274#define DIP_SPD_HDDVR 0x4
275#define DIP_SPD_DVC 0x5
276#define DIP_SPD_DSC 0x6
277#define DIP_SPD_VCD 0x7
278#define DIP_SPD_GAME 0x8
279#define DIP_SPD_PC 0x9
280#define DIP_SPD_BD 0xa
281#define DIP_SPD_SCD 0xb
282
3c17fe4b
DH		 283struct dip_infoframe {
284 uint8_t type; /* HB0 */
285 uint8_t ver; /* HB1 */
286 uint8_t len; /* HB2 - body len, not including checksum */
287 uint8_t ecc; /* Header ECC */
288 uint8_t checksum; /* PB0 */
289 union {
290 struct {
291 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
292 uint8_t Y_A_B_S;
293 /* PB2 - C 7:6, M 5:4, R 3:0 */
294 uint8_t C_M_R;
295 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
296 uint8_t ITC_EC_Q_SC;
297 /* PB4 - VIC 6:0 */
298 uint8_t VIC;
0aa534df
PZ		 299 /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
300 uint8_t YQ_CN_PR;
3c17fe4b
DH		 301 /* PB6 to PB13 */
302 uint16_t top_bar_end;
303 uint16_t bottom_bar_start;
304 uint16_t left_bar_end;
305 uint16_t right_bar_start;
81014b9d 306 } __attribute__ ((packed)) avi;
c0864cb3
JB		 307 struct {
308 uint8_t vn[8];
309 uint8_t pd[16];
310 uint8_t sdi;
81014b9d 311 } __attribute__ ((packed)) spd;
3c17fe4b
DH		 312 uint8_t payload[27];
313 } __attribute__ ((packed)) body;
314} __attribute__((packed));
315
f5bbfca3
ED		 316struct intel_hdmi {
317 struct intel_encoder base;
318 u32 sdvox_reg;
319 int ddc_bus;
320 int ddi_port;
321 uint32_t color_range;
322 bool has_hdmi_sink;
323 bool has_audio;
324 enum hdmi_force_audio force_audio;
325 void (*write_infoframe)(struct drm_encoder *encoder,
326 struct dip_infoframe *frame);
687f4d06
PZ		 327 void (*set_infoframes)(struct drm_encoder *encoder,
328 struct drm_display_mode *adjusted_mode);
f5bbfca3
ED		 329};
330
54d63ca6
SK		 331#define DP_RECEIVER_CAP_SIZE 0xf
332#define DP_LINK_CONFIGURATION_SIZE 9
333
334struct intel_dp {
335 struct intel_encoder base;
336 uint32_t output_reg;
337 uint32_t DP;
338 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
339 bool has_audio;
340 enum hdmi_force_audio force_audio;
ab9d7c30 341 enum port port;
54d63ca6 342 uint32_t color_range;
54d63ca6
SK		 343 uint8_t link_bw;
344 uint8_t lane_count;
345 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
346 struct i2c_adapter adapter;
347 struct i2c_algo_dp_aux_data algo;
348 bool is_pch_edp;
349 uint8_t train_set[4];
350 int panel_power_up_delay;
351 int panel_power_down_delay;
352 int panel_power_cycle_delay;
353 int backlight_on_delay;
354 int backlight_off_delay;
355 struct drm_display_mode *panel_fixed_mode; /* for eDP */
356 struct delayed_work panel_vdd_work;
357 bool want_panel_vdd;
358 struct edid *edid; /* cached EDID for eDP */
359 int edid_mode_count;
360};
361
f875c15a
CW		 362static inline struct drm_crtc *
363intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
364{
365 struct drm_i915_private *dev_priv = dev->dev_private;
366 return dev_priv->pipe_to_crtc_mapping[pipe];
367}
368
417ae147
CW		 369static inline struct drm_crtc *
370intel_get_crtc_for_plane(struct drm_device *dev, int plane)
371{
372 struct drm_i915_private *dev_priv = dev->dev_private;
373 return dev_priv->plane_to_crtc_mapping[plane];
374}
375
4e5359cd
SF		 376struct intel_unpin_work {
377 struct work_struct work;
378 struct drm_device *dev;
05394f39
CW		 379 struct drm_i915_gem_object *old_fb_obj;
380 struct drm_i915_gem_object *pending_flip_obj;
4e5359cd
SF		 381 struct drm_pending_vblank_event *event;
382 int pending;
383 bool enable_stall_check;
384};
385
1630fe75
CW		 386struct intel_fbc_work {
387 struct delayed_work work;
388 struct drm_crtc *crtc;
389 struct drm_framebuffer *fb;
390 int interval;
391};
392
335af9a2 393int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
f0217c42 394
3f43c48d 395extern void intel_attach_force_audio_property(struct drm_connector *connector);
e953fd7b
CW		 396extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
397
79e53945 398extern void intel_crt_init(struct drm_device *dev);
08d644ad
DV		 399extern void intel_hdmi_init(struct drm_device *dev,
400 int sdvox_reg, enum port port);
f5bbfca3 401extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
f5bbfca3 402extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
eef4eacb
DV		 403extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
404 bool is_sdvob);
79e53945
JB		 405extern void intel_dvo_init(struct drm_device *dev);
406extern void intel_tv_init(struct drm_device *dev);
f047e395
CW		 407extern void intel_mark_busy(struct drm_device *dev);
408extern void intel_mark_idle(struct drm_device *dev);
409extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj);
410extern void intel_mark_fb_idle(struct drm_i915_gem_object *obj);
c5d1b51d 411extern bool intel_lvds_init(struct drm_device *dev);
ab9d7c30
PZ		 412extern void intel_dp_init(struct drm_device *dev, int output_reg,
413 enum port port);
a4fc5ed6
KP		 414void
415intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
416 struct drm_display_mode *adjusted_mode);
cb0953d7 417extern bool intel_dpd_is_edp(struct drm_device *dev);
0206e353 418extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
94bf2ced
DV		 419extern int intel_edp_target_clock(struct intel_encoder *,
420 struct drm_display_mode *mode);
814948ad 421extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
b840d907 422extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
6f1d69b0
ED		 423extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
424 enum plane plane);
32f9d658 425
a9573556 426/* intel_panel.c */
1d8e1c75
CW		 427extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
428 struct drm_display_mode *adjusted_mode);
429extern void intel_pch_panel_fitting(struct drm_device *dev,
430 int fitting_mode,
cb1793ce 431 const struct drm_display_mode *mode,
1d8e1c75 432 struct drm_display_mode *adjusted_mode);
a9573556 433extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
a9573556 434extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
aaa6fd2a 435extern int intel_panel_setup_backlight(struct drm_device *dev);
24ded204
DV		 436extern void intel_panel_enable_backlight(struct drm_device *dev,
437 enum pipe pipe);
47356eb6 438extern void intel_panel_disable_backlight(struct drm_device *dev);
aaa6fd2a 439extern void intel_panel_destroy_backlight(struct drm_device *dev);
fe16d949 440extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1d8e1c75 441
d9e55608 442struct intel_set_config {
1aa4b628
DV		 443 struct drm_encoder **save_connector_encoders;
444 struct drm_crtc **save_encoder_crtcs;
d9e55608 445 struct drm_crtc *save_crtcs;
5e2b584e
DV		 446
447 bool fb_changed;
448 bool mode_changed;
d9e55608
DV		 449};
450
a6778b3c
DV		 451extern bool intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
452 int x, int y, struct drm_framebuffer *old_fb);
79e53945 453extern void intel_crtc_load_lut(struct drm_crtc *crtc);
b2cabb0e 454extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
5ab432ef 455extern void intel_encoder_disable(struct drm_encoder *encoder);
ea5b213a 456extern void intel_encoder_destroy(struct drm_encoder *encoder);
5ab432ef
DV		 457extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode);
458extern void intel_connector_dpms(struct drm_connector *, int mode);
f0947c37 459extern bool intel_connector_get_hw_state(struct intel_connector *connector);
0a91ca29 460extern void intel_connector_check_state(struct intel_connector *);
79e53945 461
df0e9248
CW		 462static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
463{
464 return to_intel_connector(connector)->encoder;
465}
466
467extern void intel_connector_attach_encoder(struct intel_connector *connector,
468 struct intel_encoder *encoder);
469extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
79e53945
JB		 470
471extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
472 struct drm_crtc *crtc);
08d7b3d1
CW		 473int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
474 struct drm_file *file_priv);
9d0498a2 475extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
58e10eb9 476extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
8261b191
CW		 477
478struct intel_load_detect_pipe {
d2dff872 479 struct drm_framebuffer *release_fb;
8261b191
CW		 480 bool load_detect_temp;
481 int dpms_mode;
482};
d2434ab7 483extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 484 struct drm_display_mode *mode,
8261b191 485 struct intel_load_detect_pipe *old);
d2434ab7 486extern void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 487 struct intel_load_detect_pipe *old);
79e53945 488
79e53945
JB		 489extern void intelfb_restore(void);
490extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
491 u16 blue, int regno);
b8c00ac5
DA		 492extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
493 u16 *blue, int regno);
0cdab21f 494extern void intel_enable_clock_gating(struct drm_device *dev);
79e53945 495
127bd2ac 496extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 497 struct drm_i915_gem_object *obj,
919926ae 498 struct intel_ring_buffer *pipelined);
1690e1eb 499extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
127bd2ac 500
38651674
DA		 501extern int intel_framebuffer_init(struct drm_device *dev,
502 struct intel_framebuffer *ifb,
308e5bcb 503 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 504 struct drm_i915_gem_object *obj);
38651674
DA		 505extern int intel_fbdev_init(struct drm_device *dev);
506extern void intel_fbdev_fini(struct drm_device *dev);
3fa016a0 507extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
6b95a207
KH		 508extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
509extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
1afe3e9d 510extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
6b95a207 511
02e792fb
DV		 512extern void intel_setup_overlay(struct drm_device *dev);
513extern void intel_cleanup_overlay(struct drm_device *dev);
ce453d81 514extern int intel_overlay_switch_off(struct intel_overlay *overlay);
02e792fb
DV		 515extern int intel_overlay_put_image(struct drm_device *dev, void *data,
516 struct drm_file *file_priv);
517extern int intel_overlay_attrs(struct drm_device *dev, void *data,
518 struct drm_file *file_priv);
4abe3520 519
eb1f8e4f 520extern void intel_fb_output_poll_changed(struct drm_device *dev);
e8e7a2b8 521extern void intel_fb_restore_mode(struct drm_device *dev);
645c62a5 522
b840d907
JB		 523extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
524 bool state);
525#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
526#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
527
645c62a5 528extern void intel_init_clock_gating(struct drm_device *dev);
e0dac65e
WF		 529extern void intel_write_eld(struct drm_encoder *encoder,
530 struct drm_display_mode *mode);
d4270e57 531extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
45244b87 532extern void intel_prepare_ddi(struct drm_device *dev);
c82e4d26 533extern void hsw_fdi_link_train(struct drm_crtc *crtc);
0e72a5b5 534extern void intel_ddi_init(struct drm_device *dev, enum port port);
d4270e57 535
b840d907 536/* For use by IVB LP watermark workaround in intel_sprite.c */
f681fa23 537extern void intel_update_watermarks(struct drm_device *dev);
b840d907
JB		 538extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
539 uint32_t sprite_width,
540 int pixel_size);
1f8eeabf
ED		 541extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe,
542 struct drm_display_mode *mode);
8ea30864
JB		 543
544extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
545 struct drm_file *file_priv);
546extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
547 struct drm_file *file_priv);
548
57f350b6
JB		 549extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
550
85208be0 551/* Power-related functions, located in intel_pm.c */
1fa61106 552extern void intel_init_pm(struct drm_device *dev);
85208be0 553/* FBC */
85208be0
ED		 554extern bool intel_fbc_enabled(struct drm_device *dev);
555extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
556extern void intel_update_fbc(struct drm_device *dev);
eb48eb00
DV		 557/* IPS */
558extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
559extern void intel_gpu_ips_teardown(void);
85208be0 560
0232e927 561extern void intel_init_power_wells(struct drm_device *dev);
8090c6b9
DV		 562extern void intel_enable_gt_powersave(struct drm_device *dev);
563extern void intel_disable_gt_powersave(struct drm_device *dev);
6590190d 564extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
930ebb46 565extern void ironlake_teardown_rc6(struct drm_device *dev);
b3daeaef 566
5ab432ef
DV		 567extern void intel_enable_ddi(struct intel_encoder *encoder);
568extern void intel_disable_ddi(struct intel_encoder *encoder);
85234cdc
DV		 569extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
570 enum pipe *pipe);
72662e10
ED		 571extern void intel_ddi_mode_set(struct drm_encoder *encoder,
572 struct drm_display_mode *mode,
573 struct drm_display_mode *adjusted_mode);
574
79e53945 575#endif /* __INTEL_DRV_H__ */
Linux kernel - Deliverables
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