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79e53945 JB |
1 | /* |
2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright (c) 2007-2008 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
23 | * IN THE SOFTWARE. | |
24 | */ | |
25 | #ifndef __INTEL_DRV_H__ | |
26 | #define __INTEL_DRV_H__ | |
27 | ||
d1d70677 | 28 | #include <linux/async.h> |
79e53945 | 29 | #include <linux/i2c.h> |
178f736a | 30 | #include <linux/hdmi.h> |
760285e7 | 31 | #include <drm/i915_drm.h> |
80824003 | 32 | #include "i915_drv.h" |
760285e7 DH |
33 | #include <drm/drm_crtc.h> |
34 | #include <drm/drm_crtc_helper.h> | |
35 | #include <drm/drm_fb_helper.h> | |
0e32b39c | 36 | #include <drm/drm_dp_mst_helper.h> |
eeca778a | 37 | #include <drm/drm_rect.h> |
10f81c19 | 38 | #include <drm/drm_atomic.h> |
913d8d11 | 39 | |
1d5bfac9 DV |
40 | /** |
41 | * _wait_for - magic (register) wait macro | |
42 | * | |
43 | * Does the right thing for modeset paths when run under kdgb or similar atomic | |
44 | * contexts. Note that it's important that we check the condition again after | |
45 | * having timed out, since the timeout could be due to preemption or similar and | |
46 | * we've never had a chance to check the condition before the timeout. | |
0351b939 TU |
47 | * |
48 | * TODO: When modesetting has fully transitioned to atomic, the below | |
49 | * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts | |
50 | * added. | |
1d5bfac9 | 51 | */ |
3f177625 TU |
52 | #define _wait_for(COND, US, W) ({ \ |
53 | unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \ | |
913d8d11 | 54 | int ret__ = 0; \ |
0206e353 | 55 | while (!(COND)) { \ |
913d8d11 | 56 | if (time_after(jiffies, timeout__)) { \ |
1d5bfac9 DV |
57 | if (!(COND)) \ |
58 | ret__ = -ETIMEDOUT; \ | |
913d8d11 CW |
59 | break; \ |
60 | } \ | |
9848de08 | 61 | if ((W) && drm_can_sleep()) { \ |
3f177625 | 62 | usleep_range((W), (W)*2); \ |
0cc2764c BW |
63 | } else { \ |
64 | cpu_relax(); \ | |
65 | } \ | |
913d8d11 CW |
66 | } \ |
67 | ret__; \ | |
68 | }) | |
69 | ||
3f177625 TU |
70 | #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000) |
71 | #define wait_for_us(COND, US) _wait_for((COND), (US), 1) | |
72 | ||
0351b939 TU |
73 | /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */ |
74 | #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT) | |
75 | # define _WAIT_FOR_ATOMIC_CHECK WARN_ON_ONCE(!in_atomic()) | |
76 | #else | |
77 | # define _WAIT_FOR_ATOMIC_CHECK do { } while (0) | |
78 | #endif | |
79 | ||
80 | #define _wait_for_atomic(COND, US) ({ \ | |
81 | unsigned long end__; \ | |
82 | int ret__ = 0; \ | |
83 | _WAIT_FOR_ATOMIC_CHECK; \ | |
84 | BUILD_BUG_ON((US) > 50000); \ | |
85 | end__ = (local_clock() >> 10) + (US) + 1; \ | |
86 | while (!(COND)) { \ | |
87 | if (time_after((unsigned long)(local_clock() >> 10), end__)) { \ | |
88 | /* Unlike the regular wait_for(), this atomic variant \ | |
89 | * cannot be preempted (and we'll just ignore the issue\ | |
90 | * of irq interruptions) and so we know that no time \ | |
91 | * has passed since the last check of COND and can \ | |
92 | * immediately report the timeout. \ | |
93 | */ \ | |
94 | ret__ = -ETIMEDOUT; \ | |
95 | break; \ | |
96 | } \ | |
97 | cpu_relax(); \ | |
98 | } \ | |
99 | ret__; \ | |
100 | }) | |
101 | ||
102 | #define wait_for_atomic(COND, MS) _wait_for_atomic((COND), (MS) * 1000) | |
103 | #define wait_for_atomic_us(COND, US) _wait_for_atomic((COND), (US)) | |
481b6af3 | 104 | |
49938ac4 JN |
105 | #define KHz(x) (1000 * (x)) |
106 | #define MHz(x) KHz(1000 * (x)) | |
021357ac | 107 | |
79e53945 JB |
108 | /* |
109 | * Display related stuff | |
110 | */ | |
111 | ||
112 | /* store information about an Ixxx DVO */ | |
113 | /* The i830->i865 use multiple DVOs with multiple i2cs */ | |
114 | /* the i915, i945 have a single sDVO i2c bus - which is different */ | |
115 | #define MAX_OUTPUTS 6 | |
116 | /* maximum connectors per crtcs in the mode set */ | |
79e53945 | 117 | |
4726e0b0 SK |
118 | /* Maximum cursor sizes */ |
119 | #define GEN2_CURSOR_WIDTH 64 | |
120 | #define GEN2_CURSOR_HEIGHT 64 | |
068be561 DL |
121 | #define MAX_CURSOR_WIDTH 256 |
122 | #define MAX_CURSOR_HEIGHT 256 | |
4726e0b0 | 123 | |
79e53945 JB |
124 | #define INTEL_I2C_BUS_DVO 1 |
125 | #define INTEL_I2C_BUS_SDVO 2 | |
126 | ||
127 | /* these are outputs from the chip - integrated only | |
128 | external chips are via DVO or SDVO output */ | |
6847d71b PZ |
129 | enum intel_output_type { |
130 | INTEL_OUTPUT_UNUSED = 0, | |
131 | INTEL_OUTPUT_ANALOG = 1, | |
132 | INTEL_OUTPUT_DVO = 2, | |
133 | INTEL_OUTPUT_SDVO = 3, | |
134 | INTEL_OUTPUT_LVDS = 4, | |
135 | INTEL_OUTPUT_TVOUT = 5, | |
136 | INTEL_OUTPUT_HDMI = 6, | |
137 | INTEL_OUTPUT_DISPLAYPORT = 7, | |
138 | INTEL_OUTPUT_EDP = 8, | |
139 | INTEL_OUTPUT_DSI = 9, | |
140 | INTEL_OUTPUT_UNKNOWN = 10, | |
141 | INTEL_OUTPUT_DP_MST = 11, | |
142 | }; | |
79e53945 JB |
143 | |
144 | #define INTEL_DVO_CHIP_NONE 0 | |
145 | #define INTEL_DVO_CHIP_LVDS 1 | |
146 | #define INTEL_DVO_CHIP_TMDS 2 | |
147 | #define INTEL_DVO_CHIP_TVOUT 4 | |
148 | ||
dfba2e2d SK |
149 | #define INTEL_DSI_VIDEO_MODE 0 |
150 | #define INTEL_DSI_COMMAND_MODE 1 | |
72ffa333 | 151 | |
79e53945 JB |
152 | struct intel_framebuffer { |
153 | struct drm_framebuffer base; | |
05394f39 | 154 | struct drm_i915_gem_object *obj; |
2d7a215f | 155 | struct intel_rotation_info rot_info; |
79e53945 JB |
156 | }; |
157 | ||
37811fcc CW |
158 | struct intel_fbdev { |
159 | struct drm_fb_helper helper; | |
8bcd4553 | 160 | struct intel_framebuffer *fb; |
d978ef14 | 161 | int preferred_bpp; |
37811fcc | 162 | }; |
79e53945 | 163 | |
21d40d37 | 164 | struct intel_encoder { |
4ef69c7a | 165 | struct drm_encoder base; |
9a935856 | 166 | |
6847d71b | 167 | enum intel_output_type type; |
bc079e8b | 168 | unsigned int cloneable; |
21d40d37 | 169 | void (*hot_plug)(struct intel_encoder *); |
7ae89233 | 170 | bool (*compute_config)(struct intel_encoder *, |
5cec258b | 171 | struct intel_crtc_state *); |
dafd226c | 172 | void (*pre_pll_enable)(struct intel_encoder *); |
bf49ec8c | 173 | void (*pre_enable)(struct intel_encoder *); |
ef9c3aee | 174 | void (*enable)(struct intel_encoder *); |
6cc5f341 | 175 | void (*mode_set)(struct intel_encoder *intel_encoder); |
ef9c3aee | 176 | void (*disable)(struct intel_encoder *); |
bf49ec8c | 177 | void (*post_disable)(struct intel_encoder *); |
d6db995f | 178 | void (*post_pll_disable)(struct intel_encoder *); |
f0947c37 DV |
179 | /* Read out the current hw state of this connector, returning true if |
180 | * the encoder is active. If the encoder is enabled it also set the pipe | |
181 | * it is connected to in the pipe parameter. */ | |
182 | bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); | |
045ac3b5 | 183 | /* Reconstructs the equivalent mode flags for the current hardware |
fdafa9e2 | 184 | * state. This must be called _after_ display->get_pipe_config has |
63000ef6 XZ |
185 | * pre-filled the pipe config. Note that intel_encoder->base.crtc must |
186 | * be set correctly before calling this function. */ | |
045ac3b5 | 187 | void (*get_config)(struct intel_encoder *, |
5cec258b | 188 | struct intel_crtc_state *pipe_config); |
07f9cd0b ID |
189 | /* |
190 | * Called during system suspend after all pending requests for the | |
191 | * encoder are flushed (for example for DP AUX transactions) and | |
192 | * device interrupts are disabled. | |
193 | */ | |
194 | void (*suspend)(struct intel_encoder *); | |
f8aed700 | 195 | int crtc_mask; |
1d843f9d | 196 | enum hpd_pin hpd_pin; |
79e53945 JB |
197 | }; |
198 | ||
1d508706 | 199 | struct intel_panel { |
dd06f90e | 200 | struct drm_display_mode *fixed_mode; |
ec9ed197 | 201 | struct drm_display_mode *downclock_mode; |
4d891523 | 202 | int fitting_mode; |
58c68779 JN |
203 | |
204 | /* backlight */ | |
205 | struct { | |
c91c9f32 | 206 | bool present; |
58c68779 | 207 | u32 level; |
6dda730e | 208 | u32 min; |
7bd688cd | 209 | u32 max; |
58c68779 | 210 | bool enabled; |
636baebf JN |
211 | bool combination_mode; /* gen 2/4 only */ |
212 | bool active_low_pwm; | |
b029e66f SK |
213 | |
214 | /* PWM chip */ | |
022e4e52 SK |
215 | bool util_pin_active_low; /* bxt+ */ |
216 | u8 controller; /* bxt+ only */ | |
b029e66f SK |
217 | struct pwm_device *pwm; |
218 | ||
58c68779 | 219 | struct backlight_device *device; |
ab656bb9 | 220 | |
5507faeb JN |
221 | /* Connector and platform specific backlight functions */ |
222 | int (*setup)(struct intel_connector *connector, enum pipe pipe); | |
223 | uint32_t (*get)(struct intel_connector *connector); | |
224 | void (*set)(struct intel_connector *connector, uint32_t level); | |
225 | void (*disable)(struct intel_connector *connector); | |
226 | void (*enable)(struct intel_connector *connector); | |
227 | uint32_t (*hz_to_pwm)(struct intel_connector *connector, | |
228 | uint32_t hz); | |
229 | void (*power)(struct intel_connector *, bool enable); | |
230 | } backlight; | |
1d508706 JN |
231 | }; |
232 | ||
5daa55eb ZW |
233 | struct intel_connector { |
234 | struct drm_connector base; | |
9a935856 DV |
235 | /* |
236 | * The fixed encoder this connector is connected to. | |
237 | */ | |
df0e9248 | 238 | struct intel_encoder *encoder; |
9a935856 | 239 | |
f0947c37 DV |
240 | /* Reads out the current hw, returning true if the connector is enabled |
241 | * and active (i.e. dpms ON state). */ | |
242 | bool (*get_hw_state)(struct intel_connector *); | |
1d508706 | 243 | |
4932e2c3 ID |
244 | /* |
245 | * Removes all interfaces through which the connector is accessible | |
246 | * - like sysfs, debugfs entries -, so that no new operations can be | |
247 | * started on the connector. Also makes sure all currently pending | |
248 | * operations finish before returing. | |
249 | */ | |
250 | void (*unregister)(struct intel_connector *); | |
251 | ||
1d508706 JN |
252 | /* Panel info for eDP and LVDS */ |
253 | struct intel_panel panel; | |
9cd300e0 JN |
254 | |
255 | /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ | |
256 | struct edid *edid; | |
beb60608 | 257 | struct edid *detect_edid; |
821450c6 EE |
258 | |
259 | /* since POLL and HPD connectors may use the same HPD line keep the native | |
260 | state of connector->polled in case hotplug storm detection changes it */ | |
261 | u8 polled; | |
0e32b39c DA |
262 | |
263 | void *port; /* store this opaque as its illegal to dereference it */ | |
264 | ||
265 | struct intel_dp *mst_port; | |
5daa55eb ZW |
266 | }; |
267 | ||
80ad9206 VS |
268 | typedef struct dpll { |
269 | /* given values */ | |
270 | int n; | |
271 | int m1, m2; | |
272 | int p1, p2; | |
273 | /* derived values */ | |
274 | int dot; | |
275 | int vco; | |
276 | int m; | |
277 | int p; | |
278 | } intel_clock_t; | |
279 | ||
de419ab6 ML |
280 | struct intel_atomic_state { |
281 | struct drm_atomic_state base; | |
282 | ||
27c329ed | 283 | unsigned int cdclk; |
565602d7 | 284 | |
1a617b77 ML |
285 | /* |
286 | * Calculated device cdclk, can be different from cdclk | |
287 | * only when all crtc's are DPMS off. | |
288 | */ | |
289 | unsigned int dev_cdclk; | |
290 | ||
565602d7 ML |
291 | bool dpll_set, modeset; |
292 | ||
293 | unsigned int active_crtcs; | |
294 | unsigned int min_pixclk[I915_MAX_PIPES]; | |
295 | ||
de419ab6 | 296 | struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS]; |
aa363136 | 297 | struct intel_wm_config wm_config; |
ed4a6a7c MR |
298 | |
299 | /* | |
300 | * Current watermarks can't be trusted during hardware readout, so | |
301 | * don't bother calculating intermediate watermarks. | |
302 | */ | |
303 | bool skip_intermediate_wm; | |
de419ab6 ML |
304 | }; |
305 | ||
eeca778a | 306 | struct intel_plane_state { |
2b875c22 | 307 | struct drm_plane_state base; |
eeca778a GP |
308 | struct drm_rect src; |
309 | struct drm_rect dst; | |
310 | struct drm_rect clip; | |
eeca778a | 311 | bool visible; |
32b7eeec | 312 | |
be41e336 CK |
313 | /* |
314 | * scaler_id | |
315 | * = -1 : not using a scaler | |
316 | * >= 0 : using a scalers | |
317 | * | |
318 | * plane requiring a scaler: | |
319 | * - During check_plane, its bit is set in | |
320 | * crtc_state->scaler_state.scaler_users by calling helper function | |
86adf9d7 | 321 | * update_scaler_plane. |
be41e336 CK |
322 | * - scaler_id indicates the scaler it got assigned. |
323 | * | |
324 | * plane doesn't require a scaler: | |
325 | * - this can happen when scaling is no more required or plane simply | |
326 | * got disabled. | |
327 | * - During check_plane, corresponding bit is reset in | |
328 | * crtc_state->scaler_state.scaler_users by calling helper function | |
86adf9d7 | 329 | * update_scaler_plane. |
be41e336 CK |
330 | */ |
331 | int scaler_id; | |
818ed961 ML |
332 | |
333 | struct drm_intel_sprite_colorkey ckey; | |
7580d774 ML |
334 | |
335 | /* async flip related structures */ | |
336 | struct drm_i915_gem_request *wait_req; | |
eeca778a GP |
337 | }; |
338 | ||
5724dbd1 | 339 | struct intel_initial_plane_config { |
2d14030b | 340 | struct intel_framebuffer *fb; |
49af449b | 341 | unsigned int tiling; |
46f297fb JB |
342 | int size; |
343 | u32 base; | |
344 | }; | |
345 | ||
be41e336 CK |
346 | #define SKL_MIN_SRC_W 8 |
347 | #define SKL_MAX_SRC_W 4096 | |
348 | #define SKL_MIN_SRC_H 8 | |
6156a456 | 349 | #define SKL_MAX_SRC_H 4096 |
be41e336 CK |
350 | #define SKL_MIN_DST_W 8 |
351 | #define SKL_MAX_DST_W 4096 | |
352 | #define SKL_MIN_DST_H 8 | |
6156a456 | 353 | #define SKL_MAX_DST_H 4096 |
be41e336 CK |
354 | |
355 | struct intel_scaler { | |
be41e336 CK |
356 | int in_use; |
357 | uint32_t mode; | |
358 | }; | |
359 | ||
360 | struct intel_crtc_scaler_state { | |
361 | #define SKL_NUM_SCALERS 2 | |
362 | struct intel_scaler scalers[SKL_NUM_SCALERS]; | |
363 | ||
364 | /* | |
365 | * scaler_users: keeps track of users requesting scalers on this crtc. | |
366 | * | |
367 | * If a bit is set, a user is using a scaler. | |
368 | * Here user can be a plane or crtc as defined below: | |
369 | * bits 0-30 - plane (bit position is index from drm_plane_index) | |
370 | * bit 31 - crtc | |
371 | * | |
372 | * Instead of creating a new index to cover planes and crtc, using | |
373 | * existing drm_plane_index for planes which is well less than 31 | |
374 | * planes and bit 31 for crtc. This should be fine to cover all | |
375 | * our platforms. | |
376 | * | |
377 | * intel_atomic_setup_scalers will setup available scalers to users | |
378 | * requesting scalers. It will gracefully fail if request exceeds | |
379 | * avilability. | |
380 | */ | |
381 | #define SKL_CRTC_INDEX 31 | |
382 | unsigned scaler_users; | |
383 | ||
384 | /* scaler used by crtc for panel fitting purpose */ | |
385 | int scaler_id; | |
386 | }; | |
387 | ||
1ed51de9 DV |
388 | /* drm_mode->private_flags */ |
389 | #define I915_MODE_FLAG_INHERITED 1 | |
390 | ||
4e0963c7 MR |
391 | struct intel_pipe_wm { |
392 | struct intel_wm_level wm[5]; | |
71f0a626 | 393 | struct intel_wm_level raw_wm[5]; |
4e0963c7 MR |
394 | uint32_t linetime; |
395 | bool fbc_wm_enabled; | |
396 | bool pipe_enabled; | |
397 | bool sprites_enabled; | |
398 | bool sprites_scaled; | |
399 | }; | |
400 | ||
401 | struct skl_pipe_wm { | |
402 | struct skl_wm_level wm[8]; | |
403 | struct skl_wm_level trans_wm; | |
404 | uint32_t linetime; | |
405 | }; | |
406 | ||
5cec258b | 407 | struct intel_crtc_state { |
2d112de7 ACO |
408 | struct drm_crtc_state base; |
409 | ||
bb760063 DV |
410 | /** |
411 | * quirks - bitfield with hw state readout quirks | |
412 | * | |
413 | * For various reasons the hw state readout code might not be able to | |
414 | * completely faithfully read out the current state. These cases are | |
415 | * tracked with quirk flags so that fastboot and state checker can act | |
416 | * accordingly. | |
417 | */ | |
9953599b | 418 | #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ |
bb760063 DV |
419 | unsigned long quirks; |
420 | ||
cd202f69 | 421 | unsigned fb_bits; /* framebuffers to flip */ |
ab1d3a0e ML |
422 | bool update_pipe; /* can a fast modeset be performed? */ |
423 | bool disable_cxsr; | |
caed361d | 424 | bool update_wm_pre, update_wm_post; /* watermarks are updated */ |
e8861675 | 425 | bool fb_changed; /* fb on any of the planes is changed */ |
bfd16b2a | 426 | |
37327abd VS |
427 | /* Pipe source size (ie. panel fitter input size) |
428 | * All planes will be positioned inside this space, | |
429 | * and get clipped at the edges. */ | |
430 | int pipe_src_w, pipe_src_h; | |
431 | ||
5bfe2ac0 DV |
432 | /* Whether to set up the PCH/FDI. Note that we never allow sharing |
433 | * between pch encoders and cpu encoders. */ | |
434 | bool has_pch_encoder; | |
50f3b016 | 435 | |
e43823ec JB |
436 | /* Are we sending infoframes on the attached port */ |
437 | bool has_infoframe; | |
438 | ||
3b117c8f | 439 | /* CPU Transcoder for the pipe. Currently this can only differ from the |
4d1de975 JN |
440 | * pipe on Haswell and later (where we have a special eDP transcoder) |
441 | * and Broxton (where we have special DSI transcoders). */ | |
3b117c8f DV |
442 | enum transcoder cpu_transcoder; |
443 | ||
50f3b016 DV |
444 | /* |
445 | * Use reduced/limited/broadcast rbg range, compressing from the full | |
446 | * range fed into the crtcs. | |
447 | */ | |
448 | bool limited_color_range; | |
449 | ||
03afc4a2 DV |
450 | /* DP has a bunch of special case unfortunately, so mark the pipe |
451 | * accordingly. */ | |
452 | bool has_dp_encoder; | |
d8b32247 | 453 | |
a65347ba JN |
454 | /* DSI has special cases */ |
455 | bool has_dsi_encoder; | |
456 | ||
6897b4b5 DV |
457 | /* Whether we should send NULL infoframes. Required for audio. */ |
458 | bool has_hdmi_sink; | |
459 | ||
9ed109a7 DV |
460 | /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or |
461 | * has_dp_encoder is set. */ | |
462 | bool has_audio; | |
463 | ||
d8b32247 DV |
464 | /* |
465 | * Enable dithering, used when the selected pipe bpp doesn't match the | |
466 | * plane bpp. | |
467 | */ | |
965e0c48 | 468 | bool dither; |
f47709a9 DV |
469 | |
470 | /* Controls for the clock computation, to override various stages. */ | |
471 | bool clock_set; | |
472 | ||
09ede541 DV |
473 | /* SDVO TV has a bunch of special case. To make multifunction encoders |
474 | * work correctly, we need to track this at runtime.*/ | |
475 | bool sdvo_tv_clock; | |
476 | ||
e29c22c0 DV |
477 | /* |
478 | * crtc bandwidth limit, don't increase pipe bpp or clock if not really | |
479 | * required. This is set in the 2nd loop of calling encoder's | |
480 | * ->compute_config if the first pick doesn't work out. | |
481 | */ | |
482 | bool bw_constrained; | |
483 | ||
f47709a9 DV |
484 | /* Settings for the intel dpll used on pretty much everything but |
485 | * haswell. */ | |
80ad9206 | 486 | struct dpll dpll; |
f47709a9 | 487 | |
8106ddbd ACO |
488 | /* Selected dpll when shared or NULL. */ |
489 | struct intel_shared_dpll *shared_dpll; | |
a43f6e0f | 490 | |
96b7dfb7 S |
491 | /* |
492 | * - PORT_CLK_SEL for DDI ports on HSW/BDW. | |
493 | * - enum skl_dpll on SKL | |
494 | */ | |
de7cfc63 DV |
495 | uint32_t ddi_pll_sel; |
496 | ||
66e985c0 DV |
497 | /* Actual register state of the dpll, for shared dpll cross-checking. */ |
498 | struct intel_dpll_hw_state dpll_hw_state; | |
499 | ||
965e0c48 | 500 | int pipe_bpp; |
6cf86a5e | 501 | struct intel_link_m_n dp_m_n; |
ff9a6750 | 502 | |
439d7ac0 PB |
503 | /* m2_n2 for eDP downclock */ |
504 | struct intel_link_m_n dp_m2_n2; | |
f769cd24 | 505 | bool has_drrs; |
439d7ac0 | 506 | |
ff9a6750 DV |
507 | /* |
508 | * Frequence the dpll for the port should run at. Differs from the | |
3c52f4eb VS |
509 | * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also |
510 | * already multiplied by pixel_multiplier. | |
df92b1e6 | 511 | */ |
ff9a6750 DV |
512 | int port_clock; |
513 | ||
6cc5f341 DV |
514 | /* Used by SDVO (and if we ever fix it, HDMI). */ |
515 | unsigned pixel_multiplier; | |
2dd24552 | 516 | |
90a6b7b0 VS |
517 | uint8_t lane_count; |
518 | ||
2dd24552 | 519 | /* Panel fitter controls for gen2-gen4 + VLV */ |
b074cec8 JB |
520 | struct { |
521 | u32 control; | |
522 | u32 pgm_ratios; | |
68fc8742 | 523 | u32 lvds_border_bits; |
b074cec8 JB |
524 | } gmch_pfit; |
525 | ||
526 | /* Panel fitter placement and size for Ironlake+ */ | |
527 | struct { | |
528 | u32 pos; | |
529 | u32 size; | |
fd4daa9c | 530 | bool enabled; |
fabf6e51 | 531 | bool force_thru; |
b074cec8 | 532 | } pch_pfit; |
33d29b14 | 533 | |
ca3a0ff8 | 534 | /* FDI configuration, only valid if has_pch_encoder is set. */ |
33d29b14 | 535 | int fdi_lanes; |
ca3a0ff8 | 536 | struct intel_link_m_n fdi_m_n; |
42db64ef PZ |
537 | |
538 | bool ips_enabled; | |
cf532bb2 | 539 | |
f51be2e0 PZ |
540 | bool enable_fbc; |
541 | ||
cf532bb2 | 542 | bool double_wide; |
0e32b39c DA |
543 | |
544 | bool dp_encoder_is_mst; | |
545 | int pbn; | |
be41e336 CK |
546 | |
547 | struct intel_crtc_scaler_state scaler_state; | |
99d736a2 ML |
548 | |
549 | /* w/a for waiting 2 vblanks during crtc enable */ | |
550 | enum pipe hsw_workaround_pipe; | |
d21fbe87 MR |
551 | |
552 | /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */ | |
553 | bool disable_lp_wm; | |
4e0963c7 MR |
554 | |
555 | struct { | |
556 | /* | |
ed4a6a7c MR |
557 | * Optimal watermarks, programmed post-vblank when this state |
558 | * is committed. | |
4e0963c7 MR |
559 | */ |
560 | union { | |
561 | struct intel_pipe_wm ilk; | |
562 | struct skl_pipe_wm skl; | |
563 | } optimal; | |
ed4a6a7c MR |
564 | |
565 | /* | |
566 | * Intermediate watermarks; these can be programmed immediately | |
567 | * since they satisfy both the current configuration we're | |
568 | * switching away from and the new configuration we're switching | |
569 | * to. | |
570 | */ | |
571 | struct intel_pipe_wm intermediate; | |
572 | ||
573 | /* | |
574 | * Platforms with two-step watermark programming will need to | |
575 | * update watermark programming post-vblank to switch from the | |
576 | * safe intermediate watermarks to the optimal final | |
577 | * watermarks. | |
578 | */ | |
579 | bool need_postvbl_update; | |
4e0963c7 | 580 | } wm; |
05dc698c LL |
581 | |
582 | /* Gamma mode programmed on the pipe */ | |
583 | uint32_t gamma_mode; | |
b8cecdf5 DV |
584 | }; |
585 | ||
262cd2e1 VS |
586 | struct vlv_wm_state { |
587 | struct vlv_pipe_wm wm[3]; | |
588 | struct vlv_sr_wm sr[3]; | |
589 | uint8_t num_active_planes; | |
590 | uint8_t num_levels; | |
591 | uint8_t level; | |
592 | bool cxsr; | |
593 | }; | |
594 | ||
84c33a64 | 595 | struct intel_mmio_flip { |
9362c7c5 | 596 | struct work_struct work; |
bcafc4e3 | 597 | struct drm_i915_private *i915; |
eed29a5b | 598 | struct drm_i915_gem_request *req; |
b2cfe0ab | 599 | struct intel_crtc *crtc; |
86efe24a | 600 | unsigned int rotation; |
84c33a64 SG |
601 | }; |
602 | ||
79e53945 JB |
603 | struct intel_crtc { |
604 | struct drm_crtc base; | |
80824003 JB |
605 | enum pipe pipe; |
606 | enum plane plane; | |
79e53945 | 607 | u8 lut_r[256], lut_g[256], lut_b[256]; |
08a48469 DV |
608 | /* |
609 | * Whether the crtc and the connected output pipeline is active. Implies | |
610 | * that crtc->enabled is set, i.e. the current mode configuration has | |
611 | * some outputs connected to this crtc. | |
08a48469 DV |
612 | */ |
613 | bool active; | |
6efdf354 | 614 | unsigned long enabled_power_domains; |
652c393a | 615 | bool lowfreq_avail; |
02e792fb | 616 | struct intel_overlay *overlay; |
6b95a207 | 617 | struct intel_unpin_work *unpin_work; |
cda4b7d3 | 618 | |
b4a98e57 CW |
619 | atomic_t unpin_work_count; |
620 | ||
e506a0c6 DV |
621 | /* Display surface base address adjustement for pageflips. Note that on |
622 | * gen4+ this only adjusts up to a tile, offsets within a tile are | |
623 | * handled in the hw itself (with the TILEOFF register). */ | |
54ea9da8 | 624 | u32 dspaddr_offset; |
2db3366b PZ |
625 | int adjusted_x; |
626 | int adjusted_y; | |
e506a0c6 | 627 | |
cda4b7d3 | 628 | uint32_t cursor_addr; |
4b0e333e | 629 | uint32_t cursor_cntl; |
dc41c154 | 630 | uint32_t cursor_size; |
4b0e333e | 631 | uint32_t cursor_base; |
4b645f14 | 632 | |
6e3c9717 | 633 | struct intel_crtc_state *config; |
b8cecdf5 | 634 | |
10d83730 VS |
635 | /* reset counter value when the last flip was submitted */ |
636 | unsigned int reset_counter; | |
8664281b PZ |
637 | |
638 | /* Access to these should be protected by dev_priv->irq_lock. */ | |
639 | bool cpu_fifo_underrun_disabled; | |
640 | bool pch_fifo_underrun_disabled; | |
0b2ae6d7 VS |
641 | |
642 | /* per-pipe watermark state */ | |
643 | struct { | |
644 | /* watermarks currently being used */ | |
4e0963c7 MR |
645 | union { |
646 | struct intel_pipe_wm ilk; | |
647 | struct skl_pipe_wm skl; | |
648 | } active; | |
ed4a6a7c | 649 | |
852eb00d VS |
650 | /* allow CxSR on this pipe */ |
651 | bool cxsr_allowed; | |
0b2ae6d7 | 652 | } wm; |
8d7849db | 653 | |
80715b2f | 654 | int scanline_offset; |
32b7eeec | 655 | |
eb120ef6 JB |
656 | struct { |
657 | unsigned start_vbl_count; | |
658 | ktime_t start_vbl_time; | |
659 | int min_vbl, max_vbl; | |
660 | int scanline_start; | |
661 | } debug; | |
85a62bf9 | 662 | |
be41e336 CK |
663 | /* scalers available on this crtc */ |
664 | int num_scalers; | |
262cd2e1 VS |
665 | |
666 | struct vlv_wm_state wm_state; | |
79e53945 JB |
667 | }; |
668 | ||
c35426d2 VS |
669 | struct intel_plane_wm_parameters { |
670 | uint32_t horiz_pixels; | |
ed57cb8a | 671 | uint32_t vert_pixels; |
2cd601c6 CK |
672 | /* |
673 | * For packed pixel formats: | |
674 | * bytes_per_pixel - holds bytes per pixel | |
675 | * For planar pixel formats: | |
676 | * bytes_per_pixel - holds bytes per pixel for uv-plane | |
677 | * y_bytes_per_pixel - holds bytes per pixel for y-plane | |
678 | */ | |
c35426d2 | 679 | uint8_t bytes_per_pixel; |
2cd601c6 | 680 | uint8_t y_bytes_per_pixel; |
c35426d2 VS |
681 | bool enabled; |
682 | bool scaled; | |
0fda6568 | 683 | u64 tiling; |
1fc0a8f7 | 684 | unsigned int rotation; |
6eb1a681 | 685 | uint16_t fifo_size; |
c35426d2 VS |
686 | }; |
687 | ||
b840d907 JB |
688 | struct intel_plane { |
689 | struct drm_plane base; | |
7f1f3851 | 690 | int plane; |
b840d907 | 691 | enum pipe pipe; |
2d354c34 | 692 | bool can_scale; |
b840d907 | 693 | int max_downscale; |
a9ff8714 | 694 | uint32_t frontbuffer_bit; |
526682e9 PZ |
695 | |
696 | /* Since we need to change the watermarks before/after | |
697 | * enabling/disabling the planes, we need to store the parameters here | |
698 | * as the other pieces of the struct may not reflect the values we want | |
699 | * for the watermark calculations. Currently only Haswell uses this. | |
700 | */ | |
c35426d2 | 701 | struct intel_plane_wm_parameters wm; |
526682e9 | 702 | |
8e7d688b MR |
703 | /* |
704 | * NOTE: Do not place new plane state fields here (e.g., when adding | |
705 | * new plane properties). New runtime state should now be placed in | |
2fde1391 | 706 | * the intel_plane_state structure and accessed via plane_state. |
8e7d688b MR |
707 | */ |
708 | ||
b840d907 | 709 | void (*update_plane)(struct drm_plane *plane, |
2fde1391 ML |
710 | const struct intel_crtc_state *crtc_state, |
711 | const struct intel_plane_state *plane_state); | |
b39d53f6 | 712 | void (*disable_plane)(struct drm_plane *plane, |
7fabf5ef | 713 | struct drm_crtc *crtc); |
c59cb179 | 714 | int (*check_plane)(struct drm_plane *plane, |
061e4b8d | 715 | struct intel_crtc_state *crtc_state, |
c59cb179 | 716 | struct intel_plane_state *state); |
b840d907 JB |
717 | }; |
718 | ||
b445e3b0 ED |
719 | struct intel_watermark_params { |
720 | unsigned long fifo_size; | |
721 | unsigned long max_wm; | |
722 | unsigned long default_wm; | |
723 | unsigned long guard_size; | |
724 | unsigned long cacheline_size; | |
725 | }; | |
726 | ||
727 | struct cxsr_latency { | |
728 | int is_desktop; | |
729 | int is_ddr3; | |
730 | unsigned long fsb_freq; | |
731 | unsigned long mem_freq; | |
732 | unsigned long display_sr; | |
733 | unsigned long display_hpll_disable; | |
734 | unsigned long cursor_sr; | |
735 | unsigned long cursor_hpll_disable; | |
736 | }; | |
737 | ||
de419ab6 | 738 | #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base) |
79e53945 | 739 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
10f81c19 | 740 | #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base) |
5daa55eb | 741 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
4ef69c7a | 742 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
79e53945 | 743 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
b840d907 | 744 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
ea2c67bb | 745 | #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base) |
155e6369 | 746 | #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL) |
79e53945 | 747 | |
f5bbfca3 | 748 | struct intel_hdmi { |
f0f59a00 | 749 | i915_reg_t hdmi_reg; |
f5bbfca3 | 750 | int ddc_bus; |
0f2a2a75 | 751 | bool limited_color_range; |
55bc60db | 752 | bool color_range_auto; |
f5bbfca3 ED |
753 | bool has_hdmi_sink; |
754 | bool has_audio; | |
755 | enum hdmi_force_audio force_audio; | |
abedc077 | 756 | bool rgb_quant_range_selectable; |
94a11ddc | 757 | enum hdmi_picture_aspect aspect_ratio; |
d8b4c43a | 758 | struct intel_connector *attached_connector; |
f5bbfca3 | 759 | void (*write_infoframe)(struct drm_encoder *encoder, |
178f736a | 760 | enum hdmi_infoframe_type type, |
fff63867 | 761 | const void *frame, ssize_t len); |
687f4d06 | 762 | void (*set_infoframes)(struct drm_encoder *encoder, |
6897b4b5 | 763 | bool enable, |
7c5f93b0 | 764 | const struct drm_display_mode *adjusted_mode); |
cda0aaaf VS |
765 | bool (*infoframe_enabled)(struct drm_encoder *encoder, |
766 | const struct intel_crtc_state *pipe_config); | |
f5bbfca3 ED |
767 | }; |
768 | ||
0e32b39c | 769 | struct intel_dp_mst_encoder; |
b091cd92 | 770 | #define DP_MAX_DOWNSTREAM_PORTS 0x10 |
54d63ca6 | 771 | |
fe3cd48d R |
772 | /* |
773 | * enum link_m_n_set: | |
774 | * When platform provides two set of M_N registers for dp, we can | |
775 | * program them and switch between them incase of DRRS. | |
776 | * But When only one such register is provided, we have to program the | |
777 | * required divider value on that registers itself based on the DRRS state. | |
778 | * | |
779 | * M1_N1 : Program dp_m_n on M1_N1 registers | |
780 | * dp_m2_n2 on M2_N2 registers (If supported) | |
781 | * | |
782 | * M2_N2 : Program dp_m2_n2 on M1_N1 registers | |
783 | * M2_N2 registers are not supported | |
784 | */ | |
785 | ||
786 | enum link_m_n_set { | |
787 | /* Sets the m1_n1 and m2_n2 */ | |
788 | M1_N1 = 0, | |
789 | M2_N2 | |
790 | }; | |
791 | ||
54d63ca6 | 792 | struct intel_dp { |
f0f59a00 VS |
793 | i915_reg_t output_reg; |
794 | i915_reg_t aux_ch_ctl_reg; | |
795 | i915_reg_t aux_ch_data_reg[5]; | |
54d63ca6 | 796 | uint32_t DP; |
901c2daf VS |
797 | int link_rate; |
798 | uint8_t lane_count; | |
30d9aa42 | 799 | uint8_t sink_count; |
54d63ca6 | 800 | bool has_audio; |
7d23e3c3 | 801 | bool detect_done; |
54d63ca6 | 802 | enum hdmi_force_audio force_audio; |
0f2a2a75 | 803 | bool limited_color_range; |
55bc60db | 804 | bool color_range_auto; |
54d63ca6 | 805 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; |
2293bb5c | 806 | uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; |
b091cd92 | 807 | uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; |
94ca719e VS |
808 | /* sink rates as reported by DP_SUPPORTED_LINK_RATES */ |
809 | uint8_t num_sink_rates; | |
810 | int sink_rates[DP_MAX_SUPPORTED_RATES]; | |
9d1a1031 | 811 | struct drm_dp_aux aux; |
54d63ca6 SK |
812 | uint8_t train_set[4]; |
813 | int panel_power_up_delay; | |
814 | int panel_power_down_delay; | |
815 | int panel_power_cycle_delay; | |
816 | int backlight_on_delay; | |
817 | int backlight_off_delay; | |
54d63ca6 SK |
818 | struct delayed_work panel_vdd_work; |
819 | bool want_panel_vdd; | |
dce56b3c PZ |
820 | unsigned long last_power_on; |
821 | unsigned long last_backlight_off; | |
d28d4731 | 822 | ktime_t panel_power_off_time; |
5d42f82a | 823 | |
01527b31 CT |
824 | struct notifier_block edp_notifier; |
825 | ||
a4a5d2f8 VS |
826 | /* |
827 | * Pipe whose power sequencer is currently locked into | |
828 | * this port. Only relevant on VLV/CHV. | |
829 | */ | |
830 | enum pipe pps_pipe; | |
36b5f425 | 831 | struct edp_power_seq pps_delays; |
a4a5d2f8 | 832 | |
0e32b39c DA |
833 | bool can_mst; /* this port supports mst */ |
834 | bool is_mst; | |
835 | int active_mst_links; | |
836 | /* connector directly attached - won't be use for modeset in mst world */ | |
dd06f90e | 837 | struct intel_connector *attached_connector; |
ec5b01dd | 838 | |
0e32b39c DA |
839 | /* mst connector list */ |
840 | struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; | |
841 | struct drm_dp_mst_topology_mgr mst_mgr; | |
842 | ||
ec5b01dd | 843 | uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index); |
153b1100 DL |
844 | /* |
845 | * This function returns the value we have to program the AUX_CTL | |
846 | * register with to kick off an AUX transaction. | |
847 | */ | |
848 | uint32_t (*get_aux_send_ctl)(struct intel_dp *dp, | |
849 | bool has_aux_irq, | |
850 | int send_bytes, | |
851 | uint32_t aux_clock_divider); | |
ad64217b ACO |
852 | |
853 | /* This is called before a link training is starterd */ | |
854 | void (*prepare_link_retrain)(struct intel_dp *intel_dp); | |
855 | ||
4e96c977 | 856 | bool train_set_valid; |
c5d5ab7a TP |
857 | |
858 | /* Displayport compliance testing */ | |
859 | unsigned long compliance_test_type; | |
559be30c TP |
860 | unsigned long compliance_test_data; |
861 | bool compliance_test_active; | |
54d63ca6 SK |
862 | }; |
863 | ||
da63a9f2 PZ |
864 | struct intel_digital_port { |
865 | struct intel_encoder base; | |
174edf1f | 866 | enum port port; |
bcf53de4 | 867 | u32 saved_port_bits; |
da63a9f2 PZ |
868 | struct intel_dp dp; |
869 | struct intel_hdmi hdmi; | |
b2c5c181 | 870 | enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool); |
b0b33846 | 871 | bool release_cl2_override; |
ccb1a831 | 872 | uint8_t max_lanes; |
cae666ce TI |
873 | /* for communication with audio component; protected by av_mutex */ |
874 | const struct drm_connector *audio_connector; | |
da63a9f2 PZ |
875 | }; |
876 | ||
0e32b39c DA |
877 | struct intel_dp_mst_encoder { |
878 | struct intel_encoder base; | |
879 | enum pipe pipe; | |
880 | struct intel_digital_port *primary; | |
881 | void *port; /* store this opaque as its illegal to dereference it */ | |
882 | }; | |
883 | ||
65d64cc5 | 884 | static inline enum dpio_channel |
89b667f8 JB |
885 | vlv_dport_to_channel(struct intel_digital_port *dport) |
886 | { | |
887 | switch (dport->port) { | |
888 | case PORT_B: | |
00fc31b7 | 889 | case PORT_D: |
e4607fcf | 890 | return DPIO_CH0; |
89b667f8 | 891 | case PORT_C: |
e4607fcf | 892 | return DPIO_CH1; |
89b667f8 JB |
893 | default: |
894 | BUG(); | |
895 | } | |
896 | } | |
897 | ||
65d64cc5 VS |
898 | static inline enum dpio_phy |
899 | vlv_dport_to_phy(struct intel_digital_port *dport) | |
900 | { | |
901 | switch (dport->port) { | |
902 | case PORT_B: | |
903 | case PORT_C: | |
904 | return DPIO_PHY0; | |
905 | case PORT_D: | |
906 | return DPIO_PHY1; | |
907 | default: | |
908 | BUG(); | |
909 | } | |
910 | } | |
911 | ||
912 | static inline enum dpio_channel | |
eb69b0e5 CML |
913 | vlv_pipe_to_channel(enum pipe pipe) |
914 | { | |
915 | switch (pipe) { | |
916 | case PIPE_A: | |
917 | case PIPE_C: | |
918 | return DPIO_CH0; | |
919 | case PIPE_B: | |
920 | return DPIO_CH1; | |
921 | default: | |
922 | BUG(); | |
923 | } | |
924 | } | |
925 | ||
f875c15a CW |
926 | static inline struct drm_crtc * |
927 | intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) | |
928 | { | |
929 | struct drm_i915_private *dev_priv = dev->dev_private; | |
930 | return dev_priv->pipe_to_crtc_mapping[pipe]; | |
931 | } | |
932 | ||
417ae147 CW |
933 | static inline struct drm_crtc * |
934 | intel_get_crtc_for_plane(struct drm_device *dev, int plane) | |
935 | { | |
936 | struct drm_i915_private *dev_priv = dev->dev_private; | |
937 | return dev_priv->plane_to_crtc_mapping[plane]; | |
938 | } | |
939 | ||
4e5359cd SF |
940 | struct intel_unpin_work { |
941 | struct work_struct work; | |
b4a98e57 | 942 | struct drm_crtc *crtc; |
ab8d6675 | 943 | struct drm_framebuffer *old_fb; |
05394f39 | 944 | struct drm_i915_gem_object *pending_flip_obj; |
4e5359cd | 945 | struct drm_pending_vblank_event *event; |
e7d841ca CW |
946 | atomic_t pending; |
947 | #define INTEL_FLIP_INACTIVE 0 | |
948 | #define INTEL_FLIP_PENDING 1 | |
949 | #define INTEL_FLIP_COMPLETE 2 | |
75f7f3ec VS |
950 | u32 flip_count; |
951 | u32 gtt_offset; | |
f06cc1b9 | 952 | struct drm_i915_gem_request *flip_queued_req; |
66f59c5c VS |
953 | u32 flip_queued_vblank; |
954 | u32 flip_ready_vblank; | |
4e5359cd SF |
955 | bool enable_stall_check; |
956 | }; | |
957 | ||
5f1aae65 | 958 | struct intel_load_detect_pipe { |
edde3617 | 959 | struct drm_atomic_state *restore_state; |
5f1aae65 | 960 | }; |
79e53945 | 961 | |
5f1aae65 PZ |
962 | static inline struct intel_encoder * |
963 | intel_attached_encoder(struct drm_connector *connector) | |
df0e9248 CW |
964 | { |
965 | return to_intel_connector(connector)->encoder; | |
966 | } | |
967 | ||
da63a9f2 PZ |
968 | static inline struct intel_digital_port * |
969 | enc_to_dig_port(struct drm_encoder *encoder) | |
970 | { | |
971 | return container_of(encoder, struct intel_digital_port, base.base); | |
9ff8c9ba ID |
972 | } |
973 | ||
0e32b39c DA |
974 | static inline struct intel_dp_mst_encoder * |
975 | enc_to_mst(struct drm_encoder *encoder) | |
976 | { | |
977 | return container_of(encoder, struct intel_dp_mst_encoder, base.base); | |
978 | } | |
979 | ||
9ff8c9ba ID |
980 | static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
981 | { | |
982 | return &enc_to_dig_port(encoder)->dp; | |
da63a9f2 PZ |
983 | } |
984 | ||
985 | static inline struct intel_digital_port * | |
986 | dp_to_dig_port(struct intel_dp *intel_dp) | |
987 | { | |
988 | return container_of(intel_dp, struct intel_digital_port, dp); | |
989 | } | |
990 | ||
991 | static inline struct intel_digital_port * | |
992 | hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) | |
993 | { | |
994 | return container_of(intel_hdmi, struct intel_digital_port, hdmi); | |
7739c33b PZ |
995 | } |
996 | ||
6af31a65 DL |
997 | /* |
998 | * Returns the number of planes for this pipe, ie the number of sprites + 1 | |
999 | * (primary plane). This doesn't count the cursor plane then. | |
1000 | */ | |
1001 | static inline unsigned int intel_num_planes(struct intel_crtc *crtc) | |
1002 | { | |
1003 | return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1; | |
1004 | } | |
5f1aae65 | 1005 | |
47339cd9 | 1006 | /* intel_fifo_underrun.c */ |
a72e4c9f | 1007 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, |
87440425 | 1008 | enum pipe pipe, bool enable); |
a72e4c9f | 1009 | bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, |
87440425 PZ |
1010 | enum transcoder pch_transcoder, |
1011 | bool enable); | |
1f7247c0 DV |
1012 | void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, |
1013 | enum pipe pipe); | |
1014 | void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, | |
1015 | enum transcoder pch_transcoder); | |
aca7b684 VS |
1016 | void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv); |
1017 | void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv); | |
47339cd9 DV |
1018 | |
1019 | /* i915_irq.c */ | |
480c8033 DV |
1020 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
1021 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
1022 | void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
1023 | void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
3cc134e3 | 1024 | void gen6_reset_rps_interrupts(struct drm_device *dev); |
b900b949 ID |
1025 | void gen6_enable_rps_interrupts(struct drm_device *dev); |
1026 | void gen6_disable_rps_interrupts(struct drm_device *dev); | |
59d02a1f | 1027 | u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask); |
b963291c DV |
1028 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv); |
1029 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv); | |
9df7575f JB |
1030 | static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv) |
1031 | { | |
1032 | /* | |
1033 | * We only use drm_irq_uninstall() at unload and VT switch, so | |
1034 | * this is the only thing we need to check. | |
1035 | */ | |
2aeb7d3a | 1036 | return dev_priv->pm.irqs_enabled; |
9df7575f JB |
1037 | } |
1038 | ||
a225f079 | 1039 | int intel_get_crtc_scanline(struct intel_crtc *crtc); |
4c6c03be DL |
1040 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, |
1041 | unsigned int pipe_mask); | |
aae8ba84 VS |
1042 | void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, |
1043 | unsigned int pipe_mask); | |
5f1aae65 | 1044 | |
5f1aae65 | 1045 | /* intel_crt.c */ |
87440425 | 1046 | void intel_crt_init(struct drm_device *dev); |
5f1aae65 PZ |
1047 | |
1048 | ||
1049 | /* intel_ddi.c */ | |
e404ba8d VS |
1050 | void intel_ddi_clk_select(struct intel_encoder *encoder, |
1051 | const struct intel_crtc_state *pipe_config); | |
6a7e4f99 | 1052 | void intel_prepare_ddi_buffer(struct intel_encoder *encoder); |
87440425 PZ |
1053 | void hsw_fdi_link_train(struct drm_crtc *crtc); |
1054 | void intel_ddi_init(struct drm_device *dev, enum port port); | |
1055 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder); | |
1056 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); | |
87440425 PZ |
1057 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc); |
1058 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, | |
1059 | enum transcoder cpu_transcoder); | |
1060 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); | |
1061 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); | |
190f68c5 ACO |
1062 | bool intel_ddi_pll_select(struct intel_crtc *crtc, |
1063 | struct intel_crtc_state *crtc_state); | |
87440425 | 1064 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); |
ad64217b | 1065 | void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp); |
87440425 PZ |
1066 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); |
1067 | void intel_ddi_fdi_disable(struct drm_crtc *crtc); | |
3d52ccf5 LY |
1068 | bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, |
1069 | struct intel_crtc *intel_crtc); | |
87440425 | 1070 | void intel_ddi_get_config(struct intel_encoder *encoder, |
5cec258b | 1071 | struct intel_crtc_state *pipe_config); |
bcddf610 S |
1072 | struct intel_encoder * |
1073 | intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state); | |
5f1aae65 | 1074 | |
44905a27 | 1075 | void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder); |
0e32b39c | 1076 | void intel_ddi_clock_get(struct intel_encoder *encoder, |
5cec258b | 1077 | struct intel_crtc_state *pipe_config); |
0e32b39c | 1078 | void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state); |
f8896f5d | 1079 | uint32_t ddi_signal_levels(struct intel_dp *intel_dp); |
5f1aae65 | 1080 | |
b680c37a | 1081 | /* intel_frontbuffer.c */ |
f99d7069 | 1082 | void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj, |
a4001f1b | 1083 | enum fb_op_origin origin); |
f99d7069 DV |
1084 | void intel_frontbuffer_flip_prepare(struct drm_device *dev, |
1085 | unsigned frontbuffer_bits); | |
1086 | void intel_frontbuffer_flip_complete(struct drm_device *dev, | |
1087 | unsigned frontbuffer_bits); | |
f99d7069 | 1088 | void intel_frontbuffer_flip(struct drm_device *dev, |
fdbff928 | 1089 | unsigned frontbuffer_bits); |
6761dd31 TU |
1090 | unsigned int intel_fb_align_height(struct drm_device *dev, |
1091 | unsigned int height, | |
1092 | uint32_t pixel_format, | |
1093 | uint64_t fb_format_modifier); | |
de152b62 RV |
1094 | void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire, |
1095 | enum fb_op_origin origin); | |
7b49f948 VS |
1096 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
1097 | uint64_t fb_modifier, uint32_t pixel_format); | |
b680c37a | 1098 | |
7c10a2b5 | 1099 | /* intel_audio.c */ |
88212941 | 1100 | void intel_init_audio_hooks(struct drm_i915_private *dev_priv); |
69bfe1a9 JN |
1101 | void intel_audio_codec_enable(struct intel_encoder *encoder); |
1102 | void intel_audio_codec_disable(struct intel_encoder *encoder); | |
58fddc28 ID |
1103 | void i915_audio_component_init(struct drm_i915_private *dev_priv); |
1104 | void i915_audio_component_cleanup(struct drm_i915_private *dev_priv); | |
7c10a2b5 | 1105 | |
b680c37a | 1106 | /* intel_display.c */ |
c30fec65 VS |
1107 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
1108 | const char *name, u32 reg, int ref_freq); | |
65a3fea0 | 1109 | extern const struct drm_plane_funcs intel_plane_funcs; |
88212941 | 1110 | void intel_init_display_hooks(struct drm_i915_private *dev_priv); |
1663b9d6 | 1111 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info); |
b680c37a | 1112 | bool intel_has_pending_fb_unpin(struct drm_device *dev); |
b680c37a | 1113 | void intel_mark_busy(struct drm_device *dev); |
87440425 PZ |
1114 | void intel_mark_idle(struct drm_device *dev); |
1115 | void intel_crtc_restore_mode(struct drm_crtc *crtc); | |
70e0bd74 | 1116 | int intel_display_suspend(struct drm_device *dev); |
87440425 | 1117 | void intel_encoder_destroy(struct drm_encoder *encoder); |
08d9bc92 ACO |
1118 | int intel_connector_init(struct intel_connector *); |
1119 | struct intel_connector *intel_connector_alloc(void); | |
87440425 | 1120 | bool intel_connector_get_hw_state(struct intel_connector *connector); |
87440425 PZ |
1121 | void intel_connector_attach_encoder(struct intel_connector *connector, |
1122 | struct intel_encoder *encoder); | |
1123 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector); | |
1124 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
1125 | struct drm_crtc *crtc); | |
752aa88a | 1126 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector); |
08d7b3d1 CW |
1127 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
1128 | struct drm_file *file_priv); | |
87440425 PZ |
1129 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1130 | enum pipe pipe); | |
4093561b | 1131 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type); |
4f905cf9 DV |
1132 | static inline void |
1133 | intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
1134 | { | |
1135 | drm_wait_one_vblank(dev, pipe); | |
1136 | } | |
0c241d5b VS |
1137 | static inline void |
1138 | intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe) | |
1139 | { | |
1140 | const struct intel_crtc *crtc = | |
1141 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
1142 | ||
1143 | if (crtc->active) | |
1144 | intel_wait_for_vblank(dev, pipe); | |
1145 | } | |
87440425 | 1146 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); |
e4607fcf | 1147 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1148 | struct intel_digital_port *dport, |
1149 | unsigned int expected_mask); | |
87440425 PZ |
1150 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
1151 | struct drm_display_mode *mode, | |
51fd371b RC |
1152 | struct intel_load_detect_pipe *old, |
1153 | struct drm_modeset_acquire_ctx *ctx); | |
87440425 | 1154 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
1155 | struct intel_load_detect_pipe *old, |
1156 | struct drm_modeset_acquire_ctx *ctx); | |
3465c580 VS |
1157 | int intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, |
1158 | unsigned int rotation); | |
a8bb6818 DV |
1159 | struct drm_framebuffer * |
1160 | __intel_framebuffer_create(struct drm_device *dev, | |
87440425 PZ |
1161 | struct drm_mode_fb_cmd2 *mode_cmd, |
1162 | struct drm_i915_gem_object *obj); | |
87440425 PZ |
1163 | void intel_prepare_page_flip(struct drm_device *dev, int plane); |
1164 | void intel_finish_page_flip(struct drm_device *dev, int pipe); | |
1165 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane); | |
d6bbafa1 | 1166 | void intel_check_page_flip(struct drm_device *dev, int pipe); |
6beb8c23 | 1167 | int intel_prepare_plane_fb(struct drm_plane *plane, |
d136dfee | 1168 | const struct drm_plane_state *new_state); |
38f3ce3a | 1169 | void intel_cleanup_plane_fb(struct drm_plane *plane, |
d136dfee | 1170 | const struct drm_plane_state *old_state); |
a98b3431 MR |
1171 | int intel_plane_atomic_get_property(struct drm_plane *plane, |
1172 | const struct drm_plane_state *state, | |
1173 | struct drm_property *property, | |
1174 | uint64_t *val); | |
1175 | int intel_plane_atomic_set_property(struct drm_plane *plane, | |
1176 | struct drm_plane_state *state, | |
1177 | struct drm_property *property, | |
1178 | uint64_t val); | |
da20eabd ML |
1179 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
1180 | struct drm_plane_state *plane_state); | |
716c2e55 | 1181 | |
832be82f VS |
1182 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
1183 | uint64_t fb_modifier, unsigned int cpp); | |
50470bb0 | 1184 | |
121920fa TU |
1185 | static inline bool |
1186 | intel_rotation_90_or_270(unsigned int rotation) | |
1187 | { | |
1188 | return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270)); | |
1189 | } | |
1190 | ||
3b7a5119 SJ |
1191 | void intel_create_rotation_property(struct drm_device *dev, |
1192 | struct intel_plane *plane); | |
1193 | ||
7abd4b35 ACO |
1194 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1195 | enum pipe pipe); | |
1196 | ||
3f36b937 TU |
1197 | int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
1198 | const struct dpll *dpll); | |
d288f65f | 1199 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe); |
8802e5b6 | 1200 | int lpt_get_iclkip(struct drm_i915_private *dev_priv); |
d288f65f | 1201 | |
716c2e55 | 1202 | /* modesetting asserts */ |
b680c37a DV |
1203 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1204 | enum pipe pipe); | |
55607e8a DV |
1205 | void assert_pll(struct drm_i915_private *dev_priv, |
1206 | enum pipe pipe, bool state); | |
1207 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) | |
1208 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) | |
8563b1e8 LL |
1209 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state); |
1210 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1211 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
55607e8a DV |
1212 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1213 | enum pipe pipe, bool state); | |
1214 | #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) | |
1215 | #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) | |
87440425 | 1216 | void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state); |
b840d907 JB |
1217 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) |
1218 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) | |
4f2d9934 VS |
1219 | u32 intel_compute_tile_offset(int *x, int *y, |
1220 | const struct drm_framebuffer *fb, int plane, | |
8d0deca8 VS |
1221 | unsigned int pitch, |
1222 | unsigned int rotation); | |
7514747d VS |
1223 | void intel_prepare_reset(struct drm_device *dev); |
1224 | void intel_finish_reset(struct drm_device *dev); | |
a14cb6fc PZ |
1225 | void hsw_enable_pc8(struct drm_i915_private *dev_priv); |
1226 | void hsw_disable_pc8(struct drm_i915_private *dev_priv); | |
f8437dd1 VK |
1227 | void broxton_init_cdclk(struct drm_device *dev); |
1228 | void broxton_uninit_cdclk(struct drm_device *dev); | |
5c6706e5 VK |
1229 | void broxton_ddi_phy_init(struct drm_device *dev); |
1230 | void broxton_ddi_phy_uninit(struct drm_device *dev); | |
664326f8 SK |
1231 | void bxt_enable_dc9(struct drm_i915_private *dev_priv); |
1232 | void bxt_disable_dc9(struct drm_i915_private *dev_priv); | |
5d96d8af | 1233 | void skl_init_cdclk(struct drm_i915_private *dev_priv); |
c73666f3 | 1234 | int skl_sanitize_cdclk(struct drm_i915_private *dev_priv); |
5d96d8af | 1235 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv); |
0a9d2bed AM |
1236 | void skl_enable_dc6(struct drm_i915_private *dev_priv); |
1237 | void skl_disable_dc6(struct drm_i915_private *dev_priv); | |
87440425 | 1238 | void intel_dp_get_m_n(struct intel_crtc *crtc, |
5cec258b | 1239 | struct intel_crtc_state *pipe_config); |
fe3cd48d | 1240 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n); |
87440425 | 1241 | int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); |
5ab7b0b7 ID |
1242 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
1243 | intel_clock_t *best_clock); | |
dccbea3b ID |
1244 | int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock); |
1245 | ||
87440425 | 1246 | bool intel_crtc_active(struct drm_crtc *crtc); |
20bc8673 VS |
1247 | void hsw_enable_ips(struct intel_crtc *crtc); |
1248 | void hsw_disable_ips(struct intel_crtc *crtc); | |
319be8ae ID |
1249 | enum intel_display_power_domain |
1250 | intel_display_port_power_domain(struct intel_encoder *intel_encoder); | |
25f78f58 VS |
1251 | enum intel_display_power_domain |
1252 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder); | |
f6a83288 | 1253 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 1254 | struct intel_crtc_state *pipe_config); |
86adf9d7 | 1255 | |
e435d6e5 | 1256 | int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state); |
6156a456 | 1257 | int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state); |
8ea30864 | 1258 | |
44eb0cb9 MK |
1259 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, |
1260 | struct drm_i915_gem_object *obj, | |
1261 | unsigned int plane); | |
dedf278c | 1262 | |
6156a456 CK |
1263 | u32 skl_plane_ctl_format(uint32_t pixel_format); |
1264 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier); | |
1265 | u32 skl_plane_ctl_rotation(unsigned int rotation); | |
121920fa | 1266 | |
eb805623 | 1267 | /* intel_csr.c */ |
f4448375 | 1268 | void intel_csr_ucode_init(struct drm_i915_private *); |
2abc525b | 1269 | void intel_csr_load_program(struct drm_i915_private *); |
f4448375 | 1270 | void intel_csr_ucode_fini(struct drm_i915_private *); |
eb805623 | 1271 | |
5f1aae65 | 1272 | /* intel_dp.c */ |
f0f59a00 | 1273 | void intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port); |
87440425 PZ |
1274 | bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
1275 | struct intel_connector *intel_connector); | |
901c2daf VS |
1276 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
1277 | const struct intel_crtc_state *pipe_config); | |
87440425 | 1278 | void intel_dp_start_link_train(struct intel_dp *intel_dp); |
87440425 PZ |
1279 | void intel_dp_stop_link_train(struct intel_dp *intel_dp); |
1280 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); | |
1281 | void intel_dp_encoder_destroy(struct drm_encoder *encoder); | |
d2e216d0 | 1282 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc); |
87440425 | 1283 | bool intel_dp_compute_config(struct intel_encoder *encoder, |
5cec258b | 1284 | struct intel_crtc_state *pipe_config); |
5d8a7752 | 1285 | bool intel_dp_is_edp(struct drm_device *dev, enum port port); |
b2c5c181 DV |
1286 | enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, |
1287 | bool long_hpd); | |
4be73780 DV |
1288 | void intel_edp_backlight_on(struct intel_dp *intel_dp); |
1289 | void intel_edp_backlight_off(struct intel_dp *intel_dp); | |
24f3e092 | 1290 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp); |
4be73780 DV |
1291 | void intel_edp_panel_on(struct intel_dp *intel_dp); |
1292 | void intel_edp_panel_off(struct intel_dp *intel_dp); | |
0e32b39c DA |
1293 | void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector); |
1294 | void intel_dp_mst_suspend(struct drm_device *dev); | |
1295 | void intel_dp_mst_resume(struct drm_device *dev); | |
50fec21a | 1296 | int intel_dp_max_link_rate(struct intel_dp *intel_dp); |
ed4e9c1d | 1297 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate); |
0e32b39c | 1298 | void intel_dp_hot_plug(struct intel_encoder *intel_encoder); |
773538e8 | 1299 | void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv); |
0bc12bcb | 1300 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes); |
4a3b8769 | 1301 | void intel_plane_destroy(struct drm_plane *plane); |
c395578e VK |
1302 | void intel_edp_drrs_enable(struct intel_dp *intel_dp); |
1303 | void intel_edp_drrs_disable(struct intel_dp *intel_dp); | |
a93fad0f VK |
1304 | void intel_edp_drrs_invalidate(struct drm_device *dev, |
1305 | unsigned frontbuffer_bits); | |
1306 | void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits); | |
237ed86c SJ |
1307 | bool intel_digital_port_connected(struct drm_i915_private *dev_priv, |
1308 | struct intel_digital_port *port); | |
0bc12bcb | 1309 | |
94223d04 ACO |
1310 | void |
1311 | intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, | |
1312 | uint8_t dp_train_pat); | |
1313 | void | |
1314 | intel_dp_set_signal_levels(struct intel_dp *intel_dp); | |
1315 | void intel_dp_set_idle_link_train(struct intel_dp *intel_dp); | |
1316 | uint8_t | |
1317 | intel_dp_voltage_max(struct intel_dp *intel_dp); | |
1318 | uint8_t | |
1319 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing); | |
1320 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, | |
1321 | uint8_t *link_bw, uint8_t *rate_select); | |
e588fa18 | 1322 | bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp); |
94223d04 ACO |
1323 | bool |
1324 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]); | |
1325 | ||
0e32b39c DA |
1326 | /* intel_dp_mst.c */ |
1327 | int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id); | |
1328 | void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port); | |
5f1aae65 | 1329 | /* intel_dsi.c */ |
4328633d | 1330 | void intel_dsi_init(struct drm_device *dev); |
5f1aae65 PZ |
1331 | |
1332 | ||
1333 | /* intel_dvo.c */ | |
87440425 | 1334 | void intel_dvo_init(struct drm_device *dev); |
5f1aae65 PZ |
1335 | |
1336 | ||
0632fef6 | 1337 | /* legacy fbdev emulation in intel_fbdev.c */ |
0695726e | 1338 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
4520f53a | 1339 | extern int intel_fbdev_init(struct drm_device *dev); |
e00bf696 | 1340 | extern void intel_fbdev_initial_config_async(struct drm_device *dev); |
4520f53a | 1341 | extern void intel_fbdev_fini(struct drm_device *dev); |
82e3b8c1 | 1342 | extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous); |
0632fef6 DV |
1343 | extern void intel_fbdev_output_poll_changed(struct drm_device *dev); |
1344 | extern void intel_fbdev_restore_mode(struct drm_device *dev); | |
4520f53a DV |
1345 | #else |
1346 | static inline int intel_fbdev_init(struct drm_device *dev) | |
1347 | { | |
1348 | return 0; | |
1349 | } | |
5f1aae65 | 1350 | |
e00bf696 | 1351 | static inline void intel_fbdev_initial_config_async(struct drm_device *dev) |
4520f53a DV |
1352 | { |
1353 | } | |
1354 | ||
1355 | static inline void intel_fbdev_fini(struct drm_device *dev) | |
1356 | { | |
1357 | } | |
1358 | ||
82e3b8c1 | 1359 | static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous) |
4520f53a DV |
1360 | { |
1361 | } | |
1362 | ||
0632fef6 | 1363 | static inline void intel_fbdev_restore_mode(struct drm_device *dev) |
4520f53a DV |
1364 | { |
1365 | } | |
1366 | #endif | |
5f1aae65 | 1367 | |
7ff0ebcc | 1368 | /* intel_fbc.c */ |
f51be2e0 PZ |
1369 | void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, |
1370 | struct drm_atomic_state *state); | |
0e631adc | 1371 | bool intel_fbc_is_active(struct drm_i915_private *dev_priv); |
1eb52238 PZ |
1372 | void intel_fbc_pre_update(struct intel_crtc *crtc); |
1373 | void intel_fbc_post_update(struct intel_crtc *crtc); | |
7ff0ebcc | 1374 | void intel_fbc_init(struct drm_i915_private *dev_priv); |
010cf73d | 1375 | void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv); |
d029bcad | 1376 | void intel_fbc_enable(struct intel_crtc *crtc); |
c937ab3e PZ |
1377 | void intel_fbc_disable(struct intel_crtc *crtc); |
1378 | void intel_fbc_global_disable(struct drm_i915_private *dev_priv); | |
dbef0f15 PZ |
1379 | void intel_fbc_invalidate(struct drm_i915_private *dev_priv, |
1380 | unsigned int frontbuffer_bits, | |
1381 | enum fb_op_origin origin); | |
1382 | void intel_fbc_flush(struct drm_i915_private *dev_priv, | |
6f4551fe | 1383 | unsigned int frontbuffer_bits, enum fb_op_origin origin); |
7733b49b | 1384 | void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv); |
7ff0ebcc | 1385 | |
5f1aae65 | 1386 | /* intel_hdmi.c */ |
f0f59a00 | 1387 | void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port); |
87440425 PZ |
1388 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
1389 | struct intel_connector *intel_connector); | |
1390 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); | |
1391 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, | |
5cec258b | 1392 | struct intel_crtc_state *pipe_config); |
5f1aae65 PZ |
1393 | |
1394 | ||
1395 | /* intel_lvds.c */ | |
87440425 PZ |
1396 | void intel_lvds_init(struct drm_device *dev); |
1397 | bool intel_is_dual_link_lvds(struct drm_device *dev); | |
5f1aae65 PZ |
1398 | |
1399 | ||
1400 | /* intel_modes.c */ | |
1401 | int intel_connector_update_modes(struct drm_connector *connector, | |
87440425 | 1402 | struct edid *edid); |
5f1aae65 | 1403 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); |
87440425 PZ |
1404 | void intel_attach_force_audio_property(struct drm_connector *connector); |
1405 | void intel_attach_broadcast_rgb_property(struct drm_connector *connector); | |
7949dd47 | 1406 | void intel_attach_aspect_ratio_property(struct drm_connector *connector); |
5f1aae65 PZ |
1407 | |
1408 | ||
1409 | /* intel_overlay.c */ | |
87440425 PZ |
1410 | void intel_setup_overlay(struct drm_device *dev); |
1411 | void intel_cleanup_overlay(struct drm_device *dev); | |
1412 | int intel_overlay_switch_off(struct intel_overlay *overlay); | |
1413 | int intel_overlay_put_image(struct drm_device *dev, void *data, | |
1414 | struct drm_file *file_priv); | |
1415 | int intel_overlay_attrs(struct drm_device *dev, void *data, | |
1416 | struct drm_file *file_priv); | |
1362b776 | 1417 | void intel_overlay_reset(struct drm_i915_private *dev_priv); |
5f1aae65 PZ |
1418 | |
1419 | ||
1420 | /* intel_panel.c */ | |
87440425 | 1421 | int intel_panel_init(struct intel_panel *panel, |
4b6ed685 VK |
1422 | struct drm_display_mode *fixed_mode, |
1423 | struct drm_display_mode *downclock_mode); | |
87440425 PZ |
1424 | void intel_panel_fini(struct intel_panel *panel); |
1425 | void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, | |
1426 | struct drm_display_mode *adjusted_mode); | |
1427 | void intel_pch_panel_fitting(struct intel_crtc *crtc, | |
5cec258b | 1428 | struct intel_crtc_state *pipe_config, |
87440425 PZ |
1429 | int fitting_mode); |
1430 | void intel_gmch_panel_fitting(struct intel_crtc *crtc, | |
5cec258b | 1431 | struct intel_crtc_state *pipe_config, |
87440425 | 1432 | int fitting_mode); |
6dda730e JN |
1433 | void intel_panel_set_backlight_acpi(struct intel_connector *connector, |
1434 | u32 level, u32 max); | |
6517d273 | 1435 | int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe); |
752aa88a JB |
1436 | void intel_panel_enable_backlight(struct intel_connector *connector); |
1437 | void intel_panel_disable_backlight(struct intel_connector *connector); | |
db31af1d | 1438 | void intel_panel_destroy_backlight(struct drm_connector *connector); |
87440425 | 1439 | enum drm_connector_status intel_panel_detect(struct drm_device *dev); |
ec9ed197 VK |
1440 | extern struct drm_display_mode *intel_find_panel_downclock( |
1441 | struct drm_device *dev, | |
1442 | struct drm_display_mode *fixed_mode, | |
1443 | struct drm_connector *connector); | |
0962c3c9 VS |
1444 | void intel_backlight_register(struct drm_device *dev); |
1445 | void intel_backlight_unregister(struct drm_device *dev); | |
1446 | ||
5f1aae65 | 1447 | |
0bc12bcb | 1448 | /* intel_psr.c */ |
0bc12bcb RV |
1449 | void intel_psr_enable(struct intel_dp *intel_dp); |
1450 | void intel_psr_disable(struct intel_dp *intel_dp); | |
1451 | void intel_psr_invalidate(struct drm_device *dev, | |
20c8838b | 1452 | unsigned frontbuffer_bits); |
0bc12bcb | 1453 | void intel_psr_flush(struct drm_device *dev, |
169de131 RV |
1454 | unsigned frontbuffer_bits, |
1455 | enum fb_op_origin origin); | |
0bc12bcb | 1456 | void intel_psr_init(struct drm_device *dev); |
20c8838b DV |
1457 | void intel_psr_single_frame_update(struct drm_device *dev, |
1458 | unsigned frontbuffer_bits); | |
0bc12bcb | 1459 | |
9c065a7d DV |
1460 | /* intel_runtime_pm.c */ |
1461 | int intel_power_domains_init(struct drm_i915_private *); | |
f458ebbc | 1462 | void intel_power_domains_fini(struct drm_i915_private *); |
73dfc227 ID |
1463 | void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume); |
1464 | void intel_power_domains_suspend(struct drm_i915_private *dev_priv); | |
2f693e28 DL |
1465 | void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv); |
1466 | void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv); | |
f458ebbc | 1467 | void intel_runtime_pm_enable(struct drm_i915_private *dev_priv); |
9895ad03 DS |
1468 | const char * |
1469 | intel_display_power_domain_str(enum intel_display_power_domain domain); | |
9c065a7d | 1470 | |
f458ebbc DV |
1471 | bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
1472 | enum intel_display_power_domain domain); | |
1473 | bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, | |
1474 | enum intel_display_power_domain domain); | |
9c065a7d DV |
1475 | void intel_display_power_get(struct drm_i915_private *dev_priv, |
1476 | enum intel_display_power_domain domain); | |
09731280 ID |
1477 | bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, |
1478 | enum intel_display_power_domain domain); | |
9c065a7d DV |
1479 | void intel_display_power_put(struct drm_i915_private *dev_priv, |
1480 | enum intel_display_power_domain domain); | |
da5827c3 ID |
1481 | |
1482 | static inline void | |
1483 | assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv) | |
1484 | { | |
1485 | WARN_ONCE(dev_priv->pm.suspended, | |
1486 | "Device suspended during HW access\n"); | |
1487 | } | |
1488 | ||
1489 | static inline void | |
1490 | assert_rpm_wakelock_held(struct drm_i915_private *dev_priv) | |
1491 | { | |
1492 | assert_rpm_device_not_suspended(dev_priv); | |
becd9ca2 DV |
1493 | /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes |
1494 | * too much noise. */ | |
1495 | if (!atomic_read(&dev_priv->pm.wakeref_count)) | |
1496 | DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access"); | |
da5827c3 ID |
1497 | } |
1498 | ||
2b19efeb ID |
1499 | static inline int |
1500 | assert_rpm_atomic_begin(struct drm_i915_private *dev_priv) | |
1501 | { | |
1502 | int seq = atomic_read(&dev_priv->pm.atomic_seq); | |
1503 | ||
1504 | assert_rpm_wakelock_held(dev_priv); | |
1505 | ||
1506 | return seq; | |
1507 | } | |
1508 | ||
1509 | static inline void | |
1510 | assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq) | |
1511 | { | |
1512 | WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq, | |
1513 | "HW access outside of RPM atomic section\n"); | |
1514 | } | |
1515 | ||
1f814dac ID |
1516 | /** |
1517 | * disable_rpm_wakeref_asserts - disable the RPM assert checks | |
1518 | * @dev_priv: i915 device instance | |
1519 | * | |
1520 | * This function disable asserts that check if we hold an RPM wakelock | |
1521 | * reference, while keeping the device-not-suspended checks still enabled. | |
1522 | * It's meant to be used only in special circumstances where our rule about | |
1523 | * the wakelock refcount wrt. the device power state doesn't hold. According | |
1524 | * to this rule at any point where we access the HW or want to keep the HW in | |
1525 | * an active state we must hold an RPM wakelock reference acquired via one of | |
1526 | * the intel_runtime_pm_get() helpers. Currently there are a few special spots | |
1527 | * where this rule doesn't hold: the IRQ and suspend/resume handlers, the | |
1528 | * forcewake release timer, and the GPU RPS and hangcheck works. All other | |
1529 | * users should avoid using this function. | |
1530 | * | |
1531 | * Any calls to this function must have a symmetric call to | |
1532 | * enable_rpm_wakeref_asserts(). | |
1533 | */ | |
1534 | static inline void | |
1535 | disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv) | |
1536 | { | |
1537 | atomic_inc(&dev_priv->pm.wakeref_count); | |
1538 | } | |
1539 | ||
1540 | /** | |
1541 | * enable_rpm_wakeref_asserts - re-enable the RPM assert checks | |
1542 | * @dev_priv: i915 device instance | |
1543 | * | |
1544 | * This function re-enables the RPM assert checks after disabling them with | |
1545 | * disable_rpm_wakeref_asserts. It's meant to be used only in special | |
1546 | * circumstances otherwise its use should be avoided. | |
1547 | * | |
1548 | * Any calls to this function must have a symmetric call to | |
1549 | * disable_rpm_wakeref_asserts(). | |
1550 | */ | |
1551 | static inline void | |
1552 | enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv) | |
1553 | { | |
1554 | atomic_dec(&dev_priv->pm.wakeref_count); | |
1555 | } | |
1556 | ||
1557 | /* TODO: convert users of these to rely instead on proper RPM refcounting */ | |
1558 | #define DISABLE_RPM_WAKEREF_ASSERTS(dev_priv) \ | |
1559 | disable_rpm_wakeref_asserts(dev_priv) | |
1560 | ||
1561 | #define ENABLE_RPM_WAKEREF_ASSERTS(dev_priv) \ | |
1562 | enable_rpm_wakeref_asserts(dev_priv) | |
1563 | ||
9c065a7d | 1564 | void intel_runtime_pm_get(struct drm_i915_private *dev_priv); |
09731280 | 1565 | bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv); |
9c065a7d DV |
1566 | void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv); |
1567 | void intel_runtime_pm_put(struct drm_i915_private *dev_priv); | |
1568 | ||
d9bc89d9 DV |
1569 | void intel_display_set_init_power(struct drm_i915_private *dev, bool enable); |
1570 | ||
e0fce78f VS |
1571 | void chv_phy_powergate_lanes(struct intel_encoder *encoder, |
1572 | bool override, unsigned int mask); | |
b0b33846 VS |
1573 | bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, |
1574 | enum dpio_channel ch, bool override); | |
e0fce78f VS |
1575 | |
1576 | ||
5f1aae65 | 1577 | /* intel_pm.c */ |
87440425 PZ |
1578 | void intel_init_clock_gating(struct drm_device *dev); |
1579 | void intel_suspend_hw(struct drm_device *dev); | |
546c81fd | 1580 | int ilk_wm_max_level(const struct drm_device *dev); |
87440425 | 1581 | void intel_update_watermarks(struct drm_crtc *crtc); |
87440425 | 1582 | void intel_init_pm(struct drm_device *dev); |
bb400da9 | 1583 | void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv); |
f742a552 | 1584 | void intel_pm_setup(struct drm_device *dev); |
87440425 PZ |
1585 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv); |
1586 | void intel_gpu_ips_teardown(void); | |
ae48434c ID |
1587 | void intel_init_gt_powersave(struct drm_device *dev); |
1588 | void intel_cleanup_gt_powersave(struct drm_device *dev); | |
87440425 PZ |
1589 | void intel_enable_gt_powersave(struct drm_device *dev); |
1590 | void intel_disable_gt_powersave(struct drm_device *dev); | |
156c7ca0 | 1591 | void intel_suspend_gt_powersave(struct drm_device *dev); |
c6df39b5 | 1592 | void intel_reset_gt_powersave(struct drm_device *dev); |
c67a470b | 1593 | void gen6_update_ring_freq(struct drm_device *dev); |
43cf3bf0 CW |
1594 | void gen6_rps_busy(struct drm_i915_private *dev_priv); |
1595 | void gen6_rps_reset_ei(struct drm_i915_private *dev_priv); | |
076e29f2 | 1596 | void gen6_rps_idle(struct drm_i915_private *dev_priv); |
1854d5ca | 1597 | void gen6_rps_boost(struct drm_i915_private *dev_priv, |
e61b9958 CW |
1598 | struct intel_rps_client *rps, |
1599 | unsigned long submitted); | |
6ad790c0 | 1600 | void intel_queue_rps_boost_for_request(struct drm_device *dev, |
eed29a5b | 1601 | struct drm_i915_gem_request *req); |
6eb1a681 | 1602 | void vlv_wm_get_hw_state(struct drm_device *dev); |
243e6a44 | 1603 | void ilk_wm_get_hw_state(struct drm_device *dev); |
3078999f | 1604 | void skl_wm_get_hw_state(struct drm_device *dev); |
08db6652 DL |
1605 | void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, |
1606 | struct skl_ddb_allocation *ddb /* out */); | |
8cfb3407 | 1607 | uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config); |
ed4a6a7c | 1608 | bool ilk_disable_lp_wm(struct drm_device *dev); |
274008e8 | 1609 | int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6); |
72662e10 | 1610 | |
5f1aae65 | 1611 | /* intel_sdvo.c */ |
f0f59a00 VS |
1612 | bool intel_sdvo_init(struct drm_device *dev, |
1613 | i915_reg_t reg, enum port port); | |
96a02917 | 1614 | |
2b28bb1b | 1615 | |
5f1aae65 | 1616 | /* intel_sprite.c */ |
87440425 | 1617 | int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); |
87440425 PZ |
1618 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
1619 | struct drm_file *file_priv); | |
34e0adbb ML |
1620 | void intel_pipe_update_start(struct intel_crtc *crtc); |
1621 | void intel_pipe_update_end(struct intel_crtc *crtc); | |
5f1aae65 PZ |
1622 | |
1623 | /* intel_tv.c */ | |
87440425 | 1624 | void intel_tv_init(struct drm_device *dev); |
20ddf665 | 1625 | |
ea2c67bb | 1626 | /* intel_atomic.c */ |
2545e4a6 MR |
1627 | int intel_connector_atomic_get_property(struct drm_connector *connector, |
1628 | const struct drm_connector_state *state, | |
1629 | struct drm_property *property, | |
1630 | uint64_t *val); | |
1356837e MR |
1631 | struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc); |
1632 | void intel_crtc_destroy_state(struct drm_crtc *crtc, | |
1633 | struct drm_crtc_state *state); | |
de419ab6 ML |
1634 | struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev); |
1635 | void intel_atomic_state_clear(struct drm_atomic_state *); | |
1636 | struct intel_shared_dpll_config * | |
1637 | intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s); | |
1638 | ||
10f81c19 ACO |
1639 | static inline struct intel_crtc_state * |
1640 | intel_atomic_get_crtc_state(struct drm_atomic_state *state, | |
1641 | struct intel_crtc *crtc) | |
1642 | { | |
1643 | struct drm_crtc_state *crtc_state; | |
1644 | crtc_state = drm_atomic_get_crtc_state(state, &crtc->base); | |
1645 | if (IS_ERR(crtc_state)) | |
0b6cc188 | 1646 | return ERR_CAST(crtc_state); |
10f81c19 ACO |
1647 | |
1648 | return to_intel_crtc_state(crtc_state); | |
1649 | } | |
e3bddded ML |
1650 | |
1651 | static inline struct intel_plane_state * | |
1652 | intel_atomic_get_existing_plane_state(struct drm_atomic_state *state, | |
1653 | struct intel_plane *plane) | |
1654 | { | |
1655 | struct drm_plane_state *plane_state; | |
1656 | ||
1657 | plane_state = drm_atomic_get_existing_plane_state(state, &plane->base); | |
1658 | ||
1659 | return to_intel_plane_state(plane_state); | |
1660 | } | |
1661 | ||
d03c93d4 CK |
1662 | int intel_atomic_setup_scalers(struct drm_device *dev, |
1663 | struct intel_crtc *intel_crtc, | |
1664 | struct intel_crtc_state *crtc_state); | |
5ee67f1c MR |
1665 | |
1666 | /* intel_atomic_plane.c */ | |
8e7d688b | 1667 | struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane); |
ea2c67bb MR |
1668 | struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane); |
1669 | void intel_plane_destroy_state(struct drm_plane *plane, | |
1670 | struct drm_plane_state *state); | |
1671 | extern const struct drm_plane_helper_funcs intel_plane_helper_funcs; | |
1672 | ||
8563b1e8 LL |
1673 | /* intel_color.c */ |
1674 | void intel_color_init(struct drm_crtc *crtc); | |
82cf435b | 1675 | int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state); |
b95c5321 ML |
1676 | void intel_color_set_csc(struct drm_crtc_state *crtc_state); |
1677 | void intel_color_load_luts(struct drm_crtc_state *crtc_state); | |
8563b1e8 | 1678 | |
79e53945 | 1679 | #endif /* __INTEL_DRV_H__ */ |