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79e53945 JB |
1 | /* |
2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright (c) 2007-2008 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
23 | * IN THE SOFTWARE. | |
24 | */ | |
25 | #ifndef __INTEL_DRV_H__ | |
26 | #define __INTEL_DRV_H__ | |
27 | ||
28 | #include <linux/i2c.h> | |
178f736a | 29 | #include <linux/hdmi.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
80824003 | 31 | #include "i915_drv.h" |
760285e7 DH |
32 | #include <drm/drm_crtc.h> |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/drm_fb_helper.h> | |
612a9aab | 35 | #include <drm/drm_dp_helper.h> |
913d8d11 | 36 | |
1d5bfac9 DV |
37 | /** |
38 | * _wait_for - magic (register) wait macro | |
39 | * | |
40 | * Does the right thing for modeset paths when run under kdgb or similar atomic | |
41 | * contexts. Note that it's important that we check the condition again after | |
42 | * having timed out, since the timeout could be due to preemption or similar and | |
43 | * we've never had a chance to check the condition before the timeout. | |
44 | */ | |
481b6af3 | 45 | #define _wait_for(COND, MS, W) ({ \ |
1d5bfac9 | 46 | unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ |
913d8d11 | 47 | int ret__ = 0; \ |
0206e353 | 48 | while (!(COND)) { \ |
913d8d11 | 49 | if (time_after(jiffies, timeout__)) { \ |
1d5bfac9 DV |
50 | if (!(COND)) \ |
51 | ret__ = -ETIMEDOUT; \ | |
913d8d11 CW |
52 | break; \ |
53 | } \ | |
0cc2764c BW |
54 | if (W && drm_can_sleep()) { \ |
55 | msleep(W); \ | |
56 | } else { \ | |
57 | cpu_relax(); \ | |
58 | } \ | |
913d8d11 CW |
59 | } \ |
60 | ret__; \ | |
61 | }) | |
62 | ||
481b6af3 CW |
63 | #define wait_for(COND, MS) _wait_for(COND, MS, 1) |
64 | #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) | |
6effa33b DV |
65 | #define wait_for_atomic_us(COND, US) _wait_for((COND), \ |
66 | DIV_ROUND_UP((US), 1000), 0) | |
481b6af3 | 67 | |
021357ac CW |
68 | #define KHz(x) (1000*x) |
69 | #define MHz(x) KHz(1000*x) | |
70 | ||
79e53945 JB |
71 | /* |
72 | * Display related stuff | |
73 | */ | |
74 | ||
75 | /* store information about an Ixxx DVO */ | |
76 | /* The i830->i865 use multiple DVOs with multiple i2cs */ | |
77 | /* the i915, i945 have a single sDVO i2c bus - which is different */ | |
78 | #define MAX_OUTPUTS 6 | |
79 | /* maximum connectors per crtcs in the mode set */ | |
79e53945 JB |
80 | |
81 | #define INTEL_I2C_BUS_DVO 1 | |
82 | #define INTEL_I2C_BUS_SDVO 2 | |
83 | ||
84 | /* these are outputs from the chip - integrated only | |
85 | external chips are via DVO or SDVO output */ | |
86 | #define INTEL_OUTPUT_UNUSED 0 | |
87 | #define INTEL_OUTPUT_ANALOG 1 | |
88 | #define INTEL_OUTPUT_DVO 2 | |
89 | #define INTEL_OUTPUT_SDVO 3 | |
90 | #define INTEL_OUTPUT_LVDS 4 | |
91 | #define INTEL_OUTPUT_TVOUT 5 | |
7d57382e | 92 | #define INTEL_OUTPUT_HDMI 6 |
a4fc5ed6 | 93 | #define INTEL_OUTPUT_DISPLAYPORT 7 |
32f9d658 | 94 | #define INTEL_OUTPUT_EDP 8 |
72ffa333 JN |
95 | #define INTEL_OUTPUT_DSI 9 |
96 | #define INTEL_OUTPUT_UNKNOWN 10 | |
79e53945 JB |
97 | |
98 | #define INTEL_DVO_CHIP_NONE 0 | |
99 | #define INTEL_DVO_CHIP_LVDS 1 | |
100 | #define INTEL_DVO_CHIP_TMDS 2 | |
101 | #define INTEL_DVO_CHIP_TVOUT 4 | |
102 | ||
72ffa333 JN |
103 | #define INTEL_DSI_COMMAND_MODE 0 |
104 | #define INTEL_DSI_VIDEO_MODE 1 | |
105 | ||
79e53945 JB |
106 | struct intel_framebuffer { |
107 | struct drm_framebuffer base; | |
05394f39 | 108 | struct drm_i915_gem_object *obj; |
79e53945 JB |
109 | }; |
110 | ||
37811fcc CW |
111 | struct intel_fbdev { |
112 | struct drm_fb_helper helper; | |
113 | struct intel_framebuffer ifb; | |
114 | struct list_head fbdev_list; | |
115 | struct drm_display_mode *our_mode; | |
116 | }; | |
79e53945 | 117 | |
21d40d37 | 118 | struct intel_encoder { |
4ef69c7a | 119 | struct drm_encoder base; |
9a935856 DV |
120 | /* |
121 | * The new crtc this encoder will be driven from. Only differs from | |
122 | * base->crtc while a modeset is in progress. | |
123 | */ | |
124 | struct intel_crtc *new_crtc; | |
125 | ||
79e53945 | 126 | int type; |
66a9278e DV |
127 | /* |
128 | * Intel hw has only one MUX where encoders could be clone, hence a | |
129 | * simple flag is enough to compute the possible_clones mask. | |
130 | */ | |
131 | bool cloneable; | |
5ab432ef | 132 | bool connectors_active; |
21d40d37 | 133 | void (*hot_plug)(struct intel_encoder *); |
7ae89233 DV |
134 | bool (*compute_config)(struct intel_encoder *, |
135 | struct intel_crtc_config *); | |
dafd226c | 136 | void (*pre_pll_enable)(struct intel_encoder *); |
bf49ec8c | 137 | void (*pre_enable)(struct intel_encoder *); |
ef9c3aee | 138 | void (*enable)(struct intel_encoder *); |
6cc5f341 | 139 | void (*mode_set)(struct intel_encoder *intel_encoder); |
ef9c3aee | 140 | void (*disable)(struct intel_encoder *); |
bf49ec8c | 141 | void (*post_disable)(struct intel_encoder *); |
f0947c37 DV |
142 | /* Read out the current hw state of this connector, returning true if |
143 | * the encoder is active. If the encoder is enabled it also set the pipe | |
144 | * it is connected to in the pipe parameter. */ | |
145 | bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); | |
045ac3b5 | 146 | /* Reconstructs the equivalent mode flags for the current hardware |
fdafa9e2 | 147 | * state. This must be called _after_ display->get_pipe_config has |
63000ef6 XZ |
148 | * pre-filled the pipe config. Note that intel_encoder->base.crtc must |
149 | * be set correctly before calling this function. */ | |
045ac3b5 JB |
150 | void (*get_config)(struct intel_encoder *, |
151 | struct intel_crtc_config *pipe_config); | |
f8aed700 | 152 | int crtc_mask; |
1d843f9d | 153 | enum hpd_pin hpd_pin; |
79e53945 JB |
154 | }; |
155 | ||
1d508706 | 156 | struct intel_panel { |
dd06f90e | 157 | struct drm_display_mode *fixed_mode; |
4d891523 | 158 | int fitting_mode; |
58c68779 JN |
159 | |
160 | /* backlight */ | |
161 | struct { | |
c91c9f32 | 162 | bool present; |
58c68779 JN |
163 | u32 level; |
164 | bool enabled; | |
165 | struct backlight_device *device; | |
166 | } backlight; | |
1d508706 JN |
167 | }; |
168 | ||
5daa55eb ZW |
169 | struct intel_connector { |
170 | struct drm_connector base; | |
9a935856 DV |
171 | /* |
172 | * The fixed encoder this connector is connected to. | |
173 | */ | |
df0e9248 | 174 | struct intel_encoder *encoder; |
9a935856 DV |
175 | |
176 | /* | |
177 | * The new encoder this connector will be driven. Only differs from | |
178 | * encoder while a modeset is in progress. | |
179 | */ | |
180 | struct intel_encoder *new_encoder; | |
181 | ||
f0947c37 DV |
182 | /* Reads out the current hw, returning true if the connector is enabled |
183 | * and active (i.e. dpms ON state). */ | |
184 | bool (*get_hw_state)(struct intel_connector *); | |
1d508706 JN |
185 | |
186 | /* Panel info for eDP and LVDS */ | |
187 | struct intel_panel panel; | |
9cd300e0 JN |
188 | |
189 | /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ | |
190 | struct edid *edid; | |
821450c6 EE |
191 | |
192 | /* since POLL and HPD connectors may use the same HPD line keep the native | |
193 | state of connector->polled in case hotplug storm detection changes it */ | |
194 | u8 polled; | |
5daa55eb ZW |
195 | }; |
196 | ||
80ad9206 VS |
197 | typedef struct dpll { |
198 | /* given values */ | |
199 | int n; | |
200 | int m1, m2; | |
201 | int p1, p2; | |
202 | /* derived values */ | |
203 | int dot; | |
204 | int vco; | |
205 | int m; | |
206 | int p; | |
207 | } intel_clock_t; | |
208 | ||
b8cecdf5 | 209 | struct intel_crtc_config { |
bb760063 DV |
210 | /** |
211 | * quirks - bitfield with hw state readout quirks | |
212 | * | |
213 | * For various reasons the hw state readout code might not be able to | |
214 | * completely faithfully read out the current state. These cases are | |
215 | * tracked with quirk flags so that fastboot and state checker can act | |
216 | * accordingly. | |
217 | */ | |
218 | #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ | |
219 | unsigned long quirks; | |
220 | ||
5113bc9b VS |
221 | /* User requested mode, only valid as a starting point to |
222 | * compute adjusted_mode, except in the case of (S)DVO where | |
223 | * it's also for the output timings of the (S)DVO chip. | |
224 | * adjusted_mode will then correspond to the S(DVO) chip's | |
225 | * preferred input timings. */ | |
b8cecdf5 | 226 | struct drm_display_mode requested_mode; |
3c52f4eb | 227 | /* Actual pipe timings ie. what we program into the pipe timing |
241bfc38 | 228 | * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */ |
b8cecdf5 | 229 | struct drm_display_mode adjusted_mode; |
37327abd VS |
230 | |
231 | /* Pipe source size (ie. panel fitter input size) | |
232 | * All planes will be positioned inside this space, | |
233 | * and get clipped at the edges. */ | |
234 | int pipe_src_w, pipe_src_h; | |
235 | ||
5bfe2ac0 DV |
236 | /* Whether to set up the PCH/FDI. Note that we never allow sharing |
237 | * between pch encoders and cpu encoders. */ | |
238 | bool has_pch_encoder; | |
50f3b016 | 239 | |
3b117c8f DV |
240 | /* CPU Transcoder for the pipe. Currently this can only differ from the |
241 | * pipe on Haswell (where we have a special eDP transcoder). */ | |
242 | enum transcoder cpu_transcoder; | |
243 | ||
50f3b016 DV |
244 | /* |
245 | * Use reduced/limited/broadcast rbg range, compressing from the full | |
246 | * range fed into the crtcs. | |
247 | */ | |
248 | bool limited_color_range; | |
249 | ||
03afc4a2 DV |
250 | /* DP has a bunch of special case unfortunately, so mark the pipe |
251 | * accordingly. */ | |
252 | bool has_dp_encoder; | |
d8b32247 DV |
253 | |
254 | /* | |
255 | * Enable dithering, used when the selected pipe bpp doesn't match the | |
256 | * plane bpp. | |
257 | */ | |
965e0c48 | 258 | bool dither; |
f47709a9 DV |
259 | |
260 | /* Controls for the clock computation, to override various stages. */ | |
261 | bool clock_set; | |
262 | ||
09ede541 DV |
263 | /* SDVO TV has a bunch of special case. To make multifunction encoders |
264 | * work correctly, we need to track this at runtime.*/ | |
265 | bool sdvo_tv_clock; | |
266 | ||
e29c22c0 DV |
267 | /* |
268 | * crtc bandwidth limit, don't increase pipe bpp or clock if not really | |
269 | * required. This is set in the 2nd loop of calling encoder's | |
270 | * ->compute_config if the first pick doesn't work out. | |
271 | */ | |
272 | bool bw_constrained; | |
273 | ||
f47709a9 DV |
274 | /* Settings for the intel dpll used on pretty much everything but |
275 | * haswell. */ | |
80ad9206 | 276 | struct dpll dpll; |
f47709a9 | 277 | |
a43f6e0f DV |
278 | /* Selected dpll when shared or DPLL_ID_PRIVATE. */ |
279 | enum intel_dpll_id shared_dpll; | |
280 | ||
66e985c0 DV |
281 | /* Actual register state of the dpll, for shared dpll cross-checking. */ |
282 | struct intel_dpll_hw_state dpll_hw_state; | |
283 | ||
965e0c48 | 284 | int pipe_bpp; |
6cf86a5e | 285 | struct intel_link_m_n dp_m_n; |
ff9a6750 DV |
286 | |
287 | /* | |
288 | * Frequence the dpll for the port should run at. Differs from the | |
3c52f4eb VS |
289 | * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also |
290 | * already multiplied by pixel_multiplier. | |
df92b1e6 | 291 | */ |
ff9a6750 DV |
292 | int port_clock; |
293 | ||
6cc5f341 DV |
294 | /* Used by SDVO (and if we ever fix it, HDMI). */ |
295 | unsigned pixel_multiplier; | |
2dd24552 JB |
296 | |
297 | /* Panel fitter controls for gen2-gen4 + VLV */ | |
b074cec8 JB |
298 | struct { |
299 | u32 control; | |
300 | u32 pgm_ratios; | |
68fc8742 | 301 | u32 lvds_border_bits; |
b074cec8 JB |
302 | } gmch_pfit; |
303 | ||
304 | /* Panel fitter placement and size for Ironlake+ */ | |
305 | struct { | |
306 | u32 pos; | |
307 | u32 size; | |
fd4daa9c | 308 | bool enabled; |
b074cec8 | 309 | } pch_pfit; |
33d29b14 | 310 | |
ca3a0ff8 | 311 | /* FDI configuration, only valid if has_pch_encoder is set. */ |
33d29b14 | 312 | int fdi_lanes; |
ca3a0ff8 | 313 | struct intel_link_m_n fdi_m_n; |
42db64ef PZ |
314 | |
315 | bool ips_enabled; | |
cf532bb2 VS |
316 | |
317 | bool double_wide; | |
b8cecdf5 DV |
318 | }; |
319 | ||
0b2ae6d7 VS |
320 | struct intel_pipe_wm { |
321 | struct intel_wm_level wm[5]; | |
322 | uint32_t linetime; | |
323 | bool fbc_wm_enabled; | |
324 | }; | |
325 | ||
79e53945 JB |
326 | struct intel_crtc { |
327 | struct drm_crtc base; | |
80824003 JB |
328 | enum pipe pipe; |
329 | enum plane plane; | |
79e53945 | 330 | u8 lut_r[256], lut_g[256], lut_b[256]; |
08a48469 DV |
331 | /* |
332 | * Whether the crtc and the connected output pipeline is active. Implies | |
333 | * that crtc->enabled is set, i.e. the current mode configuration has | |
334 | * some outputs connected to this crtc. | |
08a48469 DV |
335 | */ |
336 | bool active; | |
6efdf354 | 337 | unsigned long enabled_power_domains; |
7b9f35a6 | 338 | bool eld_vld; |
4c445e0e | 339 | bool primary_enabled; /* is the primary plane (partially) visible? */ |
652c393a | 340 | bool lowfreq_avail; |
02e792fb | 341 | struct intel_overlay *overlay; |
6b95a207 | 342 | struct intel_unpin_work *unpin_work; |
cda4b7d3 | 343 | |
b4a98e57 CW |
344 | atomic_t unpin_work_count; |
345 | ||
e506a0c6 DV |
346 | /* Display surface base address adjustement for pageflips. Note that on |
347 | * gen4+ this only adjusts up to a tile, offsets within a tile are | |
348 | * handled in the hw itself (with the TILEOFF register). */ | |
349 | unsigned long dspaddr_offset; | |
350 | ||
05394f39 | 351 | struct drm_i915_gem_object *cursor_bo; |
cda4b7d3 CW |
352 | uint32_t cursor_addr; |
353 | int16_t cursor_x, cursor_y; | |
354 | int16_t cursor_width, cursor_height; | |
6b383a7f | 355 | bool cursor_visible; |
4b645f14 | 356 | |
b8cecdf5 DV |
357 | struct intel_crtc_config config; |
358 | ||
6441ab5f | 359 | uint32_t ddi_pll_sel; |
10d83730 VS |
360 | |
361 | /* reset counter value when the last flip was submitted */ | |
362 | unsigned int reset_counter; | |
8664281b PZ |
363 | |
364 | /* Access to these should be protected by dev_priv->irq_lock. */ | |
365 | bool cpu_fifo_underrun_disabled; | |
366 | bool pch_fifo_underrun_disabled; | |
0b2ae6d7 VS |
367 | |
368 | /* per-pipe watermark state */ | |
369 | struct { | |
370 | /* watermarks currently being used */ | |
371 | struct intel_pipe_wm active; | |
372 | } wm; | |
79e53945 JB |
373 | }; |
374 | ||
c35426d2 VS |
375 | struct intel_plane_wm_parameters { |
376 | uint32_t horiz_pixels; | |
377 | uint8_t bytes_per_pixel; | |
378 | bool enabled; | |
379 | bool scaled; | |
380 | }; | |
381 | ||
b840d907 JB |
382 | struct intel_plane { |
383 | struct drm_plane base; | |
7f1f3851 | 384 | int plane; |
b840d907 JB |
385 | enum pipe pipe; |
386 | struct drm_i915_gem_object *obj; | |
2d354c34 | 387 | bool can_scale; |
b840d907 JB |
388 | int max_downscale; |
389 | u32 lut_r[1024], lut_g[1024], lut_b[1024]; | |
5e1bac2f JB |
390 | int crtc_x, crtc_y; |
391 | unsigned int crtc_w, crtc_h; | |
392 | uint32_t src_x, src_y; | |
393 | uint32_t src_w, src_h; | |
526682e9 PZ |
394 | |
395 | /* Since we need to change the watermarks before/after | |
396 | * enabling/disabling the planes, we need to store the parameters here | |
397 | * as the other pieces of the struct may not reflect the values we want | |
398 | * for the watermark calculations. Currently only Haswell uses this. | |
399 | */ | |
c35426d2 | 400 | struct intel_plane_wm_parameters wm; |
526682e9 | 401 | |
b840d907 | 402 | void (*update_plane)(struct drm_plane *plane, |
b39d53f6 | 403 | struct drm_crtc *crtc, |
b840d907 JB |
404 | struct drm_framebuffer *fb, |
405 | struct drm_i915_gem_object *obj, | |
406 | int crtc_x, int crtc_y, | |
407 | unsigned int crtc_w, unsigned int crtc_h, | |
408 | uint32_t x, uint32_t y, | |
409 | uint32_t src_w, uint32_t src_h); | |
b39d53f6 VS |
410 | void (*disable_plane)(struct drm_plane *plane, |
411 | struct drm_crtc *crtc); | |
8ea30864 JB |
412 | int (*update_colorkey)(struct drm_plane *plane, |
413 | struct drm_intel_sprite_colorkey *key); | |
414 | void (*get_colorkey)(struct drm_plane *plane, | |
415 | struct drm_intel_sprite_colorkey *key); | |
b840d907 JB |
416 | }; |
417 | ||
b445e3b0 ED |
418 | struct intel_watermark_params { |
419 | unsigned long fifo_size; | |
420 | unsigned long max_wm; | |
421 | unsigned long default_wm; | |
422 | unsigned long guard_size; | |
423 | unsigned long cacheline_size; | |
424 | }; | |
425 | ||
426 | struct cxsr_latency { | |
427 | int is_desktop; | |
428 | int is_ddr3; | |
429 | unsigned long fsb_freq; | |
430 | unsigned long mem_freq; | |
431 | unsigned long display_sr; | |
432 | unsigned long display_hpll_disable; | |
433 | unsigned long cursor_sr; | |
434 | unsigned long cursor_hpll_disable; | |
435 | }; | |
436 | ||
79e53945 | 437 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
5daa55eb | 438 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
4ef69c7a | 439 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
79e53945 | 440 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
b840d907 | 441 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
79e53945 | 442 | |
f5bbfca3 | 443 | struct intel_hdmi { |
b242b7f7 | 444 | u32 hdmi_reg; |
f5bbfca3 | 445 | int ddc_bus; |
f5bbfca3 | 446 | uint32_t color_range; |
55bc60db | 447 | bool color_range_auto; |
f5bbfca3 ED |
448 | bool has_hdmi_sink; |
449 | bool has_audio; | |
450 | enum hdmi_force_audio force_audio; | |
abedc077 | 451 | bool rgb_quant_range_selectable; |
f5bbfca3 | 452 | void (*write_infoframe)(struct drm_encoder *encoder, |
178f736a DL |
453 | enum hdmi_infoframe_type type, |
454 | const uint8_t *frame, ssize_t len); | |
687f4d06 PZ |
455 | void (*set_infoframes)(struct drm_encoder *encoder, |
456 | struct drm_display_mode *adjusted_mode); | |
f5bbfca3 ED |
457 | }; |
458 | ||
b091cd92 | 459 | #define DP_MAX_DOWNSTREAM_PORTS 0x10 |
54d63ca6 SK |
460 | |
461 | struct intel_dp { | |
54d63ca6 | 462 | uint32_t output_reg; |
9ed35ab1 | 463 | uint32_t aux_ch_ctl_reg; |
54d63ca6 | 464 | uint32_t DP; |
54d63ca6 SK |
465 | bool has_audio; |
466 | enum hdmi_force_audio force_audio; | |
467 | uint32_t color_range; | |
55bc60db | 468 | bool color_range_auto; |
54d63ca6 SK |
469 | uint8_t link_bw; |
470 | uint8_t lane_count; | |
471 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; | |
2293bb5c | 472 | uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; |
b091cd92 | 473 | uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; |
54d63ca6 SK |
474 | struct i2c_adapter adapter; |
475 | struct i2c_algo_dp_aux_data algo; | |
54d63ca6 SK |
476 | uint8_t train_set[4]; |
477 | int panel_power_up_delay; | |
478 | int panel_power_down_delay; | |
479 | int panel_power_cycle_delay; | |
480 | int backlight_on_delay; | |
481 | int backlight_off_delay; | |
54d63ca6 SK |
482 | struct delayed_work panel_vdd_work; |
483 | bool want_panel_vdd; | |
2b28bb1b | 484 | bool psr_setup_done; |
dd06f90e | 485 | struct intel_connector *attached_connector; |
54d63ca6 SK |
486 | }; |
487 | ||
da63a9f2 PZ |
488 | struct intel_digital_port { |
489 | struct intel_encoder base; | |
174edf1f | 490 | enum port port; |
bcf53de4 | 491 | u32 saved_port_bits; |
da63a9f2 PZ |
492 | struct intel_dp dp; |
493 | struct intel_hdmi hdmi; | |
494 | }; | |
495 | ||
89b667f8 JB |
496 | static inline int |
497 | vlv_dport_to_channel(struct intel_digital_port *dport) | |
498 | { | |
499 | switch (dport->port) { | |
500 | case PORT_B: | |
501 | return 0; | |
502 | case PORT_C: | |
503 | return 1; | |
504 | default: | |
505 | BUG(); | |
506 | } | |
507 | } | |
508 | ||
f875c15a CW |
509 | static inline struct drm_crtc * |
510 | intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) | |
511 | { | |
512 | struct drm_i915_private *dev_priv = dev->dev_private; | |
513 | return dev_priv->pipe_to_crtc_mapping[pipe]; | |
514 | } | |
515 | ||
417ae147 CW |
516 | static inline struct drm_crtc * |
517 | intel_get_crtc_for_plane(struct drm_device *dev, int plane) | |
518 | { | |
519 | struct drm_i915_private *dev_priv = dev->dev_private; | |
520 | return dev_priv->plane_to_crtc_mapping[plane]; | |
521 | } | |
522 | ||
4e5359cd SF |
523 | struct intel_unpin_work { |
524 | struct work_struct work; | |
b4a98e57 | 525 | struct drm_crtc *crtc; |
05394f39 CW |
526 | struct drm_i915_gem_object *old_fb_obj; |
527 | struct drm_i915_gem_object *pending_flip_obj; | |
4e5359cd | 528 | struct drm_pending_vblank_event *event; |
e7d841ca CW |
529 | atomic_t pending; |
530 | #define INTEL_FLIP_INACTIVE 0 | |
531 | #define INTEL_FLIP_PENDING 1 | |
532 | #define INTEL_FLIP_COMPLETE 2 | |
4e5359cd SF |
533 | bool enable_stall_check; |
534 | }; | |
535 | ||
d9e55608 | 536 | struct intel_set_config { |
1aa4b628 DV |
537 | struct drm_encoder **save_connector_encoders; |
538 | struct drm_crtc **save_encoder_crtcs; | |
5e2b584e DV |
539 | |
540 | bool fb_changed; | |
541 | bool mode_changed; | |
d9e55608 DV |
542 | }; |
543 | ||
5f1aae65 PZ |
544 | struct intel_load_detect_pipe { |
545 | struct drm_framebuffer *release_fb; | |
546 | bool load_detect_temp; | |
547 | int dpms_mode; | |
548 | }; | |
79e53945 | 549 | |
5f1aae65 PZ |
550 | static inline struct intel_encoder * |
551 | intel_attached_encoder(struct drm_connector *connector) | |
df0e9248 CW |
552 | { |
553 | return to_intel_connector(connector)->encoder; | |
554 | } | |
555 | ||
da63a9f2 PZ |
556 | static inline struct intel_digital_port * |
557 | enc_to_dig_port(struct drm_encoder *encoder) | |
558 | { | |
559 | return container_of(encoder, struct intel_digital_port, base.base); | |
9ff8c9ba ID |
560 | } |
561 | ||
562 | static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) | |
563 | { | |
564 | return &enc_to_dig_port(encoder)->dp; | |
da63a9f2 PZ |
565 | } |
566 | ||
567 | static inline struct intel_digital_port * | |
568 | dp_to_dig_port(struct intel_dp *intel_dp) | |
569 | { | |
570 | return container_of(intel_dp, struct intel_digital_port, dp); | |
571 | } | |
572 | ||
573 | static inline struct intel_digital_port * | |
574 | hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) | |
575 | { | |
576 | return container_of(intel_hdmi, struct intel_digital_port, hdmi); | |
7739c33b PZ |
577 | } |
578 | ||
5f1aae65 PZ |
579 | |
580 | /* i915_irq.c */ | |
87440425 PZ |
581 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, |
582 | enum pipe pipe, bool enable); | |
583 | bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, | |
584 | enum transcoder pch_transcoder, | |
585 | bool enable); | |
586 | void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
587 | void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
588 | void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
589 | void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
590 | void hsw_pc8_disable_interrupts(struct drm_device *dev); | |
591 | void hsw_pc8_restore_interrupts(struct drm_device *dev); | |
5f1aae65 PZ |
592 | |
593 | ||
594 | /* intel_crt.c */ | |
87440425 | 595 | void intel_crt_init(struct drm_device *dev); |
5f1aae65 PZ |
596 | |
597 | ||
598 | /* intel_ddi.c */ | |
87440425 PZ |
599 | void intel_prepare_ddi(struct drm_device *dev); |
600 | void hsw_fdi_link_train(struct drm_crtc *crtc); | |
601 | void intel_ddi_init(struct drm_device *dev, enum port port); | |
602 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder); | |
603 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); | |
604 | int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv); | |
605 | void intel_ddi_pll_init(struct drm_device *dev); | |
606 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc); | |
607 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, | |
608 | enum transcoder cpu_transcoder); | |
609 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); | |
610 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); | |
611 | void intel_ddi_setup_hw_pll_state(struct drm_device *dev); | |
612 | bool intel_ddi_pll_mode_set(struct drm_crtc *crtc); | |
613 | void intel_ddi_put_crtc_pll(struct drm_crtc *crtc); | |
614 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); | |
615 | void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder); | |
616 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); | |
617 | void intel_ddi_fdi_disable(struct drm_crtc *crtc); | |
618 | void intel_ddi_get_config(struct intel_encoder *encoder, | |
619 | struct intel_crtc_config *pipe_config); | |
5f1aae65 PZ |
620 | |
621 | ||
622 | /* intel_display.c */ | |
623 | int intel_pch_rawclk(struct drm_device *dev); | |
87440425 PZ |
624 | void intel_mark_busy(struct drm_device *dev); |
625 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj, | |
626 | struct intel_ring_buffer *ring); | |
627 | void intel_mark_idle(struct drm_device *dev); | |
628 | void intel_crtc_restore_mode(struct drm_crtc *crtc); | |
629 | void intel_crtc_update_dpms(struct drm_crtc *crtc); | |
630 | void intel_encoder_destroy(struct drm_encoder *encoder); | |
631 | void intel_connector_dpms(struct drm_connector *, int mode); | |
632 | bool intel_connector_get_hw_state(struct intel_connector *connector); | |
633 | void intel_modeset_check_state(struct drm_device *dev); | |
b0ea7d37 DL |
634 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
635 | struct intel_digital_port *port); | |
87440425 PZ |
636 | void intel_connector_attach_encoder(struct intel_connector *connector, |
637 | struct intel_encoder *encoder); | |
638 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector); | |
639 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
640 | struct drm_crtc *crtc); | |
752aa88a | 641 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector); |
08d7b3d1 CW |
642 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
643 | struct drm_file *file_priv); | |
87440425 PZ |
644 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
645 | enum pipe pipe); | |
646 | void intel_wait_for_vblank(struct drm_device *dev, int pipe); | |
647 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe); | |
648 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); | |
649 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port); | |
650 | bool intel_get_load_detect_pipe(struct drm_connector *connector, | |
651 | struct drm_display_mode *mode, | |
652 | struct intel_load_detect_pipe *old); | |
653 | void intel_release_load_detect_pipe(struct drm_connector *connector, | |
654 | struct intel_load_detect_pipe *old); | |
655 | int intel_pin_and_fence_fb_obj(struct drm_device *dev, | |
656 | struct drm_i915_gem_object *obj, | |
657 | struct intel_ring_buffer *pipelined); | |
658 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj); | |
659 | int intel_framebuffer_init(struct drm_device *dev, | |
660 | struct intel_framebuffer *ifb, | |
661 | struct drm_mode_fb_cmd2 *mode_cmd, | |
662 | struct drm_i915_gem_object *obj); | |
663 | void intel_framebuffer_fini(struct intel_framebuffer *fb); | |
664 | void intel_prepare_page_flip(struct drm_device *dev, int plane); | |
665 | void intel_finish_page_flip(struct drm_device *dev, int pipe); | |
666 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane); | |
5f1aae65 | 667 | struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc); |
55607e8a DV |
668 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
669 | struct intel_shared_dpll *pll, | |
670 | bool state); | |
671 | #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) | |
672 | #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) | |
673 | void assert_pll(struct drm_i915_private *dev_priv, | |
674 | enum pipe pipe, bool state); | |
675 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) | |
676 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) | |
677 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, | |
678 | enum pipe pipe, bool state); | |
679 | #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) | |
680 | #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) | |
87440425 | 681 | void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state); |
b840d907 JB |
682 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) |
683 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) | |
87440425 PZ |
684 | void intel_write_eld(struct drm_encoder *encoder, |
685 | struct drm_display_mode *mode); | |
686 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, | |
687 | unsigned int tiling_mode, | |
688 | unsigned int bpp, | |
689 | unsigned int pitch); | |
690 | void intel_display_handle_reset(struct drm_device *dev); | |
691 | void hsw_enable_pc8_work(struct work_struct *__work); | |
692 | void hsw_enable_package_c8(struct drm_i915_private *dev_priv); | |
693 | void hsw_disable_package_c8(struct drm_i915_private *dev_priv); | |
694 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
695 | struct intel_crtc_config *pipe_config); | |
696 | int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); | |
697 | void | |
5f1aae65 PZ |
698 | ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
699 | int dotclock); | |
87440425 PZ |
700 | bool intel_crtc_active(struct drm_crtc *crtc); |
701 | void i915_disable_vga_mem(struct drm_device *dev); | |
20bc8673 VS |
702 | void hsw_enable_ips(struct intel_crtc *crtc); |
703 | void hsw_disable_ips(struct intel_crtc *crtc); | |
baa70707 | 704 | void intel_display_set_init_power(struct drm_device *dev, bool enable); |
5a35e99e | 705 | |
8ea30864 | 706 | |
5f1aae65 | 707 | /* intel_dp.c */ |
87440425 PZ |
708 | void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); |
709 | bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, | |
710 | struct intel_connector *intel_connector); | |
87440425 PZ |
711 | void intel_dp_start_link_train(struct intel_dp *intel_dp); |
712 | void intel_dp_complete_link_train(struct intel_dp *intel_dp); | |
713 | void intel_dp_stop_link_train(struct intel_dp *intel_dp); | |
714 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); | |
715 | void intel_dp_encoder_destroy(struct drm_encoder *encoder); | |
716 | void intel_dp_check_link_status(struct intel_dp *intel_dp); | |
717 | bool intel_dp_compute_config(struct intel_encoder *encoder, | |
718 | struct intel_crtc_config *pipe_config); | |
719 | bool intel_dpd_is_edp(struct drm_device *dev); | |
720 | void ironlake_edp_backlight_on(struct intel_dp *intel_dp); | |
721 | void ironlake_edp_backlight_off(struct intel_dp *intel_dp); | |
722 | void ironlake_edp_panel_on(struct intel_dp *intel_dp); | |
723 | void ironlake_edp_panel_off(struct intel_dp *intel_dp); | |
724 | void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); | |
725 | void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); | |
726 | void intel_edp_psr_enable(struct intel_dp *intel_dp); | |
727 | void intel_edp_psr_disable(struct intel_dp *intel_dp); | |
728 | void intel_edp_psr_update(struct drm_device *dev); | |
5f1aae65 PZ |
729 | |
730 | ||
731 | /* intel_dsi.c */ | |
87440425 | 732 | bool intel_dsi_init(struct drm_device *dev); |
5f1aae65 PZ |
733 | |
734 | ||
735 | /* intel_dvo.c */ | |
87440425 | 736 | void intel_dvo_init(struct drm_device *dev); |
5f1aae65 PZ |
737 | |
738 | ||
0632fef6 | 739 | /* legacy fbdev emulation in intel_fbdev.c */ |
4520f53a DV |
740 | #ifdef CONFIG_DRM_I915_FBDEV |
741 | extern int intel_fbdev_init(struct drm_device *dev); | |
742 | extern void intel_fbdev_initial_config(struct drm_device *dev); | |
743 | extern void intel_fbdev_fini(struct drm_device *dev); | |
744 | extern void intel_fbdev_set_suspend(struct drm_device *dev, int state); | |
0632fef6 DV |
745 | extern void intel_fbdev_output_poll_changed(struct drm_device *dev); |
746 | extern void intel_fbdev_restore_mode(struct drm_device *dev); | |
4520f53a DV |
747 | #else |
748 | static inline int intel_fbdev_init(struct drm_device *dev) | |
749 | { | |
750 | return 0; | |
751 | } | |
5f1aae65 | 752 | |
4520f53a DV |
753 | static inline void intel_fbdev_initial_config(struct drm_device *dev) |
754 | { | |
755 | } | |
756 | ||
757 | static inline void intel_fbdev_fini(struct drm_device *dev) | |
758 | { | |
759 | } | |
760 | ||
761 | static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state) | |
762 | { | |
763 | } | |
764 | ||
0632fef6 | 765 | static inline void intel_fbdev_restore_mode(struct drm_device *dev) |
4520f53a DV |
766 | { |
767 | } | |
768 | #endif | |
5f1aae65 PZ |
769 | |
770 | /* intel_hdmi.c */ | |
87440425 PZ |
771 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port); |
772 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, | |
773 | struct intel_connector *intel_connector); | |
774 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); | |
775 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, | |
776 | struct intel_crtc_config *pipe_config); | |
5f1aae65 PZ |
777 | |
778 | ||
779 | /* intel_lvds.c */ | |
87440425 PZ |
780 | void intel_lvds_init(struct drm_device *dev); |
781 | bool intel_is_dual_link_lvds(struct drm_device *dev); | |
5f1aae65 PZ |
782 | |
783 | ||
784 | /* intel_modes.c */ | |
785 | int intel_connector_update_modes(struct drm_connector *connector, | |
87440425 | 786 | struct edid *edid); |
5f1aae65 | 787 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); |
87440425 PZ |
788 | void intel_attach_force_audio_property(struct drm_connector *connector); |
789 | void intel_attach_broadcast_rgb_property(struct drm_connector *connector); | |
5f1aae65 PZ |
790 | |
791 | ||
792 | /* intel_overlay.c */ | |
87440425 PZ |
793 | void intel_setup_overlay(struct drm_device *dev); |
794 | void intel_cleanup_overlay(struct drm_device *dev); | |
795 | int intel_overlay_switch_off(struct intel_overlay *overlay); | |
796 | int intel_overlay_put_image(struct drm_device *dev, void *data, | |
797 | struct drm_file *file_priv); | |
798 | int intel_overlay_attrs(struct drm_device *dev, void *data, | |
799 | struct drm_file *file_priv); | |
5f1aae65 PZ |
800 | |
801 | ||
802 | /* intel_panel.c */ | |
87440425 PZ |
803 | int intel_panel_init(struct intel_panel *panel, |
804 | struct drm_display_mode *fixed_mode); | |
805 | void intel_panel_fini(struct intel_panel *panel); | |
806 | void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, | |
807 | struct drm_display_mode *adjusted_mode); | |
808 | void intel_pch_panel_fitting(struct intel_crtc *crtc, | |
809 | struct intel_crtc_config *pipe_config, | |
810 | int fitting_mode); | |
811 | void intel_gmch_panel_fitting(struct intel_crtc *crtc, | |
812 | struct intel_crtc_config *pipe_config, | |
813 | int fitting_mode); | |
752aa88a JB |
814 | void intel_panel_set_backlight(struct intel_connector *connector, u32 level, |
815 | u32 max); | |
87440425 | 816 | int intel_panel_setup_backlight(struct drm_connector *connector); |
752aa88a JB |
817 | void intel_panel_enable_backlight(struct intel_connector *connector); |
818 | void intel_panel_disable_backlight(struct intel_connector *connector); | |
db31af1d | 819 | void intel_panel_destroy_backlight(struct drm_connector *connector); |
87440425 | 820 | enum drm_connector_status intel_panel_detect(struct drm_device *dev); |
5f1aae65 PZ |
821 | |
822 | ||
823 | /* intel_pm.c */ | |
87440425 PZ |
824 | void intel_init_clock_gating(struct drm_device *dev); |
825 | void intel_suspend_hw(struct drm_device *dev); | |
826 | void intel_update_watermarks(struct drm_crtc *crtc); | |
827 | void intel_update_sprite_watermarks(struct drm_plane *plane, | |
828 | struct drm_crtc *crtc, | |
829 | uint32_t sprite_width, int pixel_size, | |
830 | bool enabled, bool scaled); | |
831 | void intel_init_pm(struct drm_device *dev); | |
832 | bool intel_fbc_enabled(struct drm_device *dev); | |
833 | void intel_update_fbc(struct drm_device *dev); | |
834 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv); | |
835 | void intel_gpu_ips_teardown(void); | |
ddb642fb ID |
836 | int intel_power_domains_init(struct drm_device *dev); |
837 | void intel_power_domains_remove(struct drm_device *dev); | |
87440425 PZ |
838 | bool intel_display_power_enabled(struct drm_device *dev, |
839 | enum intel_display_power_domain domain); | |
840 | void intel_display_power_get(struct drm_device *dev, | |
841 | enum intel_display_power_domain domain); | |
842 | void intel_display_power_put(struct drm_device *dev, | |
843 | enum intel_display_power_domain domain); | |
ddb642fb | 844 | void intel_power_domains_init_hw(struct drm_device *dev); |
87440425 | 845 | void intel_set_power_well(struct drm_device *dev, bool enable); |
87440425 PZ |
846 | void intel_enable_gt_powersave(struct drm_device *dev); |
847 | void intel_disable_gt_powersave(struct drm_device *dev); | |
848 | void ironlake_teardown_rc6(struct drm_device *dev); | |
c67a470b | 849 | void gen6_update_ring_freq(struct drm_device *dev); |
076e29f2 DV |
850 | void gen6_rps_idle(struct drm_i915_private *dev_priv); |
851 | void gen6_rps_boost(struct drm_i915_private *dev_priv); | |
87440425 PZ |
852 | void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv); |
853 | void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv); | |
243e6a44 | 854 | void ilk_wm_get_hw_state(struct drm_device *dev); |
b3daeaef | 855 | |
72662e10 | 856 | |
5f1aae65 | 857 | /* intel_sdvo.c */ |
87440425 | 858 | bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob); |
96a02917 | 859 | |
2b28bb1b | 860 | |
5f1aae65 | 861 | /* intel_sprite.c */ |
87440425 | 862 | int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); |
1dba99f4 | 863 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
87440425 PZ |
864 | enum plane plane); |
865 | void intel_plane_restore(struct drm_plane *plane); | |
866 | void intel_plane_disable(struct drm_plane *plane); | |
867 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, | |
868 | struct drm_file *file_priv); | |
869 | int intel_sprite_get_colorkey(struct drm_device *dev, void *data, | |
870 | struct drm_file *file_priv); | |
5f1aae65 PZ |
871 | |
872 | ||
873 | /* intel_tv.c */ | |
87440425 | 874 | void intel_tv_init(struct drm_device *dev); |
20ddf665 | 875 | |
79e53945 | 876 | #endif /* __INTEL_DRV_H__ */ |