Commit | Line | Data |
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4e646495 JN |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Author: Jani Nikula <jani.nikula@intel.com> | |
24 | */ | |
25 | ||
26 | #include <drm/drmP.h> | |
c6f95f27 | 27 | #include <drm/drm_atomic_helper.h> |
4e646495 JN |
28 | #include <drm/drm_crtc.h> |
29 | #include <drm/drm_edid.h> | |
30 | #include <drm/i915_drm.h> | |
31 | #include <linux/slab.h> | |
32 | #include "i915_drv.h" | |
33 | #include "intel_drv.h" | |
34 | #include "intel_dsi.h" | |
35 | #include "intel_dsi_cmd.h" | |
36 | ||
37 | /* the sub-encoders aka panel drivers */ | |
38 | static const struct intel_dsi_device intel_dsi_devices[] = { | |
2ab8b458 SK |
39 | { |
40 | .panel_id = MIPI_DSI_GENERIC_PANEL_ID, | |
41 | .name = "vbt-generic-dsi-vid-mode-display", | |
42 | .dev_ops = &vbt_generic_dsi_display_ops, | |
43 | }, | |
4e646495 JN |
44 | }; |
45 | ||
7f6a6a4a | 46 | static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port) |
3b1808bf JN |
47 | { |
48 | struct drm_encoder *encoder = &intel_dsi->base.base; | |
49 | struct drm_device *dev = encoder->dev; | |
50 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3b1808bf JN |
51 | u32 mask; |
52 | ||
53 | mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | | |
54 | LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; | |
55 | ||
56 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100)) | |
57 | DRM_ERROR("DPI FIFOs are not empty\n"); | |
58 | } | |
59 | ||
e9fe51c6 | 60 | static void band_gap_reset(struct drm_i915_private *dev_priv) |
4ce8c9a7 SK |
61 | { |
62 | mutex_lock(&dev_priv->dpio_lock); | |
63 | ||
e9fe51c6 SK |
64 | vlv_flisdsi_write(dev_priv, 0x08, 0x0001); |
65 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); | |
66 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); | |
67 | udelay(150); | |
68 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); | |
69 | vlv_flisdsi_write(dev_priv, 0x08, 0x0000); | |
4ce8c9a7 SK |
70 | |
71 | mutex_unlock(&dev_priv->dpio_lock); | |
4ce8c9a7 SK |
72 | } |
73 | ||
4e646495 JN |
74 | static inline bool is_vid_mode(struct intel_dsi *intel_dsi) |
75 | { | |
dfba2e2d | 76 | return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE; |
4e646495 JN |
77 | } |
78 | ||
79 | static inline bool is_cmd_mode(struct intel_dsi *intel_dsi) | |
80 | { | |
dfba2e2d | 81 | return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE; |
4e646495 JN |
82 | } |
83 | ||
84 | static void intel_dsi_hot_plug(struct intel_encoder *encoder) | |
85 | { | |
86 | DRM_DEBUG_KMS("\n"); | |
87 | } | |
88 | ||
89 | static bool intel_dsi_compute_config(struct intel_encoder *encoder, | |
5cec258b | 90 | struct intel_crtc_state *config) |
4e646495 JN |
91 | { |
92 | struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, | |
93 | base); | |
94 | struct intel_connector *intel_connector = intel_dsi->attached_connector; | |
95 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
2d112de7 | 96 | struct drm_display_mode *adjusted_mode = &config->base.adjusted_mode; |
4e646495 JN |
97 | |
98 | DRM_DEBUG_KMS("\n"); | |
99 | ||
100 | if (fixed_mode) | |
101 | intel_fixed_panel_mode(fixed_mode, adjusted_mode); | |
102 | ||
f573de5a SK |
103 | /* DSI uses short packets for sync events, so clear mode flags for DSI */ |
104 | adjusted_mode->flags = 0; | |
105 | ||
4e646495 JN |
106 | return true; |
107 | } | |
108 | ||
5505a244 GS |
109 | static void intel_dsi_port_enable(struct intel_encoder *encoder) |
110 | { | |
111 | struct drm_device *dev = encoder->base.dev; | |
112 | struct drm_i915_private *dev_priv = dev->dev_private; | |
113 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
114 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
369602d3 | 115 | enum port port; |
5505a244 GS |
116 | u32 temp; |
117 | ||
a9da9bce GS |
118 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { |
119 | temp = I915_READ(VLV_CHICKEN_3); | |
120 | temp &= ~PIXEL_OVERLAP_CNT_MASK | | |
121 | intel_dsi->pixel_overlap << | |
122 | PIXEL_OVERLAP_CNT_SHIFT; | |
123 | I915_WRITE(VLV_CHICKEN_3, temp); | |
124 | } | |
125 | ||
369602d3 GS |
126 | for_each_dsi_port(port, intel_dsi->ports) { |
127 | temp = I915_READ(MIPI_PORT_CTRL(port)); | |
128 | temp &= ~LANE_CONFIGURATION_MASK; | |
129 | temp &= ~DUAL_LINK_MODE_MASK; | |
130 | ||
131 | if (intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) { | |
132 | temp |= (intel_dsi->dual_link - 1) | |
133 | << DUAL_LINK_MODE_SHIFT; | |
134 | temp |= intel_crtc->pipe ? | |
135 | LANE_CONFIGURATION_DUAL_LINK_B : | |
136 | LANE_CONFIGURATION_DUAL_LINK_A; | |
137 | } | |
138 | /* assert ip_tg_enable signal */ | |
139 | I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE); | |
140 | POSTING_READ(MIPI_PORT_CTRL(port)); | |
141 | } | |
5505a244 GS |
142 | } |
143 | ||
144 | static void intel_dsi_port_disable(struct intel_encoder *encoder) | |
145 | { | |
146 | struct drm_device *dev = encoder->base.dev; | |
147 | struct drm_i915_private *dev_priv = dev->dev_private; | |
369602d3 GS |
148 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
149 | enum port port; | |
5505a244 GS |
150 | u32 temp; |
151 | ||
369602d3 GS |
152 | for_each_dsi_port(port, intel_dsi->ports) { |
153 | /* de-assert ip_tg_enable signal */ | |
154 | temp = I915_READ(MIPI_PORT_CTRL(port)); | |
155 | I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE); | |
156 | POSTING_READ(MIPI_PORT_CTRL(port)); | |
157 | } | |
5505a244 GS |
158 | } |
159 | ||
1dbd7cb2 | 160 | static void intel_dsi_device_ready(struct intel_encoder *encoder) |
4e646495 | 161 | { |
1dbd7cb2 | 162 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
24ee0e64 GS |
163 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
164 | enum port port; | |
1dbd7cb2 SK |
165 | u32 val; |
166 | ||
4e646495 | 167 | DRM_DEBUG_KMS("\n"); |
4e646495 | 168 | |
2095f9fc SK |
169 | mutex_lock(&dev_priv->dpio_lock); |
170 | /* program rcomp for compliance, reduce from 50 ohms to 45 ohms | |
171 | * needed everytime after power gate */ | |
172 | vlv_flisdsi_write(dev_priv, 0x04, 0x0004); | |
173 | mutex_unlock(&dev_priv->dpio_lock); | |
174 | ||
175 | /* bandgap reset is needed after everytime we do power gate */ | |
176 | band_gap_reset(dev_priv); | |
177 | ||
24ee0e64 | 178 | for_each_dsi_port(port, intel_dsi->ports) { |
aceb365c | 179 | |
24ee0e64 GS |
180 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); |
181 | usleep_range(2500, 3000); | |
aceb365c | 182 | |
24ee0e64 | 183 | val = I915_READ(MIPI_PORT_CTRL(port)); |
bf344e80 GS |
184 | |
185 | /* Enable MIPI PHY transparent latch | |
186 | * Common bit for both MIPI Port A & MIPI Port C | |
187 | * No similar bit in MIPI Port C reg | |
188 | */ | |
189 | I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD); | |
24ee0e64 | 190 | usleep_range(1000, 1500); |
aceb365c | 191 | |
24ee0e64 GS |
192 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); |
193 | usleep_range(2500, 3000); | |
194 | ||
195 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); | |
196 | usleep_range(2500, 3000); | |
197 | } | |
1dbd7cb2 | 198 | } |
1dbd7cb2 SK |
199 | |
200 | static void intel_dsi_enable(struct intel_encoder *encoder) | |
201 | { | |
202 | struct drm_device *dev = encoder->base.dev; | |
203 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1dbd7cb2 | 204 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
4934b656 | 205 | enum port port; |
1dbd7cb2 SK |
206 | |
207 | DRM_DEBUG_KMS("\n"); | |
b9f5e07d | 208 | |
4934b656 JN |
209 | if (is_cmd_mode(intel_dsi)) { |
210 | for_each_dsi_port(port, intel_dsi->ports) | |
211 | I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); | |
212 | } else { | |
4e646495 | 213 | msleep(20); /* XXX */ |
f03e4179 JN |
214 | for_each_dsi_port(port, intel_dsi->ports) |
215 | dpi_send_cmd(intel_dsi, TURN_ON, DPI_LP_MODE_EN, port); | |
4e646495 JN |
216 | msleep(100); |
217 | ||
2634fd7f SK |
218 | if (intel_dsi->dev.dev_ops->enable) |
219 | intel_dsi->dev.dev_ops->enable(&intel_dsi->dev); | |
220 | ||
7f6a6a4a JN |
221 | for_each_dsi_port(port, intel_dsi->ports) |
222 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
1381308b | 223 | |
5505a244 | 224 | intel_dsi_port_enable(encoder); |
4e646495 | 225 | } |
2634fd7f SK |
226 | } |
227 | ||
228 | static void intel_dsi_pre_enable(struct intel_encoder *encoder) | |
229 | { | |
20e5bf66 SK |
230 | struct drm_device *dev = encoder->base.dev; |
231 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2634fd7f | 232 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
20e5bf66 SK |
233 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
234 | enum pipe pipe = intel_crtc->pipe; | |
7f6a6a4a | 235 | enum port port; |
20e5bf66 | 236 | u32 tmp; |
2634fd7f SK |
237 | |
238 | DRM_DEBUG_KMS("\n"); | |
239 | ||
20e5bf66 SK |
240 | /* Disable DPOunit clock gating, can stall pipe |
241 | * and we need DPLL REFA always enabled */ | |
242 | tmp = I915_READ(DPLL(pipe)); | |
243 | tmp |= DPLL_REFA_CLK_ENABLE_VLV; | |
244 | I915_WRITE(DPLL(pipe), tmp); | |
245 | ||
f573de5a | 246 | /* update the hw state for DPLL */ |
6e3c9717 | 247 | intel_crtc->config->dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV | |
7f3de833 | 248 | DPLL_REFA_CLK_ENABLE_VLV; |
f573de5a | 249 | |
20e5bf66 SK |
250 | tmp = I915_READ(DSPCLK_GATE_D); |
251 | tmp |= DPOUNIT_CLOCK_GATE_DISABLE; | |
252 | I915_WRITE(DSPCLK_GATE_D, tmp); | |
2634fd7f SK |
253 | |
254 | /* put device in ready state */ | |
255 | intel_dsi_device_ready(encoder); | |
4e646495 | 256 | |
df38e655 SK |
257 | msleep(intel_dsi->panel_on_delay); |
258 | ||
20e5bf66 SK |
259 | if (intel_dsi->dev.dev_ops->panel_reset) |
260 | intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev); | |
261 | ||
7f6a6a4a JN |
262 | for_each_dsi_port(port, intel_dsi->ports) |
263 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
1381308b | 264 | |
2634fd7f SK |
265 | /* Enable port in pre-enable phase itself because as per hw team |
266 | * recommendation, port should be enabled befor plane & pipe */ | |
267 | intel_dsi_enable(encoder); | |
268 | } | |
269 | ||
270 | static void intel_dsi_enable_nop(struct intel_encoder *encoder) | |
271 | { | |
272 | DRM_DEBUG_KMS("\n"); | |
273 | ||
274 | /* for DSI port enable has to be done before pipe | |
275 | * and plane enable, so port enable is done in | |
276 | * pre_enable phase itself unlike other encoders | |
277 | */ | |
4e646495 JN |
278 | } |
279 | ||
c315faf8 ID |
280 | static void intel_dsi_pre_disable(struct intel_encoder *encoder) |
281 | { | |
282 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
f03e4179 | 283 | enum port port; |
c315faf8 ID |
284 | |
285 | DRM_DEBUG_KMS("\n"); | |
286 | ||
287 | if (is_vid_mode(intel_dsi)) { | |
288 | /* Send Shutdown command to the panel in LP mode */ | |
f03e4179 JN |
289 | for_each_dsi_port(port, intel_dsi->ports) |
290 | dpi_send_cmd(intel_dsi, SHUTDOWN, DPI_LP_MODE_EN, port); | |
c315faf8 ID |
291 | msleep(10); |
292 | } | |
293 | } | |
294 | ||
4e646495 JN |
295 | static void intel_dsi_disable(struct intel_encoder *encoder) |
296 | { | |
1dbd7cb2 SK |
297 | struct drm_device *dev = encoder->base.dev; |
298 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4e646495 | 299 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
384f02a2 | 300 | enum port port; |
4e646495 JN |
301 | u32 temp; |
302 | ||
303 | DRM_DEBUG_KMS("\n"); | |
304 | ||
4e646495 | 305 | if (is_vid_mode(intel_dsi)) { |
7f6a6a4a JN |
306 | for_each_dsi_port(port, intel_dsi->ports) |
307 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
1381308b | 308 | |
5505a244 | 309 | intel_dsi_port_disable(encoder); |
4e646495 JN |
310 | msleep(2); |
311 | } | |
312 | ||
384f02a2 GS |
313 | for_each_dsi_port(port, intel_dsi->ports) { |
314 | /* Panel commands can be sent when clock is in LP11 */ | |
315 | I915_WRITE(MIPI_DEVICE_READY(port), 0x0); | |
339023ec | 316 | |
384f02a2 GS |
317 | temp = I915_READ(MIPI_CTRL(port)); |
318 | temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; | |
319 | I915_WRITE(MIPI_CTRL(port), temp | | |
320 | intel_dsi->escape_clk_div << | |
321 | ESCAPE_CLOCK_DIVIDER_SHIFT); | |
339023ec | 322 | |
384f02a2 | 323 | I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); |
339023ec | 324 | |
384f02a2 GS |
325 | temp = I915_READ(MIPI_DSI_FUNC_PRG(port)); |
326 | temp &= ~VID_MODE_FORMAT_MASK; | |
327 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp); | |
339023ec | 328 | |
384f02a2 GS |
329 | I915_WRITE(MIPI_DEVICE_READY(port), 0x1); |
330 | } | |
1dbd7cb2 SK |
331 | /* if disable packets are sent before sending shutdown packet then in |
332 | * some next enable sequence send turn on packet error is observed */ | |
333 | if (intel_dsi->dev.dev_ops->disable) | |
334 | intel_dsi->dev.dev_ops->disable(&intel_dsi->dev); | |
1381308b | 335 | |
7f6a6a4a JN |
336 | for_each_dsi_port(port, intel_dsi->ports) |
337 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
4e646495 JN |
338 | } |
339 | ||
1dbd7cb2 | 340 | static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) |
4e646495 | 341 | { |
1dbd7cb2 | 342 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
384f02a2 GS |
343 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
344 | enum port port; | |
1dbd7cb2 SK |
345 | u32 val; |
346 | ||
4e646495 | 347 | DRM_DEBUG_KMS("\n"); |
384f02a2 | 348 | for_each_dsi_port(port, intel_dsi->ports) { |
be4fc046 | 349 | |
384f02a2 GS |
350 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | |
351 | ULPS_STATE_ENTER); | |
352 | usleep_range(2000, 2500); | |
353 | ||
354 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | | |
355 | ULPS_STATE_EXIT); | |
356 | usleep_range(2000, 2500); | |
357 | ||
358 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | | |
359 | ULPS_STATE_ENTER); | |
360 | usleep_range(2000, 2500); | |
361 | ||
362 | /* Wait till Clock lanes are in LP-00 state for MIPI Port A | |
363 | * only. MIPI Port C has no similar bit for checking | |
364 | */ | |
365 | if (wait_for(((I915_READ(MIPI_PORT_CTRL(PORT_A)) & AFE_LATCHOUT) | |
366 | == 0x00000), 30)) | |
367 | DRM_ERROR("DSI LP not going Low\n"); | |
368 | ||
369 | val = I915_READ(MIPI_PORT_CTRL(port)); | |
370 | /* Disable MIPI PHY transparent latch | |
371 | * Common bit for both MIPI Port A & MIPI Port C | |
372 | */ | |
373 | I915_WRITE(MIPI_PORT_CTRL(PORT_A), val & ~LP_OUTPUT_HOLD); | |
374 | usleep_range(1000, 1500); | |
375 | ||
376 | I915_WRITE(MIPI_DEVICE_READY(port), 0x00); | |
377 | usleep_range(2000, 2500); | |
378 | } | |
1dbd7cb2 | 379 | |
be4fc046 | 380 | vlv_disable_dsi_pll(encoder); |
4e646495 | 381 | } |
20e5bf66 | 382 | |
1dbd7cb2 SK |
383 | static void intel_dsi_post_disable(struct intel_encoder *encoder) |
384 | { | |
20e5bf66 | 385 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
1dbd7cb2 | 386 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
20e5bf66 | 387 | u32 val; |
1dbd7cb2 SK |
388 | |
389 | DRM_DEBUG_KMS("\n"); | |
390 | ||
c315faf8 ID |
391 | intel_dsi_disable(encoder); |
392 | ||
1dbd7cb2 SK |
393 | intel_dsi_clear_device_ready(encoder); |
394 | ||
20e5bf66 SK |
395 | val = I915_READ(DSPCLK_GATE_D); |
396 | val &= ~DPOUNIT_CLOCK_GATE_DISABLE; | |
397 | I915_WRITE(DSPCLK_GATE_D, val); | |
398 | ||
1dbd7cb2 SK |
399 | if (intel_dsi->dev.dev_ops->disable_panel_power) |
400 | intel_dsi->dev.dev_ops->disable_panel_power(&intel_dsi->dev); | |
df38e655 SK |
401 | |
402 | msleep(intel_dsi->panel_off_delay); | |
403 | msleep(intel_dsi->panel_pwr_cycle_delay); | |
1dbd7cb2 | 404 | } |
4e646495 JN |
405 | |
406 | static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, | |
407 | enum pipe *pipe) | |
408 | { | |
409 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
c0beefd2 GS |
410 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
411 | struct drm_device *dev = encoder->base.dev; | |
6d129bea | 412 | enum intel_display_power_domain power_domain; |
c0beefd2 | 413 | u32 dpi_enabled, func; |
e7d7cad0 | 414 | enum port port; |
4e646495 JN |
415 | |
416 | DRM_DEBUG_KMS("\n"); | |
417 | ||
6d129bea | 418 | power_domain = intel_display_port_power_domain(encoder); |
f458ebbc | 419 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
6d129bea ID |
420 | return false; |
421 | ||
4e646495 | 422 | /* XXX: this only works for one DSI output */ |
c0beefd2 | 423 | for_each_dsi_port(port, intel_dsi->ports) { |
e7d7cad0 | 424 | func = I915_READ(MIPI_DSI_FUNC_PRG(port)); |
c0beefd2 GS |
425 | dpi_enabled = I915_READ(MIPI_PORT_CTRL(port)) & |
426 | DPI_ENABLE; | |
427 | ||
428 | /* Due to some hardware limitations on BYT, MIPI Port C DPI | |
429 | * Enable bit does not get set. To check whether DSI Port C | |
430 | * was enabled in BIOS, check the Pipe B enable bit | |
431 | */ | |
432 | if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && | |
433 | (port == PORT_C)) | |
434 | dpi_enabled = I915_READ(PIPECONF(PIPE_B)) & | |
435 | PIPECONF_ENABLE; | |
4e646495 | 436 | |
c0beefd2 | 437 | if (dpi_enabled || (func & CMD_MODE_DATA_WIDTH_MASK)) { |
e7d7cad0 | 438 | if (I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY) { |
c0beefd2 | 439 | *pipe = port == PORT_A ? PIPE_A : PIPE_B; |
4e646495 JN |
440 | return true; |
441 | } | |
442 | } | |
443 | } | |
444 | ||
445 | return false; | |
446 | } | |
447 | ||
448 | static void intel_dsi_get_config(struct intel_encoder *encoder, | |
5cec258b | 449 | struct intel_crtc_state *pipe_config) |
4e646495 | 450 | { |
f573de5a | 451 | u32 pclk; |
4e646495 JN |
452 | DRM_DEBUG_KMS("\n"); |
453 | ||
f573de5a SK |
454 | /* |
455 | * DPLL_MD is not used in case of DSI, reading will get some default value | |
456 | * set dpll_md = 0 | |
457 | */ | |
458 | pipe_config->dpll_hw_state.dpll_md = 0; | |
459 | ||
460 | pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp); | |
461 | if (!pclk) | |
462 | return; | |
463 | ||
2d112de7 | 464 | pipe_config->base.adjusted_mode.crtc_clock = pclk; |
f573de5a | 465 | pipe_config->port_clock = pclk; |
4e646495 JN |
466 | } |
467 | ||
c19de8eb DL |
468 | static enum drm_mode_status |
469 | intel_dsi_mode_valid(struct drm_connector *connector, | |
470 | struct drm_display_mode *mode) | |
4e646495 JN |
471 | { |
472 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
473 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
4e646495 JN |
474 | |
475 | DRM_DEBUG_KMS("\n"); | |
476 | ||
477 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { | |
478 | DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n"); | |
479 | return MODE_NO_DBLESCAN; | |
480 | } | |
481 | ||
482 | if (fixed_mode) { | |
483 | if (mode->hdisplay > fixed_mode->hdisplay) | |
484 | return MODE_PANEL; | |
485 | if (mode->vdisplay > fixed_mode->vdisplay) | |
486 | return MODE_PANEL; | |
487 | } | |
488 | ||
36d21f4c | 489 | return MODE_OK; |
4e646495 JN |
490 | } |
491 | ||
492 | /* return txclkesc cycles in terms of divider and duration in us */ | |
493 | static u16 txclkesc(u32 divider, unsigned int us) | |
494 | { | |
495 | switch (divider) { | |
496 | case ESCAPE_CLOCK_DIVIDER_1: | |
497 | default: | |
498 | return 20 * us; | |
499 | case ESCAPE_CLOCK_DIVIDER_2: | |
500 | return 10 * us; | |
501 | case ESCAPE_CLOCK_DIVIDER_4: | |
502 | return 5 * us; | |
503 | } | |
504 | } | |
505 | ||
506 | /* return pixels in terms of txbyteclkhs */ | |
7f0c8605 SK |
507 | static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, |
508 | u16 burst_mode_ratio) | |
4e646495 | 509 | { |
7f0c8605 | 510 | return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, |
7f3de833 | 511 | 8 * 100), lane_count); |
4e646495 JN |
512 | } |
513 | ||
514 | static void set_dsi_timings(struct drm_encoder *encoder, | |
515 | const struct drm_display_mode *mode) | |
516 | { | |
517 | struct drm_device *dev = encoder->dev; | |
518 | struct drm_i915_private *dev_priv = dev->dev_private; | |
519 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
520 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
aa102d28 | 521 | enum port port; |
6e3c9717 | 522 | unsigned int bpp = intel_crtc->config->pipe_bpp; |
4e646495 JN |
523 | unsigned int lane_count = intel_dsi->lane_count; |
524 | ||
525 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; | |
526 | ||
527 | hactive = mode->hdisplay; | |
528 | hfp = mode->hsync_start - mode->hdisplay; | |
529 | hsync = mode->hsync_end - mode->hsync_start; | |
530 | hbp = mode->htotal - mode->hsync_end; | |
531 | ||
aa102d28 GS |
532 | if (intel_dsi->dual_link) { |
533 | hactive /= 2; | |
534 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) | |
535 | hactive += intel_dsi->pixel_overlap; | |
536 | hfp /= 2; | |
537 | hsync /= 2; | |
538 | hbp /= 2; | |
539 | } | |
540 | ||
4e646495 JN |
541 | vfp = mode->vsync_start - mode->vdisplay; |
542 | vsync = mode->vsync_end - mode->vsync_start; | |
543 | vbp = mode->vtotal - mode->vsync_end; | |
544 | ||
545 | /* horizontal values are in terms of high speed byte clock */ | |
7f0c8605 | 546 | hactive = txbyteclkhs(hactive, bpp, lane_count, |
7f3de833 | 547 | intel_dsi->burst_mode_ratio); |
7f0c8605 SK |
548 | hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
549 | hsync = txbyteclkhs(hsync, bpp, lane_count, | |
7f3de833 | 550 | intel_dsi->burst_mode_ratio); |
7f0c8605 | 551 | hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
4e646495 | 552 | |
aa102d28 GS |
553 | for_each_dsi_port(port, intel_dsi->ports) { |
554 | I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); | |
555 | I915_WRITE(MIPI_HFP_COUNT(port), hfp); | |
556 | ||
557 | /* meaningful for video mode non-burst sync pulse mode only, | |
558 | * can be zero for non-burst sync events and burst modes */ | |
559 | I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); | |
560 | I915_WRITE(MIPI_HBP_COUNT(port), hbp); | |
561 | ||
562 | /* vertical values are in terms of lines */ | |
563 | I915_WRITE(MIPI_VFP_COUNT(port), vfp); | |
564 | I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); | |
565 | I915_WRITE(MIPI_VBP_COUNT(port), vbp); | |
566 | } | |
4e646495 JN |
567 | } |
568 | ||
07e4fb9e | 569 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder) |
4e646495 JN |
570 | { |
571 | struct drm_encoder *encoder = &intel_encoder->base; | |
572 | struct drm_device *dev = encoder->dev; | |
573 | struct drm_i915_private *dev_priv = dev->dev_private; | |
574 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
575 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
576 | struct drm_display_mode *adjusted_mode = | |
6e3c9717 | 577 | &intel_crtc->config->base.adjusted_mode; |
24ee0e64 | 578 | enum port port; |
6e3c9717 | 579 | unsigned int bpp = intel_crtc->config->pipe_bpp; |
4e646495 | 580 | u32 val, tmp; |
24ee0e64 | 581 | u16 mode_hdisplay; |
4e646495 | 582 | |
e7d7cad0 | 583 | DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe)); |
4e646495 | 584 | |
24ee0e64 | 585 | mode_hdisplay = adjusted_mode->hdisplay; |
4e646495 | 586 | |
24ee0e64 GS |
587 | if (intel_dsi->dual_link) { |
588 | mode_hdisplay /= 2; | |
589 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) | |
590 | mode_hdisplay += intel_dsi->pixel_overlap; | |
591 | } | |
4e646495 | 592 | |
24ee0e64 GS |
593 | for_each_dsi_port(port, intel_dsi->ports) { |
594 | /* escape clock divider, 20MHz, shared for A and C. | |
595 | * device ready must be off when doing this! txclkesc? */ | |
596 | tmp = I915_READ(MIPI_CTRL(PORT_A)); | |
597 | tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; | |
598 | I915_WRITE(MIPI_CTRL(PORT_A), tmp | ESCAPE_CLOCK_DIVIDER_1); | |
599 | ||
600 | /* read request priority is per pipe */ | |
601 | tmp = I915_READ(MIPI_CTRL(port)); | |
602 | tmp &= ~READ_REQUEST_PRIORITY_MASK; | |
603 | I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH); | |
604 | ||
605 | /* XXX: why here, why like this? handling in irq handler?! */ | |
606 | I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); | |
607 | I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); | |
608 | ||
609 | I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); | |
610 | ||
611 | I915_WRITE(MIPI_DPI_RESOLUTION(port), | |
612 | adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT | | |
613 | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); | |
614 | } | |
4e646495 JN |
615 | |
616 | set_dsi_timings(encoder, adjusted_mode); | |
617 | ||
618 | val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; | |
619 | if (is_cmd_mode(intel_dsi)) { | |
620 | val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; | |
621 | val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ | |
622 | } else { | |
623 | val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; | |
624 | ||
625 | /* XXX: cross-check bpp vs. pixel format? */ | |
626 | val |= intel_dsi->pixel_format; | |
627 | } | |
4e646495 | 628 | |
24ee0e64 GS |
629 | tmp = 0; |
630 | if (intel_dsi->eotp_pkt == 0) | |
631 | tmp |= EOT_DISABLE; | |
632 | if (intel_dsi->clock_stop) | |
633 | tmp |= CLOCKSTOP; | |
4e646495 | 634 | |
24ee0e64 GS |
635 | for_each_dsi_port(port, intel_dsi->ports) { |
636 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); | |
637 | ||
638 | /* timeouts for recovery. one frame IIUC. if counter expires, | |
639 | * EOT and stop state. */ | |
640 | ||
641 | /* | |
642 | * In burst mode, value greater than one DPI line Time in byte | |
643 | * clock (txbyteclkhs) To timeout this timer 1+ of the above | |
644 | * said value is recommended. | |
645 | * | |
646 | * In non-burst mode, Value greater than one DPI frame time in | |
647 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above | |
648 | * said value is recommended. | |
649 | * | |
650 | * In DBI only mode, value greater than one DBI frame time in | |
651 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above | |
652 | * said value is recommended. | |
653 | */ | |
4e646495 | 654 | |
24ee0e64 GS |
655 | if (is_vid_mode(intel_dsi) && |
656 | intel_dsi->video_mode_format == VIDEO_MODE_BURST) { | |
657 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), | |
658 | txbyteclkhs(adjusted_mode->htotal, bpp, | |
659 | intel_dsi->lane_count, | |
660 | intel_dsi->burst_mode_ratio) + 1); | |
661 | } else { | |
662 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), | |
663 | txbyteclkhs(adjusted_mode->vtotal * | |
664 | adjusted_mode->htotal, | |
665 | bpp, intel_dsi->lane_count, | |
666 | intel_dsi->burst_mode_ratio) + 1); | |
667 | } | |
668 | I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); | |
669 | I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), | |
670 | intel_dsi->turn_arnd_val); | |
671 | I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), | |
672 | intel_dsi->rst_timer_val); | |
f1c79f16 | 673 | |
24ee0e64 | 674 | /* dphy stuff */ |
f1c79f16 | 675 | |
24ee0e64 GS |
676 | /* in terms of low power clock */ |
677 | I915_WRITE(MIPI_INIT_COUNT(port), | |
678 | txclkesc(intel_dsi->escape_clk_div, 100)); | |
4e646495 | 679 | |
4e646495 | 680 | |
24ee0e64 GS |
681 | /* recovery disables */ |
682 | I915_WRITE(MIPI_EOT_DISABLE(port), val); | |
cf4dbd2e | 683 | |
24ee0e64 GS |
684 | /* in terms of low power clock */ |
685 | I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); | |
4e646495 | 686 | |
24ee0e64 GS |
687 | /* in terms of txbyteclkhs. actual high to low switch + |
688 | * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. | |
689 | * | |
690 | * XXX: write MIPI_STOP_STATE_STALL? | |
691 | */ | |
692 | I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), | |
693 | intel_dsi->hs_to_lp_count); | |
694 | ||
695 | /* XXX: low power clock equivalence in terms of byte clock. | |
696 | * the number of byte clocks occupied in one low power clock. | |
697 | * based on txbyteclkhs and txclkesc. | |
698 | * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL | |
699 | * ) / 105.??? | |
700 | */ | |
701 | I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); | |
702 | ||
703 | /* the bw essential for transmitting 16 long packets containing | |
704 | * 252 bytes meant for dcs write memory command is programmed in | |
705 | * this register in terms of byte clocks. based on dsi transfer | |
706 | * rate and the number of lanes configured the time taken to | |
707 | * transmit 16 long packets in a dsi stream varies. */ | |
708 | I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); | |
709 | ||
710 | I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), | |
711 | intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | | |
712 | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); | |
713 | ||
714 | if (is_vid_mode(intel_dsi)) | |
715 | /* Some panels might have resolution which is not a | |
716 | * multiple of 64 like 1366 x 768. Enable RANDOM | |
717 | * resolution support for such panels by default */ | |
718 | I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), | |
719 | intel_dsi->video_frmt_cfg_bits | | |
720 | intel_dsi->video_mode_format | | |
721 | IP_TG_CONFIG | | |
722 | RANDOM_DPI_DISPLAY_RESOLUTION); | |
723 | } | |
4e646495 JN |
724 | } |
725 | ||
07e4fb9e DV |
726 | static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder) |
727 | { | |
728 | DRM_DEBUG_KMS("\n"); | |
729 | ||
730 | intel_dsi_prepare(encoder); | |
731 | ||
732 | vlv_enable_dsi_pll(encoder); | |
733 | } | |
734 | ||
4e646495 JN |
735 | static enum drm_connector_status |
736 | intel_dsi_detect(struct drm_connector *connector, bool force) | |
737 | { | |
36d21f4c | 738 | return connector_status_connected; |
4e646495 JN |
739 | } |
740 | ||
741 | static int intel_dsi_get_modes(struct drm_connector *connector) | |
742 | { | |
743 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
744 | struct drm_display_mode *mode; | |
745 | ||
746 | DRM_DEBUG_KMS("\n"); | |
747 | ||
748 | if (!intel_connector->panel.fixed_mode) { | |
749 | DRM_DEBUG_KMS("no fixed mode\n"); | |
750 | return 0; | |
751 | } | |
752 | ||
753 | mode = drm_mode_duplicate(connector->dev, | |
754 | intel_connector->panel.fixed_mode); | |
755 | if (!mode) { | |
756 | DRM_DEBUG_KMS("drm_mode_duplicate failed\n"); | |
757 | return 0; | |
758 | } | |
759 | ||
760 | drm_mode_probed_add(connector, mode); | |
761 | return 1; | |
762 | } | |
763 | ||
764 | static void intel_dsi_destroy(struct drm_connector *connector) | |
765 | { | |
766 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
767 | ||
768 | DRM_DEBUG_KMS("\n"); | |
769 | intel_panel_fini(&intel_connector->panel); | |
4e646495 JN |
770 | drm_connector_cleanup(connector); |
771 | kfree(connector); | |
772 | } | |
773 | ||
774 | static const struct drm_encoder_funcs intel_dsi_funcs = { | |
775 | .destroy = intel_encoder_destroy, | |
776 | }; | |
777 | ||
778 | static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { | |
779 | .get_modes = intel_dsi_get_modes, | |
780 | .mode_valid = intel_dsi_mode_valid, | |
781 | .best_encoder = intel_best_encoder, | |
782 | }; | |
783 | ||
784 | static const struct drm_connector_funcs intel_dsi_connector_funcs = { | |
785 | .dpms = intel_connector_dpms, | |
786 | .detect = intel_dsi_detect, | |
787 | .destroy = intel_dsi_destroy, | |
788 | .fill_modes = drm_helper_probe_single_connector_modes, | |
2545e4a6 | 789 | .atomic_get_property = intel_connector_atomic_get_property, |
c6f95f27 | 790 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
4e646495 JN |
791 | }; |
792 | ||
4328633d | 793 | void intel_dsi_init(struct drm_device *dev) |
4e646495 JN |
794 | { |
795 | struct intel_dsi *intel_dsi; | |
796 | struct intel_encoder *intel_encoder; | |
797 | struct drm_encoder *encoder; | |
798 | struct intel_connector *intel_connector; | |
799 | struct drm_connector *connector; | |
800 | struct drm_display_mode *fixed_mode = NULL; | |
b6fdd0f2 | 801 | struct drm_i915_private *dev_priv = dev->dev_private; |
4e646495 JN |
802 | const struct intel_dsi_device *dsi; |
803 | unsigned int i; | |
804 | ||
805 | DRM_DEBUG_KMS("\n"); | |
806 | ||
3e6bd011 SK |
807 | /* There is no detection method for MIPI so rely on VBT */ |
808 | if (!dev_priv->vbt.has_mipi) | |
4328633d | 809 | return; |
3e6bd011 | 810 | |
868d665b CJ |
811 | if (IS_VALLEYVIEW(dev)) { |
812 | dev_priv->mipi_mmio_base = VLV_MIPI_BASE; | |
813 | } else { | |
814 | DRM_ERROR("Unsupported Mipi device to reg base"); | |
815 | return; | |
816 | } | |
3e6bd011 | 817 | |
4e646495 JN |
818 | intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); |
819 | if (!intel_dsi) | |
4328633d | 820 | return; |
4e646495 JN |
821 | |
822 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); | |
823 | if (!intel_connector) { | |
824 | kfree(intel_dsi); | |
4328633d | 825 | return; |
4e646495 JN |
826 | } |
827 | ||
828 | intel_encoder = &intel_dsi->base; | |
829 | encoder = &intel_encoder->base; | |
830 | intel_dsi->attached_connector = intel_connector; | |
831 | ||
832 | connector = &intel_connector->base; | |
833 | ||
834 | drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI); | |
835 | ||
836 | /* XXX: very likely not all of these are needed */ | |
837 | intel_encoder->hot_plug = intel_dsi_hot_plug; | |
838 | intel_encoder->compute_config = intel_dsi_compute_config; | |
839 | intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable; | |
840 | intel_encoder->pre_enable = intel_dsi_pre_enable; | |
2634fd7f | 841 | intel_encoder->enable = intel_dsi_enable_nop; |
c315faf8 | 842 | intel_encoder->disable = intel_dsi_pre_disable; |
4e646495 JN |
843 | intel_encoder->post_disable = intel_dsi_post_disable; |
844 | intel_encoder->get_hw_state = intel_dsi_get_hw_state; | |
845 | intel_encoder->get_config = intel_dsi_get_config; | |
846 | ||
847 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
4932e2c3 | 848 | intel_connector->unregister = intel_connector_unregister; |
4e646495 | 849 | |
e7d7cad0 | 850 | /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */ |
17af40a8 | 851 | if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) { |
e7d7cad0 | 852 | intel_encoder->crtc_mask = (1 << PIPE_A); |
17af40a8 JN |
853 | intel_dsi->ports = (1 << PORT_A); |
854 | } else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIC) { | |
e7d7cad0 | 855 | intel_encoder->crtc_mask = (1 << PIPE_B); |
17af40a8 JN |
856 | intel_dsi->ports = (1 << PORT_C); |
857 | } | |
e7d7cad0 | 858 | |
4e646495 JN |
859 | for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) { |
860 | dsi = &intel_dsi_devices[i]; | |
861 | intel_dsi->dev = *dsi; | |
862 | ||
863 | if (dsi->dev_ops->init(&intel_dsi->dev)) | |
864 | break; | |
865 | } | |
866 | ||
867 | if (i == ARRAY_SIZE(intel_dsi_devices)) { | |
868 | DRM_DEBUG_KMS("no device found\n"); | |
869 | goto err; | |
870 | } | |
871 | ||
872 | intel_encoder->type = INTEL_OUTPUT_DSI; | |
bc079e8b | 873 | intel_encoder->cloneable = 0; |
4e646495 JN |
874 | drm_connector_init(dev, connector, &intel_dsi_connector_funcs, |
875 | DRM_MODE_CONNECTOR_DSI); | |
876 | ||
877 | drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); | |
878 | ||
879 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ | |
880 | connector->interlace_allowed = false; | |
881 | connector->doublescan_allowed = false; | |
882 | ||
883 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
884 | ||
34ea3d38 | 885 | drm_connector_register(connector); |
4e646495 JN |
886 | |
887 | fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev); | |
888 | if (!fixed_mode) { | |
889 | DRM_DEBUG_KMS("no fixed mode\n"); | |
890 | goto err; | |
891 | } | |
892 | ||
893 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
4b6ed685 | 894 | intel_panel_init(&intel_connector->panel, fixed_mode, NULL); |
4e646495 | 895 | |
4328633d | 896 | return; |
4e646495 JN |
897 | |
898 | err: | |
899 | drm_encoder_cleanup(&intel_encoder->base); | |
900 | kfree(intel_dsi); | |
901 | kfree(intel_connector); | |
4e646495 | 902 | } |