Commit | Line | Data |
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4e646495 JN |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Author: Jani Nikula <jani.nikula@intel.com> | |
24 | */ | |
25 | ||
26 | #include <drm/drmP.h> | |
27 | #include <drm/drm_crtc.h> | |
28 | #include <drm/drm_edid.h> | |
29 | #include <drm/i915_drm.h> | |
30 | #include <linux/slab.h> | |
31 | #include "i915_drv.h" | |
32 | #include "intel_drv.h" | |
33 | #include "intel_dsi.h" | |
34 | #include "intel_dsi_cmd.h" | |
35 | ||
36 | /* the sub-encoders aka panel drivers */ | |
37 | static const struct intel_dsi_device intel_dsi_devices[] = { | |
2ab8b458 SK |
38 | { |
39 | .panel_id = MIPI_DSI_GENERIC_PANEL_ID, | |
40 | .name = "vbt-generic-dsi-vid-mode-display", | |
41 | .dev_ops = &vbt_generic_dsi_display_ops, | |
42 | }, | |
4e646495 JN |
43 | }; |
44 | ||
7f6a6a4a | 45 | static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port) |
3b1808bf JN |
46 | { |
47 | struct drm_encoder *encoder = &intel_dsi->base.base; | |
48 | struct drm_device *dev = encoder->dev; | |
49 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3b1808bf JN |
50 | u32 mask; |
51 | ||
52 | mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | | |
53 | LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; | |
54 | ||
55 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100)) | |
56 | DRM_ERROR("DPI FIFOs are not empty\n"); | |
57 | } | |
58 | ||
e9fe51c6 | 59 | static void band_gap_reset(struct drm_i915_private *dev_priv) |
4ce8c9a7 SK |
60 | { |
61 | mutex_lock(&dev_priv->dpio_lock); | |
62 | ||
e9fe51c6 SK |
63 | vlv_flisdsi_write(dev_priv, 0x08, 0x0001); |
64 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); | |
65 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); | |
66 | udelay(150); | |
67 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); | |
68 | vlv_flisdsi_write(dev_priv, 0x08, 0x0000); | |
4ce8c9a7 SK |
69 | |
70 | mutex_unlock(&dev_priv->dpio_lock); | |
4ce8c9a7 SK |
71 | } |
72 | ||
4e646495 JN |
73 | static inline bool is_vid_mode(struct intel_dsi *intel_dsi) |
74 | { | |
dfba2e2d | 75 | return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE; |
4e646495 JN |
76 | } |
77 | ||
78 | static inline bool is_cmd_mode(struct intel_dsi *intel_dsi) | |
79 | { | |
dfba2e2d | 80 | return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE; |
4e646495 JN |
81 | } |
82 | ||
83 | static void intel_dsi_hot_plug(struct intel_encoder *encoder) | |
84 | { | |
85 | DRM_DEBUG_KMS("\n"); | |
86 | } | |
87 | ||
88 | static bool intel_dsi_compute_config(struct intel_encoder *encoder, | |
5cec258b | 89 | struct intel_crtc_state *config) |
4e646495 JN |
90 | { |
91 | struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, | |
92 | base); | |
93 | struct intel_connector *intel_connector = intel_dsi->attached_connector; | |
94 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
2d112de7 | 95 | struct drm_display_mode *adjusted_mode = &config->base.adjusted_mode; |
4e646495 JN |
96 | |
97 | DRM_DEBUG_KMS("\n"); | |
98 | ||
99 | if (fixed_mode) | |
100 | intel_fixed_panel_mode(fixed_mode, adjusted_mode); | |
101 | ||
f573de5a SK |
102 | /* DSI uses short packets for sync events, so clear mode flags for DSI */ |
103 | adjusted_mode->flags = 0; | |
104 | ||
4e646495 JN |
105 | return true; |
106 | } | |
107 | ||
5505a244 GS |
108 | static void intel_dsi_port_enable(struct intel_encoder *encoder) |
109 | { | |
110 | struct drm_device *dev = encoder->base.dev; | |
111 | struct drm_i915_private *dev_priv = dev->dev_private; | |
112 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
113 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
369602d3 | 114 | enum port port; |
5505a244 GS |
115 | u32 temp; |
116 | ||
a9da9bce GS |
117 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { |
118 | temp = I915_READ(VLV_CHICKEN_3); | |
119 | temp &= ~PIXEL_OVERLAP_CNT_MASK | | |
120 | intel_dsi->pixel_overlap << | |
121 | PIXEL_OVERLAP_CNT_SHIFT; | |
122 | I915_WRITE(VLV_CHICKEN_3, temp); | |
123 | } | |
124 | ||
369602d3 GS |
125 | for_each_dsi_port(port, intel_dsi->ports) { |
126 | temp = I915_READ(MIPI_PORT_CTRL(port)); | |
127 | temp &= ~LANE_CONFIGURATION_MASK; | |
128 | temp &= ~DUAL_LINK_MODE_MASK; | |
129 | ||
130 | if (intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) { | |
131 | temp |= (intel_dsi->dual_link - 1) | |
132 | << DUAL_LINK_MODE_SHIFT; | |
133 | temp |= intel_crtc->pipe ? | |
134 | LANE_CONFIGURATION_DUAL_LINK_B : | |
135 | LANE_CONFIGURATION_DUAL_LINK_A; | |
136 | } | |
137 | /* assert ip_tg_enable signal */ | |
138 | I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE); | |
139 | POSTING_READ(MIPI_PORT_CTRL(port)); | |
140 | } | |
5505a244 GS |
141 | } |
142 | ||
143 | static void intel_dsi_port_disable(struct intel_encoder *encoder) | |
144 | { | |
145 | struct drm_device *dev = encoder->base.dev; | |
146 | struct drm_i915_private *dev_priv = dev->dev_private; | |
369602d3 GS |
147 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
148 | enum port port; | |
5505a244 GS |
149 | u32 temp; |
150 | ||
369602d3 GS |
151 | for_each_dsi_port(port, intel_dsi->ports) { |
152 | /* de-assert ip_tg_enable signal */ | |
153 | temp = I915_READ(MIPI_PORT_CTRL(port)); | |
154 | I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE); | |
155 | POSTING_READ(MIPI_PORT_CTRL(port)); | |
156 | } | |
5505a244 GS |
157 | } |
158 | ||
1dbd7cb2 | 159 | static void intel_dsi_device_ready(struct intel_encoder *encoder) |
4e646495 | 160 | { |
1dbd7cb2 | 161 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
24ee0e64 GS |
162 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
163 | enum port port; | |
1dbd7cb2 SK |
164 | u32 val; |
165 | ||
4e646495 | 166 | DRM_DEBUG_KMS("\n"); |
4e646495 | 167 | |
2095f9fc SK |
168 | mutex_lock(&dev_priv->dpio_lock); |
169 | /* program rcomp for compliance, reduce from 50 ohms to 45 ohms | |
170 | * needed everytime after power gate */ | |
171 | vlv_flisdsi_write(dev_priv, 0x04, 0x0004); | |
172 | mutex_unlock(&dev_priv->dpio_lock); | |
173 | ||
174 | /* bandgap reset is needed after everytime we do power gate */ | |
175 | band_gap_reset(dev_priv); | |
176 | ||
24ee0e64 | 177 | for_each_dsi_port(port, intel_dsi->ports) { |
aceb365c | 178 | |
24ee0e64 GS |
179 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); |
180 | usleep_range(2500, 3000); | |
aceb365c | 181 | |
24ee0e64 | 182 | val = I915_READ(MIPI_PORT_CTRL(port)); |
bf344e80 GS |
183 | |
184 | /* Enable MIPI PHY transparent latch | |
185 | * Common bit for both MIPI Port A & MIPI Port C | |
186 | * No similar bit in MIPI Port C reg | |
187 | */ | |
188 | I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD); | |
24ee0e64 | 189 | usleep_range(1000, 1500); |
aceb365c | 190 | |
24ee0e64 GS |
191 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); |
192 | usleep_range(2500, 3000); | |
193 | ||
194 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); | |
195 | usleep_range(2500, 3000); | |
196 | } | |
1dbd7cb2 | 197 | } |
1dbd7cb2 SK |
198 | |
199 | static void intel_dsi_enable(struct intel_encoder *encoder) | |
200 | { | |
201 | struct drm_device *dev = encoder->base.dev; | |
202 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1dbd7cb2 | 203 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
4934b656 | 204 | enum port port; |
1dbd7cb2 SK |
205 | |
206 | DRM_DEBUG_KMS("\n"); | |
b9f5e07d | 207 | |
4934b656 JN |
208 | if (is_cmd_mode(intel_dsi)) { |
209 | for_each_dsi_port(port, intel_dsi->ports) | |
210 | I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); | |
211 | } else { | |
4e646495 | 212 | msleep(20); /* XXX */ |
f03e4179 JN |
213 | for_each_dsi_port(port, intel_dsi->ports) |
214 | dpi_send_cmd(intel_dsi, TURN_ON, DPI_LP_MODE_EN, port); | |
4e646495 JN |
215 | msleep(100); |
216 | ||
2634fd7f SK |
217 | if (intel_dsi->dev.dev_ops->enable) |
218 | intel_dsi->dev.dev_ops->enable(&intel_dsi->dev); | |
219 | ||
7f6a6a4a JN |
220 | for_each_dsi_port(port, intel_dsi->ports) |
221 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
1381308b | 222 | |
5505a244 | 223 | intel_dsi_port_enable(encoder); |
4e646495 | 224 | } |
2634fd7f SK |
225 | } |
226 | ||
227 | static void intel_dsi_pre_enable(struct intel_encoder *encoder) | |
228 | { | |
20e5bf66 SK |
229 | struct drm_device *dev = encoder->base.dev; |
230 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2634fd7f | 231 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
20e5bf66 SK |
232 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
233 | enum pipe pipe = intel_crtc->pipe; | |
7f6a6a4a | 234 | enum port port; |
20e5bf66 | 235 | u32 tmp; |
2634fd7f SK |
236 | |
237 | DRM_DEBUG_KMS("\n"); | |
238 | ||
20e5bf66 SK |
239 | /* Disable DPOunit clock gating, can stall pipe |
240 | * and we need DPLL REFA always enabled */ | |
241 | tmp = I915_READ(DPLL(pipe)); | |
242 | tmp |= DPLL_REFA_CLK_ENABLE_VLV; | |
243 | I915_WRITE(DPLL(pipe), tmp); | |
244 | ||
f573de5a | 245 | /* update the hw state for DPLL */ |
6e3c9717 | 246 | intel_crtc->config->dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV | |
7f3de833 | 247 | DPLL_REFA_CLK_ENABLE_VLV; |
f573de5a | 248 | |
20e5bf66 SK |
249 | tmp = I915_READ(DSPCLK_GATE_D); |
250 | tmp |= DPOUNIT_CLOCK_GATE_DISABLE; | |
251 | I915_WRITE(DSPCLK_GATE_D, tmp); | |
2634fd7f SK |
252 | |
253 | /* put device in ready state */ | |
254 | intel_dsi_device_ready(encoder); | |
4e646495 | 255 | |
df38e655 SK |
256 | msleep(intel_dsi->panel_on_delay); |
257 | ||
20e5bf66 SK |
258 | if (intel_dsi->dev.dev_ops->panel_reset) |
259 | intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev); | |
260 | ||
7f6a6a4a JN |
261 | for_each_dsi_port(port, intel_dsi->ports) |
262 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
1381308b | 263 | |
2634fd7f SK |
264 | /* Enable port in pre-enable phase itself because as per hw team |
265 | * recommendation, port should be enabled befor plane & pipe */ | |
266 | intel_dsi_enable(encoder); | |
267 | } | |
268 | ||
269 | static void intel_dsi_enable_nop(struct intel_encoder *encoder) | |
270 | { | |
271 | DRM_DEBUG_KMS("\n"); | |
272 | ||
273 | /* for DSI port enable has to be done before pipe | |
274 | * and plane enable, so port enable is done in | |
275 | * pre_enable phase itself unlike other encoders | |
276 | */ | |
4e646495 JN |
277 | } |
278 | ||
c315faf8 ID |
279 | static void intel_dsi_pre_disable(struct intel_encoder *encoder) |
280 | { | |
281 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
f03e4179 | 282 | enum port port; |
c315faf8 ID |
283 | |
284 | DRM_DEBUG_KMS("\n"); | |
285 | ||
286 | if (is_vid_mode(intel_dsi)) { | |
287 | /* Send Shutdown command to the panel in LP mode */ | |
f03e4179 JN |
288 | for_each_dsi_port(port, intel_dsi->ports) |
289 | dpi_send_cmd(intel_dsi, SHUTDOWN, DPI_LP_MODE_EN, port); | |
c315faf8 ID |
290 | msleep(10); |
291 | } | |
292 | } | |
293 | ||
4e646495 JN |
294 | static void intel_dsi_disable(struct intel_encoder *encoder) |
295 | { | |
1dbd7cb2 SK |
296 | struct drm_device *dev = encoder->base.dev; |
297 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4e646495 | 298 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
384f02a2 | 299 | enum port port; |
4e646495 JN |
300 | u32 temp; |
301 | ||
302 | DRM_DEBUG_KMS("\n"); | |
303 | ||
4e646495 | 304 | if (is_vid_mode(intel_dsi)) { |
7f6a6a4a JN |
305 | for_each_dsi_port(port, intel_dsi->ports) |
306 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
1381308b | 307 | |
5505a244 | 308 | intel_dsi_port_disable(encoder); |
4e646495 JN |
309 | msleep(2); |
310 | } | |
311 | ||
384f02a2 GS |
312 | for_each_dsi_port(port, intel_dsi->ports) { |
313 | /* Panel commands can be sent when clock is in LP11 */ | |
314 | I915_WRITE(MIPI_DEVICE_READY(port), 0x0); | |
339023ec | 315 | |
384f02a2 GS |
316 | temp = I915_READ(MIPI_CTRL(port)); |
317 | temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; | |
318 | I915_WRITE(MIPI_CTRL(port), temp | | |
319 | intel_dsi->escape_clk_div << | |
320 | ESCAPE_CLOCK_DIVIDER_SHIFT); | |
339023ec | 321 | |
384f02a2 | 322 | I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); |
339023ec | 323 | |
384f02a2 GS |
324 | temp = I915_READ(MIPI_DSI_FUNC_PRG(port)); |
325 | temp &= ~VID_MODE_FORMAT_MASK; | |
326 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp); | |
339023ec | 327 | |
384f02a2 GS |
328 | I915_WRITE(MIPI_DEVICE_READY(port), 0x1); |
329 | } | |
1dbd7cb2 SK |
330 | /* if disable packets are sent before sending shutdown packet then in |
331 | * some next enable sequence send turn on packet error is observed */ | |
332 | if (intel_dsi->dev.dev_ops->disable) | |
333 | intel_dsi->dev.dev_ops->disable(&intel_dsi->dev); | |
1381308b | 334 | |
7f6a6a4a JN |
335 | for_each_dsi_port(port, intel_dsi->ports) |
336 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
4e646495 JN |
337 | } |
338 | ||
1dbd7cb2 | 339 | static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) |
4e646495 | 340 | { |
1dbd7cb2 | 341 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
384f02a2 GS |
342 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
343 | enum port port; | |
1dbd7cb2 SK |
344 | u32 val; |
345 | ||
4e646495 | 346 | DRM_DEBUG_KMS("\n"); |
384f02a2 | 347 | for_each_dsi_port(port, intel_dsi->ports) { |
be4fc046 | 348 | |
384f02a2 GS |
349 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | |
350 | ULPS_STATE_ENTER); | |
351 | usleep_range(2000, 2500); | |
352 | ||
353 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | | |
354 | ULPS_STATE_EXIT); | |
355 | usleep_range(2000, 2500); | |
356 | ||
357 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | | |
358 | ULPS_STATE_ENTER); | |
359 | usleep_range(2000, 2500); | |
360 | ||
361 | /* Wait till Clock lanes are in LP-00 state for MIPI Port A | |
362 | * only. MIPI Port C has no similar bit for checking | |
363 | */ | |
364 | if (wait_for(((I915_READ(MIPI_PORT_CTRL(PORT_A)) & AFE_LATCHOUT) | |
365 | == 0x00000), 30)) | |
366 | DRM_ERROR("DSI LP not going Low\n"); | |
367 | ||
368 | val = I915_READ(MIPI_PORT_CTRL(port)); | |
369 | /* Disable MIPI PHY transparent latch | |
370 | * Common bit for both MIPI Port A & MIPI Port C | |
371 | */ | |
372 | I915_WRITE(MIPI_PORT_CTRL(PORT_A), val & ~LP_OUTPUT_HOLD); | |
373 | usleep_range(1000, 1500); | |
374 | ||
375 | I915_WRITE(MIPI_DEVICE_READY(port), 0x00); | |
376 | usleep_range(2000, 2500); | |
377 | } | |
1dbd7cb2 | 378 | |
be4fc046 | 379 | vlv_disable_dsi_pll(encoder); |
4e646495 | 380 | } |
20e5bf66 | 381 | |
1dbd7cb2 SK |
382 | static void intel_dsi_post_disable(struct intel_encoder *encoder) |
383 | { | |
20e5bf66 | 384 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
1dbd7cb2 | 385 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
20e5bf66 | 386 | u32 val; |
1dbd7cb2 SK |
387 | |
388 | DRM_DEBUG_KMS("\n"); | |
389 | ||
c315faf8 ID |
390 | intel_dsi_disable(encoder); |
391 | ||
1dbd7cb2 SK |
392 | intel_dsi_clear_device_ready(encoder); |
393 | ||
20e5bf66 SK |
394 | val = I915_READ(DSPCLK_GATE_D); |
395 | val &= ~DPOUNIT_CLOCK_GATE_DISABLE; | |
396 | I915_WRITE(DSPCLK_GATE_D, val); | |
397 | ||
1dbd7cb2 SK |
398 | if (intel_dsi->dev.dev_ops->disable_panel_power) |
399 | intel_dsi->dev.dev_ops->disable_panel_power(&intel_dsi->dev); | |
df38e655 SK |
400 | |
401 | msleep(intel_dsi->panel_off_delay); | |
402 | msleep(intel_dsi->panel_pwr_cycle_delay); | |
1dbd7cb2 | 403 | } |
4e646495 JN |
404 | |
405 | static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, | |
406 | enum pipe *pipe) | |
407 | { | |
408 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
c0beefd2 GS |
409 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
410 | struct drm_device *dev = encoder->base.dev; | |
6d129bea | 411 | enum intel_display_power_domain power_domain; |
c0beefd2 | 412 | u32 dpi_enabled, func; |
e7d7cad0 | 413 | enum port port; |
4e646495 JN |
414 | |
415 | DRM_DEBUG_KMS("\n"); | |
416 | ||
6d129bea | 417 | power_domain = intel_display_port_power_domain(encoder); |
f458ebbc | 418 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
6d129bea ID |
419 | return false; |
420 | ||
4e646495 | 421 | /* XXX: this only works for one DSI output */ |
c0beefd2 | 422 | for_each_dsi_port(port, intel_dsi->ports) { |
e7d7cad0 | 423 | func = I915_READ(MIPI_DSI_FUNC_PRG(port)); |
c0beefd2 GS |
424 | dpi_enabled = I915_READ(MIPI_PORT_CTRL(port)) & |
425 | DPI_ENABLE; | |
426 | ||
427 | /* Due to some hardware limitations on BYT, MIPI Port C DPI | |
428 | * Enable bit does not get set. To check whether DSI Port C | |
429 | * was enabled in BIOS, check the Pipe B enable bit | |
430 | */ | |
431 | if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && | |
432 | (port == PORT_C)) | |
433 | dpi_enabled = I915_READ(PIPECONF(PIPE_B)) & | |
434 | PIPECONF_ENABLE; | |
4e646495 | 435 | |
c0beefd2 | 436 | if (dpi_enabled || (func & CMD_MODE_DATA_WIDTH_MASK)) { |
e7d7cad0 | 437 | if (I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY) { |
c0beefd2 | 438 | *pipe = port == PORT_A ? PIPE_A : PIPE_B; |
4e646495 JN |
439 | return true; |
440 | } | |
441 | } | |
442 | } | |
443 | ||
444 | return false; | |
445 | } | |
446 | ||
447 | static void intel_dsi_get_config(struct intel_encoder *encoder, | |
5cec258b | 448 | struct intel_crtc_state *pipe_config) |
4e646495 | 449 | { |
f573de5a | 450 | u32 pclk; |
4e646495 JN |
451 | DRM_DEBUG_KMS("\n"); |
452 | ||
f573de5a SK |
453 | /* |
454 | * DPLL_MD is not used in case of DSI, reading will get some default value | |
455 | * set dpll_md = 0 | |
456 | */ | |
457 | pipe_config->dpll_hw_state.dpll_md = 0; | |
458 | ||
459 | pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp); | |
460 | if (!pclk) | |
461 | return; | |
462 | ||
2d112de7 | 463 | pipe_config->base.adjusted_mode.crtc_clock = pclk; |
f573de5a | 464 | pipe_config->port_clock = pclk; |
4e646495 JN |
465 | } |
466 | ||
c19de8eb DL |
467 | static enum drm_mode_status |
468 | intel_dsi_mode_valid(struct drm_connector *connector, | |
469 | struct drm_display_mode *mode) | |
4e646495 JN |
470 | { |
471 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
472 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
4e646495 JN |
473 | |
474 | DRM_DEBUG_KMS("\n"); | |
475 | ||
476 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { | |
477 | DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n"); | |
478 | return MODE_NO_DBLESCAN; | |
479 | } | |
480 | ||
481 | if (fixed_mode) { | |
482 | if (mode->hdisplay > fixed_mode->hdisplay) | |
483 | return MODE_PANEL; | |
484 | if (mode->vdisplay > fixed_mode->vdisplay) | |
485 | return MODE_PANEL; | |
486 | } | |
487 | ||
36d21f4c | 488 | return MODE_OK; |
4e646495 JN |
489 | } |
490 | ||
491 | /* return txclkesc cycles in terms of divider and duration in us */ | |
492 | static u16 txclkesc(u32 divider, unsigned int us) | |
493 | { | |
494 | switch (divider) { | |
495 | case ESCAPE_CLOCK_DIVIDER_1: | |
496 | default: | |
497 | return 20 * us; | |
498 | case ESCAPE_CLOCK_DIVIDER_2: | |
499 | return 10 * us; | |
500 | case ESCAPE_CLOCK_DIVIDER_4: | |
501 | return 5 * us; | |
502 | } | |
503 | } | |
504 | ||
505 | /* return pixels in terms of txbyteclkhs */ | |
7f0c8605 SK |
506 | static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, |
507 | u16 burst_mode_ratio) | |
4e646495 | 508 | { |
7f0c8605 | 509 | return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, |
7f3de833 | 510 | 8 * 100), lane_count); |
4e646495 JN |
511 | } |
512 | ||
513 | static void set_dsi_timings(struct drm_encoder *encoder, | |
514 | const struct drm_display_mode *mode) | |
515 | { | |
516 | struct drm_device *dev = encoder->dev; | |
517 | struct drm_i915_private *dev_priv = dev->dev_private; | |
518 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
519 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
aa102d28 | 520 | enum port port; |
6e3c9717 | 521 | unsigned int bpp = intel_crtc->config->pipe_bpp; |
4e646495 JN |
522 | unsigned int lane_count = intel_dsi->lane_count; |
523 | ||
524 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; | |
525 | ||
526 | hactive = mode->hdisplay; | |
527 | hfp = mode->hsync_start - mode->hdisplay; | |
528 | hsync = mode->hsync_end - mode->hsync_start; | |
529 | hbp = mode->htotal - mode->hsync_end; | |
530 | ||
aa102d28 GS |
531 | if (intel_dsi->dual_link) { |
532 | hactive /= 2; | |
533 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) | |
534 | hactive += intel_dsi->pixel_overlap; | |
535 | hfp /= 2; | |
536 | hsync /= 2; | |
537 | hbp /= 2; | |
538 | } | |
539 | ||
4e646495 JN |
540 | vfp = mode->vsync_start - mode->vdisplay; |
541 | vsync = mode->vsync_end - mode->vsync_start; | |
542 | vbp = mode->vtotal - mode->vsync_end; | |
543 | ||
544 | /* horizontal values are in terms of high speed byte clock */ | |
7f0c8605 | 545 | hactive = txbyteclkhs(hactive, bpp, lane_count, |
7f3de833 | 546 | intel_dsi->burst_mode_ratio); |
7f0c8605 SK |
547 | hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
548 | hsync = txbyteclkhs(hsync, bpp, lane_count, | |
7f3de833 | 549 | intel_dsi->burst_mode_ratio); |
7f0c8605 | 550 | hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
4e646495 | 551 | |
aa102d28 GS |
552 | for_each_dsi_port(port, intel_dsi->ports) { |
553 | I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); | |
554 | I915_WRITE(MIPI_HFP_COUNT(port), hfp); | |
555 | ||
556 | /* meaningful for video mode non-burst sync pulse mode only, | |
557 | * can be zero for non-burst sync events and burst modes */ | |
558 | I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); | |
559 | I915_WRITE(MIPI_HBP_COUNT(port), hbp); | |
560 | ||
561 | /* vertical values are in terms of lines */ | |
562 | I915_WRITE(MIPI_VFP_COUNT(port), vfp); | |
563 | I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); | |
564 | I915_WRITE(MIPI_VBP_COUNT(port), vbp); | |
565 | } | |
4e646495 JN |
566 | } |
567 | ||
07e4fb9e | 568 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder) |
4e646495 JN |
569 | { |
570 | struct drm_encoder *encoder = &intel_encoder->base; | |
571 | struct drm_device *dev = encoder->dev; | |
572 | struct drm_i915_private *dev_priv = dev->dev_private; | |
573 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
574 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
575 | struct drm_display_mode *adjusted_mode = | |
6e3c9717 | 576 | &intel_crtc->config->base.adjusted_mode; |
24ee0e64 | 577 | enum port port; |
6e3c9717 | 578 | unsigned int bpp = intel_crtc->config->pipe_bpp; |
4e646495 | 579 | u32 val, tmp; |
24ee0e64 | 580 | u16 mode_hdisplay; |
4e646495 | 581 | |
e7d7cad0 | 582 | DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe)); |
4e646495 | 583 | |
24ee0e64 | 584 | mode_hdisplay = adjusted_mode->hdisplay; |
4e646495 | 585 | |
24ee0e64 GS |
586 | if (intel_dsi->dual_link) { |
587 | mode_hdisplay /= 2; | |
588 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) | |
589 | mode_hdisplay += intel_dsi->pixel_overlap; | |
590 | } | |
4e646495 | 591 | |
24ee0e64 GS |
592 | for_each_dsi_port(port, intel_dsi->ports) { |
593 | /* escape clock divider, 20MHz, shared for A and C. | |
594 | * device ready must be off when doing this! txclkesc? */ | |
595 | tmp = I915_READ(MIPI_CTRL(PORT_A)); | |
596 | tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; | |
597 | I915_WRITE(MIPI_CTRL(PORT_A), tmp | ESCAPE_CLOCK_DIVIDER_1); | |
598 | ||
599 | /* read request priority is per pipe */ | |
600 | tmp = I915_READ(MIPI_CTRL(port)); | |
601 | tmp &= ~READ_REQUEST_PRIORITY_MASK; | |
602 | I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH); | |
603 | ||
604 | /* XXX: why here, why like this? handling in irq handler?! */ | |
605 | I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); | |
606 | I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); | |
607 | ||
608 | I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); | |
609 | ||
610 | I915_WRITE(MIPI_DPI_RESOLUTION(port), | |
611 | adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT | | |
612 | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); | |
613 | } | |
4e646495 JN |
614 | |
615 | set_dsi_timings(encoder, adjusted_mode); | |
616 | ||
617 | val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; | |
618 | if (is_cmd_mode(intel_dsi)) { | |
619 | val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; | |
620 | val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ | |
621 | } else { | |
622 | val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; | |
623 | ||
624 | /* XXX: cross-check bpp vs. pixel format? */ | |
625 | val |= intel_dsi->pixel_format; | |
626 | } | |
4e646495 | 627 | |
24ee0e64 GS |
628 | tmp = 0; |
629 | if (intel_dsi->eotp_pkt == 0) | |
630 | tmp |= EOT_DISABLE; | |
631 | if (intel_dsi->clock_stop) | |
632 | tmp |= CLOCKSTOP; | |
4e646495 | 633 | |
24ee0e64 GS |
634 | for_each_dsi_port(port, intel_dsi->ports) { |
635 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); | |
636 | ||
637 | /* timeouts for recovery. one frame IIUC. if counter expires, | |
638 | * EOT and stop state. */ | |
639 | ||
640 | /* | |
641 | * In burst mode, value greater than one DPI line Time in byte | |
642 | * clock (txbyteclkhs) To timeout this timer 1+ of the above | |
643 | * said value is recommended. | |
644 | * | |
645 | * In non-burst mode, Value greater than one DPI frame time in | |
646 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above | |
647 | * said value is recommended. | |
648 | * | |
649 | * In DBI only mode, value greater than one DBI frame time in | |
650 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above | |
651 | * said value is recommended. | |
652 | */ | |
4e646495 | 653 | |
24ee0e64 GS |
654 | if (is_vid_mode(intel_dsi) && |
655 | intel_dsi->video_mode_format == VIDEO_MODE_BURST) { | |
656 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), | |
657 | txbyteclkhs(adjusted_mode->htotal, bpp, | |
658 | intel_dsi->lane_count, | |
659 | intel_dsi->burst_mode_ratio) + 1); | |
660 | } else { | |
661 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), | |
662 | txbyteclkhs(adjusted_mode->vtotal * | |
663 | adjusted_mode->htotal, | |
664 | bpp, intel_dsi->lane_count, | |
665 | intel_dsi->burst_mode_ratio) + 1); | |
666 | } | |
667 | I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); | |
668 | I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), | |
669 | intel_dsi->turn_arnd_val); | |
670 | I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), | |
671 | intel_dsi->rst_timer_val); | |
f1c79f16 | 672 | |
24ee0e64 | 673 | /* dphy stuff */ |
f1c79f16 | 674 | |
24ee0e64 GS |
675 | /* in terms of low power clock */ |
676 | I915_WRITE(MIPI_INIT_COUNT(port), | |
677 | txclkesc(intel_dsi->escape_clk_div, 100)); | |
4e646495 | 678 | |
4e646495 | 679 | |
24ee0e64 GS |
680 | /* recovery disables */ |
681 | I915_WRITE(MIPI_EOT_DISABLE(port), val); | |
cf4dbd2e | 682 | |
24ee0e64 GS |
683 | /* in terms of low power clock */ |
684 | I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); | |
4e646495 | 685 | |
24ee0e64 GS |
686 | /* in terms of txbyteclkhs. actual high to low switch + |
687 | * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. | |
688 | * | |
689 | * XXX: write MIPI_STOP_STATE_STALL? | |
690 | */ | |
691 | I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), | |
692 | intel_dsi->hs_to_lp_count); | |
693 | ||
694 | /* XXX: low power clock equivalence in terms of byte clock. | |
695 | * the number of byte clocks occupied in one low power clock. | |
696 | * based on txbyteclkhs and txclkesc. | |
697 | * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL | |
698 | * ) / 105.??? | |
699 | */ | |
700 | I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); | |
701 | ||
702 | /* the bw essential for transmitting 16 long packets containing | |
703 | * 252 bytes meant for dcs write memory command is programmed in | |
704 | * this register in terms of byte clocks. based on dsi transfer | |
705 | * rate and the number of lanes configured the time taken to | |
706 | * transmit 16 long packets in a dsi stream varies. */ | |
707 | I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); | |
708 | ||
709 | I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), | |
710 | intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | | |
711 | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); | |
712 | ||
713 | if (is_vid_mode(intel_dsi)) | |
714 | /* Some panels might have resolution which is not a | |
715 | * multiple of 64 like 1366 x 768. Enable RANDOM | |
716 | * resolution support for such panels by default */ | |
717 | I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), | |
718 | intel_dsi->video_frmt_cfg_bits | | |
719 | intel_dsi->video_mode_format | | |
720 | IP_TG_CONFIG | | |
721 | RANDOM_DPI_DISPLAY_RESOLUTION); | |
722 | } | |
4e646495 JN |
723 | } |
724 | ||
07e4fb9e DV |
725 | static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder) |
726 | { | |
727 | DRM_DEBUG_KMS("\n"); | |
728 | ||
729 | intel_dsi_prepare(encoder); | |
730 | ||
731 | vlv_enable_dsi_pll(encoder); | |
732 | } | |
733 | ||
4e646495 JN |
734 | static enum drm_connector_status |
735 | intel_dsi_detect(struct drm_connector *connector, bool force) | |
736 | { | |
36d21f4c | 737 | return connector_status_connected; |
4e646495 JN |
738 | } |
739 | ||
740 | static int intel_dsi_get_modes(struct drm_connector *connector) | |
741 | { | |
742 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
743 | struct drm_display_mode *mode; | |
744 | ||
745 | DRM_DEBUG_KMS("\n"); | |
746 | ||
747 | if (!intel_connector->panel.fixed_mode) { | |
748 | DRM_DEBUG_KMS("no fixed mode\n"); | |
749 | return 0; | |
750 | } | |
751 | ||
752 | mode = drm_mode_duplicate(connector->dev, | |
753 | intel_connector->panel.fixed_mode); | |
754 | if (!mode) { | |
755 | DRM_DEBUG_KMS("drm_mode_duplicate failed\n"); | |
756 | return 0; | |
757 | } | |
758 | ||
759 | drm_mode_probed_add(connector, mode); | |
760 | return 1; | |
761 | } | |
762 | ||
763 | static void intel_dsi_destroy(struct drm_connector *connector) | |
764 | { | |
765 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
766 | ||
767 | DRM_DEBUG_KMS("\n"); | |
768 | intel_panel_fini(&intel_connector->panel); | |
4e646495 JN |
769 | drm_connector_cleanup(connector); |
770 | kfree(connector); | |
771 | } | |
772 | ||
773 | static const struct drm_encoder_funcs intel_dsi_funcs = { | |
774 | .destroy = intel_encoder_destroy, | |
775 | }; | |
776 | ||
777 | static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { | |
778 | .get_modes = intel_dsi_get_modes, | |
779 | .mode_valid = intel_dsi_mode_valid, | |
780 | .best_encoder = intel_best_encoder, | |
781 | }; | |
782 | ||
783 | static const struct drm_connector_funcs intel_dsi_connector_funcs = { | |
784 | .dpms = intel_connector_dpms, | |
785 | .detect = intel_dsi_detect, | |
786 | .destroy = intel_dsi_destroy, | |
787 | .fill_modes = drm_helper_probe_single_connector_modes, | |
788 | }; | |
789 | ||
4328633d | 790 | void intel_dsi_init(struct drm_device *dev) |
4e646495 JN |
791 | { |
792 | struct intel_dsi *intel_dsi; | |
793 | struct intel_encoder *intel_encoder; | |
794 | struct drm_encoder *encoder; | |
795 | struct intel_connector *intel_connector; | |
796 | struct drm_connector *connector; | |
797 | struct drm_display_mode *fixed_mode = NULL; | |
b6fdd0f2 | 798 | struct drm_i915_private *dev_priv = dev->dev_private; |
4e646495 JN |
799 | const struct intel_dsi_device *dsi; |
800 | unsigned int i; | |
801 | ||
802 | DRM_DEBUG_KMS("\n"); | |
803 | ||
3e6bd011 SK |
804 | /* There is no detection method for MIPI so rely on VBT */ |
805 | if (!dev_priv->vbt.has_mipi) | |
4328633d | 806 | return; |
3e6bd011 | 807 | |
868d665b CJ |
808 | if (IS_VALLEYVIEW(dev)) { |
809 | dev_priv->mipi_mmio_base = VLV_MIPI_BASE; | |
810 | } else { | |
811 | DRM_ERROR("Unsupported Mipi device to reg base"); | |
812 | return; | |
813 | } | |
3e6bd011 | 814 | |
4e646495 JN |
815 | intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); |
816 | if (!intel_dsi) | |
4328633d | 817 | return; |
4e646495 JN |
818 | |
819 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); | |
820 | if (!intel_connector) { | |
821 | kfree(intel_dsi); | |
4328633d | 822 | return; |
4e646495 JN |
823 | } |
824 | ||
825 | intel_encoder = &intel_dsi->base; | |
826 | encoder = &intel_encoder->base; | |
827 | intel_dsi->attached_connector = intel_connector; | |
828 | ||
829 | connector = &intel_connector->base; | |
830 | ||
831 | drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI); | |
832 | ||
833 | /* XXX: very likely not all of these are needed */ | |
834 | intel_encoder->hot_plug = intel_dsi_hot_plug; | |
835 | intel_encoder->compute_config = intel_dsi_compute_config; | |
836 | intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable; | |
837 | intel_encoder->pre_enable = intel_dsi_pre_enable; | |
2634fd7f | 838 | intel_encoder->enable = intel_dsi_enable_nop; |
c315faf8 | 839 | intel_encoder->disable = intel_dsi_pre_disable; |
4e646495 JN |
840 | intel_encoder->post_disable = intel_dsi_post_disable; |
841 | intel_encoder->get_hw_state = intel_dsi_get_hw_state; | |
842 | intel_encoder->get_config = intel_dsi_get_config; | |
843 | ||
844 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
4932e2c3 | 845 | intel_connector->unregister = intel_connector_unregister; |
4e646495 | 846 | |
e7d7cad0 | 847 | /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */ |
17af40a8 | 848 | if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) { |
e7d7cad0 | 849 | intel_encoder->crtc_mask = (1 << PIPE_A); |
17af40a8 JN |
850 | intel_dsi->ports = (1 << PORT_A); |
851 | } else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIC) { | |
e7d7cad0 | 852 | intel_encoder->crtc_mask = (1 << PIPE_B); |
17af40a8 JN |
853 | intel_dsi->ports = (1 << PORT_C); |
854 | } | |
e7d7cad0 | 855 | |
4e646495 JN |
856 | for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) { |
857 | dsi = &intel_dsi_devices[i]; | |
858 | intel_dsi->dev = *dsi; | |
859 | ||
860 | if (dsi->dev_ops->init(&intel_dsi->dev)) | |
861 | break; | |
862 | } | |
863 | ||
864 | if (i == ARRAY_SIZE(intel_dsi_devices)) { | |
865 | DRM_DEBUG_KMS("no device found\n"); | |
866 | goto err; | |
867 | } | |
868 | ||
869 | intel_encoder->type = INTEL_OUTPUT_DSI; | |
bc079e8b | 870 | intel_encoder->cloneable = 0; |
4e646495 JN |
871 | drm_connector_init(dev, connector, &intel_dsi_connector_funcs, |
872 | DRM_MODE_CONNECTOR_DSI); | |
873 | ||
874 | drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); | |
875 | ||
876 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ | |
877 | connector->interlace_allowed = false; | |
878 | connector->doublescan_allowed = false; | |
879 | ||
880 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
881 | ||
34ea3d38 | 882 | drm_connector_register(connector); |
4e646495 JN |
883 | |
884 | fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev); | |
885 | if (!fixed_mode) { | |
886 | DRM_DEBUG_KMS("no fixed mode\n"); | |
887 | goto err; | |
888 | } | |
889 | ||
890 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
4b6ed685 | 891 | intel_panel_init(&intel_connector->panel, fixed_mode, NULL); |
4e646495 | 892 | |
4328633d | 893 | return; |
4e646495 JN |
894 | |
895 | err: | |
896 | drm_encoder_cleanup(&intel_encoder->base); | |
897 | kfree(intel_dsi); | |
898 | kfree(intel_connector); | |
4e646495 | 899 | } |