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drm/i915: Detect if MIPI panel based on VBT and initialize only if present
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dsi.c
CommitLineData
4e646495
JN		 1/*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Author: Jani Nikula <jani.nikula@intel.com>
24 */
25
26#include <drm/drmP.h>
27#include <drm/drm_crtc.h>
28#include <drm/drm_edid.h>
29#include <drm/i915_drm.h>
30#include <linux/slab.h>
31#include "i915_drv.h"
32#include "intel_drv.h"
33#include "intel_dsi.h"
34#include "intel_dsi_cmd.h"
35
36/* the sub-encoders aka panel drivers */
37static const struct intel_dsi_device intel_dsi_devices[] = {
2ab8b458
SK		 38 {
39 .panel_id = MIPI_DSI_GENERIC_PANEL_ID,
40 .name = "vbt-generic-dsi-vid-mode-display",
41 .dev_ops = &vbt_generic_dsi_display_ops,
42 },
4e646495
JN		 43};
44
e9fe51c6 45static void band_gap_reset(struct drm_i915_private *dev_priv)
4ce8c9a7
SK		 46{
47 mutex_lock(&dev_priv->dpio_lock);
48
e9fe51c6
SK		 49 vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
50 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
51 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
52 udelay(150);
53 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
54 vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
4ce8c9a7
SK		 55
56 mutex_unlock(&dev_priv->dpio_lock);
4ce8c9a7
SK		 57}
58
4e646495
JN		 59static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector)
60{
61 return container_of(intel_attached_encoder(connector),
62 struct intel_dsi, base);
63}
64
65static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
66{
dfba2e2d 67 return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
4e646495
JN		 68}
69
70static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
71{
dfba2e2d 72 return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
4e646495
JN		 73}
74
75static void intel_dsi_hot_plug(struct intel_encoder *encoder)
76{
77 DRM_DEBUG_KMS("\n");
78}
79
80static bool intel_dsi_compute_config(struct intel_encoder *encoder,
81 struct intel_crtc_config *config)
82{
83 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
84 base);
85 struct intel_connector *intel_connector = intel_dsi->attached_connector;
86 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
87 struct drm_display_mode *adjusted_mode = &config->adjusted_mode;
88 struct drm_display_mode *mode = &config->requested_mode;
89
90 DRM_DEBUG_KMS("\n");
91
92 if (fixed_mode)
93 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
94
95 if (intel_dsi->dev.dev_ops->mode_fixup)
96 return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev,
97 mode, adjusted_mode);
98
99 return true;
100}
101
1dbd7cb2 102static void intel_dsi_device_ready(struct intel_encoder *encoder)
4e646495 103{
1dbd7cb2
SK		 104 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
105 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
106 int pipe = intel_crtc->pipe;
107 u32 val;
108
4e646495 109 DRM_DEBUG_KMS("\n");
4e646495 110
2095f9fc
SK		 111 mutex_lock(&dev_priv->dpio_lock);
112 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
113 * needed everytime after power gate */
114 vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
115 mutex_unlock(&dev_priv->dpio_lock);
116
117 /* bandgap reset is needed after everytime we do power gate */
118 band_gap_reset(dev_priv);
119
1dbd7cb2
SK		 120 val = I915_READ(MIPI_PORT_CTRL(pipe));
121 I915_WRITE(MIPI_PORT_CTRL(pipe), val | LP_OUTPUT_HOLD);
122 usleep_range(1000, 1500);
123 I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT);
124 usleep_range(2000, 2500);
125 I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY);
126 usleep_range(2000, 2500);
127 I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00);
128 usleep_range(2000, 2500);
129 I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY);
130 usleep_range(2000, 2500);
131}
1dbd7cb2
SK		 132
133static void intel_dsi_enable(struct intel_encoder *encoder)
134{
135 struct drm_device *dev = encoder->base.dev;
136 struct drm_i915_private *dev_priv = dev->dev_private;
137 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
138 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
139 int pipe = intel_crtc->pipe;
140 u32 temp;
141
142 DRM_DEBUG_KMS("\n");
b9f5e07d 143
4e646495
JN		 144 if (is_cmd_mode(intel_dsi))
145 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4);
1dbd7cb2 146 else {
4e646495 147 msleep(20); /* XXX */
e1047028 148 dpi_send_cmd(intel_dsi, TURN_ON, DPI_LP_MODE_EN);
4e646495
JN		 149 msleep(100);
150
2634fd7f
SK		 151 if (intel_dsi->dev.dev_ops->enable)
152 intel_dsi->dev.dev_ops->enable(&intel_dsi->dev);
153
4e646495 154 /* assert ip_tg_enable signal */
f6da2842
SK		 155 temp = I915_READ(MIPI_PORT_CTRL(pipe)) & ~LANE_CONFIGURATION_MASK;
156 temp = temp | intel_dsi->port_bits;
4e646495
JN		 157 I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE);
158 POSTING_READ(MIPI_PORT_CTRL(pipe));
159 }
2634fd7f
SK		 160}
161
162static void intel_dsi_pre_enable(struct intel_encoder *encoder)
163{
20e5bf66
SK		 164 struct drm_device *dev = encoder->base.dev;
165 struct drm_i915_private *dev_priv = dev->dev_private;
2634fd7f 166 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
20e5bf66
SK		 167 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
168 enum pipe pipe = intel_crtc->pipe;
169 u32 tmp;
2634fd7f
SK		 170
171 DRM_DEBUG_KMS("\n");
172
20e5bf66
SK		 173 /* Disable DPOunit clock gating, can stall pipe
174 * and we need DPLL REFA always enabled */
175 tmp = I915_READ(DPLL(pipe));
176 tmp |= DPLL_REFA_CLK_ENABLE_VLV;
177 I915_WRITE(DPLL(pipe), tmp);
178
179 tmp = I915_READ(DSPCLK_GATE_D);
180 tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
181 I915_WRITE(DSPCLK_GATE_D, tmp);
2634fd7f
SK		 182
183 /* put device in ready state */
184 intel_dsi_device_ready(encoder);
4e646495 185
df38e655
SK		 186 msleep(intel_dsi->panel_on_delay);
187
20e5bf66
SK		 188 if (intel_dsi->dev.dev_ops->panel_reset)
189 intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev);
190
2634fd7f
SK		 191 if (intel_dsi->dev.dev_ops->send_otp_cmds)
192 intel_dsi->dev.dev_ops->send_otp_cmds(&intel_dsi->dev);
193
194 /* Enable port in pre-enable phase itself because as per hw team
195 * recommendation, port should be enabled befor plane & pipe */
196 intel_dsi_enable(encoder);
197}
198
199static void intel_dsi_enable_nop(struct intel_encoder *encoder)
200{
201 DRM_DEBUG_KMS("\n");
202
203 /* for DSI port enable has to be done before pipe
204 * and plane enable, so port enable is done in
205 * pre_enable phase itself unlike other encoders
206 */
4e646495
JN		 207}
208
209static void intel_dsi_disable(struct intel_encoder *encoder)
210{
1dbd7cb2
SK		 211 struct drm_device *dev = encoder->base.dev;
212 struct drm_i915_private *dev_priv = dev->dev_private;
4e646495
JN		 213 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
214 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
215 int pipe = intel_crtc->pipe;
216 u32 temp;
217
218 DRM_DEBUG_KMS("\n");
219
4e646495 220 if (is_vid_mode(intel_dsi)) {
e1047028
SK		 221 /* Send Shutdown command to the panel in LP mode */
222 dpi_send_cmd(intel_dsi, SHUTDOWN, DPI_LP_MODE_EN);
4e646495
JN		 223 msleep(10);
224
225 /* de-assert ip_tg_enable signal */
226 temp = I915_READ(MIPI_PORT_CTRL(pipe));
227 I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE);
228 POSTING_READ(MIPI_PORT_CTRL(pipe));
229
230 msleep(2);
231 }
232
339023ec
SK		 233 /* Panel commands can be sent when clock is in LP11 */
234 I915_WRITE(MIPI_DEVICE_READY(pipe), 0x0);
235
236 temp = I915_READ(MIPI_CTRL(pipe));
237 temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
238 I915_WRITE(MIPI_CTRL(pipe), temp |
239 intel_dsi->escape_clk_div <<
240 ESCAPE_CLOCK_DIVIDER_SHIFT);
241
242 I915_WRITE(MIPI_EOT_DISABLE(pipe), CLOCKSTOP);
243
244 temp = I915_READ(MIPI_DSI_FUNC_PRG(pipe));
245 temp &= ~VID_MODE_FORMAT_MASK;
246 I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), temp);
247
248 I915_WRITE(MIPI_DEVICE_READY(pipe), 0x1);
249
1dbd7cb2
SK		 250 /* if disable packets are sent before sending shutdown packet then in
251 * some next enable sequence send turn on packet error is observed */
252 if (intel_dsi->dev.dev_ops->disable)
253 intel_dsi->dev.dev_ops->disable(&intel_dsi->dev);
4e646495
JN		 254}
255
1dbd7cb2 256static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
4e646495 257{
1dbd7cb2
SK		 258 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
259 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
260 int pipe = intel_crtc->pipe;
261 u32 val;
262
4e646495 263 DRM_DEBUG_KMS("\n");
be4fc046 264
1dbd7cb2
SK		 265 I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
266 usleep_range(2000, 2500);
267
268 I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT);
269 usleep_range(2000, 2500);
270
271 I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
272 usleep_range(2000, 2500);
273
274 val = I915_READ(MIPI_PORT_CTRL(pipe));
275 I915_WRITE(MIPI_PORT_CTRL(pipe), val & ~LP_OUTPUT_HOLD);
276 usleep_range(1000, 1500);
277
278 if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & AFE_LATCHOUT)
279 == 0x00000), 30))
280 DRM_ERROR("DSI LP not going Low\n");
281
282 I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00);
283 usleep_range(2000, 2500);
284
be4fc046 285 vlv_disable_dsi_pll(encoder);
4e646495 286}
20e5bf66 287
1dbd7cb2
SK		 288static void intel_dsi_post_disable(struct intel_encoder *encoder)
289{
20e5bf66 290 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1dbd7cb2 291 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
20e5bf66 292 u32 val;
1dbd7cb2
SK		 293
294 DRM_DEBUG_KMS("\n");
295
296 intel_dsi_clear_device_ready(encoder);
297
20e5bf66
SK		 298 val = I915_READ(DSPCLK_GATE_D);
299 val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
300 I915_WRITE(DSPCLK_GATE_D, val);
301
1dbd7cb2
SK		 302 if (intel_dsi->dev.dev_ops->disable_panel_power)
303 intel_dsi->dev.dev_ops->disable_panel_power(&intel_dsi->dev);
df38e655
SK		 304
305 msleep(intel_dsi->panel_off_delay);
306 msleep(intel_dsi->panel_pwr_cycle_delay);
1dbd7cb2 307}
4e646495
JN		 308
309static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
310 enum pipe *pipe)
311{
312 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
6d129bea 313 enum intel_display_power_domain power_domain;
4e646495
JN		 314 u32 port, func;
315 enum pipe p;
316
317 DRM_DEBUG_KMS("\n");
318
6d129bea
ID		 319 power_domain = intel_display_port_power_domain(encoder);
320 if (!intel_display_power_enabled(dev_priv, power_domain))
321 return false;
322
4e646495
JN		 323 /* XXX: this only works for one DSI output */
324 for (p = PIPE_A; p <= PIPE_B; p++) {
325 port = I915_READ(MIPI_PORT_CTRL(p));
326 func = I915_READ(MIPI_DSI_FUNC_PRG(p));
327
328 if ((port & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) {
329 if (I915_READ(MIPI_DEVICE_READY(p)) & DEVICE_READY) {
330 *pipe = p;
331 return true;
332 }
333 }
334 }
335
336 return false;
337}
338
339static void intel_dsi_get_config(struct intel_encoder *encoder,
340 struct intel_crtc_config *pipe_config)
341{
342 DRM_DEBUG_KMS("\n");
343
344 /* XXX: read flags, set to adjusted_mode */
345}
346
c19de8eb
DL		 347static enum drm_mode_status
348intel_dsi_mode_valid(struct drm_connector *connector,
349 struct drm_display_mode *mode)
4e646495
JN		 350{
351 struct intel_connector *intel_connector = to_intel_connector(connector);
352 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
353 struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
354
355 DRM_DEBUG_KMS("\n");
356
357 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
358 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
359 return MODE_NO_DBLESCAN;
360 }
361
362 if (fixed_mode) {
363 if (mode->hdisplay > fixed_mode->hdisplay)
364 return MODE_PANEL;
365 if (mode->vdisplay > fixed_mode->vdisplay)
366 return MODE_PANEL;
367 }
368
369 return intel_dsi->dev.dev_ops->mode_valid(&intel_dsi->dev, mode);
370}
371
372/* return txclkesc cycles in terms of divider and duration in us */
373static u16 txclkesc(u32 divider, unsigned int us)
374{
375 switch (divider) {
376 case ESCAPE_CLOCK_DIVIDER_1:
377 default:
378 return 20 * us;
379 case ESCAPE_CLOCK_DIVIDER_2:
380 return 10 * us;
381 case ESCAPE_CLOCK_DIVIDER_4:
382 return 5 * us;
383 }
384}
385
386/* return pixels in terms of txbyteclkhs */
387static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count)
388{
389 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp, 8), lane_count);
390}
391
392static void set_dsi_timings(struct drm_encoder *encoder,
393 const struct drm_display_mode *mode)
394{
395 struct drm_device *dev = encoder->dev;
396 struct drm_i915_private *dev_priv = dev->dev_private;
397 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
398 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
399 int pipe = intel_crtc->pipe;
400 unsigned int bpp = intel_crtc->config.pipe_bpp;
401 unsigned int lane_count = intel_dsi->lane_count;
402
403 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
404
405 hactive = mode->hdisplay;
406 hfp = mode->hsync_start - mode->hdisplay;
407 hsync = mode->hsync_end - mode->hsync_start;
408 hbp = mode->htotal - mode->hsync_end;
409
410 vfp = mode->vsync_start - mode->vdisplay;
411 vsync = mode->vsync_end - mode->vsync_start;
412 vbp = mode->vtotal - mode->vsync_end;
413
414 /* horizontal values are in terms of high speed byte clock */
415 hactive = txbyteclkhs(hactive, bpp, lane_count);
416 hfp = txbyteclkhs(hfp, bpp, lane_count);
417 hsync = txbyteclkhs(hsync, bpp, lane_count);
418 hbp = txbyteclkhs(hbp, bpp, lane_count);
419
420 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive);
421 I915_WRITE(MIPI_HFP_COUNT(pipe), hfp);
422
423 /* meaningful for video mode non-burst sync pulse mode only, can be zero
424 * for non-burst sync events and burst modes */
425 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(pipe), hsync);
426 I915_WRITE(MIPI_HBP_COUNT(pipe), hbp);
427
428 /* vertical values are in terms of lines */
429 I915_WRITE(MIPI_VFP_COUNT(pipe), vfp);
430 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(pipe), vsync);
431 I915_WRITE(MIPI_VBP_COUNT(pipe), vbp);
432}
433
07e4fb9e 434static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
4e646495
JN		 435{
436 struct drm_encoder *encoder = &intel_encoder->base;
437 struct drm_device *dev = encoder->dev;
438 struct drm_i915_private *dev_priv = dev->dev_private;
439 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
440 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
441 struct drm_display_mode *adjusted_mode =
442 &intel_crtc->config.adjusted_mode;
443 int pipe = intel_crtc->pipe;
444 unsigned int bpp = intel_crtc->config.pipe_bpp;
445 u32 val, tmp;
446
6f2bcceb 447 DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe));
4e646495
JN		 448
449 /* escape clock divider, 20MHz, shared for A and C. device ready must be
450 * off when doing this! txclkesc? */
451 tmp = I915_READ(MIPI_CTRL(0));
452 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
453 I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1);
454
455 /* read request priority is per pipe */
456 tmp = I915_READ(MIPI_CTRL(pipe));
457 tmp &= ~READ_REQUEST_PRIORITY_MASK;
458 I915_WRITE(MIPI_CTRL(pipe), tmp | READ_REQUEST_PRIORITY_HIGH);
459
460 /* XXX: why here, why like this? handling in irq handler?! */
461 I915_WRITE(MIPI_INTR_STAT(pipe), 0xffffffff);
462 I915_WRITE(MIPI_INTR_EN(pipe), 0xffffffff);
463
f6da2842 464 I915_WRITE(MIPI_DPHY_PARAM(pipe), intel_dsi->dphy_reg);
4e646495
JN		 465
466 I915_WRITE(MIPI_DPI_RESOLUTION(pipe),
467 adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
468 adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT);
469
470 set_dsi_timings(encoder, adjusted_mode);
471
472 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
473 if (is_cmd_mode(intel_dsi)) {
474 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
475 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
476 } else {
477 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
478
479 /* XXX: cross-check bpp vs. pixel format? */
480 val |= intel_dsi->pixel_format;
481 }
482 I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val);
483
484 /* timeouts for recovery. one frame IIUC. if counter expires, EOT and
485 * stop state. */
486
487 /*
488 * In burst mode, value greater than one DPI line Time in byte clock
489 * (txbyteclkhs) To timeout this timer 1+ of the above said value is
490 * recommended.
491 *
492 * In non-burst mode, Value greater than one DPI frame time in byte
493 * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
494 * is recommended.
495 *
496 * In DBI only mode, value greater than one DBI frame time in byte
497 * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
498 * is recommended.
499 */
500
501 if (is_vid_mode(intel_dsi) &&
502 intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
503 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
504 txbyteclkhs(adjusted_mode->htotal, bpp,
505 intel_dsi->lane_count) + 1);
506 } else {
507 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
508 txbyteclkhs(adjusted_mode->vtotal *
509 adjusted_mode->htotal,
510 bpp, intel_dsi->lane_count) + 1);
511 }
f6da2842
SK		 512 I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), intel_dsi->lp_rx_timeout);
513 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), intel_dsi->turn_arnd_val);
514 I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), intel_dsi->rst_timer_val);
4e646495
JN		 515
516 /* dphy stuff */
517
518 /* in terms of low power clock */
f1c79f16
SK		 519 I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(intel_dsi->escape_clk_div, 100));
520
521 val = 0;
522 if (intel_dsi->eotp_pkt == 0)
523 val |= EOT_DISABLE;
524
525 if (intel_dsi->clock_stop)
526 val |= CLOCKSTOP;
4e646495
JN		 527
528 /* recovery disables */
f1c79f16 529 I915_WRITE(MIPI_EOT_DISABLE(pipe), val);
4e646495 530
cf4dbd2e
SK		 531 /* in terms of low power clock */
532 I915_WRITE(MIPI_INIT_COUNT(pipe), intel_dsi->init_count);
533
4e646495
JN		 534 /* in terms of txbyteclkhs. actual high to low switch +
535 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
536 *
537 * XXX: write MIPI_STOP_STATE_STALL?
538 */
f6da2842
SK		 539 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe),
540 intel_dsi->hs_to_lp_count);
4e646495
JN		 541
542 /* XXX: low power clock equivalence in terms of byte clock. the number
543 * of byte clocks occupied in one low power clock. based on txbyteclkhs
544 * and txclkesc. txclkesc time / txbyteclk time * (105 +
545 * MIPI_STOP_STATE_STALL) / 105.???
546 */
f6da2842 547 I915_WRITE(MIPI_LP_BYTECLK(pipe), intel_dsi->lp_byte_clk);
4e646495
JN		 548
549 /* the bw essential for transmitting 16 long packets containing 252
550 * bytes meant for dcs write memory command is programmed in this
551 * register in terms of byte clocks. based on dsi transfer rate and the
552 * number of lanes configured the time taken to transmit 16 long packets
553 * in a dsi stream varies. */
f6da2842 554 I915_WRITE(MIPI_DBI_BW_CTRL(pipe), intel_dsi->bw_timer);
4e646495
JN		 555
556 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe),
f6da2842
SK		 557 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
558 intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
4e646495
JN		 559
560 if (is_vid_mode(intel_dsi))
24d9c401
SK		 561 /* Some panels might have resolution which is not a multiple of
562 * 64 like 1366 x 768. Enable RANDOM resolution support for such
563 * panels by default */
4e646495 564 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe),
f6da2842 565 intel_dsi->video_frmt_cfg_bits |
24d9c401
SK		 566 intel_dsi->video_mode_format |
567 IP_TG_CONFIG |
568 RANDOM_DPI_DISPLAY_RESOLUTION);
4e646495
JN		 569}
570
07e4fb9e
DV		 571static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
572{
573 DRM_DEBUG_KMS("\n");
574
575 intel_dsi_prepare(encoder);
576
577 vlv_enable_dsi_pll(encoder);
578}
579
4e646495
JN		 580static enum drm_connector_status
581intel_dsi_detect(struct drm_connector *connector, bool force)
582{
583 struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
671dedd2
ID		 584 struct intel_encoder *intel_encoder = &intel_dsi->base;
585 enum intel_display_power_domain power_domain;
586 enum drm_connector_status connector_status;
587 struct drm_i915_private *dev_priv = intel_encoder->base.dev->dev_private;
588
4e646495 589 DRM_DEBUG_KMS("\n");
671dedd2
ID		 590 power_domain = intel_display_port_power_domain(intel_encoder);
591
592 intel_display_power_get(dev_priv, power_domain);
593 connector_status = intel_dsi->dev.dev_ops->detect(&intel_dsi->dev);
594 intel_display_power_put(dev_priv, power_domain);
595
596 return connector_status;
4e646495
JN		 597}
598
599static int intel_dsi_get_modes(struct drm_connector *connector)
600{
601 struct intel_connector *intel_connector = to_intel_connector(connector);
602 struct drm_display_mode *mode;
603
604 DRM_DEBUG_KMS("\n");
605
606 if (!intel_connector->panel.fixed_mode) {
607 DRM_DEBUG_KMS("no fixed mode\n");
608 return 0;
609 }
610
611 mode = drm_mode_duplicate(connector->dev,
612 intel_connector->panel.fixed_mode);
613 if (!mode) {
614 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
615 return 0;
616 }
617
618 drm_mode_probed_add(connector, mode);
619 return 1;
620}
621
622static void intel_dsi_destroy(struct drm_connector *connector)
623{
624 struct intel_connector *intel_connector = to_intel_connector(connector);
625
626 DRM_DEBUG_KMS("\n");
627 intel_panel_fini(&intel_connector->panel);
4e646495
JN		 628 drm_connector_cleanup(connector);
629 kfree(connector);
630}
631
632static const struct drm_encoder_funcs intel_dsi_funcs = {
633 .destroy = intel_encoder_destroy,
634};
635
636static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
637 .get_modes = intel_dsi_get_modes,
638 .mode_valid = intel_dsi_mode_valid,
639 .best_encoder = intel_best_encoder,
640};
641
642static const struct drm_connector_funcs intel_dsi_connector_funcs = {
643 .dpms = intel_connector_dpms,
644 .detect = intel_dsi_detect,
645 .destroy = intel_dsi_destroy,
646 .fill_modes = drm_helper_probe_single_connector_modes,
647};
648
649bool intel_dsi_init(struct drm_device *dev)
650{
651 struct intel_dsi *intel_dsi;
652 struct intel_encoder *intel_encoder;
653 struct drm_encoder *encoder;
654 struct intel_connector *intel_connector;
655 struct drm_connector *connector;
656 struct drm_display_mode *fixed_mode = NULL;
b6fdd0f2 657 struct drm_i915_private *dev_priv = dev->dev_private;
4e646495
JN		 658 const struct intel_dsi_device *dsi;
659 unsigned int i;
660
661 DRM_DEBUG_KMS("\n");
662
3e6bd011
SK		 663 /* There is no detection method for MIPI so rely on VBT */
664 if (!dev_priv->vbt.has_mipi)
665 return false;
666
4e646495
JN		 667 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
668 if (!intel_dsi)
669 return false;
670
671 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
672 if (!intel_connector) {
673 kfree(intel_dsi);
674 return false;
675 }
676
677 intel_encoder = &intel_dsi->base;
678 encoder = &intel_encoder->base;
679 intel_dsi->attached_connector = intel_connector;
680
b6fdd0f2
SS		 681 if (IS_VALLEYVIEW(dev)) {
682 dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
683 } else {
684 DRM_ERROR("Unsupported Mipi device to reg base");
685 return false;
686 }
687
4e646495
JN		 688 connector = &intel_connector->base;
689
690 drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI);
691
692 /* XXX: very likely not all of these are needed */
693 intel_encoder->hot_plug = intel_dsi_hot_plug;
694 intel_encoder->compute_config = intel_dsi_compute_config;
695 intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable;
696 intel_encoder->pre_enable = intel_dsi_pre_enable;
2634fd7f 697 intel_encoder->enable = intel_dsi_enable_nop;
4e646495
JN		 698 intel_encoder->disable = intel_dsi_disable;
699 intel_encoder->post_disable = intel_dsi_post_disable;
700 intel_encoder->get_hw_state = intel_dsi_get_hw_state;
701 intel_encoder->get_config = intel_dsi_get_config;
702
703 intel_connector->get_hw_state = intel_connector_get_hw_state;
4932e2c3 704 intel_connector->unregister = intel_connector_unregister;
4e646495
JN		 705
706 for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) {
707 dsi = &intel_dsi_devices[i];
708 intel_dsi->dev = *dsi;
709
710 if (dsi->dev_ops->init(&intel_dsi->dev))
711 break;
712 }
713
714 if (i == ARRAY_SIZE(intel_dsi_devices)) {
715 DRM_DEBUG_KMS("no device found\n");
716 goto err;
717 }
718
719 intel_encoder->type = INTEL_OUTPUT_DSI;
720 intel_encoder->crtc_mask = (1 << 0); /* XXX */
721
bc079e8b 722 intel_encoder->cloneable = 0;
4e646495
JN		 723 drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
724 DRM_MODE_CONNECTOR_DSI);
725
726 drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
727
728 connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
729 connector->interlace_allowed = false;
730 connector->doublescan_allowed = false;
731
732 intel_connector_attach_encoder(intel_connector, intel_encoder);
733
734 drm_sysfs_connector_add(connector);
735
736 fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev);
737 if (!fixed_mode) {
738 DRM_DEBUG_KMS("no fixed mode\n");
739 goto err;
740 }
741
742 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4b6ed685 743 intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
4e646495
JN		 744
745 return true;
746
747err:
748 drm_encoder_cleanup(&intel_encoder->base);
749 kfree(intel_dsi);
750 kfree(intel_connector);
751
752 return false;
753}
Linux kernel - Deliverables
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