Commit | Line | Data |
---|---|---|
4e646495 JN |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Author: Jani Nikula <jani.nikula@intel.com> | |
24 | */ | |
25 | ||
26 | #include <drm/drmP.h> | |
c6f95f27 | 27 | #include <drm/drm_atomic_helper.h> |
4e646495 JN |
28 | #include <drm/drm_crtc.h> |
29 | #include <drm/drm_edid.h> | |
30 | #include <drm/i915_drm.h> | |
593e0622 | 31 | #include <drm/drm_panel.h> |
7e9804fd | 32 | #include <drm/drm_mipi_dsi.h> |
4e646495 | 33 | #include <linux/slab.h> |
fc45e821 | 34 | #include <linux/gpio/consumer.h> |
4e646495 JN |
35 | #include "i915_drv.h" |
36 | #include "intel_drv.h" | |
37 | #include "intel_dsi.h" | |
4e646495 | 38 | |
593e0622 JN |
39 | static const struct { |
40 | u16 panel_id; | |
41 | struct drm_panel * (*init)(struct intel_dsi *intel_dsi, u16 panel_id); | |
42 | } intel_dsi_drivers[] = { | |
2ab8b458 SK |
43 | { |
44 | .panel_id = MIPI_DSI_GENERIC_PANEL_ID, | |
593e0622 | 45 | .init = vbt_panel_init, |
2ab8b458 | 46 | }, |
4e646495 JN |
47 | }; |
48 | ||
43367ec9 R |
49 | enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) |
50 | { | |
51 | /* It just so happens the VBT matches register contents. */ | |
52 | switch (fmt) { | |
53 | case VID_MODE_FORMAT_RGB888: | |
54 | return MIPI_DSI_FMT_RGB888; | |
55 | case VID_MODE_FORMAT_RGB666: | |
56 | return MIPI_DSI_FMT_RGB666; | |
57 | case VID_MODE_FORMAT_RGB666_PACKED: | |
58 | return MIPI_DSI_FMT_RGB666_PACKED; | |
59 | case VID_MODE_FORMAT_RGB565: | |
60 | return MIPI_DSI_FMT_RGB565; | |
61 | default: | |
62 | MISSING_CASE(fmt); | |
63 | return MIPI_DSI_FMT_RGB666; | |
64 | } | |
65 | } | |
66 | ||
7f6a6a4a | 67 | static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port) |
3b1808bf JN |
68 | { |
69 | struct drm_encoder *encoder = &intel_dsi->base.base; | |
70 | struct drm_device *dev = encoder->dev; | |
71 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3b1808bf JN |
72 | u32 mask; |
73 | ||
74 | mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | | |
75 | LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; | |
76 | ||
77 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100)) | |
78 | DRM_ERROR("DPI FIFOs are not empty\n"); | |
79 | } | |
80 | ||
f0f59a00 VS |
81 | static void write_data(struct drm_i915_private *dev_priv, |
82 | i915_reg_t reg, | |
7e9804fd JN |
83 | const u8 *data, u32 len) |
84 | { | |
85 | u32 i, j; | |
86 | ||
87 | for (i = 0; i < len; i += 4) { | |
88 | u32 val = 0; | |
89 | ||
90 | for (j = 0; j < min_t(u32, len - i, 4); j++) | |
91 | val |= *data++ << 8 * j; | |
92 | ||
93 | I915_WRITE(reg, val); | |
94 | } | |
95 | } | |
96 | ||
f0f59a00 VS |
97 | static void read_data(struct drm_i915_private *dev_priv, |
98 | i915_reg_t reg, | |
7e9804fd JN |
99 | u8 *data, u32 len) |
100 | { | |
101 | u32 i, j; | |
102 | ||
103 | for (i = 0; i < len; i += 4) { | |
104 | u32 val = I915_READ(reg); | |
105 | ||
106 | for (j = 0; j < min_t(u32, len - i, 4); j++) | |
107 | *data++ = val >> 8 * j; | |
108 | } | |
109 | } | |
110 | ||
111 | static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, | |
112 | const struct mipi_dsi_msg *msg) | |
113 | { | |
114 | struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); | |
115 | struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev; | |
116 | struct drm_i915_private *dev_priv = dev->dev_private; | |
117 | enum port port = intel_dsi_host->port; | |
118 | struct mipi_dsi_packet packet; | |
119 | ssize_t ret; | |
120 | const u8 *header, *data; | |
f0f59a00 VS |
121 | i915_reg_t data_reg, ctrl_reg; |
122 | u32 data_mask, ctrl_mask; | |
7e9804fd JN |
123 | |
124 | ret = mipi_dsi_create_packet(&packet, msg); | |
125 | if (ret < 0) | |
126 | return ret; | |
127 | ||
128 | header = packet.header; | |
129 | data = packet.payload; | |
130 | ||
131 | if (msg->flags & MIPI_DSI_MSG_USE_LPM) { | |
132 | data_reg = MIPI_LP_GEN_DATA(port); | |
133 | data_mask = LP_DATA_FIFO_FULL; | |
134 | ctrl_reg = MIPI_LP_GEN_CTRL(port); | |
135 | ctrl_mask = LP_CTRL_FIFO_FULL; | |
136 | } else { | |
137 | data_reg = MIPI_HS_GEN_DATA(port); | |
138 | data_mask = HS_DATA_FIFO_FULL; | |
139 | ctrl_reg = MIPI_HS_GEN_CTRL(port); | |
140 | ctrl_mask = HS_CTRL_FIFO_FULL; | |
141 | } | |
142 | ||
143 | /* note: this is never true for reads */ | |
144 | if (packet.payload_length) { | |
145 | ||
146 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & data_mask) == 0, 50)) | |
147 | DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n"); | |
148 | ||
149 | write_data(dev_priv, data_reg, packet.payload, | |
150 | packet.payload_length); | |
151 | } | |
152 | ||
153 | if (msg->rx_len) { | |
154 | I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); | |
155 | } | |
156 | ||
157 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & ctrl_mask) == 0, 50)) { | |
158 | DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n"); | |
159 | } | |
160 | ||
161 | I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]); | |
162 | ||
163 | /* ->rx_len is set only for reads */ | |
164 | if (msg->rx_len) { | |
165 | data_mask = GEN_READ_DATA_AVAIL; | |
166 | if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & data_mask) == data_mask, 50)) | |
167 | DRM_ERROR("Timeout waiting for read data.\n"); | |
168 | ||
169 | read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); | |
170 | } | |
171 | ||
172 | /* XXX: fix for reads and writes */ | |
173 | return 4 + packet.payload_length; | |
174 | } | |
175 | ||
176 | static int intel_dsi_host_attach(struct mipi_dsi_host *host, | |
177 | struct mipi_dsi_device *dsi) | |
178 | { | |
179 | return 0; | |
180 | } | |
181 | ||
182 | static int intel_dsi_host_detach(struct mipi_dsi_host *host, | |
183 | struct mipi_dsi_device *dsi) | |
184 | { | |
185 | return 0; | |
186 | } | |
187 | ||
188 | static const struct mipi_dsi_host_ops intel_dsi_host_ops = { | |
189 | .attach = intel_dsi_host_attach, | |
190 | .detach = intel_dsi_host_detach, | |
191 | .transfer = intel_dsi_host_transfer, | |
192 | }; | |
193 | ||
194 | static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi, | |
195 | enum port port) | |
196 | { | |
197 | struct intel_dsi_host *host; | |
198 | struct mipi_dsi_device *device; | |
199 | ||
200 | host = kzalloc(sizeof(*host), GFP_KERNEL); | |
201 | if (!host) | |
202 | return NULL; | |
203 | ||
204 | host->base.ops = &intel_dsi_host_ops; | |
205 | host->intel_dsi = intel_dsi; | |
206 | host->port = port; | |
207 | ||
208 | /* | |
209 | * We should call mipi_dsi_host_register(&host->base) here, but we don't | |
210 | * have a host->dev, and we don't have OF stuff either. So just use the | |
211 | * dsi framework as a library and hope for the best. Create the dsi | |
212 | * devices by ourselves here too. Need to be careful though, because we | |
213 | * don't initialize any of the driver model devices here. | |
214 | */ | |
215 | device = kzalloc(sizeof(*device), GFP_KERNEL); | |
216 | if (!device) { | |
217 | kfree(host); | |
218 | return NULL; | |
219 | } | |
220 | ||
221 | device->host = &host->base; | |
222 | host->device = device; | |
223 | ||
224 | return host; | |
225 | } | |
226 | ||
a2581a9e JN |
227 | /* |
228 | * send a video mode command | |
229 | * | |
230 | * XXX: commands with data in MIPI_DPI_DATA? | |
231 | */ | |
232 | static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, | |
233 | enum port port) | |
234 | { | |
235 | struct drm_encoder *encoder = &intel_dsi->base.base; | |
236 | struct drm_device *dev = encoder->dev; | |
237 | struct drm_i915_private *dev_priv = dev->dev_private; | |
238 | u32 mask; | |
239 | ||
240 | /* XXX: pipe, hs */ | |
241 | if (hs) | |
242 | cmd &= ~DPI_LP_MODE; | |
243 | else | |
244 | cmd |= DPI_LP_MODE; | |
245 | ||
246 | /* clear bit */ | |
247 | I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); | |
248 | ||
249 | /* XXX: old code skips write if control unchanged */ | |
250 | if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) | |
251 | DRM_ERROR("Same special packet %02x twice in a row.\n", cmd); | |
252 | ||
253 | I915_WRITE(MIPI_DPI_CONTROL(port), cmd); | |
254 | ||
255 | mask = SPL_PKT_SENT_INTERRUPT; | |
256 | if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100)) | |
257 | DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd); | |
258 | ||
259 | return 0; | |
260 | } | |
261 | ||
e9fe51c6 | 262 | static void band_gap_reset(struct drm_i915_private *dev_priv) |
4ce8c9a7 | 263 | { |
a580516d | 264 | mutex_lock(&dev_priv->sb_lock); |
4ce8c9a7 | 265 | |
e9fe51c6 SK |
266 | vlv_flisdsi_write(dev_priv, 0x08, 0x0001); |
267 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); | |
268 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); | |
269 | udelay(150); | |
270 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); | |
271 | vlv_flisdsi_write(dev_priv, 0x08, 0x0000); | |
4ce8c9a7 | 272 | |
a580516d | 273 | mutex_unlock(&dev_priv->sb_lock); |
4ce8c9a7 SK |
274 | } |
275 | ||
4e646495 JN |
276 | static inline bool is_vid_mode(struct intel_dsi *intel_dsi) |
277 | { | |
dfba2e2d | 278 | return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE; |
4e646495 JN |
279 | } |
280 | ||
281 | static inline bool is_cmd_mode(struct intel_dsi *intel_dsi) | |
282 | { | |
dfba2e2d | 283 | return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE; |
4e646495 JN |
284 | } |
285 | ||
4e646495 | 286 | static bool intel_dsi_compute_config(struct intel_encoder *encoder, |
a65347ba | 287 | struct intel_crtc_state *pipe_config) |
4e646495 | 288 | { |
4d1de975 | 289 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
4e646495 JN |
290 | struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, |
291 | base); | |
292 | struct intel_connector *intel_connector = intel_dsi->attached_connector; | |
293 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
a65347ba | 294 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
4e646495 JN |
295 | |
296 | DRM_DEBUG_KMS("\n"); | |
297 | ||
a65347ba JN |
298 | pipe_config->has_dsi_encoder = true; |
299 | ||
4e646495 JN |
300 | if (fixed_mode) |
301 | intel_fixed_panel_mode(fixed_mode, adjusted_mode); | |
302 | ||
f573de5a SK |
303 | /* DSI uses short packets for sync events, so clear mode flags for DSI */ |
304 | adjusted_mode->flags = 0; | |
305 | ||
4d1de975 JN |
306 | if (IS_BROXTON(dev_priv)) { |
307 | /* Dual link goes to DSI transcoder A. */ | |
308 | if (intel_dsi->ports == BIT(PORT_C)) | |
309 | pipe_config->cpu_transcoder = TRANSCODER_DSI_C; | |
310 | else | |
311 | pipe_config->cpu_transcoder = TRANSCODER_DSI_A; | |
312 | } | |
313 | ||
4e646495 JN |
314 | return true; |
315 | } | |
316 | ||
37ab0810 | 317 | static void bxt_dsi_device_ready(struct intel_encoder *encoder) |
5505a244 | 318 | { |
37ab0810 | 319 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
5505a244 | 320 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
369602d3 | 321 | enum port port; |
37ab0810 | 322 | u32 val; |
5505a244 | 323 | |
37ab0810 | 324 | DRM_DEBUG_KMS("\n"); |
a9da9bce | 325 | |
37ab0810 | 326 | /* Exit Low power state in 4 steps*/ |
369602d3 | 327 | for_each_dsi_port(port, intel_dsi->ports) { |
5505a244 | 328 | |
37ab0810 SS |
329 | /* 1. Enable MIPI PHY transparent latch */ |
330 | val = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
331 | I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD); | |
332 | usleep_range(2000, 2500); | |
333 | ||
334 | /* 2. Enter ULPS */ | |
335 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
336 | val &= ~ULPS_STATE_MASK; | |
337 | val |= (ULPS_STATE_ENTER | DEVICE_READY); | |
338 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
339 | usleep_range(2, 3); | |
340 | ||
341 | /* 3. Exit ULPS */ | |
342 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
343 | val &= ~ULPS_STATE_MASK; | |
344 | val |= (ULPS_STATE_EXIT | DEVICE_READY); | |
345 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
346 | usleep_range(1000, 1500); | |
5505a244 | 347 | |
37ab0810 SS |
348 | /* Clear ULPS and set device ready */ |
349 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
350 | val &= ~ULPS_STATE_MASK; | |
351 | val |= DEVICE_READY; | |
352 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
369602d3 | 353 | } |
5505a244 GS |
354 | } |
355 | ||
37ab0810 | 356 | static void vlv_dsi_device_ready(struct intel_encoder *encoder) |
4e646495 | 357 | { |
1dbd7cb2 | 358 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
24ee0e64 GS |
359 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
360 | enum port port; | |
1dbd7cb2 SK |
361 | u32 val; |
362 | ||
4e646495 | 363 | DRM_DEBUG_KMS("\n"); |
4e646495 | 364 | |
a580516d | 365 | mutex_lock(&dev_priv->sb_lock); |
2095f9fc SK |
366 | /* program rcomp for compliance, reduce from 50 ohms to 45 ohms |
367 | * needed everytime after power gate */ | |
368 | vlv_flisdsi_write(dev_priv, 0x04, 0x0004); | |
a580516d | 369 | mutex_unlock(&dev_priv->sb_lock); |
2095f9fc SK |
370 | |
371 | /* bandgap reset is needed after everytime we do power gate */ | |
372 | band_gap_reset(dev_priv); | |
373 | ||
24ee0e64 | 374 | for_each_dsi_port(port, intel_dsi->ports) { |
aceb365c | 375 | |
24ee0e64 GS |
376 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); |
377 | usleep_range(2500, 3000); | |
aceb365c | 378 | |
bf344e80 GS |
379 | /* Enable MIPI PHY transparent latch |
380 | * Common bit for both MIPI Port A & MIPI Port C | |
381 | * No similar bit in MIPI Port C reg | |
382 | */ | |
4ba7d93a | 383 | val = I915_READ(MIPI_PORT_CTRL(PORT_A)); |
bf344e80 | 384 | I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD); |
24ee0e64 | 385 | usleep_range(1000, 1500); |
aceb365c | 386 | |
24ee0e64 GS |
387 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); |
388 | usleep_range(2500, 3000); | |
389 | ||
390 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); | |
391 | usleep_range(2500, 3000); | |
392 | } | |
1dbd7cb2 | 393 | } |
1dbd7cb2 | 394 | |
37ab0810 SS |
395 | static void intel_dsi_device_ready(struct intel_encoder *encoder) |
396 | { | |
397 | struct drm_device *dev = encoder->base.dev; | |
398 | ||
666a4537 | 399 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
37ab0810 SS |
400 | vlv_dsi_device_ready(encoder); |
401 | else if (IS_BROXTON(dev)) | |
402 | bxt_dsi_device_ready(encoder); | |
403 | } | |
404 | ||
405 | static void intel_dsi_port_enable(struct intel_encoder *encoder) | |
406 | { | |
407 | struct drm_device *dev = encoder->base.dev; | |
408 | struct drm_i915_private *dev_priv = dev->dev_private; | |
409 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
410 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
411 | enum port port; | |
37ab0810 SS |
412 | |
413 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { | |
f0f59a00 VS |
414 | u32 temp; |
415 | ||
37ab0810 SS |
416 | temp = I915_READ(VLV_CHICKEN_3); |
417 | temp &= ~PIXEL_OVERLAP_CNT_MASK | | |
418 | intel_dsi->pixel_overlap << | |
419 | PIXEL_OVERLAP_CNT_SHIFT; | |
420 | I915_WRITE(VLV_CHICKEN_3, temp); | |
421 | } | |
422 | ||
423 | for_each_dsi_port(port, intel_dsi->ports) { | |
f0f59a00 VS |
424 | i915_reg_t port_ctrl = IS_BROXTON(dev) ? |
425 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); | |
426 | u32 temp; | |
37ab0810 SS |
427 | |
428 | temp = I915_READ(port_ctrl); | |
429 | ||
430 | temp &= ~LANE_CONFIGURATION_MASK; | |
431 | temp &= ~DUAL_LINK_MODE_MASK; | |
432 | ||
701d25b4 | 433 | if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { |
37ab0810 SS |
434 | temp |= (intel_dsi->dual_link - 1) |
435 | << DUAL_LINK_MODE_SHIFT; | |
436 | temp |= intel_crtc->pipe ? | |
437 | LANE_CONFIGURATION_DUAL_LINK_B : | |
438 | LANE_CONFIGURATION_DUAL_LINK_A; | |
439 | } | |
440 | /* assert ip_tg_enable signal */ | |
441 | I915_WRITE(port_ctrl, temp | DPI_ENABLE); | |
442 | POSTING_READ(port_ctrl); | |
443 | } | |
444 | } | |
445 | ||
446 | static void intel_dsi_port_disable(struct intel_encoder *encoder) | |
447 | { | |
448 | struct drm_device *dev = encoder->base.dev; | |
449 | struct drm_i915_private *dev_priv = dev->dev_private; | |
450 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
451 | enum port port; | |
37ab0810 SS |
452 | |
453 | for_each_dsi_port(port, intel_dsi->ports) { | |
f0f59a00 VS |
454 | i915_reg_t port_ctrl = IS_BROXTON(dev) ? |
455 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); | |
456 | u32 temp; | |
457 | ||
37ab0810 | 458 | /* de-assert ip_tg_enable signal */ |
b389a45c SS |
459 | temp = I915_READ(port_ctrl); |
460 | I915_WRITE(port_ctrl, temp & ~DPI_ENABLE); | |
461 | POSTING_READ(port_ctrl); | |
37ab0810 SS |
462 | } |
463 | } | |
464 | ||
1dbd7cb2 SK |
465 | static void intel_dsi_enable(struct intel_encoder *encoder) |
466 | { | |
467 | struct drm_device *dev = encoder->base.dev; | |
468 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1dbd7cb2 | 469 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
4934b656 | 470 | enum port port; |
1dbd7cb2 SK |
471 | |
472 | DRM_DEBUG_KMS("\n"); | |
b9f5e07d | 473 | |
4934b656 JN |
474 | if (is_cmd_mode(intel_dsi)) { |
475 | for_each_dsi_port(port, intel_dsi->ports) | |
476 | I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); | |
477 | } else { | |
4e646495 | 478 | msleep(20); /* XXX */ |
f03e4179 | 479 | for_each_dsi_port(port, intel_dsi->ports) |
a2581a9e | 480 | dpi_send_cmd(intel_dsi, TURN_ON, false, port); |
4e646495 JN |
481 | msleep(100); |
482 | ||
593e0622 | 483 | drm_panel_enable(intel_dsi->panel); |
2634fd7f | 484 | |
7f6a6a4a JN |
485 | for_each_dsi_port(port, intel_dsi->ports) |
486 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
1381308b | 487 | |
5505a244 | 488 | intel_dsi_port_enable(encoder); |
4e646495 | 489 | } |
b029e66f SK |
490 | |
491 | intel_panel_enable_backlight(intel_dsi->attached_connector); | |
2634fd7f SK |
492 | } |
493 | ||
e3488e75 JN |
494 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder); |
495 | ||
2634fd7f SK |
496 | static void intel_dsi_pre_enable(struct intel_encoder *encoder) |
497 | { | |
20e5bf66 SK |
498 | struct drm_device *dev = encoder->base.dev; |
499 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2634fd7f | 500 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
20e5bf66 SK |
501 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
502 | enum pipe pipe = intel_crtc->pipe; | |
7f6a6a4a | 503 | enum port port; |
20e5bf66 | 504 | u32 tmp; |
2634fd7f SK |
505 | |
506 | DRM_DEBUG_KMS("\n"); | |
507 | ||
e3488e75 | 508 | intel_enable_dsi_pll(encoder); |
58d4d32f | 509 | intel_dsi_prepare(encoder); |
e3488e75 | 510 | |
fc45e821 SK |
511 | /* Panel Enable over CRC PMIC */ |
512 | if (intel_dsi->gpio_panel) | |
513 | gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); | |
514 | ||
515 | msleep(intel_dsi->panel_on_delay); | |
516 | ||
666a4537 | 517 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
37ab0810 SS |
518 | /* |
519 | * Disable DPOunit clock gating, can stall pipe | |
520 | * and we need DPLL REFA always enabled | |
521 | */ | |
522 | tmp = I915_READ(DPLL(pipe)); | |
523 | tmp |= DPLL_REF_CLK_ENABLE_VLV; | |
524 | I915_WRITE(DPLL(pipe), tmp); | |
525 | ||
526 | /* update the hw state for DPLL */ | |
527 | intel_crtc->config->dpll_hw_state.dpll = | |
528 | DPLL_INTEGRATED_REF_CLK_VLV | | |
529 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
530 | ||
531 | tmp = I915_READ(DSPCLK_GATE_D); | |
532 | tmp |= DPOUNIT_CLOCK_GATE_DISABLE; | |
533 | I915_WRITE(DSPCLK_GATE_D, tmp); | |
534 | } | |
2634fd7f SK |
535 | |
536 | /* put device in ready state */ | |
537 | intel_dsi_device_ready(encoder); | |
4e646495 | 538 | |
593e0622 | 539 | drm_panel_prepare(intel_dsi->panel); |
20e5bf66 | 540 | |
7f6a6a4a JN |
541 | for_each_dsi_port(port, intel_dsi->ports) |
542 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
1381308b | 543 | |
2634fd7f SK |
544 | /* Enable port in pre-enable phase itself because as per hw team |
545 | * recommendation, port should be enabled befor plane & pipe */ | |
546 | intel_dsi_enable(encoder); | |
547 | } | |
548 | ||
549 | static void intel_dsi_enable_nop(struct intel_encoder *encoder) | |
550 | { | |
551 | DRM_DEBUG_KMS("\n"); | |
552 | ||
553 | /* for DSI port enable has to be done before pipe | |
554 | * and plane enable, so port enable is done in | |
555 | * pre_enable phase itself unlike other encoders | |
556 | */ | |
4e646495 JN |
557 | } |
558 | ||
c315faf8 ID |
559 | static void intel_dsi_pre_disable(struct intel_encoder *encoder) |
560 | { | |
561 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
f03e4179 | 562 | enum port port; |
c315faf8 ID |
563 | |
564 | DRM_DEBUG_KMS("\n"); | |
565 | ||
b029e66f SK |
566 | intel_panel_disable_backlight(intel_dsi->attached_connector); |
567 | ||
c315faf8 ID |
568 | if (is_vid_mode(intel_dsi)) { |
569 | /* Send Shutdown command to the panel in LP mode */ | |
f03e4179 | 570 | for_each_dsi_port(port, intel_dsi->ports) |
a2581a9e | 571 | dpi_send_cmd(intel_dsi, SHUTDOWN, false, port); |
c315faf8 ID |
572 | msleep(10); |
573 | } | |
574 | } | |
575 | ||
4e646495 JN |
576 | static void intel_dsi_disable(struct intel_encoder *encoder) |
577 | { | |
1dbd7cb2 SK |
578 | struct drm_device *dev = encoder->base.dev; |
579 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4e646495 | 580 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
384f02a2 | 581 | enum port port; |
4e646495 JN |
582 | u32 temp; |
583 | ||
584 | DRM_DEBUG_KMS("\n"); | |
585 | ||
4e646495 | 586 | if (is_vid_mode(intel_dsi)) { |
7f6a6a4a JN |
587 | for_each_dsi_port(port, intel_dsi->ports) |
588 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
1381308b | 589 | |
5505a244 | 590 | intel_dsi_port_disable(encoder); |
4e646495 JN |
591 | msleep(2); |
592 | } | |
593 | ||
384f02a2 GS |
594 | for_each_dsi_port(port, intel_dsi->ports) { |
595 | /* Panel commands can be sent when clock is in LP11 */ | |
596 | I915_WRITE(MIPI_DEVICE_READY(port), 0x0); | |
339023ec | 597 | |
b389a45c | 598 | intel_dsi_reset_clocks(encoder, port); |
384f02a2 | 599 | I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); |
339023ec | 600 | |
384f02a2 GS |
601 | temp = I915_READ(MIPI_DSI_FUNC_PRG(port)); |
602 | temp &= ~VID_MODE_FORMAT_MASK; | |
603 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp); | |
339023ec | 604 | |
384f02a2 GS |
605 | I915_WRITE(MIPI_DEVICE_READY(port), 0x1); |
606 | } | |
1dbd7cb2 SK |
607 | /* if disable packets are sent before sending shutdown packet then in |
608 | * some next enable sequence send turn on packet error is observed */ | |
593e0622 | 609 | drm_panel_disable(intel_dsi->panel); |
1381308b | 610 | |
7f6a6a4a JN |
611 | for_each_dsi_port(port, intel_dsi->ports) |
612 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
4e646495 JN |
613 | } |
614 | ||
1dbd7cb2 | 615 | static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) |
4e646495 | 616 | { |
b389a45c | 617 | struct drm_device *dev = encoder->base.dev; |
1dbd7cb2 | 618 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
384f02a2 GS |
619 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
620 | enum port port; | |
1dbd7cb2 | 621 | |
4e646495 | 622 | DRM_DEBUG_KMS("\n"); |
384f02a2 | 623 | for_each_dsi_port(port, intel_dsi->ports) { |
f0f59a00 VS |
624 | /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ |
625 | i915_reg_t port_ctrl = IS_BROXTON(dev) ? | |
626 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A); | |
627 | u32 val; | |
be4fc046 | 628 | |
384f02a2 GS |
629 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | |
630 | ULPS_STATE_ENTER); | |
631 | usleep_range(2000, 2500); | |
632 | ||
633 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | | |
634 | ULPS_STATE_EXIT); | |
635 | usleep_range(2000, 2500); | |
636 | ||
637 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | | |
638 | ULPS_STATE_ENTER); | |
639 | usleep_range(2000, 2500); | |
640 | ||
641 | /* Wait till Clock lanes are in LP-00 state for MIPI Port A | |
642 | * only. MIPI Port C has no similar bit for checking | |
643 | */ | |
b389a45c SS |
644 | if (wait_for(((I915_READ(port_ctrl) & AFE_LATCHOUT) |
645 | == 0x00000), 30)) | |
384f02a2 GS |
646 | DRM_ERROR("DSI LP not going Low\n"); |
647 | ||
b389a45c SS |
648 | /* Disable MIPI PHY transparent latch */ |
649 | val = I915_READ(port_ctrl); | |
650 | I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD); | |
384f02a2 GS |
651 | usleep_range(1000, 1500); |
652 | ||
653 | I915_WRITE(MIPI_DEVICE_READY(port), 0x00); | |
654 | usleep_range(2000, 2500); | |
655 | } | |
1dbd7cb2 | 656 | |
fe88fc68 | 657 | intel_disable_dsi_pll(encoder); |
4e646495 | 658 | } |
20e5bf66 | 659 | |
1dbd7cb2 SK |
660 | static void intel_dsi_post_disable(struct intel_encoder *encoder) |
661 | { | |
20e5bf66 | 662 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
1dbd7cb2 SK |
663 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
664 | ||
665 | DRM_DEBUG_KMS("\n"); | |
666 | ||
c315faf8 ID |
667 | intel_dsi_disable(encoder); |
668 | ||
1dbd7cb2 SK |
669 | intel_dsi_clear_device_ready(encoder); |
670 | ||
d6e3af54 US |
671 | if (!IS_BROXTON(dev_priv)) { |
672 | u32 val; | |
673 | ||
674 | val = I915_READ(DSPCLK_GATE_D); | |
675 | val &= ~DPOUNIT_CLOCK_GATE_DISABLE; | |
676 | I915_WRITE(DSPCLK_GATE_D, val); | |
677 | } | |
20e5bf66 | 678 | |
593e0622 | 679 | drm_panel_unprepare(intel_dsi->panel); |
df38e655 SK |
680 | |
681 | msleep(intel_dsi->panel_off_delay); | |
682 | msleep(intel_dsi->panel_pwr_cycle_delay); | |
fc45e821 SK |
683 | |
684 | /* Panel Disable over CRC PMIC */ | |
685 | if (intel_dsi->gpio_panel) | |
686 | gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0); | |
1dbd7cb2 | 687 | } |
4e646495 JN |
688 | |
689 | static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, | |
690 | enum pipe *pipe) | |
691 | { | |
692 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
c0beefd2 GS |
693 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
694 | struct drm_device *dev = encoder->base.dev; | |
6d129bea | 695 | enum intel_display_power_domain power_domain; |
e7d7cad0 | 696 | enum port port; |
1dcec2f3 | 697 | bool active = false; |
4e646495 JN |
698 | |
699 | DRM_DEBUG_KMS("\n"); | |
700 | ||
6d129bea | 701 | power_domain = intel_display_port_power_domain(encoder); |
3f3f42b8 | 702 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
6d129bea ID |
703 | return false; |
704 | ||
db18b6a6 ID |
705 | /* |
706 | * On Broxton the PLL needs to be enabled with a valid divider | |
707 | * configuration, otherwise accessing DSI registers will hang the | |
708 | * machine. See BSpec North Display Engine registers/MIPI[BXT]. | |
709 | */ | |
710 | if (IS_BROXTON(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv)) | |
711 | goto out_put_power; | |
712 | ||
4e646495 | 713 | /* XXX: this only works for one DSI output */ |
c0beefd2 | 714 | for_each_dsi_port(port, intel_dsi->ports) { |
f0f59a00 VS |
715 | i915_reg_t ctrl_reg = IS_BROXTON(dev) ? |
716 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); | |
1dcec2f3 | 717 | bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE; |
c0beefd2 GS |
718 | |
719 | /* Due to some hardware limitations on BYT, MIPI Port C DPI | |
720 | * Enable bit does not get set. To check whether DSI Port C | |
721 | * was enabled in BIOS, check the Pipe B enable bit | |
722 | */ | |
666a4537 | 723 | if (IS_VALLEYVIEW(dev) && port == PORT_C) |
1dcec2f3 | 724 | enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; |
4e646495 | 725 | |
1dcec2f3 JN |
726 | /* Try command mode if video mode not enabled */ |
727 | if (!enabled) { | |
728 | u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port)); | |
729 | enabled = tmp & CMD_MODE_DATA_WIDTH_MASK; | |
4e646495 | 730 | } |
1dcec2f3 JN |
731 | |
732 | if (!enabled) | |
733 | continue; | |
734 | ||
735 | if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) | |
736 | continue; | |
737 | ||
6b93e9c8 JN |
738 | if (IS_BROXTON(dev_priv)) { |
739 | u32 tmp = I915_READ(MIPI_CTRL(port)); | |
740 | tmp &= BXT_PIPE_SELECT_MASK; | |
741 | tmp >>= BXT_PIPE_SELECT_SHIFT; | |
742 | ||
743 | if (WARN_ON(tmp > PIPE_C)) | |
744 | continue; | |
745 | ||
746 | *pipe = tmp; | |
747 | } else { | |
748 | *pipe = port == PORT_A ? PIPE_A : PIPE_B; | |
749 | } | |
750 | ||
1dcec2f3 JN |
751 | active = true; |
752 | break; | |
4e646495 | 753 | } |
1dcec2f3 | 754 | |
db18b6a6 | 755 | out_put_power: |
3f3f42b8 | 756 | intel_display_power_put(dev_priv, power_domain); |
4e646495 | 757 | |
1dcec2f3 | 758 | return active; |
4e646495 JN |
759 | } |
760 | ||
6f0e7535 R |
761 | static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, |
762 | struct intel_crtc_state *pipe_config) | |
763 | { | |
764 | struct drm_device *dev = encoder->base.dev; | |
765 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766 | struct drm_display_mode *adjusted_mode = | |
767 | &pipe_config->base.adjusted_mode; | |
768 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
769 | unsigned int bpp, fmt; | |
770 | enum port port; | |
771 | u16 vfp, vsync, vbp; | |
772 | ||
773 | /* | |
774 | * Atleast one port is active as encoder->get_config called only if | |
775 | * encoder->get_hw_state() returns true. | |
776 | */ | |
777 | for_each_dsi_port(port, intel_dsi->ports) { | |
778 | if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) | |
779 | break; | |
780 | } | |
781 | ||
782 | fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; | |
783 | pipe_config->pipe_bpp = | |
784 | mipi_dsi_pixel_format_to_bpp( | |
785 | pixel_format_from_register_bits(fmt)); | |
786 | bpp = pipe_config->pipe_bpp; | |
787 | ||
788 | /* In terms of pixels */ | |
789 | adjusted_mode->crtc_hdisplay = | |
790 | I915_READ(BXT_MIPI_TRANS_HACTIVE(port)); | |
791 | adjusted_mode->crtc_vdisplay = | |
792 | I915_READ(BXT_MIPI_TRANS_VACTIVE(port)); | |
793 | adjusted_mode->crtc_vtotal = | |
794 | I915_READ(BXT_MIPI_TRANS_VTOTAL(port)); | |
795 | ||
796 | /* | |
797 | * TODO: Retrieve hfp, hsync and hbp. Adjust them for dual link and | |
798 | * calculate hsync_start, hsync_end, htotal and hblank_end | |
799 | */ | |
800 | ||
801 | /* vertical values are in terms of lines */ | |
802 | vfp = I915_READ(MIPI_VFP_COUNT(port)); | |
803 | vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port)); | |
804 | vbp = I915_READ(MIPI_VBP_COUNT(port)); | |
805 | ||
806 | adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; | |
807 | ||
808 | adjusted_mode->crtc_vsync_start = | |
809 | vfp + adjusted_mode->crtc_vdisplay; | |
810 | adjusted_mode->crtc_vsync_end = | |
811 | vsync + adjusted_mode->crtc_vsync_start; | |
812 | adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; | |
813 | adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; | |
814 | } | |
815 | ||
816 | ||
4e646495 | 817 | static void intel_dsi_get_config(struct intel_encoder *encoder, |
5cec258b | 818 | struct intel_crtc_state *pipe_config) |
4e646495 | 819 | { |
6f0e7535 | 820 | struct drm_device *dev = encoder->base.dev; |
d7d85d85 | 821 | u32 pclk; |
4e646495 JN |
822 | DRM_DEBUG_KMS("\n"); |
823 | ||
a65347ba JN |
824 | pipe_config->has_dsi_encoder = true; |
825 | ||
6f0e7535 R |
826 | if (IS_BROXTON(dev)) |
827 | bxt_dsi_get_pipe_config(encoder, pipe_config); | |
828 | ||
f573de5a SK |
829 | /* |
830 | * DPLL_MD is not used in case of DSI, reading will get some default value | |
831 | * set dpll_md = 0 | |
832 | */ | |
833 | pipe_config->dpll_hw_state.dpll_md = 0; | |
834 | ||
d7d85d85 | 835 | pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp); |
f573de5a SK |
836 | if (!pclk) |
837 | return; | |
838 | ||
2d112de7 | 839 | pipe_config->base.adjusted_mode.crtc_clock = pclk; |
f573de5a | 840 | pipe_config->port_clock = pclk; |
4e646495 JN |
841 | } |
842 | ||
c19de8eb DL |
843 | static enum drm_mode_status |
844 | intel_dsi_mode_valid(struct drm_connector *connector, | |
845 | struct drm_display_mode *mode) | |
4e646495 JN |
846 | { |
847 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
848 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
759a1e98 | 849 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
4e646495 JN |
850 | |
851 | DRM_DEBUG_KMS("\n"); | |
852 | ||
853 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { | |
854 | DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n"); | |
855 | return MODE_NO_DBLESCAN; | |
856 | } | |
857 | ||
858 | if (fixed_mode) { | |
859 | if (mode->hdisplay > fixed_mode->hdisplay) | |
860 | return MODE_PANEL; | |
861 | if (mode->vdisplay > fixed_mode->vdisplay) | |
862 | return MODE_PANEL; | |
759a1e98 MK |
863 | if (fixed_mode->clock > max_dotclk) |
864 | return MODE_CLOCK_HIGH; | |
4e646495 JN |
865 | } |
866 | ||
36d21f4c | 867 | return MODE_OK; |
4e646495 JN |
868 | } |
869 | ||
870 | /* return txclkesc cycles in terms of divider and duration in us */ | |
871 | static u16 txclkesc(u32 divider, unsigned int us) | |
872 | { | |
873 | switch (divider) { | |
874 | case ESCAPE_CLOCK_DIVIDER_1: | |
875 | default: | |
876 | return 20 * us; | |
877 | case ESCAPE_CLOCK_DIVIDER_2: | |
878 | return 10 * us; | |
879 | case ESCAPE_CLOCK_DIVIDER_4: | |
880 | return 5 * us; | |
881 | } | |
882 | } | |
883 | ||
884 | /* return pixels in terms of txbyteclkhs */ | |
7f0c8605 SK |
885 | static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, |
886 | u16 burst_mode_ratio) | |
4e646495 | 887 | { |
7f0c8605 | 888 | return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, |
7f3de833 | 889 | 8 * 100), lane_count); |
4e646495 JN |
890 | } |
891 | ||
892 | static void set_dsi_timings(struct drm_encoder *encoder, | |
5e7234c9 | 893 | const struct drm_display_mode *adjusted_mode) |
4e646495 JN |
894 | { |
895 | struct drm_device *dev = encoder->dev; | |
896 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4e646495 | 897 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
aa102d28 | 898 | enum port port; |
1e78aa01 | 899 | unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); |
4e646495 JN |
900 | unsigned int lane_count = intel_dsi->lane_count; |
901 | ||
902 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; | |
903 | ||
aad941d5 VS |
904 | hactive = adjusted_mode->crtc_hdisplay; |
905 | hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; | |
906 | hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; | |
907 | hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; | |
4e646495 | 908 | |
aa102d28 GS |
909 | if (intel_dsi->dual_link) { |
910 | hactive /= 2; | |
911 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) | |
912 | hactive += intel_dsi->pixel_overlap; | |
913 | hfp /= 2; | |
914 | hsync /= 2; | |
915 | hbp /= 2; | |
916 | } | |
917 | ||
aad941d5 VS |
918 | vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; |
919 | vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; | |
920 | vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; | |
4e646495 JN |
921 | |
922 | /* horizontal values are in terms of high speed byte clock */ | |
7f0c8605 | 923 | hactive = txbyteclkhs(hactive, bpp, lane_count, |
7f3de833 | 924 | intel_dsi->burst_mode_ratio); |
7f0c8605 SK |
925 | hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
926 | hsync = txbyteclkhs(hsync, bpp, lane_count, | |
7f3de833 | 927 | intel_dsi->burst_mode_ratio); |
7f0c8605 | 928 | hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
4e646495 | 929 | |
aa102d28 | 930 | for_each_dsi_port(port, intel_dsi->ports) { |
d2e08c0f SS |
931 | if (IS_BROXTON(dev)) { |
932 | /* | |
933 | * Program hdisplay and vdisplay on MIPI transcoder. | |
934 | * This is different from calculated hactive and | |
935 | * vactive, as they are calculated per channel basis, | |
936 | * whereas these values should be based on resolution. | |
937 | */ | |
938 | I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port), | |
aad941d5 | 939 | adjusted_mode->crtc_hdisplay); |
d2e08c0f | 940 | I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port), |
aad941d5 | 941 | adjusted_mode->crtc_vdisplay); |
d2e08c0f | 942 | I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port), |
aad941d5 | 943 | adjusted_mode->crtc_vtotal); |
d2e08c0f SS |
944 | } |
945 | ||
aa102d28 GS |
946 | I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); |
947 | I915_WRITE(MIPI_HFP_COUNT(port), hfp); | |
948 | ||
949 | /* meaningful for video mode non-burst sync pulse mode only, | |
950 | * can be zero for non-burst sync events and burst modes */ | |
951 | I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); | |
952 | I915_WRITE(MIPI_HBP_COUNT(port), hbp); | |
953 | ||
954 | /* vertical values are in terms of lines */ | |
955 | I915_WRITE(MIPI_VFP_COUNT(port), vfp); | |
956 | I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); | |
957 | I915_WRITE(MIPI_VBP_COUNT(port), vbp); | |
958 | } | |
4e646495 JN |
959 | } |
960 | ||
1e78aa01 JN |
961 | static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt) |
962 | { | |
963 | switch (fmt) { | |
964 | case MIPI_DSI_FMT_RGB888: | |
965 | return VID_MODE_FORMAT_RGB888; | |
966 | case MIPI_DSI_FMT_RGB666: | |
967 | return VID_MODE_FORMAT_RGB666; | |
968 | case MIPI_DSI_FMT_RGB666_PACKED: | |
969 | return VID_MODE_FORMAT_RGB666_PACKED; | |
970 | case MIPI_DSI_FMT_RGB565: | |
971 | return VID_MODE_FORMAT_RGB565; | |
972 | default: | |
973 | MISSING_CASE(fmt); | |
974 | return VID_MODE_FORMAT_RGB666; | |
975 | } | |
976 | } | |
977 | ||
07e4fb9e | 978 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder) |
4e646495 JN |
979 | { |
980 | struct drm_encoder *encoder = &intel_encoder->base; | |
981 | struct drm_device *dev = encoder->dev; | |
982 | struct drm_i915_private *dev_priv = dev->dev_private; | |
983 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
984 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
7c5f93b0 | 985 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
24ee0e64 | 986 | enum port port; |
1e78aa01 | 987 | unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); |
4e646495 | 988 | u32 val, tmp; |
24ee0e64 | 989 | u16 mode_hdisplay; |
4e646495 | 990 | |
e7d7cad0 | 991 | DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe)); |
4e646495 | 992 | |
aad941d5 | 993 | mode_hdisplay = adjusted_mode->crtc_hdisplay; |
4e646495 | 994 | |
24ee0e64 GS |
995 | if (intel_dsi->dual_link) { |
996 | mode_hdisplay /= 2; | |
997 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) | |
998 | mode_hdisplay += intel_dsi->pixel_overlap; | |
999 | } | |
4e646495 | 1000 | |
24ee0e64 | 1001 | for_each_dsi_port(port, intel_dsi->ports) { |
666a4537 | 1002 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
d2e08c0f SS |
1003 | /* |
1004 | * escape clock divider, 20MHz, shared for A and C. | |
1005 | * device ready must be off when doing this! txclkesc? | |
1006 | */ | |
1007 | tmp = I915_READ(MIPI_CTRL(PORT_A)); | |
1008 | tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; | |
1009 | I915_WRITE(MIPI_CTRL(PORT_A), tmp | | |
1010 | ESCAPE_CLOCK_DIVIDER_1); | |
1011 | ||
1012 | /* read request priority is per pipe */ | |
1013 | tmp = I915_READ(MIPI_CTRL(port)); | |
1014 | tmp &= ~READ_REQUEST_PRIORITY_MASK; | |
1015 | I915_WRITE(MIPI_CTRL(port), tmp | | |
1016 | READ_REQUEST_PRIORITY_HIGH); | |
1017 | } else if (IS_BROXTON(dev)) { | |
56c48978 D |
1018 | enum pipe pipe = intel_crtc->pipe; |
1019 | ||
d2e08c0f SS |
1020 | tmp = I915_READ(MIPI_CTRL(port)); |
1021 | tmp &= ~BXT_PIPE_SELECT_MASK; | |
1022 | ||
56c48978 | 1023 | tmp |= BXT_PIPE_SELECT(pipe); |
d2e08c0f SS |
1024 | I915_WRITE(MIPI_CTRL(port), tmp); |
1025 | } | |
24ee0e64 GS |
1026 | |
1027 | /* XXX: why here, why like this? handling in irq handler?! */ | |
1028 | I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); | |
1029 | I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); | |
1030 | ||
1031 | I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); | |
1032 | ||
1033 | I915_WRITE(MIPI_DPI_RESOLUTION(port), | |
aad941d5 | 1034 | adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | |
24ee0e64 GS |
1035 | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); |
1036 | } | |
4e646495 JN |
1037 | |
1038 | set_dsi_timings(encoder, adjusted_mode); | |
1039 | ||
1040 | val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; | |
1041 | if (is_cmd_mode(intel_dsi)) { | |
1042 | val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; | |
1043 | val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ | |
1044 | } else { | |
1045 | val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; | |
1e78aa01 | 1046 | val |= pixel_format_to_reg(intel_dsi->pixel_format); |
4e646495 | 1047 | } |
4e646495 | 1048 | |
24ee0e64 GS |
1049 | tmp = 0; |
1050 | if (intel_dsi->eotp_pkt == 0) | |
1051 | tmp |= EOT_DISABLE; | |
1052 | if (intel_dsi->clock_stop) | |
1053 | tmp |= CLOCKSTOP; | |
4e646495 | 1054 | |
24ee0e64 GS |
1055 | for_each_dsi_port(port, intel_dsi->ports) { |
1056 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); | |
1057 | ||
1058 | /* timeouts for recovery. one frame IIUC. if counter expires, | |
1059 | * EOT and stop state. */ | |
1060 | ||
1061 | /* | |
1062 | * In burst mode, value greater than one DPI line Time in byte | |
1063 | * clock (txbyteclkhs) To timeout this timer 1+ of the above | |
1064 | * said value is recommended. | |
1065 | * | |
1066 | * In non-burst mode, Value greater than one DPI frame time in | |
1067 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above | |
1068 | * said value is recommended. | |
1069 | * | |
1070 | * In DBI only mode, value greater than one DBI frame time in | |
1071 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above | |
1072 | * said value is recommended. | |
1073 | */ | |
4e646495 | 1074 | |
24ee0e64 GS |
1075 | if (is_vid_mode(intel_dsi) && |
1076 | intel_dsi->video_mode_format == VIDEO_MODE_BURST) { | |
1077 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), | |
aad941d5 | 1078 | txbyteclkhs(adjusted_mode->crtc_htotal, bpp, |
124abe07 VS |
1079 | intel_dsi->lane_count, |
1080 | intel_dsi->burst_mode_ratio) + 1); | |
24ee0e64 GS |
1081 | } else { |
1082 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), | |
aad941d5 VS |
1083 | txbyteclkhs(adjusted_mode->crtc_vtotal * |
1084 | adjusted_mode->crtc_htotal, | |
124abe07 VS |
1085 | bpp, intel_dsi->lane_count, |
1086 | intel_dsi->burst_mode_ratio) + 1); | |
24ee0e64 GS |
1087 | } |
1088 | I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); | |
1089 | I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), | |
1090 | intel_dsi->turn_arnd_val); | |
1091 | I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), | |
1092 | intel_dsi->rst_timer_val); | |
f1c79f16 | 1093 | |
24ee0e64 | 1094 | /* dphy stuff */ |
f1c79f16 | 1095 | |
24ee0e64 GS |
1096 | /* in terms of low power clock */ |
1097 | I915_WRITE(MIPI_INIT_COUNT(port), | |
1098 | txclkesc(intel_dsi->escape_clk_div, 100)); | |
4e646495 | 1099 | |
d2e08c0f SS |
1100 | if (IS_BROXTON(dev) && (!intel_dsi->dual_link)) { |
1101 | /* | |
1102 | * BXT spec says write MIPI_INIT_COUNT for | |
1103 | * both the ports, even if only one is | |
1104 | * getting used. So write the other port | |
1105 | * if not in dual link mode. | |
1106 | */ | |
1107 | I915_WRITE(MIPI_INIT_COUNT(port == | |
1108 | PORT_A ? PORT_C : PORT_A), | |
1109 | intel_dsi->init_count); | |
1110 | } | |
4e646495 | 1111 | |
24ee0e64 | 1112 | /* recovery disables */ |
87c54d0e | 1113 | I915_WRITE(MIPI_EOT_DISABLE(port), tmp); |
cf4dbd2e | 1114 | |
24ee0e64 GS |
1115 | /* in terms of low power clock */ |
1116 | I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); | |
4e646495 | 1117 | |
24ee0e64 GS |
1118 | /* in terms of txbyteclkhs. actual high to low switch + |
1119 | * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. | |
1120 | * | |
1121 | * XXX: write MIPI_STOP_STATE_STALL? | |
1122 | */ | |
1123 | I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), | |
1124 | intel_dsi->hs_to_lp_count); | |
1125 | ||
1126 | /* XXX: low power clock equivalence in terms of byte clock. | |
1127 | * the number of byte clocks occupied in one low power clock. | |
1128 | * based on txbyteclkhs and txclkesc. | |
1129 | * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL | |
1130 | * ) / 105.??? | |
1131 | */ | |
1132 | I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); | |
1133 | ||
1134 | /* the bw essential for transmitting 16 long packets containing | |
1135 | * 252 bytes meant for dcs write memory command is programmed in | |
1136 | * this register in terms of byte clocks. based on dsi transfer | |
1137 | * rate and the number of lanes configured the time taken to | |
1138 | * transmit 16 long packets in a dsi stream varies. */ | |
1139 | I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); | |
1140 | ||
1141 | I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), | |
1142 | intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | | |
1143 | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); | |
1144 | ||
1145 | if (is_vid_mode(intel_dsi)) | |
1146 | /* Some panels might have resolution which is not a | |
1147 | * multiple of 64 like 1366 x 768. Enable RANDOM | |
1148 | * resolution support for such panels by default */ | |
1149 | I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), | |
1150 | intel_dsi->video_frmt_cfg_bits | | |
1151 | intel_dsi->video_mode_format | | |
1152 | IP_TG_CONFIG | | |
1153 | RANDOM_DPI_DISPLAY_RESOLUTION); | |
1154 | } | |
4e646495 JN |
1155 | } |
1156 | ||
1157 | static enum drm_connector_status | |
1158 | intel_dsi_detect(struct drm_connector *connector, bool force) | |
1159 | { | |
36d21f4c | 1160 | return connector_status_connected; |
4e646495 JN |
1161 | } |
1162 | ||
1163 | static int intel_dsi_get_modes(struct drm_connector *connector) | |
1164 | { | |
1165 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
1166 | struct drm_display_mode *mode; | |
1167 | ||
1168 | DRM_DEBUG_KMS("\n"); | |
1169 | ||
1170 | if (!intel_connector->panel.fixed_mode) { | |
1171 | DRM_DEBUG_KMS("no fixed mode\n"); | |
1172 | return 0; | |
1173 | } | |
1174 | ||
1175 | mode = drm_mode_duplicate(connector->dev, | |
1176 | intel_connector->panel.fixed_mode); | |
1177 | if (!mode) { | |
1178 | DRM_DEBUG_KMS("drm_mode_duplicate failed\n"); | |
1179 | return 0; | |
1180 | } | |
1181 | ||
1182 | drm_mode_probed_add(connector, mode); | |
1183 | return 1; | |
1184 | } | |
1185 | ||
593e0622 | 1186 | static void intel_dsi_connector_destroy(struct drm_connector *connector) |
4e646495 JN |
1187 | { |
1188 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
1189 | ||
1190 | DRM_DEBUG_KMS("\n"); | |
1191 | intel_panel_fini(&intel_connector->panel); | |
4e646495 JN |
1192 | drm_connector_cleanup(connector); |
1193 | kfree(connector); | |
1194 | } | |
1195 | ||
593e0622 JN |
1196 | static void intel_dsi_encoder_destroy(struct drm_encoder *encoder) |
1197 | { | |
1198 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
1199 | ||
1200 | if (intel_dsi->panel) { | |
1201 | drm_panel_detach(intel_dsi->panel); | |
1202 | /* XXX: Logically this call belongs in the panel driver. */ | |
1203 | drm_panel_remove(intel_dsi->panel); | |
1204 | } | |
fc45e821 SK |
1205 | |
1206 | /* dispose of the gpios */ | |
1207 | if (intel_dsi->gpio_panel) | |
1208 | gpiod_put(intel_dsi->gpio_panel); | |
1209 | ||
593e0622 JN |
1210 | intel_encoder_destroy(encoder); |
1211 | } | |
1212 | ||
4e646495 | 1213 | static const struct drm_encoder_funcs intel_dsi_funcs = { |
593e0622 | 1214 | .destroy = intel_dsi_encoder_destroy, |
4e646495 JN |
1215 | }; |
1216 | ||
1217 | static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { | |
1218 | .get_modes = intel_dsi_get_modes, | |
1219 | .mode_valid = intel_dsi_mode_valid, | |
1220 | .best_encoder = intel_best_encoder, | |
1221 | }; | |
1222 | ||
1223 | static const struct drm_connector_funcs intel_dsi_connector_funcs = { | |
4d688a2a | 1224 | .dpms = drm_atomic_helper_connector_dpms, |
4e646495 | 1225 | .detect = intel_dsi_detect, |
593e0622 | 1226 | .destroy = intel_dsi_connector_destroy, |
4e646495 | 1227 | .fill_modes = drm_helper_probe_single_connector_modes, |
2545e4a6 | 1228 | .atomic_get_property = intel_connector_atomic_get_property, |
c6f95f27 | 1229 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 1230 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
4e646495 JN |
1231 | }; |
1232 | ||
4328633d | 1233 | void intel_dsi_init(struct drm_device *dev) |
4e646495 JN |
1234 | { |
1235 | struct intel_dsi *intel_dsi; | |
1236 | struct intel_encoder *intel_encoder; | |
1237 | struct drm_encoder *encoder; | |
1238 | struct intel_connector *intel_connector; | |
1239 | struct drm_connector *connector; | |
593e0622 | 1240 | struct drm_display_mode *scan, *fixed_mode = NULL; |
b6fdd0f2 | 1241 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e9804fd | 1242 | enum port port; |
4e646495 JN |
1243 | unsigned int i; |
1244 | ||
1245 | DRM_DEBUG_KMS("\n"); | |
1246 | ||
3e6bd011 | 1247 | /* There is no detection method for MIPI so rely on VBT */ |
7137aec1 | 1248 | if (!intel_bios_is_dsi_present(dev_priv, &port)) |
4328633d | 1249 | return; |
3e6bd011 | 1250 | |
666a4537 | 1251 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
868d665b | 1252 | dev_priv->mipi_mmio_base = VLV_MIPI_BASE; |
c6c794a2 SS |
1253 | } else if (IS_BROXTON(dev)) { |
1254 | dev_priv->mipi_mmio_base = BXT_MIPI_BASE; | |
868d665b CJ |
1255 | } else { |
1256 | DRM_ERROR("Unsupported Mipi device to reg base"); | |
1257 | return; | |
1258 | } | |
3e6bd011 | 1259 | |
4e646495 JN |
1260 | intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); |
1261 | if (!intel_dsi) | |
4328633d | 1262 | return; |
4e646495 | 1263 | |
08d9bc92 | 1264 | intel_connector = intel_connector_alloc(); |
4e646495 JN |
1265 | if (!intel_connector) { |
1266 | kfree(intel_dsi); | |
4328633d | 1267 | return; |
4e646495 JN |
1268 | } |
1269 | ||
1270 | intel_encoder = &intel_dsi->base; | |
1271 | encoder = &intel_encoder->base; | |
1272 | intel_dsi->attached_connector = intel_connector; | |
1273 | ||
1274 | connector = &intel_connector->base; | |
1275 | ||
13a3d91f VS |
1276 | drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI, |
1277 | NULL); | |
4e646495 | 1278 | |
4e646495 | 1279 | intel_encoder->compute_config = intel_dsi_compute_config; |
4e646495 | 1280 | intel_encoder->pre_enable = intel_dsi_pre_enable; |
2634fd7f | 1281 | intel_encoder->enable = intel_dsi_enable_nop; |
c315faf8 | 1282 | intel_encoder->disable = intel_dsi_pre_disable; |
4e646495 JN |
1283 | intel_encoder->post_disable = intel_dsi_post_disable; |
1284 | intel_encoder->get_hw_state = intel_dsi_get_hw_state; | |
1285 | intel_encoder->get_config = intel_dsi_get_config; | |
1286 | ||
1287 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
4932e2c3 | 1288 | intel_connector->unregister = intel_connector_unregister; |
4e646495 | 1289 | |
2e85ab4f JN |
1290 | /* |
1291 | * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI | |
1292 | * port C. BXT isn't limited like this. | |
1293 | */ | |
1294 | if (IS_BROXTON(dev_priv)) | |
1295 | intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); | |
1296 | else if (port == PORT_A) | |
701d25b4 | 1297 | intel_encoder->crtc_mask = BIT(PIPE_A); |
7137aec1 | 1298 | else |
701d25b4 | 1299 | intel_encoder->crtc_mask = BIT(PIPE_B); |
e7d7cad0 | 1300 | |
82425785 | 1301 | if (dev_priv->vbt.dsi.config->dual_link) |
701d25b4 | 1302 | intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); |
7137aec1 | 1303 | else |
701d25b4 | 1304 | intel_dsi->ports = BIT(port); |
82425785 | 1305 | |
7e9804fd JN |
1306 | /* Create a DSI host (and a device) for each port. */ |
1307 | for_each_dsi_port(port, intel_dsi->ports) { | |
1308 | struct intel_dsi_host *host; | |
1309 | ||
1310 | host = intel_dsi_host_init(intel_dsi, port); | |
1311 | if (!host) | |
1312 | goto err; | |
1313 | ||
1314 | intel_dsi->dsi_hosts[port] = host; | |
1315 | } | |
1316 | ||
593e0622 JN |
1317 | for (i = 0; i < ARRAY_SIZE(intel_dsi_drivers); i++) { |
1318 | intel_dsi->panel = intel_dsi_drivers[i].init(intel_dsi, | |
1319 | intel_dsi_drivers[i].panel_id); | |
1320 | if (intel_dsi->panel) | |
4e646495 JN |
1321 | break; |
1322 | } | |
1323 | ||
593e0622 | 1324 | if (!intel_dsi->panel) { |
4e646495 JN |
1325 | DRM_DEBUG_KMS("no device found\n"); |
1326 | goto err; | |
1327 | } | |
1328 | ||
fc45e821 SK |
1329 | /* |
1330 | * In case of BYT with CRC PMIC, we need to use GPIO for | |
1331 | * Panel control. | |
1332 | */ | |
1333 | if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) { | |
1334 | intel_dsi->gpio_panel = | |
1335 | gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH); | |
1336 | ||
1337 | if (IS_ERR(intel_dsi->gpio_panel)) { | |
1338 | DRM_ERROR("Failed to own gpio for panel control\n"); | |
1339 | intel_dsi->gpio_panel = NULL; | |
1340 | } | |
1341 | } | |
1342 | ||
4e646495 | 1343 | intel_encoder->type = INTEL_OUTPUT_DSI; |
bc079e8b | 1344 | intel_encoder->cloneable = 0; |
4e646495 JN |
1345 | drm_connector_init(dev, connector, &intel_dsi_connector_funcs, |
1346 | DRM_MODE_CONNECTOR_DSI); | |
1347 | ||
1348 | drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); | |
1349 | ||
1350 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ | |
1351 | connector->interlace_allowed = false; | |
1352 | connector->doublescan_allowed = false; | |
1353 | ||
1354 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
1355 | ||
34ea3d38 | 1356 | drm_connector_register(connector); |
4e646495 | 1357 | |
593e0622 JN |
1358 | drm_panel_attach(intel_dsi->panel, connector); |
1359 | ||
1360 | mutex_lock(&dev->mode_config.mutex); | |
1361 | drm_panel_get_modes(intel_dsi->panel); | |
1362 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
1363 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { | |
1364 | fixed_mode = drm_mode_duplicate(dev, scan); | |
1365 | break; | |
1366 | } | |
1367 | } | |
1368 | mutex_unlock(&dev->mode_config.mutex); | |
1369 | ||
4e646495 JN |
1370 | if (!fixed_mode) { |
1371 | DRM_DEBUG_KMS("no fixed mode\n"); | |
1372 | goto err; | |
1373 | } | |
1374 | ||
4b6ed685 | 1375 | intel_panel_init(&intel_connector->panel, fixed_mode, NULL); |
b029e66f | 1376 | intel_panel_setup_backlight(connector, INVALID_PIPE); |
4e646495 | 1377 | |
4328633d | 1378 | return; |
4e646495 JN |
1379 | |
1380 | err: | |
1381 | drm_encoder_cleanup(&intel_encoder->base); | |
1382 | kfree(intel_dsi); | |
1383 | kfree(intel_connector); | |
4e646495 | 1384 | } |