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drm/i915: Remove redundant DSI PLL enabling
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dsi.c
CommitLineData
4e646495
JN		 1/*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Author: Jani Nikula <jani.nikula@intel.com>
24 */
25
26#include <drm/drmP.h>
27#include <drm/drm_crtc.h>
28#include <drm/drm_edid.h>
29#include <drm/i915_drm.h>
30#include <linux/slab.h>
31#include "i915_drv.h"
32#include "intel_drv.h"
33#include "intel_dsi.h"
34#include "intel_dsi_cmd.h"
35
36/* the sub-encoders aka panel drivers */
37static const struct intel_dsi_device intel_dsi_devices[] = {
38};
39
e9fe51c6 40static void band_gap_reset(struct drm_i915_private *dev_priv)
4ce8c9a7
SK		 41{
42 mutex_lock(&dev_priv->dpio_lock);
43
e9fe51c6
SK		 44 vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
45 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
46 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
47 udelay(150);
48 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
49 vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
4ce8c9a7
SK		 50
51 mutex_unlock(&dev_priv->dpio_lock);
4ce8c9a7
SK		 52}
53
4e646495
JN		 54static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector)
55{
56 return container_of(intel_attached_encoder(connector),
57 struct intel_dsi, base);
58}
59
60static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
61{
62 return intel_dsi->dev.type == INTEL_DSI_VIDEO_MODE;
63}
64
65static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
66{
67 return intel_dsi->dev.type == INTEL_DSI_COMMAND_MODE;
68}
69
70static void intel_dsi_hot_plug(struct intel_encoder *encoder)
71{
72 DRM_DEBUG_KMS("\n");
73}
74
75static bool intel_dsi_compute_config(struct intel_encoder *encoder,
76 struct intel_crtc_config *config)
77{
78 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
79 base);
80 struct intel_connector *intel_connector = intel_dsi->attached_connector;
81 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
82 struct drm_display_mode *adjusted_mode = &config->adjusted_mode;
83 struct drm_display_mode *mode = &config->requested_mode;
84
85 DRM_DEBUG_KMS("\n");
86
87 if (fixed_mode)
88 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
89
90 if (intel_dsi->dev.dev_ops->mode_fixup)
91 return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev,
92 mode, adjusted_mode);
93
94 return true;
95}
96
97static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
98{
99 DRM_DEBUG_KMS("\n");
be4fc046 100
101 vlv_enable_dsi_pll(encoder);
4e646495
JN		 102}
103
1dbd7cb2 104static void intel_dsi_device_ready(struct intel_encoder *encoder)
4e646495 105{
1dbd7cb2
SK		 106 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
107 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
108 int pipe = intel_crtc->pipe;
109 u32 val;
110
4e646495 111 DRM_DEBUG_KMS("\n");
4e646495 112
1dbd7cb2
SK		 113 val = I915_READ(MIPI_PORT_CTRL(pipe));
114 I915_WRITE(MIPI_PORT_CTRL(pipe), val | LP_OUTPUT_HOLD);
115 usleep_range(1000, 1500);
116 I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT);
117 usleep_range(2000, 2500);
118 I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY);
119 usleep_range(2000, 2500);
120 I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00);
121 usleep_range(2000, 2500);
122 I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY);
123 usleep_range(2000, 2500);
124}
125static void intel_dsi_pre_enable(struct intel_encoder *encoder)
4e646495 126{
4e646495 127 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
4e646495
JN		 128
129 DRM_DEBUG_KMS("\n");
130
b9f5e07d
SK		 131 if (intel_dsi->dev.dev_ops->panel_reset)
132 intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev);
133
1dbd7cb2
SK		 134 /* put device in ready state */
135 intel_dsi_device_ready(encoder);
4e646495 136
b9f5e07d
SK		 137 if (intel_dsi->dev.dev_ops->send_otp_cmds)
138 intel_dsi->dev.dev_ops->send_otp_cmds(&intel_dsi->dev);
1dbd7cb2
SK		 139}
140
141static void intel_dsi_enable(struct intel_encoder *encoder)
142{
143 struct drm_device *dev = encoder->base.dev;
144 struct drm_i915_private *dev_priv = dev->dev_private;
145 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
146 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
147 int pipe = intel_crtc->pipe;
148 u32 temp;
149
150 DRM_DEBUG_KMS("\n");
b9f5e07d 151
4e646495
JN		 152 if (is_cmd_mode(intel_dsi))
153 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4);
1dbd7cb2 154 else {
4e646495
JN		 155 msleep(20); /* XXX */
156 dpi_send_cmd(intel_dsi, TURN_ON);
157 msleep(100);
158
159 /* assert ip_tg_enable signal */
160 temp = I915_READ(MIPI_PORT_CTRL(pipe));
161 I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE);
162 POSTING_READ(MIPI_PORT_CTRL(pipe));
163 }
164
b9f5e07d
SK		 165 if (intel_dsi->dev.dev_ops->enable)
166 intel_dsi->dev.dev_ops->enable(&intel_dsi->dev);
4e646495
JN		 167}
168
169static void intel_dsi_disable(struct intel_encoder *encoder)
170{
1dbd7cb2
SK		 171 struct drm_device *dev = encoder->base.dev;
172 struct drm_i915_private *dev_priv = dev->dev_private;
4e646495
JN		 173 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
174 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
175 int pipe = intel_crtc->pipe;
176 u32 temp;
177
178 DRM_DEBUG_KMS("\n");
179
4e646495
JN		 180 if (is_vid_mode(intel_dsi)) {
181 dpi_send_cmd(intel_dsi, SHUTDOWN);
182 msleep(10);
183
184 /* de-assert ip_tg_enable signal */
185 temp = I915_READ(MIPI_PORT_CTRL(pipe));
186 I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE);
187 POSTING_READ(MIPI_PORT_CTRL(pipe));
188
189 msleep(2);
190 }
191
1dbd7cb2
SK		 192 /* if disable packets are sent before sending shutdown packet then in
193 * some next enable sequence send turn on packet error is observed */
194 if (intel_dsi->dev.dev_ops->disable)
195 intel_dsi->dev.dev_ops->disable(&intel_dsi->dev);
4e646495
JN		 196}
197
1dbd7cb2 198static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
4e646495 199{
1dbd7cb2
SK		 200 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
201 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
202 int pipe = intel_crtc->pipe;
203 u32 val;
204
4e646495 205 DRM_DEBUG_KMS("\n");
be4fc046 206
1dbd7cb2
SK		 207 I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
208 usleep_range(2000, 2500);
209
210 I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT);
211 usleep_range(2000, 2500);
212
213 I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
214 usleep_range(2000, 2500);
215
216 val = I915_READ(MIPI_PORT_CTRL(pipe));
217 I915_WRITE(MIPI_PORT_CTRL(pipe), val & ~LP_OUTPUT_HOLD);
218 usleep_range(1000, 1500);
219
220 if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & AFE_LATCHOUT)
221 == 0x00000), 30))
222 DRM_ERROR("DSI LP not going Low\n");
223
224 I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00);
225 usleep_range(2000, 2500);
226
be4fc046 227 vlv_disable_dsi_pll(encoder);
4e646495 228}
1dbd7cb2
SK		 229static void intel_dsi_post_disable(struct intel_encoder *encoder)
230{
231 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
232
233 DRM_DEBUG_KMS("\n");
234
235 intel_dsi_clear_device_ready(encoder);
236
237 if (intel_dsi->dev.dev_ops->disable_panel_power)
238 intel_dsi->dev.dev_ops->disable_panel_power(&intel_dsi->dev);
239}
4e646495
JN		 240
241static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
242 enum pipe *pipe)
243{
244 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
245 u32 port, func;
246 enum pipe p;
247
248 DRM_DEBUG_KMS("\n");
249
250 /* XXX: this only works for one DSI output */
251 for (p = PIPE_A; p <= PIPE_B; p++) {
252 port = I915_READ(MIPI_PORT_CTRL(p));
253 func = I915_READ(MIPI_DSI_FUNC_PRG(p));
254
255 if ((port & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) {
256 if (I915_READ(MIPI_DEVICE_READY(p)) & DEVICE_READY) {
257 *pipe = p;
258 return true;
259 }
260 }
261 }
262
263 return false;
264}
265
266static void intel_dsi_get_config(struct intel_encoder *encoder,
267 struct intel_crtc_config *pipe_config)
268{
269 DRM_DEBUG_KMS("\n");
270
271 /* XXX: read flags, set to adjusted_mode */
272}
273
c19de8eb
DL		 274static enum drm_mode_status
275intel_dsi_mode_valid(struct drm_connector *connector,
276 struct drm_display_mode *mode)
4e646495
JN		 277{
278 struct intel_connector *intel_connector = to_intel_connector(connector);
279 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
280 struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
281
282 DRM_DEBUG_KMS("\n");
283
284 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
285 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
286 return MODE_NO_DBLESCAN;
287 }
288
289 if (fixed_mode) {
290 if (mode->hdisplay > fixed_mode->hdisplay)
291 return MODE_PANEL;
292 if (mode->vdisplay > fixed_mode->vdisplay)
293 return MODE_PANEL;
294 }
295
296 return intel_dsi->dev.dev_ops->mode_valid(&intel_dsi->dev, mode);
297}
298
299/* return txclkesc cycles in terms of divider and duration in us */
300static u16 txclkesc(u32 divider, unsigned int us)
301{
302 switch (divider) {
303 case ESCAPE_CLOCK_DIVIDER_1:
304 default:
305 return 20 * us;
306 case ESCAPE_CLOCK_DIVIDER_2:
307 return 10 * us;
308 case ESCAPE_CLOCK_DIVIDER_4:
309 return 5 * us;
310 }
311}
312
313/* return pixels in terms of txbyteclkhs */
314static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count)
315{
316 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp, 8), lane_count);
317}
318
319static void set_dsi_timings(struct drm_encoder *encoder,
320 const struct drm_display_mode *mode)
321{
322 struct drm_device *dev = encoder->dev;
323 struct drm_i915_private *dev_priv = dev->dev_private;
324 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
325 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
326 int pipe = intel_crtc->pipe;
327 unsigned int bpp = intel_crtc->config.pipe_bpp;
328 unsigned int lane_count = intel_dsi->lane_count;
329
330 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
331
332 hactive = mode->hdisplay;
333 hfp = mode->hsync_start - mode->hdisplay;
334 hsync = mode->hsync_end - mode->hsync_start;
335 hbp = mode->htotal - mode->hsync_end;
336
337 vfp = mode->vsync_start - mode->vdisplay;
338 vsync = mode->vsync_end - mode->vsync_start;
339 vbp = mode->vtotal - mode->vsync_end;
340
341 /* horizontal values are in terms of high speed byte clock */
342 hactive = txbyteclkhs(hactive, bpp, lane_count);
343 hfp = txbyteclkhs(hfp, bpp, lane_count);
344 hsync = txbyteclkhs(hsync, bpp, lane_count);
345 hbp = txbyteclkhs(hbp, bpp, lane_count);
346
347 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive);
348 I915_WRITE(MIPI_HFP_COUNT(pipe), hfp);
349
350 /* meaningful for video mode non-burst sync pulse mode only, can be zero
351 * for non-burst sync events and burst modes */
352 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(pipe), hsync);
353 I915_WRITE(MIPI_HBP_COUNT(pipe), hbp);
354
355 /* vertical values are in terms of lines */
356 I915_WRITE(MIPI_VFP_COUNT(pipe), vfp);
357 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(pipe), vsync);
358 I915_WRITE(MIPI_VBP_COUNT(pipe), vbp);
359}
360
361static void intel_dsi_mode_set(struct intel_encoder *intel_encoder)
362{
363 struct drm_encoder *encoder = &intel_encoder->base;
364 struct drm_device *dev = encoder->dev;
365 struct drm_i915_private *dev_priv = dev->dev_private;
366 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
367 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
368 struct drm_display_mode *adjusted_mode =
369 &intel_crtc->config.adjusted_mode;
370 int pipe = intel_crtc->pipe;
371 unsigned int bpp = intel_crtc->config.pipe_bpp;
372 u32 val, tmp;
373
6f2bcceb 374 DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe));
4e646495 375
4ce8c9a7 376 /* XXX: Location of the call */
e9fe51c6 377 band_gap_reset(dev_priv);
4ce8c9a7 378
4e646495
JN		 379 /* escape clock divider, 20MHz, shared for A and C. device ready must be
380 * off when doing this! txclkesc? */
381 tmp = I915_READ(MIPI_CTRL(0));
382 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
383 I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1);
384
385 /* read request priority is per pipe */
386 tmp = I915_READ(MIPI_CTRL(pipe));
387 tmp &= ~READ_REQUEST_PRIORITY_MASK;
388 I915_WRITE(MIPI_CTRL(pipe), tmp | READ_REQUEST_PRIORITY_HIGH);
389
390 /* XXX: why here, why like this? handling in irq handler?! */
391 I915_WRITE(MIPI_INTR_STAT(pipe), 0xffffffff);
392 I915_WRITE(MIPI_INTR_EN(pipe), 0xffffffff);
393
394 I915_WRITE(MIPI_DPHY_PARAM(pipe),
395 0x3c << EXIT_ZERO_COUNT_SHIFT |
396 0x1f << TRAIL_COUNT_SHIFT |
397 0xc5 << CLK_ZERO_COUNT_SHIFT |
398 0x1f << PREPARE_COUNT_SHIFT);
399
400 I915_WRITE(MIPI_DPI_RESOLUTION(pipe),
401 adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
402 adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT);
403
404 set_dsi_timings(encoder, adjusted_mode);
405
406 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
407 if (is_cmd_mode(intel_dsi)) {
408 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
409 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
410 } else {
411 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
412
413 /* XXX: cross-check bpp vs. pixel format? */
414 val |= intel_dsi->pixel_format;
415 }
416 I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val);
417
418 /* timeouts for recovery. one frame IIUC. if counter expires, EOT and
419 * stop state. */
420
421 /*
422 * In burst mode, value greater than one DPI line Time in byte clock
423 * (txbyteclkhs) To timeout this timer 1+ of the above said value is
424 * recommended.
425 *
426 * In non-burst mode, Value greater than one DPI frame time in byte
427 * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
428 * is recommended.
429 *
430 * In DBI only mode, value greater than one DBI frame time in byte
431 * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
432 * is recommended.
433 */
434
435 if (is_vid_mode(intel_dsi) &&
436 intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
437 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
438 txbyteclkhs(adjusted_mode->htotal, bpp,
439 intel_dsi->lane_count) + 1);
440 } else {
441 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
442 txbyteclkhs(adjusted_mode->vtotal *
443 adjusted_mode->htotal,
444 bpp, intel_dsi->lane_count) + 1);
445 }
446 I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), 8309); /* max */
447 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), 0x14); /* max */
448 I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), 0xffff); /* max */
449
450 /* dphy stuff */
451
452 /* in terms of low power clock */
453 I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(ESCAPE_CLOCK_DIVIDER_1, 100));
454
455 /* recovery disables */
456 I915_WRITE(MIPI_EOT_DISABLE(pipe), intel_dsi->eot_disable);
457
458 /* in terms of txbyteclkhs. actual high to low switch +
459 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
460 *
461 * XXX: write MIPI_STOP_STATE_STALL?
462 */
463 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe), 0x46);
464
465 /* XXX: low power clock equivalence in terms of byte clock. the number
466 * of byte clocks occupied in one low power clock. based on txbyteclkhs
467 * and txclkesc. txclkesc time / txbyteclk time * (105 +
468 * MIPI_STOP_STATE_STALL) / 105.???
469 */
470 I915_WRITE(MIPI_LP_BYTECLK(pipe), 4);
471
472 /* the bw essential for transmitting 16 long packets containing 252
473 * bytes meant for dcs write memory command is programmed in this
474 * register in terms of byte clocks. based on dsi transfer rate and the
475 * number of lanes configured the time taken to transmit 16 long packets
476 * in a dsi stream varies. */
477 I915_WRITE(MIPI_DBI_BW_CTRL(pipe), 0x820);
478
479 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe),
480 0xa << LP_HS_SSW_CNT_SHIFT |
481 0x14 << HS_LP_PWR_SW_CNT_SHIFT);
482
483 if (is_vid_mode(intel_dsi))
484 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe),
485 intel_dsi->video_mode_format);
486}
487
488static enum drm_connector_status
489intel_dsi_detect(struct drm_connector *connector, bool force)
490{
491 struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
492 DRM_DEBUG_KMS("\n");
493 return intel_dsi->dev.dev_ops->detect(&intel_dsi->dev);
494}
495
496static int intel_dsi_get_modes(struct drm_connector *connector)
497{
498 struct intel_connector *intel_connector = to_intel_connector(connector);
499 struct drm_display_mode *mode;
500
501 DRM_DEBUG_KMS("\n");
502
503 if (!intel_connector->panel.fixed_mode) {
504 DRM_DEBUG_KMS("no fixed mode\n");
505 return 0;
506 }
507
508 mode = drm_mode_duplicate(connector->dev,
509 intel_connector->panel.fixed_mode);
510 if (!mode) {
511 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
512 return 0;
513 }
514
515 drm_mode_probed_add(connector, mode);
516 return 1;
517}
518
519static void intel_dsi_destroy(struct drm_connector *connector)
520{
521 struct intel_connector *intel_connector = to_intel_connector(connector);
522
523 DRM_DEBUG_KMS("\n");
524 intel_panel_fini(&intel_connector->panel);
4e646495
JN		 525 drm_connector_cleanup(connector);
526 kfree(connector);
527}
528
529static const struct drm_encoder_funcs intel_dsi_funcs = {
530 .destroy = intel_encoder_destroy,
531};
532
533static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
534 .get_modes = intel_dsi_get_modes,
535 .mode_valid = intel_dsi_mode_valid,
536 .best_encoder = intel_best_encoder,
537};
538
539static const struct drm_connector_funcs intel_dsi_connector_funcs = {
540 .dpms = intel_connector_dpms,
541 .detect = intel_dsi_detect,
542 .destroy = intel_dsi_destroy,
543 .fill_modes = drm_helper_probe_single_connector_modes,
544};
545
546bool intel_dsi_init(struct drm_device *dev)
547{
548 struct intel_dsi *intel_dsi;
549 struct intel_encoder *intel_encoder;
550 struct drm_encoder *encoder;
551 struct intel_connector *intel_connector;
552 struct drm_connector *connector;
553 struct drm_display_mode *fixed_mode = NULL;
554 const struct intel_dsi_device *dsi;
555 unsigned int i;
556
557 DRM_DEBUG_KMS("\n");
558
559 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
560 if (!intel_dsi)
561 return false;
562
563 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
564 if (!intel_connector) {
565 kfree(intel_dsi);
566 return false;
567 }
568
569 intel_encoder = &intel_dsi->base;
570 encoder = &intel_encoder->base;
571 intel_dsi->attached_connector = intel_connector;
572
573 connector = &intel_connector->base;
574
575 drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI);
576
577 /* XXX: very likely not all of these are needed */
578 intel_encoder->hot_plug = intel_dsi_hot_plug;
579 intel_encoder->compute_config = intel_dsi_compute_config;
580 intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable;
581 intel_encoder->pre_enable = intel_dsi_pre_enable;
582 intel_encoder->enable = intel_dsi_enable;
583 intel_encoder->mode_set = intel_dsi_mode_set;
584 intel_encoder->disable = intel_dsi_disable;
585 intel_encoder->post_disable = intel_dsi_post_disable;
586 intel_encoder->get_hw_state = intel_dsi_get_hw_state;
587 intel_encoder->get_config = intel_dsi_get_config;
588
589 intel_connector->get_hw_state = intel_connector_get_hw_state;
590
591 for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) {
592 dsi = &intel_dsi_devices[i];
593 intel_dsi->dev = *dsi;
594
595 if (dsi->dev_ops->init(&intel_dsi->dev))
596 break;
597 }
598
599 if (i == ARRAY_SIZE(intel_dsi_devices)) {
600 DRM_DEBUG_KMS("no device found\n");
601 goto err;
602 }
603
604 intel_encoder->type = INTEL_OUTPUT_DSI;
605 intel_encoder->crtc_mask = (1 << 0); /* XXX */
606
607 intel_encoder->cloneable = false;
608 drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
609 DRM_MODE_CONNECTOR_DSI);
610
611 drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
612
613 connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
614 connector->interlace_allowed = false;
615 connector->doublescan_allowed = false;
616
617 intel_connector_attach_encoder(intel_connector, intel_encoder);
618
619 drm_sysfs_connector_add(connector);
620
621 fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev);
622 if (!fixed_mode) {
623 DRM_DEBUG_KMS("no fixed mode\n");
624 goto err;
625 }
626
627 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
628 intel_panel_init(&intel_connector->panel, fixed_mode);
629
630 return true;
631
632err:
633 drm_encoder_cleanup(&intel_encoder->base);
634 kfree(intel_dsi);
635 kfree(intel_connector);
636
637 return false;
638}
Linux kernel - Deliverables
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