Commit | Line | Data |
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4e646495 JN |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Author: Jani Nikula <jani.nikula@intel.com> | |
24 | */ | |
25 | ||
26 | #include <drm/drmP.h> | |
c6f95f27 | 27 | #include <drm/drm_atomic_helper.h> |
4e646495 JN |
28 | #include <drm/drm_crtc.h> |
29 | #include <drm/drm_edid.h> | |
30 | #include <drm/i915_drm.h> | |
593e0622 | 31 | #include <drm/drm_panel.h> |
7e9804fd | 32 | #include <drm/drm_mipi_dsi.h> |
4e646495 | 33 | #include <linux/slab.h> |
fc45e821 | 34 | #include <linux/gpio/consumer.h> |
4e646495 JN |
35 | #include "i915_drv.h" |
36 | #include "intel_drv.h" | |
37 | #include "intel_dsi.h" | |
4e646495 | 38 | |
593e0622 JN |
39 | static const struct { |
40 | u16 panel_id; | |
41 | struct drm_panel * (*init)(struct intel_dsi *intel_dsi, u16 panel_id); | |
42 | } intel_dsi_drivers[] = { | |
2ab8b458 SK |
43 | { |
44 | .panel_id = MIPI_DSI_GENERIC_PANEL_ID, | |
593e0622 | 45 | .init = vbt_panel_init, |
2ab8b458 | 46 | }, |
4e646495 JN |
47 | }; |
48 | ||
43367ec9 R |
49 | enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) |
50 | { | |
51 | /* It just so happens the VBT matches register contents. */ | |
52 | switch (fmt) { | |
53 | case VID_MODE_FORMAT_RGB888: | |
54 | return MIPI_DSI_FMT_RGB888; | |
55 | case VID_MODE_FORMAT_RGB666: | |
56 | return MIPI_DSI_FMT_RGB666; | |
57 | case VID_MODE_FORMAT_RGB666_PACKED: | |
58 | return MIPI_DSI_FMT_RGB666_PACKED; | |
59 | case VID_MODE_FORMAT_RGB565: | |
60 | return MIPI_DSI_FMT_RGB565; | |
61 | default: | |
62 | MISSING_CASE(fmt); | |
63 | return MIPI_DSI_FMT_RGB666; | |
64 | } | |
65 | } | |
66 | ||
7f6a6a4a | 67 | static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port) |
3b1808bf JN |
68 | { |
69 | struct drm_encoder *encoder = &intel_dsi->base.base; | |
70 | struct drm_device *dev = encoder->dev; | |
71 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3b1808bf JN |
72 | u32 mask; |
73 | ||
74 | mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | | |
75 | LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; | |
76 | ||
77 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100)) | |
78 | DRM_ERROR("DPI FIFOs are not empty\n"); | |
79 | } | |
80 | ||
f0f59a00 VS |
81 | static void write_data(struct drm_i915_private *dev_priv, |
82 | i915_reg_t reg, | |
7e9804fd JN |
83 | const u8 *data, u32 len) |
84 | { | |
85 | u32 i, j; | |
86 | ||
87 | for (i = 0; i < len; i += 4) { | |
88 | u32 val = 0; | |
89 | ||
90 | for (j = 0; j < min_t(u32, len - i, 4); j++) | |
91 | val |= *data++ << 8 * j; | |
92 | ||
93 | I915_WRITE(reg, val); | |
94 | } | |
95 | } | |
96 | ||
f0f59a00 VS |
97 | static void read_data(struct drm_i915_private *dev_priv, |
98 | i915_reg_t reg, | |
7e9804fd JN |
99 | u8 *data, u32 len) |
100 | { | |
101 | u32 i, j; | |
102 | ||
103 | for (i = 0; i < len; i += 4) { | |
104 | u32 val = I915_READ(reg); | |
105 | ||
106 | for (j = 0; j < min_t(u32, len - i, 4); j++) | |
107 | *data++ = val >> 8 * j; | |
108 | } | |
109 | } | |
110 | ||
111 | static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, | |
112 | const struct mipi_dsi_msg *msg) | |
113 | { | |
114 | struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); | |
115 | struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev; | |
116 | struct drm_i915_private *dev_priv = dev->dev_private; | |
117 | enum port port = intel_dsi_host->port; | |
118 | struct mipi_dsi_packet packet; | |
119 | ssize_t ret; | |
120 | const u8 *header, *data; | |
f0f59a00 VS |
121 | i915_reg_t data_reg, ctrl_reg; |
122 | u32 data_mask, ctrl_mask; | |
7e9804fd JN |
123 | |
124 | ret = mipi_dsi_create_packet(&packet, msg); | |
125 | if (ret < 0) | |
126 | return ret; | |
127 | ||
128 | header = packet.header; | |
129 | data = packet.payload; | |
130 | ||
131 | if (msg->flags & MIPI_DSI_MSG_USE_LPM) { | |
132 | data_reg = MIPI_LP_GEN_DATA(port); | |
133 | data_mask = LP_DATA_FIFO_FULL; | |
134 | ctrl_reg = MIPI_LP_GEN_CTRL(port); | |
135 | ctrl_mask = LP_CTRL_FIFO_FULL; | |
136 | } else { | |
137 | data_reg = MIPI_HS_GEN_DATA(port); | |
138 | data_mask = HS_DATA_FIFO_FULL; | |
139 | ctrl_reg = MIPI_HS_GEN_CTRL(port); | |
140 | ctrl_mask = HS_CTRL_FIFO_FULL; | |
141 | } | |
142 | ||
143 | /* note: this is never true for reads */ | |
144 | if (packet.payload_length) { | |
145 | ||
146 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & data_mask) == 0, 50)) | |
147 | DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n"); | |
148 | ||
149 | write_data(dev_priv, data_reg, packet.payload, | |
150 | packet.payload_length); | |
151 | } | |
152 | ||
153 | if (msg->rx_len) { | |
154 | I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); | |
155 | } | |
156 | ||
157 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & ctrl_mask) == 0, 50)) { | |
158 | DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n"); | |
159 | } | |
160 | ||
161 | I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]); | |
162 | ||
163 | /* ->rx_len is set only for reads */ | |
164 | if (msg->rx_len) { | |
165 | data_mask = GEN_READ_DATA_AVAIL; | |
166 | if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & data_mask) == data_mask, 50)) | |
167 | DRM_ERROR("Timeout waiting for read data.\n"); | |
168 | ||
169 | read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); | |
170 | } | |
171 | ||
172 | /* XXX: fix for reads and writes */ | |
173 | return 4 + packet.payload_length; | |
174 | } | |
175 | ||
176 | static int intel_dsi_host_attach(struct mipi_dsi_host *host, | |
177 | struct mipi_dsi_device *dsi) | |
178 | { | |
179 | return 0; | |
180 | } | |
181 | ||
182 | static int intel_dsi_host_detach(struct mipi_dsi_host *host, | |
183 | struct mipi_dsi_device *dsi) | |
184 | { | |
185 | return 0; | |
186 | } | |
187 | ||
188 | static const struct mipi_dsi_host_ops intel_dsi_host_ops = { | |
189 | .attach = intel_dsi_host_attach, | |
190 | .detach = intel_dsi_host_detach, | |
191 | .transfer = intel_dsi_host_transfer, | |
192 | }; | |
193 | ||
194 | static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi, | |
195 | enum port port) | |
196 | { | |
197 | struct intel_dsi_host *host; | |
198 | struct mipi_dsi_device *device; | |
199 | ||
200 | host = kzalloc(sizeof(*host), GFP_KERNEL); | |
201 | if (!host) | |
202 | return NULL; | |
203 | ||
204 | host->base.ops = &intel_dsi_host_ops; | |
205 | host->intel_dsi = intel_dsi; | |
206 | host->port = port; | |
207 | ||
208 | /* | |
209 | * We should call mipi_dsi_host_register(&host->base) here, but we don't | |
210 | * have a host->dev, and we don't have OF stuff either. So just use the | |
211 | * dsi framework as a library and hope for the best. Create the dsi | |
212 | * devices by ourselves here too. Need to be careful though, because we | |
213 | * don't initialize any of the driver model devices here. | |
214 | */ | |
215 | device = kzalloc(sizeof(*device), GFP_KERNEL); | |
216 | if (!device) { | |
217 | kfree(host); | |
218 | return NULL; | |
219 | } | |
220 | ||
221 | device->host = &host->base; | |
222 | host->device = device; | |
223 | ||
224 | return host; | |
225 | } | |
226 | ||
a2581a9e JN |
227 | /* |
228 | * send a video mode command | |
229 | * | |
230 | * XXX: commands with data in MIPI_DPI_DATA? | |
231 | */ | |
232 | static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, | |
233 | enum port port) | |
234 | { | |
235 | struct drm_encoder *encoder = &intel_dsi->base.base; | |
236 | struct drm_device *dev = encoder->dev; | |
237 | struct drm_i915_private *dev_priv = dev->dev_private; | |
238 | u32 mask; | |
239 | ||
240 | /* XXX: pipe, hs */ | |
241 | if (hs) | |
242 | cmd &= ~DPI_LP_MODE; | |
243 | else | |
244 | cmd |= DPI_LP_MODE; | |
245 | ||
246 | /* clear bit */ | |
247 | I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); | |
248 | ||
249 | /* XXX: old code skips write if control unchanged */ | |
250 | if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) | |
251 | DRM_ERROR("Same special packet %02x twice in a row.\n", cmd); | |
252 | ||
253 | I915_WRITE(MIPI_DPI_CONTROL(port), cmd); | |
254 | ||
255 | mask = SPL_PKT_SENT_INTERRUPT; | |
256 | if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100)) | |
257 | DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd); | |
258 | ||
259 | return 0; | |
260 | } | |
261 | ||
e9fe51c6 | 262 | static void band_gap_reset(struct drm_i915_private *dev_priv) |
4ce8c9a7 | 263 | { |
a580516d | 264 | mutex_lock(&dev_priv->sb_lock); |
4ce8c9a7 | 265 | |
e9fe51c6 SK |
266 | vlv_flisdsi_write(dev_priv, 0x08, 0x0001); |
267 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); | |
268 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); | |
269 | udelay(150); | |
270 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); | |
271 | vlv_flisdsi_write(dev_priv, 0x08, 0x0000); | |
4ce8c9a7 | 272 | |
a580516d | 273 | mutex_unlock(&dev_priv->sb_lock); |
4ce8c9a7 SK |
274 | } |
275 | ||
4e646495 JN |
276 | static inline bool is_vid_mode(struct intel_dsi *intel_dsi) |
277 | { | |
dfba2e2d | 278 | return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE; |
4e646495 JN |
279 | } |
280 | ||
281 | static inline bool is_cmd_mode(struct intel_dsi *intel_dsi) | |
282 | { | |
dfba2e2d | 283 | return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE; |
4e646495 JN |
284 | } |
285 | ||
4e646495 | 286 | static bool intel_dsi_compute_config(struct intel_encoder *encoder, |
a65347ba | 287 | struct intel_crtc_state *pipe_config) |
4e646495 | 288 | { |
4d1de975 | 289 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
4e646495 JN |
290 | struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, |
291 | base); | |
292 | struct intel_connector *intel_connector = intel_dsi->attached_connector; | |
f4ee265f VS |
293 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
294 | const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
a65347ba | 295 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
47eacbab | 296 | int ret; |
4e646495 JN |
297 | |
298 | DRM_DEBUG_KMS("\n"); | |
299 | ||
a65347ba JN |
300 | pipe_config->has_dsi_encoder = true; |
301 | ||
f4ee265f | 302 | if (fixed_mode) { |
4e646495 JN |
303 | intel_fixed_panel_mode(fixed_mode, adjusted_mode); |
304 | ||
f4ee265f VS |
305 | if (HAS_GMCH_DISPLAY(dev_priv)) |
306 | intel_gmch_panel_fitting(crtc, pipe_config, | |
307 | intel_connector->panel.fitting_mode); | |
308 | else | |
309 | intel_pch_panel_fitting(crtc, pipe_config, | |
310 | intel_connector->panel.fitting_mode); | |
311 | } | |
312 | ||
f573de5a SK |
313 | /* DSI uses short packets for sync events, so clear mode flags for DSI */ |
314 | adjusted_mode->flags = 0; | |
315 | ||
4d1de975 JN |
316 | if (IS_BROXTON(dev_priv)) { |
317 | /* Dual link goes to DSI transcoder A. */ | |
318 | if (intel_dsi->ports == BIT(PORT_C)) | |
319 | pipe_config->cpu_transcoder = TRANSCODER_DSI_C; | |
320 | else | |
321 | pipe_config->cpu_transcoder = TRANSCODER_DSI_A; | |
322 | } | |
323 | ||
47eacbab VS |
324 | ret = intel_compute_dsi_pll(encoder, pipe_config); |
325 | if (ret) | |
326 | return false; | |
327 | ||
cd2d34d9 VS |
328 | pipe_config->clock_set = true; |
329 | ||
4e646495 JN |
330 | return true; |
331 | } | |
332 | ||
37ab0810 | 333 | static void bxt_dsi_device_ready(struct intel_encoder *encoder) |
5505a244 | 334 | { |
37ab0810 | 335 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
5505a244 | 336 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
369602d3 | 337 | enum port port; |
37ab0810 | 338 | u32 val; |
5505a244 | 339 | |
37ab0810 | 340 | DRM_DEBUG_KMS("\n"); |
a9da9bce | 341 | |
37ab0810 | 342 | /* Exit Low power state in 4 steps*/ |
369602d3 | 343 | for_each_dsi_port(port, intel_dsi->ports) { |
5505a244 | 344 | |
37ab0810 SS |
345 | /* 1. Enable MIPI PHY transparent latch */ |
346 | val = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
347 | I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD); | |
348 | usleep_range(2000, 2500); | |
349 | ||
350 | /* 2. Enter ULPS */ | |
351 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
352 | val &= ~ULPS_STATE_MASK; | |
353 | val |= (ULPS_STATE_ENTER | DEVICE_READY); | |
354 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
355 | usleep_range(2, 3); | |
356 | ||
357 | /* 3. Exit ULPS */ | |
358 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
359 | val &= ~ULPS_STATE_MASK; | |
360 | val |= (ULPS_STATE_EXIT | DEVICE_READY); | |
361 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
362 | usleep_range(1000, 1500); | |
5505a244 | 363 | |
37ab0810 SS |
364 | /* Clear ULPS and set device ready */ |
365 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
366 | val &= ~ULPS_STATE_MASK; | |
367 | val |= DEVICE_READY; | |
368 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
369602d3 | 369 | } |
5505a244 GS |
370 | } |
371 | ||
37ab0810 | 372 | static void vlv_dsi_device_ready(struct intel_encoder *encoder) |
4e646495 | 373 | { |
1dbd7cb2 | 374 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
24ee0e64 GS |
375 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
376 | enum port port; | |
1dbd7cb2 SK |
377 | u32 val; |
378 | ||
4e646495 | 379 | DRM_DEBUG_KMS("\n"); |
4e646495 | 380 | |
a580516d | 381 | mutex_lock(&dev_priv->sb_lock); |
2095f9fc SK |
382 | /* program rcomp for compliance, reduce from 50 ohms to 45 ohms |
383 | * needed everytime after power gate */ | |
384 | vlv_flisdsi_write(dev_priv, 0x04, 0x0004); | |
a580516d | 385 | mutex_unlock(&dev_priv->sb_lock); |
2095f9fc SK |
386 | |
387 | /* bandgap reset is needed after everytime we do power gate */ | |
388 | band_gap_reset(dev_priv); | |
389 | ||
24ee0e64 | 390 | for_each_dsi_port(port, intel_dsi->ports) { |
aceb365c | 391 | |
24ee0e64 GS |
392 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); |
393 | usleep_range(2500, 3000); | |
aceb365c | 394 | |
bf344e80 GS |
395 | /* Enable MIPI PHY transparent latch |
396 | * Common bit for both MIPI Port A & MIPI Port C | |
397 | * No similar bit in MIPI Port C reg | |
398 | */ | |
4ba7d93a | 399 | val = I915_READ(MIPI_PORT_CTRL(PORT_A)); |
bf344e80 | 400 | I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD); |
24ee0e64 | 401 | usleep_range(1000, 1500); |
aceb365c | 402 | |
24ee0e64 GS |
403 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); |
404 | usleep_range(2500, 3000); | |
405 | ||
406 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); | |
407 | usleep_range(2500, 3000); | |
408 | } | |
1dbd7cb2 | 409 | } |
1dbd7cb2 | 410 | |
37ab0810 SS |
411 | static void intel_dsi_device_ready(struct intel_encoder *encoder) |
412 | { | |
413 | struct drm_device *dev = encoder->base.dev; | |
414 | ||
666a4537 | 415 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
37ab0810 SS |
416 | vlv_dsi_device_ready(encoder); |
417 | else if (IS_BROXTON(dev)) | |
418 | bxt_dsi_device_ready(encoder); | |
419 | } | |
420 | ||
421 | static void intel_dsi_port_enable(struct intel_encoder *encoder) | |
422 | { | |
423 | struct drm_device *dev = encoder->base.dev; | |
424 | struct drm_i915_private *dev_priv = dev->dev_private; | |
425 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
426 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
427 | enum port port; | |
37ab0810 SS |
428 | |
429 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { | |
f0f59a00 VS |
430 | u32 temp; |
431 | ||
37ab0810 SS |
432 | temp = I915_READ(VLV_CHICKEN_3); |
433 | temp &= ~PIXEL_OVERLAP_CNT_MASK | | |
434 | intel_dsi->pixel_overlap << | |
435 | PIXEL_OVERLAP_CNT_SHIFT; | |
436 | I915_WRITE(VLV_CHICKEN_3, temp); | |
437 | } | |
438 | ||
439 | for_each_dsi_port(port, intel_dsi->ports) { | |
f0f59a00 VS |
440 | i915_reg_t port_ctrl = IS_BROXTON(dev) ? |
441 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); | |
442 | u32 temp; | |
37ab0810 SS |
443 | |
444 | temp = I915_READ(port_ctrl); | |
445 | ||
446 | temp &= ~LANE_CONFIGURATION_MASK; | |
447 | temp &= ~DUAL_LINK_MODE_MASK; | |
448 | ||
701d25b4 | 449 | if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { |
37ab0810 SS |
450 | temp |= (intel_dsi->dual_link - 1) |
451 | << DUAL_LINK_MODE_SHIFT; | |
452 | temp |= intel_crtc->pipe ? | |
453 | LANE_CONFIGURATION_DUAL_LINK_B : | |
454 | LANE_CONFIGURATION_DUAL_LINK_A; | |
455 | } | |
456 | /* assert ip_tg_enable signal */ | |
457 | I915_WRITE(port_ctrl, temp | DPI_ENABLE); | |
458 | POSTING_READ(port_ctrl); | |
459 | } | |
460 | } | |
461 | ||
462 | static void intel_dsi_port_disable(struct intel_encoder *encoder) | |
463 | { | |
464 | struct drm_device *dev = encoder->base.dev; | |
465 | struct drm_i915_private *dev_priv = dev->dev_private; | |
466 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
467 | enum port port; | |
37ab0810 SS |
468 | |
469 | for_each_dsi_port(port, intel_dsi->ports) { | |
f0f59a00 VS |
470 | i915_reg_t port_ctrl = IS_BROXTON(dev) ? |
471 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); | |
472 | u32 temp; | |
473 | ||
37ab0810 | 474 | /* de-assert ip_tg_enable signal */ |
b389a45c SS |
475 | temp = I915_READ(port_ctrl); |
476 | I915_WRITE(port_ctrl, temp & ~DPI_ENABLE); | |
477 | POSTING_READ(port_ctrl); | |
37ab0810 SS |
478 | } |
479 | } | |
480 | ||
1dbd7cb2 SK |
481 | static void intel_dsi_enable(struct intel_encoder *encoder) |
482 | { | |
483 | struct drm_device *dev = encoder->base.dev; | |
484 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1dbd7cb2 | 485 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
4934b656 | 486 | enum port port; |
1dbd7cb2 SK |
487 | |
488 | DRM_DEBUG_KMS("\n"); | |
b9f5e07d | 489 | |
4934b656 JN |
490 | if (is_cmd_mode(intel_dsi)) { |
491 | for_each_dsi_port(port, intel_dsi->ports) | |
492 | I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); | |
493 | } else { | |
4e646495 | 494 | msleep(20); /* XXX */ |
f03e4179 | 495 | for_each_dsi_port(port, intel_dsi->ports) |
a2581a9e | 496 | dpi_send_cmd(intel_dsi, TURN_ON, false, port); |
4e646495 JN |
497 | msleep(100); |
498 | ||
593e0622 | 499 | drm_panel_enable(intel_dsi->panel); |
2634fd7f | 500 | |
7f6a6a4a JN |
501 | for_each_dsi_port(port, intel_dsi->ports) |
502 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
1381308b | 503 | |
5505a244 | 504 | intel_dsi_port_enable(encoder); |
4e646495 | 505 | } |
b029e66f SK |
506 | |
507 | intel_panel_enable_backlight(intel_dsi->attached_connector); | |
2634fd7f SK |
508 | } |
509 | ||
e3488e75 JN |
510 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder); |
511 | ||
2634fd7f SK |
512 | static void intel_dsi_pre_enable(struct intel_encoder *encoder) |
513 | { | |
20e5bf66 SK |
514 | struct drm_device *dev = encoder->base.dev; |
515 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2634fd7f | 516 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
47eacbab | 517 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
7f6a6a4a | 518 | enum port port; |
20e5bf66 | 519 | u32 tmp; |
2634fd7f SK |
520 | |
521 | DRM_DEBUG_KMS("\n"); | |
522 | ||
f00b5689 VS |
523 | /* |
524 | * The BIOS may leave the PLL in a wonky state where it doesn't | |
525 | * lock. It needs to be fully powered down to fix it. | |
526 | */ | |
527 | intel_disable_dsi_pll(encoder); | |
47eacbab | 528 | intel_enable_dsi_pll(encoder, crtc->config); |
f00b5689 | 529 | |
58d4d32f | 530 | intel_dsi_prepare(encoder); |
e3488e75 | 531 | |
fc45e821 SK |
532 | /* Panel Enable over CRC PMIC */ |
533 | if (intel_dsi->gpio_panel) | |
534 | gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); | |
535 | ||
536 | msleep(intel_dsi->panel_on_delay); | |
537 | ||
666a4537 | 538 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
cd2d34d9 | 539 | /* Disable DPOunit clock gating, can stall pipe */ |
37ab0810 SS |
540 | tmp = I915_READ(DSPCLK_GATE_D); |
541 | tmp |= DPOUNIT_CLOCK_GATE_DISABLE; | |
542 | I915_WRITE(DSPCLK_GATE_D, tmp); | |
543 | } | |
2634fd7f SK |
544 | |
545 | /* put device in ready state */ | |
546 | intel_dsi_device_ready(encoder); | |
4e646495 | 547 | |
593e0622 | 548 | drm_panel_prepare(intel_dsi->panel); |
20e5bf66 | 549 | |
7f6a6a4a JN |
550 | for_each_dsi_port(port, intel_dsi->ports) |
551 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
1381308b | 552 | |
2634fd7f SK |
553 | /* Enable port in pre-enable phase itself because as per hw team |
554 | * recommendation, port should be enabled befor plane & pipe */ | |
555 | intel_dsi_enable(encoder); | |
556 | } | |
557 | ||
558 | static void intel_dsi_enable_nop(struct intel_encoder *encoder) | |
559 | { | |
560 | DRM_DEBUG_KMS("\n"); | |
561 | ||
562 | /* for DSI port enable has to be done before pipe | |
563 | * and plane enable, so port enable is done in | |
564 | * pre_enable phase itself unlike other encoders | |
565 | */ | |
4e646495 JN |
566 | } |
567 | ||
c315faf8 ID |
568 | static void intel_dsi_pre_disable(struct intel_encoder *encoder) |
569 | { | |
570 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
f03e4179 | 571 | enum port port; |
c315faf8 ID |
572 | |
573 | DRM_DEBUG_KMS("\n"); | |
574 | ||
b029e66f SK |
575 | intel_panel_disable_backlight(intel_dsi->attached_connector); |
576 | ||
c315faf8 ID |
577 | if (is_vid_mode(intel_dsi)) { |
578 | /* Send Shutdown command to the panel in LP mode */ | |
f03e4179 | 579 | for_each_dsi_port(port, intel_dsi->ports) |
a2581a9e | 580 | dpi_send_cmd(intel_dsi, SHUTDOWN, false, port); |
c315faf8 ID |
581 | msleep(10); |
582 | } | |
583 | } | |
584 | ||
4e646495 JN |
585 | static void intel_dsi_disable(struct intel_encoder *encoder) |
586 | { | |
1dbd7cb2 SK |
587 | struct drm_device *dev = encoder->base.dev; |
588 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4e646495 | 589 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
384f02a2 | 590 | enum port port; |
4e646495 JN |
591 | u32 temp; |
592 | ||
593 | DRM_DEBUG_KMS("\n"); | |
594 | ||
4e646495 | 595 | if (is_vid_mode(intel_dsi)) { |
7f6a6a4a JN |
596 | for_each_dsi_port(port, intel_dsi->ports) |
597 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
1381308b | 598 | |
5505a244 | 599 | intel_dsi_port_disable(encoder); |
4e646495 JN |
600 | msleep(2); |
601 | } | |
602 | ||
384f02a2 GS |
603 | for_each_dsi_port(port, intel_dsi->ports) { |
604 | /* Panel commands can be sent when clock is in LP11 */ | |
605 | I915_WRITE(MIPI_DEVICE_READY(port), 0x0); | |
339023ec | 606 | |
b389a45c | 607 | intel_dsi_reset_clocks(encoder, port); |
384f02a2 | 608 | I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); |
339023ec | 609 | |
384f02a2 GS |
610 | temp = I915_READ(MIPI_DSI_FUNC_PRG(port)); |
611 | temp &= ~VID_MODE_FORMAT_MASK; | |
612 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp); | |
339023ec | 613 | |
384f02a2 GS |
614 | I915_WRITE(MIPI_DEVICE_READY(port), 0x1); |
615 | } | |
1dbd7cb2 SK |
616 | /* if disable packets are sent before sending shutdown packet then in |
617 | * some next enable sequence send turn on packet error is observed */ | |
593e0622 | 618 | drm_panel_disable(intel_dsi->panel); |
1381308b | 619 | |
7f6a6a4a JN |
620 | for_each_dsi_port(port, intel_dsi->ports) |
621 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
4e646495 JN |
622 | } |
623 | ||
1dbd7cb2 | 624 | static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) |
4e646495 | 625 | { |
b389a45c | 626 | struct drm_device *dev = encoder->base.dev; |
1dbd7cb2 | 627 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
384f02a2 GS |
628 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
629 | enum port port; | |
1dbd7cb2 | 630 | |
4e646495 | 631 | DRM_DEBUG_KMS("\n"); |
384f02a2 | 632 | for_each_dsi_port(port, intel_dsi->ports) { |
f0f59a00 VS |
633 | /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ |
634 | i915_reg_t port_ctrl = IS_BROXTON(dev) ? | |
635 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A); | |
636 | u32 val; | |
be4fc046 | 637 | |
384f02a2 GS |
638 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | |
639 | ULPS_STATE_ENTER); | |
640 | usleep_range(2000, 2500); | |
641 | ||
642 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | | |
643 | ULPS_STATE_EXIT); | |
644 | usleep_range(2000, 2500); | |
645 | ||
646 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | | |
647 | ULPS_STATE_ENTER); | |
648 | usleep_range(2000, 2500); | |
649 | ||
650 | /* Wait till Clock lanes are in LP-00 state for MIPI Port A | |
651 | * only. MIPI Port C has no similar bit for checking | |
652 | */ | |
b389a45c SS |
653 | if (wait_for(((I915_READ(port_ctrl) & AFE_LATCHOUT) |
654 | == 0x00000), 30)) | |
384f02a2 GS |
655 | DRM_ERROR("DSI LP not going Low\n"); |
656 | ||
b389a45c SS |
657 | /* Disable MIPI PHY transparent latch */ |
658 | val = I915_READ(port_ctrl); | |
659 | I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD); | |
384f02a2 GS |
660 | usleep_range(1000, 1500); |
661 | ||
662 | I915_WRITE(MIPI_DEVICE_READY(port), 0x00); | |
663 | usleep_range(2000, 2500); | |
664 | } | |
1dbd7cb2 | 665 | |
fe88fc68 | 666 | intel_disable_dsi_pll(encoder); |
4e646495 | 667 | } |
20e5bf66 | 668 | |
1dbd7cb2 SK |
669 | static void intel_dsi_post_disable(struct intel_encoder *encoder) |
670 | { | |
20e5bf66 | 671 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
1dbd7cb2 SK |
672 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
673 | ||
674 | DRM_DEBUG_KMS("\n"); | |
675 | ||
c315faf8 ID |
676 | intel_dsi_disable(encoder); |
677 | ||
1dbd7cb2 SK |
678 | intel_dsi_clear_device_ready(encoder); |
679 | ||
d6e3af54 US |
680 | if (!IS_BROXTON(dev_priv)) { |
681 | u32 val; | |
682 | ||
683 | val = I915_READ(DSPCLK_GATE_D); | |
684 | val &= ~DPOUNIT_CLOCK_GATE_DISABLE; | |
685 | I915_WRITE(DSPCLK_GATE_D, val); | |
686 | } | |
20e5bf66 | 687 | |
593e0622 | 688 | drm_panel_unprepare(intel_dsi->panel); |
df38e655 SK |
689 | |
690 | msleep(intel_dsi->panel_off_delay); | |
691 | msleep(intel_dsi->panel_pwr_cycle_delay); | |
fc45e821 SK |
692 | |
693 | /* Panel Disable over CRC PMIC */ | |
694 | if (intel_dsi->gpio_panel) | |
695 | gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0); | |
1dbd7cb2 | 696 | } |
4e646495 JN |
697 | |
698 | static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, | |
699 | enum pipe *pipe) | |
700 | { | |
701 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
c0beefd2 GS |
702 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
703 | struct drm_device *dev = encoder->base.dev; | |
6d129bea | 704 | enum intel_display_power_domain power_domain; |
e7d7cad0 | 705 | enum port port; |
1dcec2f3 | 706 | bool active = false; |
4e646495 JN |
707 | |
708 | DRM_DEBUG_KMS("\n"); | |
709 | ||
6d129bea | 710 | power_domain = intel_display_port_power_domain(encoder); |
3f3f42b8 | 711 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
6d129bea ID |
712 | return false; |
713 | ||
db18b6a6 ID |
714 | /* |
715 | * On Broxton the PLL needs to be enabled with a valid divider | |
716 | * configuration, otherwise accessing DSI registers will hang the | |
717 | * machine. See BSpec North Display Engine registers/MIPI[BXT]. | |
718 | */ | |
719 | if (IS_BROXTON(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv)) | |
720 | goto out_put_power; | |
721 | ||
4e646495 | 722 | /* XXX: this only works for one DSI output */ |
c0beefd2 | 723 | for_each_dsi_port(port, intel_dsi->ports) { |
f0f59a00 VS |
724 | i915_reg_t ctrl_reg = IS_BROXTON(dev) ? |
725 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); | |
1dcec2f3 | 726 | bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE; |
c0beefd2 GS |
727 | |
728 | /* Due to some hardware limitations on BYT, MIPI Port C DPI | |
729 | * Enable bit does not get set. To check whether DSI Port C | |
730 | * was enabled in BIOS, check the Pipe B enable bit | |
731 | */ | |
666a4537 | 732 | if (IS_VALLEYVIEW(dev) && port == PORT_C) |
1dcec2f3 | 733 | enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; |
4e646495 | 734 | |
1dcec2f3 JN |
735 | /* Try command mode if video mode not enabled */ |
736 | if (!enabled) { | |
737 | u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port)); | |
738 | enabled = tmp & CMD_MODE_DATA_WIDTH_MASK; | |
4e646495 | 739 | } |
1dcec2f3 JN |
740 | |
741 | if (!enabled) | |
742 | continue; | |
743 | ||
744 | if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) | |
745 | continue; | |
746 | ||
6b93e9c8 JN |
747 | if (IS_BROXTON(dev_priv)) { |
748 | u32 tmp = I915_READ(MIPI_CTRL(port)); | |
749 | tmp &= BXT_PIPE_SELECT_MASK; | |
750 | tmp >>= BXT_PIPE_SELECT_SHIFT; | |
751 | ||
752 | if (WARN_ON(tmp > PIPE_C)) | |
753 | continue; | |
754 | ||
755 | *pipe = tmp; | |
756 | } else { | |
757 | *pipe = port == PORT_A ? PIPE_A : PIPE_B; | |
758 | } | |
759 | ||
1dcec2f3 JN |
760 | active = true; |
761 | break; | |
4e646495 | 762 | } |
1dcec2f3 | 763 | |
db18b6a6 | 764 | out_put_power: |
3f3f42b8 | 765 | intel_display_power_put(dev_priv, power_domain); |
4e646495 | 766 | |
1dcec2f3 | 767 | return active; |
4e646495 JN |
768 | } |
769 | ||
6f0e7535 R |
770 | static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, |
771 | struct intel_crtc_state *pipe_config) | |
772 | { | |
773 | struct drm_device *dev = encoder->base.dev; | |
774 | struct drm_i915_private *dev_priv = dev->dev_private; | |
775 | struct drm_display_mode *adjusted_mode = | |
776 | &pipe_config->base.adjusted_mode; | |
777 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
778 | unsigned int bpp, fmt; | |
779 | enum port port; | |
780 | u16 vfp, vsync, vbp; | |
781 | ||
782 | /* | |
783 | * Atleast one port is active as encoder->get_config called only if | |
784 | * encoder->get_hw_state() returns true. | |
785 | */ | |
786 | for_each_dsi_port(port, intel_dsi->ports) { | |
787 | if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) | |
788 | break; | |
789 | } | |
790 | ||
791 | fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; | |
792 | pipe_config->pipe_bpp = | |
793 | mipi_dsi_pixel_format_to_bpp( | |
794 | pixel_format_from_register_bits(fmt)); | |
795 | bpp = pipe_config->pipe_bpp; | |
796 | ||
797 | /* In terms of pixels */ | |
798 | adjusted_mode->crtc_hdisplay = | |
799 | I915_READ(BXT_MIPI_TRANS_HACTIVE(port)); | |
800 | adjusted_mode->crtc_vdisplay = | |
801 | I915_READ(BXT_MIPI_TRANS_VACTIVE(port)); | |
802 | adjusted_mode->crtc_vtotal = | |
803 | I915_READ(BXT_MIPI_TRANS_VTOTAL(port)); | |
804 | ||
805 | /* | |
806 | * TODO: Retrieve hfp, hsync and hbp. Adjust them for dual link and | |
807 | * calculate hsync_start, hsync_end, htotal and hblank_end | |
808 | */ | |
809 | ||
810 | /* vertical values are in terms of lines */ | |
811 | vfp = I915_READ(MIPI_VFP_COUNT(port)); | |
812 | vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port)); | |
813 | vbp = I915_READ(MIPI_VBP_COUNT(port)); | |
814 | ||
815 | adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; | |
816 | ||
817 | adjusted_mode->crtc_vsync_start = | |
818 | vfp + adjusted_mode->crtc_vdisplay; | |
819 | adjusted_mode->crtc_vsync_end = | |
820 | vsync + adjusted_mode->crtc_vsync_start; | |
821 | adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; | |
822 | adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; | |
823 | } | |
824 | ||
825 | ||
4e646495 | 826 | static void intel_dsi_get_config(struct intel_encoder *encoder, |
5cec258b | 827 | struct intel_crtc_state *pipe_config) |
4e646495 | 828 | { |
6f0e7535 | 829 | struct drm_device *dev = encoder->base.dev; |
d7d85d85 | 830 | u32 pclk; |
4e646495 JN |
831 | DRM_DEBUG_KMS("\n"); |
832 | ||
a65347ba JN |
833 | pipe_config->has_dsi_encoder = true; |
834 | ||
6f0e7535 R |
835 | if (IS_BROXTON(dev)) |
836 | bxt_dsi_get_pipe_config(encoder, pipe_config); | |
837 | ||
47eacbab VS |
838 | pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp, |
839 | pipe_config); | |
f573de5a SK |
840 | if (!pclk) |
841 | return; | |
842 | ||
2d112de7 | 843 | pipe_config->base.adjusted_mode.crtc_clock = pclk; |
f573de5a | 844 | pipe_config->port_clock = pclk; |
4e646495 JN |
845 | } |
846 | ||
c19de8eb DL |
847 | static enum drm_mode_status |
848 | intel_dsi_mode_valid(struct drm_connector *connector, | |
849 | struct drm_display_mode *mode) | |
4e646495 JN |
850 | { |
851 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
f4ee265f | 852 | const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
759a1e98 | 853 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
4e646495 JN |
854 | |
855 | DRM_DEBUG_KMS("\n"); | |
856 | ||
857 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { | |
858 | DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n"); | |
859 | return MODE_NO_DBLESCAN; | |
860 | } | |
861 | ||
862 | if (fixed_mode) { | |
863 | if (mode->hdisplay > fixed_mode->hdisplay) | |
864 | return MODE_PANEL; | |
865 | if (mode->vdisplay > fixed_mode->vdisplay) | |
866 | return MODE_PANEL; | |
759a1e98 MK |
867 | if (fixed_mode->clock > max_dotclk) |
868 | return MODE_CLOCK_HIGH; | |
4e646495 JN |
869 | } |
870 | ||
36d21f4c | 871 | return MODE_OK; |
4e646495 JN |
872 | } |
873 | ||
874 | /* return txclkesc cycles in terms of divider and duration in us */ | |
875 | static u16 txclkesc(u32 divider, unsigned int us) | |
876 | { | |
877 | switch (divider) { | |
878 | case ESCAPE_CLOCK_DIVIDER_1: | |
879 | default: | |
880 | return 20 * us; | |
881 | case ESCAPE_CLOCK_DIVIDER_2: | |
882 | return 10 * us; | |
883 | case ESCAPE_CLOCK_DIVIDER_4: | |
884 | return 5 * us; | |
885 | } | |
886 | } | |
887 | ||
888 | /* return pixels in terms of txbyteclkhs */ | |
7f0c8605 SK |
889 | static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, |
890 | u16 burst_mode_ratio) | |
4e646495 | 891 | { |
7f0c8605 | 892 | return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, |
7f3de833 | 893 | 8 * 100), lane_count); |
4e646495 JN |
894 | } |
895 | ||
896 | static void set_dsi_timings(struct drm_encoder *encoder, | |
5e7234c9 | 897 | const struct drm_display_mode *adjusted_mode) |
4e646495 JN |
898 | { |
899 | struct drm_device *dev = encoder->dev; | |
900 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4e646495 | 901 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
aa102d28 | 902 | enum port port; |
1e78aa01 | 903 | unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); |
4e646495 JN |
904 | unsigned int lane_count = intel_dsi->lane_count; |
905 | ||
906 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; | |
907 | ||
aad941d5 VS |
908 | hactive = adjusted_mode->crtc_hdisplay; |
909 | hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; | |
910 | hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; | |
911 | hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; | |
4e646495 | 912 | |
aa102d28 GS |
913 | if (intel_dsi->dual_link) { |
914 | hactive /= 2; | |
915 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) | |
916 | hactive += intel_dsi->pixel_overlap; | |
917 | hfp /= 2; | |
918 | hsync /= 2; | |
919 | hbp /= 2; | |
920 | } | |
921 | ||
aad941d5 VS |
922 | vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; |
923 | vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; | |
924 | vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; | |
4e646495 JN |
925 | |
926 | /* horizontal values are in terms of high speed byte clock */ | |
7f0c8605 | 927 | hactive = txbyteclkhs(hactive, bpp, lane_count, |
7f3de833 | 928 | intel_dsi->burst_mode_ratio); |
7f0c8605 SK |
929 | hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
930 | hsync = txbyteclkhs(hsync, bpp, lane_count, | |
7f3de833 | 931 | intel_dsi->burst_mode_ratio); |
7f0c8605 | 932 | hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
4e646495 | 933 | |
aa102d28 | 934 | for_each_dsi_port(port, intel_dsi->ports) { |
d2e08c0f SS |
935 | if (IS_BROXTON(dev)) { |
936 | /* | |
937 | * Program hdisplay and vdisplay on MIPI transcoder. | |
938 | * This is different from calculated hactive and | |
939 | * vactive, as they are calculated per channel basis, | |
940 | * whereas these values should be based on resolution. | |
941 | */ | |
942 | I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port), | |
aad941d5 | 943 | adjusted_mode->crtc_hdisplay); |
d2e08c0f | 944 | I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port), |
aad941d5 | 945 | adjusted_mode->crtc_vdisplay); |
d2e08c0f | 946 | I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port), |
aad941d5 | 947 | adjusted_mode->crtc_vtotal); |
d2e08c0f SS |
948 | } |
949 | ||
aa102d28 GS |
950 | I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); |
951 | I915_WRITE(MIPI_HFP_COUNT(port), hfp); | |
952 | ||
953 | /* meaningful for video mode non-burst sync pulse mode only, | |
954 | * can be zero for non-burst sync events and burst modes */ | |
955 | I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); | |
956 | I915_WRITE(MIPI_HBP_COUNT(port), hbp); | |
957 | ||
958 | /* vertical values are in terms of lines */ | |
959 | I915_WRITE(MIPI_VFP_COUNT(port), vfp); | |
960 | I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); | |
961 | I915_WRITE(MIPI_VBP_COUNT(port), vbp); | |
962 | } | |
4e646495 JN |
963 | } |
964 | ||
1e78aa01 JN |
965 | static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt) |
966 | { | |
967 | switch (fmt) { | |
968 | case MIPI_DSI_FMT_RGB888: | |
969 | return VID_MODE_FORMAT_RGB888; | |
970 | case MIPI_DSI_FMT_RGB666: | |
971 | return VID_MODE_FORMAT_RGB666; | |
972 | case MIPI_DSI_FMT_RGB666_PACKED: | |
973 | return VID_MODE_FORMAT_RGB666_PACKED; | |
974 | case MIPI_DSI_FMT_RGB565: | |
975 | return VID_MODE_FORMAT_RGB565; | |
976 | default: | |
977 | MISSING_CASE(fmt); | |
978 | return VID_MODE_FORMAT_RGB666; | |
979 | } | |
980 | } | |
981 | ||
07e4fb9e | 982 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder) |
4e646495 JN |
983 | { |
984 | struct drm_encoder *encoder = &intel_encoder->base; | |
985 | struct drm_device *dev = encoder->dev; | |
986 | struct drm_i915_private *dev_priv = dev->dev_private; | |
987 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
988 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
7c5f93b0 | 989 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
24ee0e64 | 990 | enum port port; |
1e78aa01 | 991 | unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); |
4e646495 | 992 | u32 val, tmp; |
24ee0e64 | 993 | u16 mode_hdisplay; |
4e646495 | 994 | |
e7d7cad0 | 995 | DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe)); |
4e646495 | 996 | |
aad941d5 | 997 | mode_hdisplay = adjusted_mode->crtc_hdisplay; |
4e646495 | 998 | |
24ee0e64 GS |
999 | if (intel_dsi->dual_link) { |
1000 | mode_hdisplay /= 2; | |
1001 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) | |
1002 | mode_hdisplay += intel_dsi->pixel_overlap; | |
1003 | } | |
4e646495 | 1004 | |
24ee0e64 | 1005 | for_each_dsi_port(port, intel_dsi->ports) { |
666a4537 | 1006 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
d2e08c0f SS |
1007 | /* |
1008 | * escape clock divider, 20MHz, shared for A and C. | |
1009 | * device ready must be off when doing this! txclkesc? | |
1010 | */ | |
1011 | tmp = I915_READ(MIPI_CTRL(PORT_A)); | |
1012 | tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; | |
1013 | I915_WRITE(MIPI_CTRL(PORT_A), tmp | | |
1014 | ESCAPE_CLOCK_DIVIDER_1); | |
1015 | ||
1016 | /* read request priority is per pipe */ | |
1017 | tmp = I915_READ(MIPI_CTRL(port)); | |
1018 | tmp &= ~READ_REQUEST_PRIORITY_MASK; | |
1019 | I915_WRITE(MIPI_CTRL(port), tmp | | |
1020 | READ_REQUEST_PRIORITY_HIGH); | |
1021 | } else if (IS_BROXTON(dev)) { | |
56c48978 D |
1022 | enum pipe pipe = intel_crtc->pipe; |
1023 | ||
d2e08c0f SS |
1024 | tmp = I915_READ(MIPI_CTRL(port)); |
1025 | tmp &= ~BXT_PIPE_SELECT_MASK; | |
1026 | ||
56c48978 | 1027 | tmp |= BXT_PIPE_SELECT(pipe); |
d2e08c0f SS |
1028 | I915_WRITE(MIPI_CTRL(port), tmp); |
1029 | } | |
24ee0e64 GS |
1030 | |
1031 | /* XXX: why here, why like this? handling in irq handler?! */ | |
1032 | I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); | |
1033 | I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); | |
1034 | ||
1035 | I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); | |
1036 | ||
1037 | I915_WRITE(MIPI_DPI_RESOLUTION(port), | |
aad941d5 | 1038 | adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | |
24ee0e64 GS |
1039 | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); |
1040 | } | |
4e646495 JN |
1041 | |
1042 | set_dsi_timings(encoder, adjusted_mode); | |
1043 | ||
1044 | val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; | |
1045 | if (is_cmd_mode(intel_dsi)) { | |
1046 | val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; | |
1047 | val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ | |
1048 | } else { | |
1049 | val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; | |
1e78aa01 | 1050 | val |= pixel_format_to_reg(intel_dsi->pixel_format); |
4e646495 | 1051 | } |
4e646495 | 1052 | |
24ee0e64 GS |
1053 | tmp = 0; |
1054 | if (intel_dsi->eotp_pkt == 0) | |
1055 | tmp |= EOT_DISABLE; | |
1056 | if (intel_dsi->clock_stop) | |
1057 | tmp |= CLOCKSTOP; | |
4e646495 | 1058 | |
24ee0e64 GS |
1059 | for_each_dsi_port(port, intel_dsi->ports) { |
1060 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); | |
1061 | ||
1062 | /* timeouts for recovery. one frame IIUC. if counter expires, | |
1063 | * EOT and stop state. */ | |
1064 | ||
1065 | /* | |
1066 | * In burst mode, value greater than one DPI line Time in byte | |
1067 | * clock (txbyteclkhs) To timeout this timer 1+ of the above | |
1068 | * said value is recommended. | |
1069 | * | |
1070 | * In non-burst mode, Value greater than one DPI frame time in | |
1071 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above | |
1072 | * said value is recommended. | |
1073 | * | |
1074 | * In DBI only mode, value greater than one DBI frame time in | |
1075 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above | |
1076 | * said value is recommended. | |
1077 | */ | |
4e646495 | 1078 | |
24ee0e64 GS |
1079 | if (is_vid_mode(intel_dsi) && |
1080 | intel_dsi->video_mode_format == VIDEO_MODE_BURST) { | |
1081 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), | |
aad941d5 | 1082 | txbyteclkhs(adjusted_mode->crtc_htotal, bpp, |
124abe07 VS |
1083 | intel_dsi->lane_count, |
1084 | intel_dsi->burst_mode_ratio) + 1); | |
24ee0e64 GS |
1085 | } else { |
1086 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), | |
aad941d5 VS |
1087 | txbyteclkhs(adjusted_mode->crtc_vtotal * |
1088 | adjusted_mode->crtc_htotal, | |
124abe07 VS |
1089 | bpp, intel_dsi->lane_count, |
1090 | intel_dsi->burst_mode_ratio) + 1); | |
24ee0e64 GS |
1091 | } |
1092 | I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); | |
1093 | I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), | |
1094 | intel_dsi->turn_arnd_val); | |
1095 | I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), | |
1096 | intel_dsi->rst_timer_val); | |
f1c79f16 | 1097 | |
24ee0e64 | 1098 | /* dphy stuff */ |
f1c79f16 | 1099 | |
24ee0e64 GS |
1100 | /* in terms of low power clock */ |
1101 | I915_WRITE(MIPI_INIT_COUNT(port), | |
1102 | txclkesc(intel_dsi->escape_clk_div, 100)); | |
4e646495 | 1103 | |
d2e08c0f SS |
1104 | if (IS_BROXTON(dev) && (!intel_dsi->dual_link)) { |
1105 | /* | |
1106 | * BXT spec says write MIPI_INIT_COUNT for | |
1107 | * both the ports, even if only one is | |
1108 | * getting used. So write the other port | |
1109 | * if not in dual link mode. | |
1110 | */ | |
1111 | I915_WRITE(MIPI_INIT_COUNT(port == | |
1112 | PORT_A ? PORT_C : PORT_A), | |
1113 | intel_dsi->init_count); | |
1114 | } | |
4e646495 | 1115 | |
24ee0e64 | 1116 | /* recovery disables */ |
87c54d0e | 1117 | I915_WRITE(MIPI_EOT_DISABLE(port), tmp); |
cf4dbd2e | 1118 | |
24ee0e64 GS |
1119 | /* in terms of low power clock */ |
1120 | I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); | |
4e646495 | 1121 | |
24ee0e64 GS |
1122 | /* in terms of txbyteclkhs. actual high to low switch + |
1123 | * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. | |
1124 | * | |
1125 | * XXX: write MIPI_STOP_STATE_STALL? | |
1126 | */ | |
1127 | I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), | |
1128 | intel_dsi->hs_to_lp_count); | |
1129 | ||
1130 | /* XXX: low power clock equivalence in terms of byte clock. | |
1131 | * the number of byte clocks occupied in one low power clock. | |
1132 | * based on txbyteclkhs and txclkesc. | |
1133 | * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL | |
1134 | * ) / 105.??? | |
1135 | */ | |
1136 | I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); | |
1137 | ||
1138 | /* the bw essential for transmitting 16 long packets containing | |
1139 | * 252 bytes meant for dcs write memory command is programmed in | |
1140 | * this register in terms of byte clocks. based on dsi transfer | |
1141 | * rate and the number of lanes configured the time taken to | |
1142 | * transmit 16 long packets in a dsi stream varies. */ | |
1143 | I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); | |
1144 | ||
1145 | I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), | |
1146 | intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | | |
1147 | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); | |
1148 | ||
1149 | if (is_vid_mode(intel_dsi)) | |
1150 | /* Some panels might have resolution which is not a | |
1151 | * multiple of 64 like 1366 x 768. Enable RANDOM | |
1152 | * resolution support for such panels by default */ | |
1153 | I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), | |
1154 | intel_dsi->video_frmt_cfg_bits | | |
1155 | intel_dsi->video_mode_format | | |
1156 | IP_TG_CONFIG | | |
1157 | RANDOM_DPI_DISPLAY_RESOLUTION); | |
1158 | } | |
4e646495 JN |
1159 | } |
1160 | ||
1161 | static enum drm_connector_status | |
1162 | intel_dsi_detect(struct drm_connector *connector, bool force) | |
1163 | { | |
36d21f4c | 1164 | return connector_status_connected; |
4e646495 JN |
1165 | } |
1166 | ||
1167 | static int intel_dsi_get_modes(struct drm_connector *connector) | |
1168 | { | |
1169 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
1170 | struct drm_display_mode *mode; | |
1171 | ||
1172 | DRM_DEBUG_KMS("\n"); | |
1173 | ||
1174 | if (!intel_connector->panel.fixed_mode) { | |
1175 | DRM_DEBUG_KMS("no fixed mode\n"); | |
1176 | return 0; | |
1177 | } | |
1178 | ||
1179 | mode = drm_mode_duplicate(connector->dev, | |
1180 | intel_connector->panel.fixed_mode); | |
1181 | if (!mode) { | |
1182 | DRM_DEBUG_KMS("drm_mode_duplicate failed\n"); | |
1183 | return 0; | |
1184 | } | |
1185 | ||
1186 | drm_mode_probed_add(connector, mode); | |
1187 | return 1; | |
1188 | } | |
1189 | ||
f4ee265f VS |
1190 | static int intel_dsi_set_property(struct drm_connector *connector, |
1191 | struct drm_property *property, | |
1192 | uint64_t val) | |
1193 | { | |
1194 | struct drm_device *dev = connector->dev; | |
1195 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
1196 | struct drm_crtc *crtc; | |
1197 | int ret; | |
1198 | ||
1199 | ret = drm_object_property_set_value(&connector->base, property, val); | |
1200 | if (ret) | |
1201 | return ret; | |
1202 | ||
1203 | if (property == dev->mode_config.scaling_mode_property) { | |
1204 | if (val == DRM_MODE_SCALE_NONE) { | |
1205 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
1206 | return -EINVAL; | |
1207 | } | |
1208 | ||
1209 | if (intel_connector->panel.fitting_mode == val) | |
1210 | return 0; | |
1211 | ||
1212 | intel_connector->panel.fitting_mode = val; | |
1213 | } | |
1214 | ||
1215 | crtc = intel_attached_encoder(connector)->base.crtc; | |
1216 | if (crtc && crtc->state->enable) { | |
1217 | /* | |
1218 | * If the CRTC is enabled, the display will be changed | |
1219 | * according to the new panel fitting mode. | |
1220 | */ | |
1221 | intel_crtc_restore_mode(crtc); | |
1222 | } | |
1223 | ||
1224 | return 0; | |
1225 | } | |
1226 | ||
593e0622 | 1227 | static void intel_dsi_connector_destroy(struct drm_connector *connector) |
4e646495 JN |
1228 | { |
1229 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
1230 | ||
1231 | DRM_DEBUG_KMS("\n"); | |
1232 | intel_panel_fini(&intel_connector->panel); | |
4e646495 JN |
1233 | drm_connector_cleanup(connector); |
1234 | kfree(connector); | |
1235 | } | |
1236 | ||
593e0622 JN |
1237 | static void intel_dsi_encoder_destroy(struct drm_encoder *encoder) |
1238 | { | |
1239 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
1240 | ||
1241 | if (intel_dsi->panel) { | |
1242 | drm_panel_detach(intel_dsi->panel); | |
1243 | /* XXX: Logically this call belongs in the panel driver. */ | |
1244 | drm_panel_remove(intel_dsi->panel); | |
1245 | } | |
fc45e821 SK |
1246 | |
1247 | /* dispose of the gpios */ | |
1248 | if (intel_dsi->gpio_panel) | |
1249 | gpiod_put(intel_dsi->gpio_panel); | |
1250 | ||
593e0622 JN |
1251 | intel_encoder_destroy(encoder); |
1252 | } | |
1253 | ||
4e646495 | 1254 | static const struct drm_encoder_funcs intel_dsi_funcs = { |
593e0622 | 1255 | .destroy = intel_dsi_encoder_destroy, |
4e646495 JN |
1256 | }; |
1257 | ||
1258 | static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { | |
1259 | .get_modes = intel_dsi_get_modes, | |
1260 | .mode_valid = intel_dsi_mode_valid, | |
1261 | .best_encoder = intel_best_encoder, | |
1262 | }; | |
1263 | ||
1264 | static const struct drm_connector_funcs intel_dsi_connector_funcs = { | |
4d688a2a | 1265 | .dpms = drm_atomic_helper_connector_dpms, |
4e646495 | 1266 | .detect = intel_dsi_detect, |
593e0622 | 1267 | .destroy = intel_dsi_connector_destroy, |
4e646495 | 1268 | .fill_modes = drm_helper_probe_single_connector_modes, |
f4ee265f | 1269 | .set_property = intel_dsi_set_property, |
2545e4a6 | 1270 | .atomic_get_property = intel_connector_atomic_get_property, |
c6f95f27 | 1271 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 1272 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
4e646495 JN |
1273 | }; |
1274 | ||
f4ee265f VS |
1275 | static void intel_dsi_add_properties(struct intel_connector *connector) |
1276 | { | |
1277 | struct drm_device *dev = connector->base.dev; | |
1278 | ||
1279 | if (connector->panel.fixed_mode) { | |
1280 | drm_mode_create_scaling_mode_property(dev); | |
1281 | drm_object_attach_property(&connector->base.base, | |
1282 | dev->mode_config.scaling_mode_property, | |
1283 | DRM_MODE_SCALE_ASPECT); | |
1284 | connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; | |
1285 | } | |
1286 | } | |
1287 | ||
4328633d | 1288 | void intel_dsi_init(struct drm_device *dev) |
4e646495 JN |
1289 | { |
1290 | struct intel_dsi *intel_dsi; | |
1291 | struct intel_encoder *intel_encoder; | |
1292 | struct drm_encoder *encoder; | |
1293 | struct intel_connector *intel_connector; | |
1294 | struct drm_connector *connector; | |
593e0622 | 1295 | struct drm_display_mode *scan, *fixed_mode = NULL; |
b6fdd0f2 | 1296 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e9804fd | 1297 | enum port port; |
4e646495 JN |
1298 | unsigned int i; |
1299 | ||
1300 | DRM_DEBUG_KMS("\n"); | |
1301 | ||
3e6bd011 | 1302 | /* There is no detection method for MIPI so rely on VBT */ |
7137aec1 | 1303 | if (!intel_bios_is_dsi_present(dev_priv, &port)) |
4328633d | 1304 | return; |
3e6bd011 | 1305 | |
666a4537 | 1306 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
868d665b | 1307 | dev_priv->mipi_mmio_base = VLV_MIPI_BASE; |
c6c794a2 SS |
1308 | } else if (IS_BROXTON(dev)) { |
1309 | dev_priv->mipi_mmio_base = BXT_MIPI_BASE; | |
868d665b CJ |
1310 | } else { |
1311 | DRM_ERROR("Unsupported Mipi device to reg base"); | |
1312 | return; | |
1313 | } | |
3e6bd011 | 1314 | |
4e646495 JN |
1315 | intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); |
1316 | if (!intel_dsi) | |
4328633d | 1317 | return; |
4e646495 | 1318 | |
08d9bc92 | 1319 | intel_connector = intel_connector_alloc(); |
4e646495 JN |
1320 | if (!intel_connector) { |
1321 | kfree(intel_dsi); | |
4328633d | 1322 | return; |
4e646495 JN |
1323 | } |
1324 | ||
1325 | intel_encoder = &intel_dsi->base; | |
1326 | encoder = &intel_encoder->base; | |
1327 | intel_dsi->attached_connector = intel_connector; | |
1328 | ||
1329 | connector = &intel_connector->base; | |
1330 | ||
13a3d91f VS |
1331 | drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI, |
1332 | NULL); | |
4e646495 | 1333 | |
4e646495 | 1334 | intel_encoder->compute_config = intel_dsi_compute_config; |
4e646495 | 1335 | intel_encoder->pre_enable = intel_dsi_pre_enable; |
2634fd7f | 1336 | intel_encoder->enable = intel_dsi_enable_nop; |
c315faf8 | 1337 | intel_encoder->disable = intel_dsi_pre_disable; |
4e646495 JN |
1338 | intel_encoder->post_disable = intel_dsi_post_disable; |
1339 | intel_encoder->get_hw_state = intel_dsi_get_hw_state; | |
1340 | intel_encoder->get_config = intel_dsi_get_config; | |
1341 | ||
1342 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
4932e2c3 | 1343 | intel_connector->unregister = intel_connector_unregister; |
4e646495 | 1344 | |
2e85ab4f JN |
1345 | /* |
1346 | * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI | |
1347 | * port C. BXT isn't limited like this. | |
1348 | */ | |
1349 | if (IS_BROXTON(dev_priv)) | |
1350 | intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); | |
1351 | else if (port == PORT_A) | |
701d25b4 | 1352 | intel_encoder->crtc_mask = BIT(PIPE_A); |
7137aec1 | 1353 | else |
701d25b4 | 1354 | intel_encoder->crtc_mask = BIT(PIPE_B); |
e7d7cad0 | 1355 | |
82425785 | 1356 | if (dev_priv->vbt.dsi.config->dual_link) |
701d25b4 | 1357 | intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); |
7137aec1 | 1358 | else |
701d25b4 | 1359 | intel_dsi->ports = BIT(port); |
82425785 | 1360 | |
7e9804fd JN |
1361 | /* Create a DSI host (and a device) for each port. */ |
1362 | for_each_dsi_port(port, intel_dsi->ports) { | |
1363 | struct intel_dsi_host *host; | |
1364 | ||
1365 | host = intel_dsi_host_init(intel_dsi, port); | |
1366 | if (!host) | |
1367 | goto err; | |
1368 | ||
1369 | intel_dsi->dsi_hosts[port] = host; | |
1370 | } | |
1371 | ||
593e0622 JN |
1372 | for (i = 0; i < ARRAY_SIZE(intel_dsi_drivers); i++) { |
1373 | intel_dsi->panel = intel_dsi_drivers[i].init(intel_dsi, | |
1374 | intel_dsi_drivers[i].panel_id); | |
1375 | if (intel_dsi->panel) | |
4e646495 JN |
1376 | break; |
1377 | } | |
1378 | ||
593e0622 | 1379 | if (!intel_dsi->panel) { |
4e646495 JN |
1380 | DRM_DEBUG_KMS("no device found\n"); |
1381 | goto err; | |
1382 | } | |
1383 | ||
fc45e821 SK |
1384 | /* |
1385 | * In case of BYT with CRC PMIC, we need to use GPIO for | |
1386 | * Panel control. | |
1387 | */ | |
1388 | if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) { | |
1389 | intel_dsi->gpio_panel = | |
1390 | gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH); | |
1391 | ||
1392 | if (IS_ERR(intel_dsi->gpio_panel)) { | |
1393 | DRM_ERROR("Failed to own gpio for panel control\n"); | |
1394 | intel_dsi->gpio_panel = NULL; | |
1395 | } | |
1396 | } | |
1397 | ||
4e646495 | 1398 | intel_encoder->type = INTEL_OUTPUT_DSI; |
bc079e8b | 1399 | intel_encoder->cloneable = 0; |
4e646495 JN |
1400 | drm_connector_init(dev, connector, &intel_dsi_connector_funcs, |
1401 | DRM_MODE_CONNECTOR_DSI); | |
1402 | ||
1403 | drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); | |
1404 | ||
1405 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ | |
1406 | connector->interlace_allowed = false; | |
1407 | connector->doublescan_allowed = false; | |
1408 | ||
1409 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
1410 | ||
593e0622 JN |
1411 | drm_panel_attach(intel_dsi->panel, connector); |
1412 | ||
1413 | mutex_lock(&dev->mode_config.mutex); | |
1414 | drm_panel_get_modes(intel_dsi->panel); | |
1415 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
1416 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { | |
1417 | fixed_mode = drm_mode_duplicate(dev, scan); | |
1418 | break; | |
1419 | } | |
1420 | } | |
1421 | mutex_unlock(&dev->mode_config.mutex); | |
1422 | ||
4e646495 JN |
1423 | if (!fixed_mode) { |
1424 | DRM_DEBUG_KMS("no fixed mode\n"); | |
1425 | goto err; | |
1426 | } | |
1427 | ||
4b6ed685 | 1428 | intel_panel_init(&intel_connector->panel, fixed_mode, NULL); |
f4ee265f VS |
1429 | |
1430 | intel_dsi_add_properties(intel_connector); | |
1431 | ||
1432 | drm_connector_register(connector); | |
1433 | ||
b029e66f | 1434 | intel_panel_setup_backlight(connector, INVALID_PIPE); |
4e646495 | 1435 | |
4328633d | 1436 | return; |
4e646495 JN |
1437 | |
1438 | err: | |
1439 | drm_encoder_cleanup(&intel_encoder->base); | |
1440 | kfree(intel_dsi); | |
1441 | kfree(intel_connector); | |
4e646495 | 1442 | } |