[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dsi_cmd.h

/*
 * Copyright © 2013 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Author: Jani Nikula <jani.nikula@intel.com>
 */

#ifndef _INTEL_DSI_DSI_H
#define _INTEL_DSI_DSI_H

#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <video/mipi_display.h>
#include "i915_drv.h"
#include "intel_drv.h"
#include "intel_dsi.h"

#define DPI_LP_MODE_EN	false
#define DPI_HS_MODE_EN	true

void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable);

int dsi_vc_dcs_write(struct intel_dsi *intel_dsi, int channel,
		     const u8 *data, int len);

int dsi_vc_generic_write(struct intel_dsi *intel_dsi, int channel,
			 const u8 *data, int len);

int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
		    u8 *buf, int buflen);

int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
			u8 *reqdata, int reqlen, u8 *buf, int buflen);

int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs);
void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi);

/* XXX: questionable write helpers */
static inline int dsi_vc_dcs_write_0(struct intel_dsi *intel_dsi,
				     int channel, u8 dcs_cmd)
{
	return dsi_vc_dcs_write(intel_dsi, channel, &dcs_cmd, 1);
}

static inline int dsi_vc_dcs_write_1(struct intel_dsi *intel_dsi,
				     int channel, u8 dcs_cmd, u8 param)
{
	u8 buf[2] = { dcs_cmd, param };
	return dsi_vc_dcs_write(intel_dsi, channel, buf, 2);
}

static inline int dsi_vc_generic_write_0(struct intel_dsi *intel_dsi,
					 int channel)
{
	return dsi_vc_generic_write(intel_dsi, channel, NULL, 0);
}

static inline int dsi_vc_generic_write_1(struct intel_dsi *intel_dsi,
					 int channel, u8 param)
{
	return dsi_vc_generic_write(intel_dsi, channel, &param, 1);
}

static inline int dsi_vc_generic_write_2(struct intel_dsi *intel_dsi,
					 int channel, u8 param1, u8 param2)
{
	u8 buf[2] = { param1, param2 };
	return dsi_vc_generic_write(intel_dsi, channel, buf, 2);
}

/* XXX: questionable read helpers */
static inline int dsi_vc_generic_read_0(struct intel_dsi *intel_dsi,
					int channel, u8 *buf, int buflen)
{
	return dsi_vc_generic_read(intel_dsi, channel, NULL, 0, buf, buflen);
}

static inline int dsi_vc_generic_read_1(struct intel_dsi *intel_dsi,
					int channel, u8 param, u8 *buf,
					int buflen)
{
	return dsi_vc_generic_read(intel_dsi, channel, &param, 1, buf, buflen);
}

static inline int dsi_vc_generic_read_2(struct intel_dsi *intel_dsi,
					int channel, u8 param1, u8 param2,
					u8 *buf, int buflen)
{
	u8 req[2] = { param1, param2 };

	return dsi_vc_generic_read(intel_dsi, channel, req, 2, buf, buflen);
}


#endif /* _INTEL_DSI_DSI_H */
Commit	Line	Data
69c05eb2 JN	1	/*
	2	* Copyright © 2013 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*
	23	* Author: Jani Nikula <jani.nikula@intel.com>
	24	*/
	25
	26	#ifndef _INTEL_DSI_DSI_H
	27	#define _INTEL_DSI_DSI_H
	28
	29	#include <drm/drmP.h>
	30	#include <drm/drm_crtc.h>
	31	#include <video/mipi_display.h>
	32	#include "i915_drv.h"
	33	#include "intel_drv.h"
	34	#include "intel_dsi.h"
	35
e1047028 SK	36	#define DPI_LP_MODE_EN false
	37	#define DPI_HS_MODE_EN true
	38
69c05eb2 JN	39	void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable);
	40
	41	int dsi_vc_dcs_write(struct intel_dsi *intel_dsi, int channel,
3e33a840	42	const u8 *data, int len);
69c05eb2 JN	43
69c05eb2 JN	44	int dsi_vc_generic_write(struct intel_dsi *intel_dsi, int channel,
3e33a840	45	const u8 *data, int len);
69c05eb2 JN	46
69c05eb2 JN	47	int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
3e33a840	48	u8 *buf, int buflen);
69c05eb2 JN	49
69c05eb2 JN	50	int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
3e33a840	51	u8 reqdata, int reqlen, u8 buf, int buflen);
69c05eb2	52
e1047028	53	int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs);
1381308b	54	void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi);
69c05eb2 JN	55
	56	/* XXX: questionable write helpers */
	57	static inline int dsi_vc_dcs_write_0(struct intel_dsi *intel_dsi,
	58	int channel, u8 dcs_cmd)
	59	{
	60	return dsi_vc_dcs_write(intel_dsi, channel, &dcs_cmd, 1);
	61	}
	62
	63	static inline int dsi_vc_dcs_write_1(struct intel_dsi *intel_dsi,
	64	int channel, u8 dcs_cmd, u8 param)
	65	{
	66	u8 buf[2] = { dcs_cmd, param };
	67	return dsi_vc_dcs_write(intel_dsi, channel, buf, 2);
	68	}
	69
	70	static inline int dsi_vc_generic_write_0(struct intel_dsi *intel_dsi,
	71	int channel)
	72	{
	73	return dsi_vc_generic_write(intel_dsi, channel, NULL, 0);
	74	}
	75
	76	static inline int dsi_vc_generic_write_1(struct intel_dsi *intel_dsi,
	77	int channel, u8 param)
	78	{
	79	return dsi_vc_generic_write(intel_dsi, channel, &param, 1);
	80	}
	81
	82	static inline int dsi_vc_generic_write_2(struct intel_dsi *intel_dsi,
	83	int channel, u8 param1, u8 param2)
	84	{
	85	u8 buf[2] = { param1, param2 };
	86	return dsi_vc_generic_write(intel_dsi, channel, buf, 2);
	87	}
	88
	89	/* XXX: questionable read helpers */
	90	static inline int dsi_vc_generic_read_0(struct intel_dsi *intel_dsi,
3e33a840	91	int channel, u8 *buf, int buflen)
69c05eb2 JN	92	{
	93	return dsi_vc_generic_read(intel_dsi, channel, NULL, 0, buf, buflen);
	94	}
	95
	96	static inline int dsi_vc_generic_read_1(struct intel_dsi *intel_dsi,
	97	int channel, u8 param, u8 *buf,
3e33a840	98	int buflen)
69c05eb2 JN	99	{
	100	return dsi_vc_generic_read(intel_dsi, channel, &param, 1, buf, buflen);
	101	}
	102
	103	static inline int dsi_vc_generic_read_2(struct intel_dsi *intel_dsi,
	104	int channel, u8 param1, u8 param2,
3e33a840	105	u8 *buf, int buflen)
69c05eb2 JN	106	{
	107	u8 req[2] = { param1, param2 };
	108
	109	return dsi_vc_generic_read(intel_dsi, channel, req, 2, buf, buflen);
	110	}
	111
	112
	113	#endif /* _INTEL_DSI_DSI_H */