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2ab8b458 SK |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Author: Shobhit Kumar <shobhit.kumar@intel.com> | |
24 | * | |
25 | */ | |
26 | ||
27 | #include <drm/drmP.h> | |
28 | #include <drm/drm_crtc.h> | |
29 | #include <drm/drm_edid.h> | |
30 | #include <drm/i915_drm.h> | |
593e0622 | 31 | #include <drm/drm_panel.h> |
2ab8b458 SK |
32 | #include <linux/slab.h> |
33 | #include <video/mipi_display.h> | |
34 | #include <asm/intel-mid.h> | |
35 | #include <video/mipi_display.h> | |
36 | #include "i915_drv.h" | |
37 | #include "intel_drv.h" | |
38 | #include "intel_dsi.h" | |
2ab8b458 | 39 | |
593e0622 JN |
40 | struct vbt_panel { |
41 | struct drm_panel panel; | |
42 | struct intel_dsi *intel_dsi; | |
43 | }; | |
44 | ||
45 | static inline struct vbt_panel *to_vbt_panel(struct drm_panel *panel) | |
46 | { | |
47 | return container_of(panel, struct vbt_panel, panel); | |
48 | } | |
49 | ||
2ab8b458 SK |
50 | #define MIPI_TRANSFER_MODE_SHIFT 0 |
51 | #define MIPI_VIRTUAL_CHANNEL_SHIFT 1 | |
52 | #define MIPI_PORT_SHIFT 3 | |
53 | ||
54 | #define PREPARE_CNT_MAX 0x3F | |
55 | #define EXIT_ZERO_CNT_MAX 0x3F | |
56 | #define CLK_ZERO_CNT_MAX 0xFF | |
57 | #define TRAIL_CNT_MAX 0x1F | |
58 | ||
59 | #define NS_KHZ_RATIO 1000000 | |
60 | ||
b0c91cd0 JN |
61 | /* base offsets for gpio pads */ |
62 | #define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130 | |
63 | #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120 | |
64 | #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110 | |
65 | #define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140 | |
66 | #define VLV_GPIO_NC_4_PANEL0_BKLTEN 0x4150 | |
67 | #define VLV_GPIO_NC_5_PANEL0_BKLTCTL 0x4160 | |
68 | #define VLV_GPIO_NC_6_HV_DDI1_HPD 0x4180 | |
69 | #define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA 0x4190 | |
70 | #define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL 0x4170 | |
71 | #define VLV_GPIO_NC_9_PANEL1_VDDEN 0x4100 | |
72 | #define VLV_GPIO_NC_10_PANEL1_BKLTEN 0x40E0 | |
73 | #define VLV_GPIO_NC_11_PANEL1_BKLTCTL 0x40F0 | |
74 | ||
75 | #define VLV_GPIO_PCONF0(base_offset) (base_offset) | |
76 | #define VLV_GPIO_PAD_VAL(base_offset) ((base_offset) + 8) | |
2ab8b458 | 77 | |
b13d8e28 | 78 | struct gpio_map { |
b0c91cd0 JN |
79 | u16 base_offset; |
80 | bool init; | |
2ab8b458 SK |
81 | }; |
82 | ||
b13d8e28 | 83 | static struct gpio_map vlv_gpio_table[] = { |
b0c91cd0 JN |
84 | { VLV_GPIO_NC_0_HV_DDI0_HPD }, |
85 | { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA }, | |
86 | { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL }, | |
87 | { VLV_GPIO_NC_3_PANEL0_VDDEN }, | |
88 | { VLV_GPIO_NC_4_PANEL0_BKLTEN }, | |
89 | { VLV_GPIO_NC_5_PANEL0_BKLTCTL }, | |
90 | { VLV_GPIO_NC_6_HV_DDI1_HPD }, | |
91 | { VLV_GPIO_NC_7_HV_DDI1_DDC_SDA }, | |
92 | { VLV_GPIO_NC_8_HV_DDI1_DDC_SCL }, | |
93 | { VLV_GPIO_NC_9_PANEL1_VDDEN }, | |
94 | { VLV_GPIO_NC_10_PANEL1_BKLTEN }, | |
95 | { VLV_GPIO_NC_11_PANEL1_BKLTCTL }, | |
2ab8b458 SK |
96 | }; |
97 | ||
8f4d2683 GS |
98 | static inline enum port intel_dsi_seq_port_to_port(u8 port) |
99 | { | |
100 | return port ? PORT_C : PORT_A; | |
101 | } | |
102 | ||
5b48ca0f JN |
103 | static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, |
104 | const u8 *data) | |
2ab8b458 | 105 | { |
759d10c2 JN |
106 | struct mipi_dsi_device *dsi_device; |
107 | u8 type, flags, seq_port; | |
2ab8b458 | 108 | u16 len; |
8f4d2683 | 109 | enum port port; |
2ab8b458 | 110 | |
759d10c2 JN |
111 | flags = *data++; |
112 | type = *data++; | |
113 | ||
114 | len = *((u16 *) data); | |
115 | data += 2; | |
116 | ||
117 | seq_port = (flags >> MIPI_PORT_SHIFT) & 3; | |
2ab8b458 | 118 | |
f915084e GS |
119 | /* For DSI single link on Port A & C, the seq_port value which is |
120 | * parsed from Sequence Block#53 of VBT has been set to 0 | |
121 | * Now, read/write of packets for the DSI single link on Port A and | |
122 | * Port C will based on the DVO port from VBT block 2. | |
123 | */ | |
124 | if (intel_dsi->ports == (1 << PORT_C)) | |
125 | port = PORT_C; | |
126 | else | |
127 | port = intel_dsi_seq_port_to_port(seq_port); | |
2ab8b458 | 128 | |
759d10c2 JN |
129 | dsi_device = intel_dsi->dsi_hosts[port]->device; |
130 | if (!dsi_device) { | |
131 | DRM_DEBUG_KMS("no dsi device for port %c\n", port_name(port)); | |
132 | goto out; | |
133 | } | |
2ab8b458 | 134 | |
759d10c2 JN |
135 | if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1) |
136 | dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM; | |
137 | else | |
138 | dsi_device->mode_flags |= MIPI_DSI_MODE_LPM; | |
139 | ||
140 | dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3; | |
2ab8b458 SK |
141 | |
142 | switch (type) { | |
143 | case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: | |
759d10c2 | 144 | mipi_dsi_generic_write(dsi_device, NULL, 0); |
2ab8b458 SK |
145 | break; |
146 | case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: | |
759d10c2 | 147 | mipi_dsi_generic_write(dsi_device, data, 1); |
2ab8b458 SK |
148 | break; |
149 | case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: | |
759d10c2 | 150 | mipi_dsi_generic_write(dsi_device, data, 2); |
2ab8b458 SK |
151 | break; |
152 | case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: | |
153 | case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: | |
154 | case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: | |
155 | DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n"); | |
156 | break; | |
157 | case MIPI_DSI_GENERIC_LONG_WRITE: | |
759d10c2 | 158 | mipi_dsi_generic_write(dsi_device, data, len); |
2ab8b458 SK |
159 | break; |
160 | case MIPI_DSI_DCS_SHORT_WRITE: | |
759d10c2 | 161 | mipi_dsi_dcs_write_buffer(dsi_device, data, 1); |
2ab8b458 SK |
162 | break; |
163 | case MIPI_DSI_DCS_SHORT_WRITE_PARAM: | |
759d10c2 | 164 | mipi_dsi_dcs_write_buffer(dsi_device, data, 2); |
2ab8b458 SK |
165 | break; |
166 | case MIPI_DSI_DCS_READ: | |
167 | DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n"); | |
168 | break; | |
169 | case MIPI_DSI_DCS_LONG_WRITE: | |
759d10c2 | 170 | mipi_dsi_dcs_write_buffer(dsi_device, data, len); |
2ab8b458 | 171 | break; |
b5fbcd98 | 172 | } |
2ab8b458 | 173 | |
759d10c2 | 174 | out: |
2ab8b458 SK |
175 | data += len; |
176 | ||
177 | return data; | |
178 | } | |
179 | ||
5b48ca0f | 180 | static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data) |
2ab8b458 | 181 | { |
5b48ca0f | 182 | u32 delay = *((const u32 *) data); |
2ab8b458 SK |
183 | |
184 | usleep_range(delay, delay + 10); | |
185 | data += 4; | |
186 | ||
187 | return data; | |
188 | } | |
189 | ||
515d07de JN |
190 | static void vlv_exec_gpio(struct drm_i915_private *dev_priv, |
191 | u8 gpio_source, u8 gpio_index, bool value) | |
2ab8b458 | 192 | { |
b13d8e28 | 193 | struct gpio_map *map; |
b0c91cd0 | 194 | u16 pconf0, padval; |
515d07de JN |
195 | u32 tmp; |
196 | u8 port; | |
2ab8b458 | 197 | |
b0c91cd0 | 198 | if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) { |
e37788fd | 199 | DRM_DEBUG_KMS("unknown gpio index %u\n", gpio_index); |
515d07de | 200 | return; |
96afef1d JN |
201 | } |
202 | ||
b13d8e28 JN |
203 | map = &vlv_gpio_table[gpio_index]; |
204 | ||
96afef1d JN |
205 | if (dev_priv->vbt.dsi.seq_version >= 3) { |
206 | DRM_DEBUG_KMS("GPIO element v3 not supported\n"); | |
515d07de | 207 | return; |
1d96a4a8 JN |
208 | } else { |
209 | if (gpio_source == 0) { | |
210 | port = IOSF_PORT_GPIO_NC; | |
211 | } else if (gpio_source == 1) { | |
212 | port = IOSF_PORT_GPIO_SC; | |
213 | } else { | |
214 | DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source); | |
515d07de | 215 | return; |
1d96a4a8 | 216 | } |
96afef1d JN |
217 | } |
218 | ||
b13d8e28 JN |
219 | pconf0 = VLV_GPIO_PCONF0(map->base_offset); |
220 | padval = VLV_GPIO_PAD_VAL(map->base_offset); | |
2ab8b458 | 221 | |
a580516d | 222 | mutex_lock(&dev_priv->sb_lock); |
b13d8e28 | 223 | if (!map->init) { |
2ab8b458 | 224 | /* FIXME: remove constant below */ |
b0c91cd0 | 225 | vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00); |
b13d8e28 | 226 | map->init = true; |
2ab8b458 SK |
227 | } |
228 | ||
515d07de JN |
229 | tmp = 0x4 | value; |
230 | vlv_iosf_sb_write(dev_priv, port, padval, tmp); | |
231 | mutex_unlock(&dev_priv->sb_lock); | |
232 | } | |
233 | ||
234 | static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) | |
235 | { | |
236 | struct drm_device *dev = intel_dsi->base.base.dev; | |
237 | struct drm_i915_private *dev_priv = dev->dev_private; | |
238 | u8 gpio_source, gpio_index; | |
239 | bool value; | |
240 | ||
241 | if (dev_priv->vbt.dsi.seq_version >= 3) | |
242 | data++; | |
243 | ||
244 | gpio_index = *data++; | |
245 | ||
246 | /* gpio source in sequence v2 only */ | |
247 | if (dev_priv->vbt.dsi.seq_version == 2) | |
248 | gpio_source = (*data >> 1) & 3; | |
249 | else | |
250 | gpio_source = 0; | |
2ab8b458 SK |
251 | |
252 | /* pull up/down */ | |
515d07de JN |
253 | value = *data++ & 1; |
254 | ||
255 | if (IS_VALLEYVIEW(dev_priv)) | |
256 | vlv_exec_gpio(dev_priv, gpio_source, gpio_index, value); | |
257 | else | |
258 | DRM_DEBUG_KMS("GPIO element not supported on this platform\n"); | |
2ab8b458 SK |
259 | |
260 | return data; | |
261 | } | |
262 | ||
29bbdcb0 JN |
263 | static const u8 *mipi_exec_i2c_skip(struct intel_dsi *intel_dsi, const u8 *data) |
264 | { | |
265 | return data + *(data + 6) + 7; | |
266 | } | |
267 | ||
5b48ca0f JN |
268 | typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi, |
269 | const u8 *data); | |
2ab8b458 | 270 | static const fn_mipi_elem_exec exec_elem[] = { |
28c72840 JN |
271 | [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet, |
272 | [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay, | |
273 | [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio, | |
29bbdcb0 | 274 | [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c_skip, |
2ab8b458 SK |
275 | }; |
276 | ||
277 | /* | |
278 | * MIPI Sequence from VBT #53 parsing logic | |
279 | * We have already separated each seqence during bios parsing | |
280 | * Following is generic execution function for any sequence | |
281 | */ | |
282 | ||
283 | static const char * const seq_name[] = { | |
5cda0d20 JN |
284 | [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET", |
285 | [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP", | |
286 | [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON", | |
287 | [MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF", | |
288 | [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET", | |
bc95ce7f JN |
289 | [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON", |
290 | [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF", | |
291 | [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON", | |
292 | [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF", | |
293 | [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON", | |
294 | [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF", | |
2ab8b458 SK |
295 | }; |
296 | ||
5cda0d20 JN |
297 | static const char *sequence_name(enum mipi_seq seq_id) |
298 | { | |
299 | if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id]) | |
300 | return seq_name[seq_id]; | |
301 | else | |
302 | return "(unknown)"; | |
303 | } | |
304 | ||
c67fed85 | 305 | static void generic_exec_sequence(struct drm_panel *panel, enum mipi_seq seq_id) |
2ab8b458 | 306 | { |
c67fed85 JN |
307 | struct vbt_panel *vbt_panel = to_vbt_panel(panel); |
308 | struct intel_dsi *intel_dsi = vbt_panel->intel_dsi; | |
2a33d934 | 309 | struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); |
c67fed85 | 310 | const u8 *data; |
2ab8b458 | 311 | fn_mipi_elem_exec mipi_elem_exec; |
2ab8b458 | 312 | |
c67fed85 | 313 | if (WARN_ON(seq_id >= ARRAY_SIZE(dev_priv->vbt.dsi.sequence))) |
2ab8b458 SK |
314 | return; |
315 | ||
c67fed85 JN |
316 | data = dev_priv->vbt.dsi.sequence[seq_id]; |
317 | if (!data) { | |
318 | DRM_DEBUG_KMS("MIPI sequence %d - %s not available\n", | |
319 | seq_id, sequence_name(seq_id)); | |
320 | return; | |
321 | } | |
2ab8b458 | 322 | |
c67fed85 JN |
323 | WARN_ON(*data != seq_id); |
324 | ||
325 | DRM_DEBUG_KMS("Starting MIPI sequence %d - %s\n", | |
326 | seq_id, sequence_name(seq_id)); | |
327 | ||
328 | /* Skip Sequence Byte. */ | |
2ab8b458 SK |
329 | data++; |
330 | ||
2a33d934 JN |
331 | /* Skip Size of Sequence. */ |
332 | if (dev_priv->vbt.dsi.seq_version >= 3) | |
333 | data += 4; | |
334 | ||
2ab8b458 | 335 | while (1) { |
28c72840 | 336 | u8 operation_byte = *data++; |
40795782 JN |
337 | u8 operation_size = 0; |
338 | ||
339 | if (operation_byte == MIPI_SEQ_ELEM_END) | |
340 | break; | |
341 | ||
342 | if (operation_byte < ARRAY_SIZE(exec_elem)) | |
343 | mipi_elem_exec = exec_elem[operation_byte]; | |
344 | else | |
345 | mipi_elem_exec = NULL; | |
346 | ||
347 | /* Size of Operation. */ | |
348 | if (dev_priv->vbt.dsi.seq_version >= 3) | |
349 | operation_size = *data++; | |
350 | ||
351 | if (mipi_elem_exec) { | |
352 | data = mipi_elem_exec(intel_dsi, data); | |
353 | } else if (operation_size) { | |
354 | /* We have size, skip. */ | |
355 | DRM_DEBUG_KMS("Unsupported MIPI operation byte %u\n", | |
356 | operation_byte); | |
357 | data += operation_size; | |
358 | } else { | |
359 | /* No size, can't skip without parsing. */ | |
28c72840 JN |
360 | DRM_ERROR("Unsupported MIPI operation byte %u\n", |
361 | operation_byte); | |
2ab8b458 SK |
362 | return; |
363 | } | |
2ab8b458 SK |
364 | } |
365 | } | |
366 | ||
593e0622 JN |
367 | static int vbt_panel_prepare(struct drm_panel *panel) |
368 | { | |
c67fed85 JN |
369 | generic_exec_sequence(panel, MIPI_SEQ_ASSERT_RESET); |
370 | generic_exec_sequence(panel, MIPI_SEQ_INIT_OTP); | |
593e0622 JN |
371 | |
372 | return 0; | |
373 | } | |
374 | ||
375 | static int vbt_panel_unprepare(struct drm_panel *panel) | |
376 | { | |
c67fed85 | 377 | generic_exec_sequence(panel, MIPI_SEQ_DEASSERT_RESET); |
593e0622 JN |
378 | |
379 | return 0; | |
380 | } | |
381 | ||
382 | static int vbt_panel_enable(struct drm_panel *panel) | |
383 | { | |
c67fed85 | 384 | generic_exec_sequence(panel, MIPI_SEQ_DISPLAY_ON); |
593e0622 JN |
385 | |
386 | return 0; | |
387 | } | |
388 | ||
389 | static int vbt_panel_disable(struct drm_panel *panel) | |
390 | { | |
c67fed85 | 391 | generic_exec_sequence(panel, MIPI_SEQ_DISPLAY_OFF); |
593e0622 JN |
392 | |
393 | return 0; | |
394 | } | |
395 | ||
396 | static int vbt_panel_get_modes(struct drm_panel *panel) | |
397 | { | |
398 | struct vbt_panel *vbt_panel = to_vbt_panel(panel); | |
399 | struct intel_dsi *intel_dsi = vbt_panel->intel_dsi; | |
400 | struct drm_device *dev = intel_dsi->base.base.dev; | |
401 | struct drm_i915_private *dev_priv = dev->dev_private; | |
402 | struct drm_display_mode *mode; | |
403 | ||
404 | if (!panel->connector) | |
405 | return 0; | |
406 | ||
407 | mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode); | |
408 | if (!mode) | |
409 | return 0; | |
410 | ||
411 | mode->type |= DRM_MODE_TYPE_PREFERRED; | |
412 | ||
413 | drm_mode_probed_add(panel->connector, mode); | |
414 | ||
415 | return 1; | |
416 | } | |
417 | ||
418 | static const struct drm_panel_funcs vbt_panel_funcs = { | |
419 | .disable = vbt_panel_disable, | |
420 | .unprepare = vbt_panel_unprepare, | |
421 | .prepare = vbt_panel_prepare, | |
422 | .enable = vbt_panel_enable, | |
423 | .get_modes = vbt_panel_get_modes, | |
424 | }; | |
425 | ||
426 | struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id) | |
2ab8b458 | 427 | { |
2ab8b458 SK |
428 | struct drm_device *dev = intel_dsi->base.base.dev; |
429 | struct drm_i915_private *dev_priv = dev->dev_private; | |
430 | struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; | |
431 | struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps; | |
432 | struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode; | |
593e0622 | 433 | struct vbt_panel *vbt_panel; |
1e78aa01 | 434 | u32 bpp; |
2ab8b458 SK |
435 | u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui; |
436 | u32 ui_num, ui_den; | |
437 | u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; | |
438 | u32 ths_prepare_ns, tclk_trail_ns; | |
439 | u32 tclk_prepare_clkzero, ths_prepare_hszero; | |
440 | u32 lp_to_hs_switch, hs_to_lp_switch; | |
7f0c8605 SK |
441 | u32 pclk, computed_ddr; |
442 | u16 burst_mode_ratio; | |
759d10c2 | 443 | enum port port; |
2ab8b458 SK |
444 | |
445 | DRM_DEBUG_KMS("\n"); | |
446 | ||
447 | intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1; | |
448 | intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0; | |
449 | intel_dsi->lane_count = mipi_config->lane_cnt + 1; | |
43367ec9 R |
450 | intel_dsi->pixel_format = |
451 | pixel_format_from_register_bits( | |
452 | mipi_config->videomode_color_format << 7); | |
1e78aa01 JN |
453 | bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); |
454 | ||
369602d3 | 455 | intel_dsi->dual_link = mipi_config->dual_link; |
a9da9bce | 456 | intel_dsi->pixel_overlap = mipi_config->pixel_overlap; |
2ab8b458 SK |
457 | intel_dsi->operation_mode = mipi_config->is_cmd_mode; |
458 | intel_dsi->video_mode_format = mipi_config->video_transfer_mode; | |
459 | intel_dsi->escape_clk_div = mipi_config->byte_clk_sel; | |
460 | intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout; | |
461 | intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout; | |
462 | intel_dsi->rst_timer_val = mipi_config->device_reset_timer; | |
463 | intel_dsi->init_count = mipi_config->master_init_timer; | |
464 | intel_dsi->bw_timer = mipi_config->dbi_bw_timer; | |
b5fbcd98 SK |
465 | intel_dsi->video_frmt_cfg_bits = |
466 | mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0; | |
2ab8b458 | 467 | |
7f0c8605 SK |
468 | pclk = mode->clock; |
469 | ||
a9da9bce GS |
470 | /* In dual link mode each port needs half of pixel clock */ |
471 | if (intel_dsi->dual_link) { | |
472 | pclk = pclk / 2; | |
473 | ||
474 | /* we can enable pixel_overlap if needed by panel. In this | |
475 | * case we need to increase the pixelclock for extra pixels | |
476 | */ | |
477 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { | |
478 | pclk += DIV_ROUND_UP(mode->vtotal * | |
479 | intel_dsi->pixel_overlap * | |
480 | 60, 1000); | |
481 | } | |
482 | } | |
483 | ||
7f0c8605 SK |
484 | /* Burst Mode Ratio |
485 | * Target ddr frequency from VBT / non burst ddr freq | |
486 | * multiply by 100 to preserve remainder | |
487 | */ | |
488 | if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) { | |
489 | if (mipi_config->target_burst_mode_freq) { | |
1e78aa01 | 490 | computed_ddr = (pclk * bpp) / intel_dsi->lane_count; |
7f0c8605 SK |
491 | |
492 | if (mipi_config->target_burst_mode_freq < | |
493 | computed_ddr) { | |
494 | DRM_ERROR("Burst mode freq is less than computed\n"); | |
593e0622 | 495 | return NULL; |
7f0c8605 SK |
496 | } |
497 | ||
498 | burst_mode_ratio = DIV_ROUND_UP( | |
499 | mipi_config->target_burst_mode_freq * 100, | |
500 | computed_ddr); | |
501 | ||
502 | pclk = DIV_ROUND_UP(pclk * burst_mode_ratio, 100); | |
503 | } else { | |
504 | DRM_ERROR("Burst mode target is not set\n"); | |
593e0622 | 505 | return NULL; |
7f0c8605 SK |
506 | } |
507 | } else | |
508 | burst_mode_ratio = 100; | |
509 | ||
510 | intel_dsi->burst_mode_ratio = burst_mode_ratio; | |
511 | intel_dsi->pclk = pclk; | |
512 | ||
1e78aa01 | 513 | bitrate = (pclk * bpp) / intel_dsi->lane_count; |
7f0c8605 | 514 | |
2ab8b458 SK |
515 | switch (intel_dsi->escape_clk_div) { |
516 | case 0: | |
517 | tlpx_ns = 50; | |
518 | break; | |
519 | case 1: | |
520 | tlpx_ns = 100; | |
521 | break; | |
522 | ||
523 | case 2: | |
524 | tlpx_ns = 200; | |
525 | break; | |
526 | default: | |
527 | tlpx_ns = 50; | |
528 | break; | |
529 | } | |
530 | ||
531 | switch (intel_dsi->lane_count) { | |
532 | case 1: | |
533 | case 2: | |
534 | extra_byte_count = 2; | |
535 | break; | |
536 | case 3: | |
537 | extra_byte_count = 4; | |
538 | break; | |
539 | case 4: | |
540 | default: | |
541 | extra_byte_count = 3; | |
542 | break; | |
543 | } | |
544 | ||
545 | /* | |
546 | * ui(s) = 1/f [f in hz] | |
547 | * ui(ns) = 10^9 / (f*10^6) [f in Mhz] -> 10^3/f(Mhz) | |
548 | */ | |
549 | ||
550 | /* in Kbps */ | |
551 | ui_num = NS_KHZ_RATIO; | |
552 | ui_den = bitrate; | |
553 | ||
554 | tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero; | |
555 | ths_prepare_hszero = mipi_config->ths_prepare_hszero; | |
556 | ||
557 | /* | |
558 | * B060 | |
559 | * LP byte clock = TLPX/ (8UI) | |
560 | */ | |
561 | intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num); | |
562 | ||
563 | /* count values in UI = (ns value) * (bitrate / (2 * 10^6)) | |
564 | * | |
565 | * Since txddrclkhs_i is 2xUI, all the count values programmed in | |
566 | * DPHY param register are divided by 2 | |
567 | * | |
568 | * prepare count | |
569 | */ | |
b5fbcd98 SK |
570 | ths_prepare_ns = max(mipi_config->ths_prepare, |
571 | mipi_config->tclk_prepare); | |
2ab8b458 SK |
572 | prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2); |
573 | ||
574 | /* exit zero count */ | |
575 | exit_zero_cnt = DIV_ROUND_UP( | |
576 | (ths_prepare_hszero - ths_prepare_ns) * ui_den, | |
577 | ui_num * 2 | |
578 | ); | |
579 | ||
580 | /* | |
581 | * Exit zero is unified val ths_zero and ths_exit | |
582 | * minimum value for ths_exit = 110ns | |
583 | * min (exit_zero_cnt * 2) = 110/UI | |
584 | * exit_zero_cnt = 55/UI | |
585 | */ | |
586 | if (exit_zero_cnt < (55 * ui_den / ui_num)) | |
587 | if ((55 * ui_den) % ui_num) | |
588 | exit_zero_cnt += 1; | |
589 | ||
590 | /* clk zero count */ | |
591 | clk_zero_cnt = DIV_ROUND_UP( | |
592 | (tclk_prepare_clkzero - ths_prepare_ns) | |
593 | * ui_den, 2 * ui_num); | |
594 | ||
595 | /* trail count */ | |
596 | tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); | |
597 | trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num); | |
598 | ||
599 | if (prepare_cnt > PREPARE_CNT_MAX || | |
600 | exit_zero_cnt > EXIT_ZERO_CNT_MAX || | |
601 | clk_zero_cnt > CLK_ZERO_CNT_MAX || | |
602 | trail_cnt > TRAIL_CNT_MAX) | |
603 | DRM_DEBUG_DRIVER("Values crossing maximum limits, restricting to max values\n"); | |
604 | ||
605 | if (prepare_cnt > PREPARE_CNT_MAX) | |
606 | prepare_cnt = PREPARE_CNT_MAX; | |
607 | ||
608 | if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) | |
609 | exit_zero_cnt = EXIT_ZERO_CNT_MAX; | |
610 | ||
611 | if (clk_zero_cnt > CLK_ZERO_CNT_MAX) | |
612 | clk_zero_cnt = CLK_ZERO_CNT_MAX; | |
613 | ||
614 | if (trail_cnt > TRAIL_CNT_MAX) | |
615 | trail_cnt = TRAIL_CNT_MAX; | |
616 | ||
617 | /* B080 */ | |
618 | intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 | | |
619 | clk_zero_cnt << 8 | prepare_cnt; | |
620 | ||
621 | /* | |
622 | * LP to HS switch count = 4TLPX + PREP_COUNT * 2 + EXIT_ZERO_COUNT * 2 | |
623 | * + 10UI + Extra Byte Count | |
624 | * | |
625 | * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count | |
626 | * Extra Byte Count is calculated according to number of lanes. | |
627 | * High Low Switch Count is the Max of LP to HS and | |
628 | * HS to LP switch count | |
629 | * | |
630 | */ | |
631 | tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num); | |
632 | ||
633 | /* B044 */ | |
634 | /* FIXME: | |
635 | * The comment above does not match with the code */ | |
636 | lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * 2 + | |
637 | exit_zero_cnt * 2 + 10, 8); | |
638 | ||
639 | hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8); | |
640 | ||
641 | intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch); | |
642 | intel_dsi->hs_to_lp_count += extra_byte_count; | |
643 | ||
644 | /* B088 */ | |
645 | /* LP -> HS for clock lanes | |
646 | * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero + | |
647 | * extra byte count | |
648 | * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt * | |
649 | * 2(in UI) + extra byte count | |
650 | * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) / | |
651 | * 8 + extra byte count | |
652 | */ | |
653 | intel_dsi->clk_lp_to_hs_count = | |
654 | DIV_ROUND_UP( | |
655 | 4 * tlpx_ui + prepare_cnt * 2 + | |
656 | clk_zero_cnt * 2, | |
657 | 8); | |
658 | ||
659 | intel_dsi->clk_lp_to_hs_count += extra_byte_count; | |
660 | ||
661 | /* HS->LP for Clock Lanes | |
662 | * Low Power clock synchronisations + 1Tx byteclk + tclk_trail + | |
663 | * Extra byte count | |
664 | * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count | |
665 | * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 + | |
666 | * Extra byte count | |
667 | */ | |
668 | intel_dsi->clk_hs_to_lp_count = | |
669 | DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8, | |
670 | 8); | |
671 | intel_dsi->clk_hs_to_lp_count += extra_byte_count; | |
672 | ||
673 | DRM_DEBUG_KMS("Eot %s\n", intel_dsi->eotp_pkt ? "enabled" : "disabled"); | |
674 | DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi->clock_stop ? | |
675 | "disabled" : "enabled"); | |
676 | DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video"); | |
a9da9bce GS |
677 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) |
678 | DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n"); | |
679 | else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT) | |
680 | DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n"); | |
681 | else | |
682 | DRM_DEBUG_KMS("Dual link: NONE\n"); | |
2ab8b458 SK |
683 | DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format); |
684 | DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div); | |
685 | DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout); | |
686 | DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val); | |
687 | DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi->init_count); | |
688 | DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count); | |
689 | DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi->lp_byte_clk); | |
690 | DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi->bw_timer); | |
691 | DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count); | |
692 | DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count); | |
693 | DRM_DEBUG_KMS("BTA %s\n", | |
694 | intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA ? | |
695 | "disabled" : "enabled"); | |
696 | ||
697 | /* delays in VBT are in unit of 100us, so need to convert | |
698 | * here in ms | |
699 | * Delay (100us) * 100 /1000 = Delay / 10 (ms) */ | |
700 | intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10; | |
701 | intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10; | |
702 | intel_dsi->panel_on_delay = pps->panel_on_delay / 10; | |
703 | intel_dsi->panel_off_delay = pps->panel_off_delay / 10; | |
704 | intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10; | |
705 | ||
593e0622 JN |
706 | /* This is cheating a bit with the cleanup. */ |
707 | vbt_panel = devm_kzalloc(dev->dev, sizeof(*vbt_panel), GFP_KERNEL); | |
62ab420f IY |
708 | if (!vbt_panel) |
709 | return NULL; | |
2ab8b458 | 710 | |
593e0622 JN |
711 | vbt_panel->intel_dsi = intel_dsi; |
712 | drm_panel_init(&vbt_panel->panel); | |
713 | vbt_panel->panel.funcs = &vbt_panel_funcs; | |
714 | drm_panel_add(&vbt_panel->panel); | |
2ab8b458 | 715 | |
759d10c2 JN |
716 | /* a regular driver would get the device in probe */ |
717 | for_each_dsi_port(port, intel_dsi->ports) { | |
718 | mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device); | |
719 | } | |
720 | ||
593e0622 | 721 | return &vbt_panel->panel; |
2ab8b458 | 722 | } |