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2ab8b458 SK |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Author: Shobhit Kumar <shobhit.kumar@intel.com> | |
24 | * | |
25 | */ | |
26 | ||
27 | #include <drm/drmP.h> | |
28 | #include <drm/drm_crtc.h> | |
29 | #include <drm/drm_edid.h> | |
30 | #include <drm/i915_drm.h> | |
593e0622 | 31 | #include <drm/drm_panel.h> |
2ab8b458 SK |
32 | #include <linux/slab.h> |
33 | #include <video/mipi_display.h> | |
34 | #include <asm/intel-mid.h> | |
35 | #include <video/mipi_display.h> | |
36 | #include "i915_drv.h" | |
37 | #include "intel_drv.h" | |
38 | #include "intel_dsi.h" | |
2ab8b458 | 39 | |
593e0622 JN |
40 | struct vbt_panel { |
41 | struct drm_panel panel; | |
42 | struct intel_dsi *intel_dsi; | |
43 | }; | |
44 | ||
45 | static inline struct vbt_panel *to_vbt_panel(struct drm_panel *panel) | |
46 | { | |
47 | return container_of(panel, struct vbt_panel, panel); | |
48 | } | |
49 | ||
2ab8b458 SK |
50 | #define MIPI_TRANSFER_MODE_SHIFT 0 |
51 | #define MIPI_VIRTUAL_CHANNEL_SHIFT 1 | |
52 | #define MIPI_PORT_SHIFT 3 | |
53 | ||
54 | #define PREPARE_CNT_MAX 0x3F | |
55 | #define EXIT_ZERO_CNT_MAX 0x3F | |
56 | #define CLK_ZERO_CNT_MAX 0xFF | |
57 | #define TRAIL_CNT_MAX 0x1F | |
58 | ||
59 | #define NS_KHZ_RATIO 1000000 | |
60 | ||
61 | #define GPI0_NC_0_HV_DDI0_HPD 0x4130 | |
62 | #define GPIO_NC_0_HV_DDI0_PAD 0x4138 | |
63 | #define GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120 | |
64 | #define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD 0x4128 | |
65 | #define GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110 | |
66 | #define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD 0x4118 | |
67 | #define GPIO_NC_3_PANEL0_VDDEN 0x4140 | |
68 | #define GPIO_NC_3_PANEL0_VDDEN_PAD 0x4148 | |
69 | #define GPIO_NC_4_PANEL0_BLKEN 0x4150 | |
70 | #define GPIO_NC_4_PANEL0_BLKEN_PAD 0x4158 | |
71 | #define GPIO_NC_5_PANEL0_BLKCTL 0x4160 | |
72 | #define GPIO_NC_5_PANEL0_BLKCTL_PAD 0x4168 | |
73 | #define GPIO_NC_6_PCONF0 0x4180 | |
74 | #define GPIO_NC_6_PAD 0x4188 | |
75 | #define GPIO_NC_7_PCONF0 0x4190 | |
76 | #define GPIO_NC_7_PAD 0x4198 | |
77 | #define GPIO_NC_8_PCONF0 0x4170 | |
78 | #define GPIO_NC_8_PAD 0x4178 | |
79 | #define GPIO_NC_9_PCONF0 0x4100 | |
80 | #define GPIO_NC_9_PAD 0x4108 | |
81 | #define GPIO_NC_10_PCONF0 0x40E0 | |
82 | #define GPIO_NC_10_PAD 0x40E8 | |
83 | #define GPIO_NC_11_PCONF0 0x40F0 | |
84 | #define GPIO_NC_11_PAD 0x40F8 | |
85 | ||
86 | struct gpio_table { | |
87 | u16 function_reg; | |
88 | u16 pad_reg; | |
89 | u8 init; | |
90 | }; | |
91 | ||
92 | static struct gpio_table gtable[] = { | |
93 | { GPI0_NC_0_HV_DDI0_HPD, GPIO_NC_0_HV_DDI0_PAD, 0 }, | |
94 | { GPIO_NC_1_HV_DDI0_DDC_SDA, GPIO_NC_1_HV_DDI0_DDC_SDA_PAD, 0 }, | |
95 | { GPIO_NC_2_HV_DDI0_DDC_SCL, GPIO_NC_2_HV_DDI0_DDC_SCL_PAD, 0 }, | |
96 | { GPIO_NC_3_PANEL0_VDDEN, GPIO_NC_3_PANEL0_VDDEN_PAD, 0 }, | |
97 | { GPIO_NC_4_PANEL0_BLKEN, GPIO_NC_4_PANEL0_BLKEN_PAD, 0 }, | |
98 | { GPIO_NC_5_PANEL0_BLKCTL, GPIO_NC_5_PANEL0_BLKCTL_PAD, 0 }, | |
99 | { GPIO_NC_6_PCONF0, GPIO_NC_6_PAD, 0 }, | |
100 | { GPIO_NC_7_PCONF0, GPIO_NC_7_PAD, 0 }, | |
101 | { GPIO_NC_8_PCONF0, GPIO_NC_8_PAD, 0 }, | |
102 | { GPIO_NC_9_PCONF0, GPIO_NC_9_PAD, 0 }, | |
103 | { GPIO_NC_10_PCONF0, GPIO_NC_10_PAD, 0}, | |
104 | { GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0} | |
105 | }; | |
106 | ||
8f4d2683 GS |
107 | static inline enum port intel_dsi_seq_port_to_port(u8 port) |
108 | { | |
109 | return port ? PORT_C : PORT_A; | |
110 | } | |
111 | ||
5b48ca0f JN |
112 | static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, |
113 | const u8 *data) | |
2ab8b458 | 114 | { |
759d10c2 JN |
115 | struct mipi_dsi_device *dsi_device; |
116 | u8 type, flags, seq_port; | |
2ab8b458 | 117 | u16 len; |
8f4d2683 | 118 | enum port port; |
2ab8b458 | 119 | |
759d10c2 JN |
120 | flags = *data++; |
121 | type = *data++; | |
122 | ||
123 | len = *((u16 *) data); | |
124 | data += 2; | |
125 | ||
126 | seq_port = (flags >> MIPI_PORT_SHIFT) & 3; | |
2ab8b458 | 127 | |
f915084e GS |
128 | /* For DSI single link on Port A & C, the seq_port value which is |
129 | * parsed from Sequence Block#53 of VBT has been set to 0 | |
130 | * Now, read/write of packets for the DSI single link on Port A and | |
131 | * Port C will based on the DVO port from VBT block 2. | |
132 | */ | |
133 | if (intel_dsi->ports == (1 << PORT_C)) | |
134 | port = PORT_C; | |
135 | else | |
136 | port = intel_dsi_seq_port_to_port(seq_port); | |
2ab8b458 | 137 | |
759d10c2 JN |
138 | dsi_device = intel_dsi->dsi_hosts[port]->device; |
139 | if (!dsi_device) { | |
140 | DRM_DEBUG_KMS("no dsi device for port %c\n", port_name(port)); | |
141 | goto out; | |
142 | } | |
2ab8b458 | 143 | |
759d10c2 JN |
144 | if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1) |
145 | dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM; | |
146 | else | |
147 | dsi_device->mode_flags |= MIPI_DSI_MODE_LPM; | |
148 | ||
149 | dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3; | |
2ab8b458 SK |
150 | |
151 | switch (type) { | |
152 | case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: | |
759d10c2 | 153 | mipi_dsi_generic_write(dsi_device, NULL, 0); |
2ab8b458 SK |
154 | break; |
155 | case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: | |
759d10c2 | 156 | mipi_dsi_generic_write(dsi_device, data, 1); |
2ab8b458 SK |
157 | break; |
158 | case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: | |
759d10c2 | 159 | mipi_dsi_generic_write(dsi_device, data, 2); |
2ab8b458 SK |
160 | break; |
161 | case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: | |
162 | case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: | |
163 | case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: | |
164 | DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n"); | |
165 | break; | |
166 | case MIPI_DSI_GENERIC_LONG_WRITE: | |
759d10c2 | 167 | mipi_dsi_generic_write(dsi_device, data, len); |
2ab8b458 SK |
168 | break; |
169 | case MIPI_DSI_DCS_SHORT_WRITE: | |
759d10c2 | 170 | mipi_dsi_dcs_write_buffer(dsi_device, data, 1); |
2ab8b458 SK |
171 | break; |
172 | case MIPI_DSI_DCS_SHORT_WRITE_PARAM: | |
759d10c2 | 173 | mipi_dsi_dcs_write_buffer(dsi_device, data, 2); |
2ab8b458 SK |
174 | break; |
175 | case MIPI_DSI_DCS_READ: | |
176 | DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n"); | |
177 | break; | |
178 | case MIPI_DSI_DCS_LONG_WRITE: | |
759d10c2 | 179 | mipi_dsi_dcs_write_buffer(dsi_device, data, len); |
2ab8b458 | 180 | break; |
b5fbcd98 | 181 | } |
2ab8b458 | 182 | |
759d10c2 | 183 | out: |
2ab8b458 SK |
184 | data += len; |
185 | ||
186 | return data; | |
187 | } | |
188 | ||
5b48ca0f | 189 | static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data) |
2ab8b458 | 190 | { |
5b48ca0f | 191 | u32 delay = *((const u32 *) data); |
2ab8b458 SK |
192 | |
193 | usleep_range(delay, delay + 10); | |
194 | data += 4; | |
195 | ||
196 | return data; | |
197 | } | |
198 | ||
5b48ca0f | 199 | static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) |
2ab8b458 SK |
200 | { |
201 | u8 gpio, action; | |
202 | u16 function, pad; | |
203 | u32 val; | |
204 | struct drm_device *dev = intel_dsi->base.base.dev; | |
205 | struct drm_i915_private *dev_priv = dev->dev_private; | |
206 | ||
207 | gpio = *data++; | |
208 | ||
209 | /* pull up/down */ | |
210 | action = *data++; | |
211 | ||
212 | function = gtable[gpio].function_reg; | |
213 | pad = gtable[gpio].pad_reg; | |
214 | ||
a580516d | 215 | mutex_lock(&dev_priv->sb_lock); |
2ab8b458 SK |
216 | if (!gtable[gpio].init) { |
217 | /* program the function */ | |
218 | /* FIXME: remove constant below */ | |
219 | vlv_gpio_nc_write(dev_priv, function, 0x2000CC00); | |
220 | gtable[gpio].init = 1; | |
221 | } | |
222 | ||
223 | val = 0x4 | action; | |
224 | ||
225 | /* pull up/down */ | |
226 | vlv_gpio_nc_write(dev_priv, pad, val); | |
a580516d | 227 | mutex_unlock(&dev_priv->sb_lock); |
2ab8b458 SK |
228 | |
229 | return data; | |
230 | } | |
231 | ||
29bbdcb0 JN |
232 | static const u8 *mipi_exec_i2c_skip(struct intel_dsi *intel_dsi, const u8 *data) |
233 | { | |
234 | return data + *(data + 6) + 7; | |
235 | } | |
236 | ||
5b48ca0f JN |
237 | typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi, |
238 | const u8 *data); | |
2ab8b458 | 239 | static const fn_mipi_elem_exec exec_elem[] = { |
28c72840 JN |
240 | [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet, |
241 | [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay, | |
242 | [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio, | |
29bbdcb0 | 243 | [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c_skip, |
2ab8b458 SK |
244 | }; |
245 | ||
246 | /* | |
247 | * MIPI Sequence from VBT #53 parsing logic | |
248 | * We have already separated each seqence during bios parsing | |
249 | * Following is generic execution function for any sequence | |
250 | */ | |
251 | ||
252 | static const char * const seq_name[] = { | |
5cda0d20 JN |
253 | [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET", |
254 | [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP", | |
255 | [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON", | |
256 | [MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF", | |
257 | [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET", | |
2ab8b458 SK |
258 | }; |
259 | ||
5cda0d20 JN |
260 | static const char *sequence_name(enum mipi_seq seq_id) |
261 | { | |
262 | if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id]) | |
263 | return seq_name[seq_id]; | |
264 | else | |
265 | return "(unknown)"; | |
266 | } | |
267 | ||
5b48ca0f | 268 | static void generic_exec_sequence(struct intel_dsi *intel_dsi, const u8 *data) |
2ab8b458 | 269 | { |
2a33d934 | 270 | struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); |
2ab8b458 | 271 | fn_mipi_elem_exec mipi_elem_exec; |
2ab8b458 | 272 | |
5b48ca0f | 273 | if (!data) |
2ab8b458 SK |
274 | return; |
275 | ||
5cda0d20 JN |
276 | DRM_DEBUG_DRIVER("Starting MIPI sequence %u - %s\n", |
277 | *data, sequence_name(*data)); | |
2ab8b458 SK |
278 | |
279 | /* go to the first element of the sequence */ | |
280 | data++; | |
281 | ||
2a33d934 JN |
282 | /* Skip Size of Sequence. */ |
283 | if (dev_priv->vbt.dsi.seq_version >= 3) | |
284 | data += 4; | |
285 | ||
2ab8b458 SK |
286 | /* parse each byte till we reach end of sequence byte - 0x00 */ |
287 | while (1) { | |
28c72840 JN |
288 | u8 operation_byte = *data++; |
289 | if (operation_byte >= ARRAY_SIZE(exec_elem) || | |
290 | !exec_elem[operation_byte]) { | |
291 | DRM_ERROR("Unsupported MIPI operation byte %u\n", | |
292 | operation_byte); | |
2ab8b458 SK |
293 | return; |
294 | } | |
28c72840 | 295 | mipi_elem_exec = exec_elem[operation_byte]; |
2ab8b458 | 296 | |
2a33d934 JN |
297 | /* Skip Size of Operation. */ |
298 | if (dev_priv->vbt.dsi.seq_version >= 3) | |
299 | data++; | |
300 | ||
2ab8b458 SK |
301 | /* execute the element specific rotines */ |
302 | data = mipi_elem_exec(intel_dsi, data); | |
303 | ||
304 | /* | |
305 | * After processing the element, data should point to | |
306 | * next element or end of sequence | |
307 | * check if have we reached end of sequence | |
308 | */ | |
309 | if (*data == 0x00) | |
310 | break; | |
311 | } | |
312 | } | |
313 | ||
593e0622 JN |
314 | static int vbt_panel_prepare(struct drm_panel *panel) |
315 | { | |
316 | struct vbt_panel *vbt_panel = to_vbt_panel(panel); | |
317 | struct intel_dsi *intel_dsi = vbt_panel->intel_dsi; | |
318 | struct drm_device *dev = intel_dsi->base.base.dev; | |
319 | struct drm_i915_private *dev_priv = dev->dev_private; | |
320 | const u8 *sequence; | |
321 | ||
322 | sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET]; | |
323 | generic_exec_sequence(intel_dsi, sequence); | |
324 | ||
325 | sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP]; | |
326 | generic_exec_sequence(intel_dsi, sequence); | |
327 | ||
328 | return 0; | |
329 | } | |
330 | ||
331 | static int vbt_panel_unprepare(struct drm_panel *panel) | |
332 | { | |
333 | struct vbt_panel *vbt_panel = to_vbt_panel(panel); | |
334 | struct intel_dsi *intel_dsi = vbt_panel->intel_dsi; | |
335 | struct drm_device *dev = intel_dsi->base.base.dev; | |
336 | struct drm_i915_private *dev_priv = dev->dev_private; | |
337 | const u8 *sequence; | |
338 | ||
339 | sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET]; | |
340 | generic_exec_sequence(intel_dsi, sequence); | |
341 | ||
342 | return 0; | |
343 | } | |
344 | ||
345 | static int vbt_panel_enable(struct drm_panel *panel) | |
346 | { | |
347 | struct vbt_panel *vbt_panel = to_vbt_panel(panel); | |
348 | struct intel_dsi *intel_dsi = vbt_panel->intel_dsi; | |
349 | struct drm_device *dev = intel_dsi->base.base.dev; | |
350 | struct drm_i915_private *dev_priv = dev->dev_private; | |
351 | const u8 *sequence; | |
352 | ||
353 | sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_ON]; | |
354 | generic_exec_sequence(intel_dsi, sequence); | |
355 | ||
356 | return 0; | |
357 | } | |
358 | ||
359 | static int vbt_panel_disable(struct drm_panel *panel) | |
360 | { | |
361 | struct vbt_panel *vbt_panel = to_vbt_panel(panel); | |
362 | struct intel_dsi *intel_dsi = vbt_panel->intel_dsi; | |
363 | struct drm_device *dev = intel_dsi->base.base.dev; | |
364 | struct drm_i915_private *dev_priv = dev->dev_private; | |
365 | const u8 *sequence; | |
366 | ||
367 | sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_OFF]; | |
368 | generic_exec_sequence(intel_dsi, sequence); | |
369 | ||
370 | return 0; | |
371 | } | |
372 | ||
373 | static int vbt_panel_get_modes(struct drm_panel *panel) | |
374 | { | |
375 | struct vbt_panel *vbt_panel = to_vbt_panel(panel); | |
376 | struct intel_dsi *intel_dsi = vbt_panel->intel_dsi; | |
377 | struct drm_device *dev = intel_dsi->base.base.dev; | |
378 | struct drm_i915_private *dev_priv = dev->dev_private; | |
379 | struct drm_display_mode *mode; | |
380 | ||
381 | if (!panel->connector) | |
382 | return 0; | |
383 | ||
384 | mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode); | |
385 | if (!mode) | |
386 | return 0; | |
387 | ||
388 | mode->type |= DRM_MODE_TYPE_PREFERRED; | |
389 | ||
390 | drm_mode_probed_add(panel->connector, mode); | |
391 | ||
392 | return 1; | |
393 | } | |
394 | ||
395 | static const struct drm_panel_funcs vbt_panel_funcs = { | |
396 | .disable = vbt_panel_disable, | |
397 | .unprepare = vbt_panel_unprepare, | |
398 | .prepare = vbt_panel_prepare, | |
399 | .enable = vbt_panel_enable, | |
400 | .get_modes = vbt_panel_get_modes, | |
401 | }; | |
402 | ||
403 | struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id) | |
2ab8b458 | 404 | { |
2ab8b458 SK |
405 | struct drm_device *dev = intel_dsi->base.base.dev; |
406 | struct drm_i915_private *dev_priv = dev->dev_private; | |
407 | struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; | |
408 | struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps; | |
409 | struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode; | |
593e0622 | 410 | struct vbt_panel *vbt_panel; |
2ab8b458 SK |
411 | u32 bits_per_pixel = 24; |
412 | u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui; | |
413 | u32 ui_num, ui_den; | |
414 | u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; | |
415 | u32 ths_prepare_ns, tclk_trail_ns; | |
416 | u32 tclk_prepare_clkzero, ths_prepare_hszero; | |
417 | u32 lp_to_hs_switch, hs_to_lp_switch; | |
7f0c8605 SK |
418 | u32 pclk, computed_ddr; |
419 | u16 burst_mode_ratio; | |
759d10c2 | 420 | enum port port; |
2ab8b458 SK |
421 | |
422 | DRM_DEBUG_KMS("\n"); | |
423 | ||
424 | intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1; | |
425 | intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0; | |
426 | intel_dsi->lane_count = mipi_config->lane_cnt + 1; | |
427 | intel_dsi->pixel_format = mipi_config->videomode_color_format << 7; | |
369602d3 | 428 | intel_dsi->dual_link = mipi_config->dual_link; |
a9da9bce | 429 | intel_dsi->pixel_overlap = mipi_config->pixel_overlap; |
369602d3 | 430 | |
2ab8b458 SK |
431 | if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666) |
432 | bits_per_pixel = 18; | |
433 | else if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB565) | |
434 | bits_per_pixel = 16; | |
435 | ||
2ab8b458 SK |
436 | intel_dsi->operation_mode = mipi_config->is_cmd_mode; |
437 | intel_dsi->video_mode_format = mipi_config->video_transfer_mode; | |
438 | intel_dsi->escape_clk_div = mipi_config->byte_clk_sel; | |
439 | intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout; | |
440 | intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout; | |
441 | intel_dsi->rst_timer_val = mipi_config->device_reset_timer; | |
442 | intel_dsi->init_count = mipi_config->master_init_timer; | |
443 | intel_dsi->bw_timer = mipi_config->dbi_bw_timer; | |
b5fbcd98 SK |
444 | intel_dsi->video_frmt_cfg_bits = |
445 | mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0; | |
2ab8b458 | 446 | |
7f0c8605 SK |
447 | pclk = mode->clock; |
448 | ||
a9da9bce GS |
449 | /* In dual link mode each port needs half of pixel clock */ |
450 | if (intel_dsi->dual_link) { | |
451 | pclk = pclk / 2; | |
452 | ||
453 | /* we can enable pixel_overlap if needed by panel. In this | |
454 | * case we need to increase the pixelclock for extra pixels | |
455 | */ | |
456 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { | |
457 | pclk += DIV_ROUND_UP(mode->vtotal * | |
458 | intel_dsi->pixel_overlap * | |
459 | 60, 1000); | |
460 | } | |
461 | } | |
462 | ||
7f0c8605 SK |
463 | /* Burst Mode Ratio |
464 | * Target ddr frequency from VBT / non burst ddr freq | |
465 | * multiply by 100 to preserve remainder | |
466 | */ | |
467 | if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) { | |
468 | if (mipi_config->target_burst_mode_freq) { | |
469 | computed_ddr = | |
470 | (pclk * bits_per_pixel) / intel_dsi->lane_count; | |
471 | ||
472 | if (mipi_config->target_burst_mode_freq < | |
473 | computed_ddr) { | |
474 | DRM_ERROR("Burst mode freq is less than computed\n"); | |
593e0622 | 475 | return NULL; |
7f0c8605 SK |
476 | } |
477 | ||
478 | burst_mode_ratio = DIV_ROUND_UP( | |
479 | mipi_config->target_burst_mode_freq * 100, | |
480 | computed_ddr); | |
481 | ||
482 | pclk = DIV_ROUND_UP(pclk * burst_mode_ratio, 100); | |
483 | } else { | |
484 | DRM_ERROR("Burst mode target is not set\n"); | |
593e0622 | 485 | return NULL; |
7f0c8605 SK |
486 | } |
487 | } else | |
488 | burst_mode_ratio = 100; | |
489 | ||
490 | intel_dsi->burst_mode_ratio = burst_mode_ratio; | |
491 | intel_dsi->pclk = pclk; | |
492 | ||
493 | bitrate = (pclk * bits_per_pixel) / intel_dsi->lane_count; | |
494 | ||
2ab8b458 SK |
495 | switch (intel_dsi->escape_clk_div) { |
496 | case 0: | |
497 | tlpx_ns = 50; | |
498 | break; | |
499 | case 1: | |
500 | tlpx_ns = 100; | |
501 | break; | |
502 | ||
503 | case 2: | |
504 | tlpx_ns = 200; | |
505 | break; | |
506 | default: | |
507 | tlpx_ns = 50; | |
508 | break; | |
509 | } | |
510 | ||
511 | switch (intel_dsi->lane_count) { | |
512 | case 1: | |
513 | case 2: | |
514 | extra_byte_count = 2; | |
515 | break; | |
516 | case 3: | |
517 | extra_byte_count = 4; | |
518 | break; | |
519 | case 4: | |
520 | default: | |
521 | extra_byte_count = 3; | |
522 | break; | |
523 | } | |
524 | ||
525 | /* | |
526 | * ui(s) = 1/f [f in hz] | |
527 | * ui(ns) = 10^9 / (f*10^6) [f in Mhz] -> 10^3/f(Mhz) | |
528 | */ | |
529 | ||
530 | /* in Kbps */ | |
531 | ui_num = NS_KHZ_RATIO; | |
532 | ui_den = bitrate; | |
533 | ||
534 | tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero; | |
535 | ths_prepare_hszero = mipi_config->ths_prepare_hszero; | |
536 | ||
537 | /* | |
538 | * B060 | |
539 | * LP byte clock = TLPX/ (8UI) | |
540 | */ | |
541 | intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num); | |
542 | ||
543 | /* count values in UI = (ns value) * (bitrate / (2 * 10^6)) | |
544 | * | |
545 | * Since txddrclkhs_i is 2xUI, all the count values programmed in | |
546 | * DPHY param register are divided by 2 | |
547 | * | |
548 | * prepare count | |
549 | */ | |
b5fbcd98 SK |
550 | ths_prepare_ns = max(mipi_config->ths_prepare, |
551 | mipi_config->tclk_prepare); | |
2ab8b458 SK |
552 | prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2); |
553 | ||
554 | /* exit zero count */ | |
555 | exit_zero_cnt = DIV_ROUND_UP( | |
556 | (ths_prepare_hszero - ths_prepare_ns) * ui_den, | |
557 | ui_num * 2 | |
558 | ); | |
559 | ||
560 | /* | |
561 | * Exit zero is unified val ths_zero and ths_exit | |
562 | * minimum value for ths_exit = 110ns | |
563 | * min (exit_zero_cnt * 2) = 110/UI | |
564 | * exit_zero_cnt = 55/UI | |
565 | */ | |
566 | if (exit_zero_cnt < (55 * ui_den / ui_num)) | |
567 | if ((55 * ui_den) % ui_num) | |
568 | exit_zero_cnt += 1; | |
569 | ||
570 | /* clk zero count */ | |
571 | clk_zero_cnt = DIV_ROUND_UP( | |
572 | (tclk_prepare_clkzero - ths_prepare_ns) | |
573 | * ui_den, 2 * ui_num); | |
574 | ||
575 | /* trail count */ | |
576 | tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); | |
577 | trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num); | |
578 | ||
579 | if (prepare_cnt > PREPARE_CNT_MAX || | |
580 | exit_zero_cnt > EXIT_ZERO_CNT_MAX || | |
581 | clk_zero_cnt > CLK_ZERO_CNT_MAX || | |
582 | trail_cnt > TRAIL_CNT_MAX) | |
583 | DRM_DEBUG_DRIVER("Values crossing maximum limits, restricting to max values\n"); | |
584 | ||
585 | if (prepare_cnt > PREPARE_CNT_MAX) | |
586 | prepare_cnt = PREPARE_CNT_MAX; | |
587 | ||
588 | if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) | |
589 | exit_zero_cnt = EXIT_ZERO_CNT_MAX; | |
590 | ||
591 | if (clk_zero_cnt > CLK_ZERO_CNT_MAX) | |
592 | clk_zero_cnt = CLK_ZERO_CNT_MAX; | |
593 | ||
594 | if (trail_cnt > TRAIL_CNT_MAX) | |
595 | trail_cnt = TRAIL_CNT_MAX; | |
596 | ||
597 | /* B080 */ | |
598 | intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 | | |
599 | clk_zero_cnt << 8 | prepare_cnt; | |
600 | ||
601 | /* | |
602 | * LP to HS switch count = 4TLPX + PREP_COUNT * 2 + EXIT_ZERO_COUNT * 2 | |
603 | * + 10UI + Extra Byte Count | |
604 | * | |
605 | * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count | |
606 | * Extra Byte Count is calculated according to number of lanes. | |
607 | * High Low Switch Count is the Max of LP to HS and | |
608 | * HS to LP switch count | |
609 | * | |
610 | */ | |
611 | tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num); | |
612 | ||
613 | /* B044 */ | |
614 | /* FIXME: | |
615 | * The comment above does not match with the code */ | |
616 | lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * 2 + | |
617 | exit_zero_cnt * 2 + 10, 8); | |
618 | ||
619 | hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8); | |
620 | ||
621 | intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch); | |
622 | intel_dsi->hs_to_lp_count += extra_byte_count; | |
623 | ||
624 | /* B088 */ | |
625 | /* LP -> HS for clock lanes | |
626 | * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero + | |
627 | * extra byte count | |
628 | * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt * | |
629 | * 2(in UI) + extra byte count | |
630 | * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) / | |
631 | * 8 + extra byte count | |
632 | */ | |
633 | intel_dsi->clk_lp_to_hs_count = | |
634 | DIV_ROUND_UP( | |
635 | 4 * tlpx_ui + prepare_cnt * 2 + | |
636 | clk_zero_cnt * 2, | |
637 | 8); | |
638 | ||
639 | intel_dsi->clk_lp_to_hs_count += extra_byte_count; | |
640 | ||
641 | /* HS->LP for Clock Lanes | |
642 | * Low Power clock synchronisations + 1Tx byteclk + tclk_trail + | |
643 | * Extra byte count | |
644 | * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count | |
645 | * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 + | |
646 | * Extra byte count | |
647 | */ | |
648 | intel_dsi->clk_hs_to_lp_count = | |
649 | DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8, | |
650 | 8); | |
651 | intel_dsi->clk_hs_to_lp_count += extra_byte_count; | |
652 | ||
653 | DRM_DEBUG_KMS("Eot %s\n", intel_dsi->eotp_pkt ? "enabled" : "disabled"); | |
654 | DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi->clock_stop ? | |
655 | "disabled" : "enabled"); | |
656 | DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video"); | |
a9da9bce GS |
657 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) |
658 | DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n"); | |
659 | else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT) | |
660 | DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n"); | |
661 | else | |
662 | DRM_DEBUG_KMS("Dual link: NONE\n"); | |
2ab8b458 SK |
663 | DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format); |
664 | DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div); | |
665 | DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout); | |
666 | DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val); | |
667 | DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi->init_count); | |
668 | DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count); | |
669 | DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi->lp_byte_clk); | |
670 | DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi->bw_timer); | |
671 | DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count); | |
672 | DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count); | |
673 | DRM_DEBUG_KMS("BTA %s\n", | |
674 | intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA ? | |
675 | "disabled" : "enabled"); | |
676 | ||
677 | /* delays in VBT are in unit of 100us, so need to convert | |
678 | * here in ms | |
679 | * Delay (100us) * 100 /1000 = Delay / 10 (ms) */ | |
680 | intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10; | |
681 | intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10; | |
682 | intel_dsi->panel_on_delay = pps->panel_on_delay / 10; | |
683 | intel_dsi->panel_off_delay = pps->panel_off_delay / 10; | |
684 | intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10; | |
685 | ||
593e0622 JN |
686 | /* This is cheating a bit with the cleanup. */ |
687 | vbt_panel = devm_kzalloc(dev->dev, sizeof(*vbt_panel), GFP_KERNEL); | |
62ab420f IY |
688 | if (!vbt_panel) |
689 | return NULL; | |
2ab8b458 | 690 | |
593e0622 JN |
691 | vbt_panel->intel_dsi = intel_dsi; |
692 | drm_panel_init(&vbt_panel->panel); | |
693 | vbt_panel->panel.funcs = &vbt_panel_funcs; | |
694 | drm_panel_add(&vbt_panel->panel); | |
2ab8b458 | 695 | |
759d10c2 JN |
696 | /* a regular driver would get the device in probe */ |
697 | for_each_dsi_port(port, intel_dsi->ports) { | |
698 | mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device); | |
699 | } | |
700 | ||
593e0622 | 701 | return &vbt_panel->panel; |
2ab8b458 | 702 | } |