[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dsi_panel_vbt.c

/*
 * Copyright © 2014 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Author: Shobhit Kumar <shobhit.kumar@intel.com>
 *
 */

#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <drm/drm_edid.h>
#include <drm/i915_drm.h>
#include <linux/slab.h>
#include <video/mipi_display.h>
#include <asm/intel-mid.h>
#include <video/mipi_display.h>
#include "i915_drv.h"
#include "intel_drv.h"
#include "intel_dsi.h"
#include "intel_dsi_cmd.h"

#define MIPI_TRANSFER_MODE_SHIFT	0
#define MIPI_VIRTUAL_CHANNEL_SHIFT	1
#define MIPI_PORT_SHIFT			3

#define PREPARE_CNT_MAX		0x3F
#define EXIT_ZERO_CNT_MAX	0x3F
#define CLK_ZERO_CNT_MAX	0xFF
#define TRAIL_CNT_MAX		0x1F

#define NS_KHZ_RATIO 1000000

#define GPI0_NC_0_HV_DDI0_HPD           0x4130
#define GPIO_NC_0_HV_DDI0_PAD           0x4138
#define GPIO_NC_1_HV_DDI0_DDC_SDA       0x4120
#define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD   0x4128
#define GPIO_NC_2_HV_DDI0_DDC_SCL       0x4110
#define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD   0x4118
#define GPIO_NC_3_PANEL0_VDDEN          0x4140
#define GPIO_NC_3_PANEL0_VDDEN_PAD      0x4148
#define GPIO_NC_4_PANEL0_BLKEN          0x4150
#define GPIO_NC_4_PANEL0_BLKEN_PAD      0x4158
#define GPIO_NC_5_PANEL0_BLKCTL         0x4160
#define GPIO_NC_5_PANEL0_BLKCTL_PAD     0x4168
#define GPIO_NC_6_PCONF0                0x4180
#define GPIO_NC_6_PAD                   0x4188
#define GPIO_NC_7_PCONF0                0x4190
#define GPIO_NC_7_PAD                   0x4198
#define GPIO_NC_8_PCONF0                0x4170
#define GPIO_NC_8_PAD                   0x4178
#define GPIO_NC_9_PCONF0                0x4100
#define GPIO_NC_9_PAD                   0x4108
#define GPIO_NC_10_PCONF0               0x40E0
#define GPIO_NC_10_PAD                  0x40E8
#define GPIO_NC_11_PCONF0               0x40F0
#define GPIO_NC_11_PAD                  0x40F8

struct gpio_table {
	u16 function_reg;
	u16 pad_reg;
	u8 init;
};

static struct gpio_table gtable[] = {
	{ GPI0_NC_0_HV_DDI0_HPD, GPIO_NC_0_HV_DDI0_PAD, 0 },
	{ GPIO_NC_1_HV_DDI0_DDC_SDA, GPIO_NC_1_HV_DDI0_DDC_SDA_PAD, 0 },
	{ GPIO_NC_2_HV_DDI0_DDC_SCL, GPIO_NC_2_HV_DDI0_DDC_SCL_PAD, 0 },
	{ GPIO_NC_3_PANEL0_VDDEN, GPIO_NC_3_PANEL0_VDDEN_PAD, 0 },
	{ GPIO_NC_4_PANEL0_BLKEN, GPIO_NC_4_PANEL0_BLKEN_PAD, 0 },
	{ GPIO_NC_5_PANEL0_BLKCTL, GPIO_NC_5_PANEL0_BLKCTL_PAD, 0 },
	{ GPIO_NC_6_PCONF0, GPIO_NC_6_PAD, 0 },
	{ GPIO_NC_7_PCONF0, GPIO_NC_7_PAD, 0 },
	{ GPIO_NC_8_PCONF0, GPIO_NC_8_PAD, 0 },
	{ GPIO_NC_9_PCONF0, GPIO_NC_9_PAD, 0 },
	{ GPIO_NC_10_PCONF0, GPIO_NC_10_PAD, 0},
	{ GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0}
};

static inline enum port intel_dsi_seq_port_to_port(u8 port)
{
	return port ? PORT_C : PORT_A;
}

static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data)
{
	u8 type, byte, mode, vc, seq_port;
	u16 len;
	enum port port;

	byte = *data++;
	mode = (byte >> MIPI_TRANSFER_MODE_SHIFT) & 0x1;
	vc = (byte >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 0x3;
	seq_port = (byte >> MIPI_PORT_SHIFT) & 0x3;

	/* For DSI single link on Port A & C, the seq_port value which is
	 * parsed from Sequence Block#53 of VBT has been set to 0
	 * Now, read/write of packets for the DSI single link on Port A and
	 * Port C will based on the DVO port from VBT block 2.
	 */
	if (intel_dsi->ports == (1 << PORT_C))
		port = PORT_C;
	else
		port = intel_dsi_seq_port_to_port(seq_port);
	/* LP or HS mode */
	intel_dsi->hs = mode;

	/* get packet type and increment the pointer */
	type = *data++;

	len = *((u16 *) data);
	data += 2;

	switch (type) {
	case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
		dsi_vc_generic_write_0(intel_dsi, vc, port);
		break;
	case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
		dsi_vc_generic_write_1(intel_dsi, vc, *data, port);
		break;
	case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
		dsi_vc_generic_write_2(intel_dsi, vc, *data, *(data + 1), port);
		break;
	case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
	case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
	case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
		DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n");
		break;
	case MIPI_DSI_GENERIC_LONG_WRITE:
		dsi_vc_generic_write(intel_dsi, vc, data, len, port);
		break;
	case MIPI_DSI_DCS_SHORT_WRITE:
		dsi_vc_dcs_write_0(intel_dsi, vc, *data, port);
		break;
	case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
		dsi_vc_dcs_write_1(intel_dsi, vc, *data, *(data + 1), port);
		break;
	case MIPI_DSI_DCS_READ:
		DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n");
		break;
	case MIPI_DSI_DCS_LONG_WRITE:
		dsi_vc_dcs_write(intel_dsi, vc, data, len, port);
		break;
	}

	data += len;

	return data;
}

static u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, u8 *data)
{
	u32 delay = *((u32 *) data);

	usleep_range(delay, delay + 10);
	data += 4;

	return data;
}

static u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, u8 *data)
{
	u8 gpio, action;
	u16 function, pad;
	u32 val;
	struct drm_device *dev = intel_dsi->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	gpio = *data++;

	/* pull up/down */
	action = *data++;

	function = gtable[gpio].function_reg;
	pad = gtable[gpio].pad_reg;

	mutex_lock(&dev_priv->dpio_lock);
	if (!gtable[gpio].init) {
		/* program the function */
		/* FIXME: remove constant below */
		vlv_gpio_nc_write(dev_priv, function, 0x2000CC00);
		gtable[gpio].init = 1;
	}

	val = 0x4 | action;

	/* pull up/down */
	vlv_gpio_nc_write(dev_priv, pad, val);
	mutex_unlock(&dev_priv->dpio_lock);

	return data;
}

typedef u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi, u8 *data);
static const fn_mipi_elem_exec exec_elem[] = {
	NULL, /* reserved */
	mipi_exec_send_packet,
	mipi_exec_delay,
	mipi_exec_gpio,
	NULL, /* status read; later */
};

/*
 * MIPI Sequence from VBT #53 parsing logic
 * We have already separated each seqence during bios parsing
 * Following is generic execution function for any sequence
 */

static const char * const seq_name[] = {
	"UNDEFINED",
	"MIPI_SEQ_ASSERT_RESET",
	"MIPI_SEQ_INIT_OTP",
	"MIPI_SEQ_DISPLAY_ON",
	"MIPI_SEQ_DISPLAY_OFF",
	"MIPI_SEQ_DEASSERT_RESET"
};

static void generic_exec_sequence(struct intel_dsi *intel_dsi, char *sequence)
{
	u8 *data = sequence;
	fn_mipi_elem_exec mipi_elem_exec;
	int index;

	if (!sequence)
		return;

	DRM_DEBUG_DRIVER("Starting MIPI sequence - %s\n", seq_name[*data]);

	/* go to the first element of the sequence */
	data++;

	/* parse each byte till we reach end of sequence byte - 0x00 */
	while (1) {
		index = *data;
		mipi_elem_exec = exec_elem[index];
		if (!mipi_elem_exec) {
			DRM_ERROR("Unsupported MIPI element, skipping sequence execution\n");
			return;
		}

		/* goto element payload */
		data++;

		/* execute the element specific rotines */
		data = mipi_elem_exec(intel_dsi, data);

		/*
		 * After processing the element, data should point to
		 * next element or end of sequence
		 * check if have we reached end of sequence
		 */
		if (*data == 0x00)
			break;
	}
}

static bool generic_init(struct intel_dsi_device *dsi)
{
	struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
	struct drm_device *dev = intel_dsi->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
	struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
	struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
	u32 bits_per_pixel = 24;
	u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui;
	u32 ui_num, ui_den;
	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
	u32 ths_prepare_ns, tclk_trail_ns;
	u32 tclk_prepare_clkzero, ths_prepare_hszero;
	u32 lp_to_hs_switch, hs_to_lp_switch;
	u32 pclk, computed_ddr;
	u16 burst_mode_ratio;

	DRM_DEBUG_KMS("\n");

	intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
	intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
	intel_dsi->lane_count = mipi_config->lane_cnt + 1;
	intel_dsi->pixel_format = mipi_config->videomode_color_format << 7;
	intel_dsi->dual_link = mipi_config->dual_link;
	intel_dsi->pixel_overlap = mipi_config->pixel_overlap;

	if (intel_dsi->dual_link)
		intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));

	if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666)
		bits_per_pixel = 18;
	else if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB565)
		bits_per_pixel = 16;

	intel_dsi->operation_mode = mipi_config->is_cmd_mode;
	intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
	intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
	intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
	intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
	intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
	intel_dsi->init_count = mipi_config->master_init_timer;
	intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
	intel_dsi->video_frmt_cfg_bits =
		mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;

	pclk = mode->clock;

	/* In dual link mode each port needs half of pixel clock */
	if (intel_dsi->dual_link) {
		pclk = pclk / 2;

		/* we can enable pixel_overlap if needed by panel. In this
		 * case we need to increase the pixelclock for extra pixels
		 */
		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
			pclk += DIV_ROUND_UP(mode->vtotal *
						intel_dsi->pixel_overlap *
						60, 1000);
		}
	}

	/* Burst Mode Ratio
	 * Target ddr frequency from VBT / non burst ddr freq
	 * multiply by 100 to preserve remainder
	 */
	if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
		if (mipi_config->target_burst_mode_freq) {
			computed_ddr =
				(pclk * bits_per_pixel) / intel_dsi->lane_count;

			if (mipi_config->target_burst_mode_freq <
								computed_ddr) {
				DRM_ERROR("Burst mode freq is less than computed\n");
				return false;
			}

			burst_mode_ratio = DIV_ROUND_UP(
				mipi_config->target_burst_mode_freq * 100,
				computed_ddr);

			pclk = DIV_ROUND_UP(pclk * burst_mode_ratio, 100);
		} else {
			DRM_ERROR("Burst mode target is not set\n");
			return false;
		}
	} else
		burst_mode_ratio = 100;

	intel_dsi->burst_mode_ratio = burst_mode_ratio;
	intel_dsi->pclk = pclk;

	bitrate = (pclk * bits_per_pixel) / intel_dsi->lane_count;

	switch (intel_dsi->escape_clk_div) {
	case 0:
		tlpx_ns = 50;
		break;
	case 1:
		tlpx_ns = 100;
		break;

	case 2:
		tlpx_ns = 200;
		break;
	default:
		tlpx_ns = 50;
		break;
	}

	switch (intel_dsi->lane_count) {
	case 1:
	case 2:
		extra_byte_count = 2;
		break;
	case 3:
		extra_byte_count = 4;
		break;
	case 4:
	default:
		extra_byte_count = 3;
		break;
	}

	/*
	 * ui(s) = 1/f [f in hz]
	 * ui(ns) = 10^9 / (f*10^6) [f in Mhz] -> 10^3/f(Mhz)
	 */

	/* in Kbps */
	ui_num = NS_KHZ_RATIO;
	ui_den = bitrate;

	tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
	ths_prepare_hszero = mipi_config->ths_prepare_hszero;

	/*
	 * B060
	 * LP byte clock = TLPX/ (8UI)
	 */
	intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);

	/* count values in UI = (ns value) * (bitrate / (2 * 10^6))
	 *
	 * Since txddrclkhs_i is 2xUI, all the count values programmed in
	 * DPHY param register are divided by 2
	 *
	 * prepare count
	 */
	ths_prepare_ns = max(mipi_config->ths_prepare,
			     mipi_config->tclk_prepare);
	prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2);

	/* exit zero count */
	exit_zero_cnt = DIV_ROUND_UP(
				(ths_prepare_hszero - ths_prepare_ns) * ui_den,
				ui_num * 2
				);

	/*
	 * Exit zero  is unified val ths_zero and ths_exit
	 * minimum value for ths_exit = 110ns
	 * min (exit_zero_cnt * 2) = 110/UI
	 * exit_zero_cnt = 55/UI
	 */
	 if (exit_zero_cnt < (55 * ui_den / ui_num))
		if ((55 * ui_den) % ui_num)
			exit_zero_cnt += 1;

	/* clk zero count */
	clk_zero_cnt = DIV_ROUND_UP(
			(tclk_prepare_clkzero -	ths_prepare_ns)
			* ui_den, 2 * ui_num);

	/* trail count */
	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
	trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);

	if (prepare_cnt > PREPARE_CNT_MAX ||
		exit_zero_cnt > EXIT_ZERO_CNT_MAX ||
		clk_zero_cnt > CLK_ZERO_CNT_MAX ||
		trail_cnt > TRAIL_CNT_MAX)
		DRM_DEBUG_DRIVER("Values crossing maximum limits, restricting to max values\n");

	if (prepare_cnt > PREPARE_CNT_MAX)
		prepare_cnt = PREPARE_CNT_MAX;

	if (exit_zero_cnt > EXIT_ZERO_CNT_MAX)
		exit_zero_cnt = EXIT_ZERO_CNT_MAX;

	if (clk_zero_cnt > CLK_ZERO_CNT_MAX)
		clk_zero_cnt = CLK_ZERO_CNT_MAX;

	if (trail_cnt > TRAIL_CNT_MAX)
		trail_cnt = TRAIL_CNT_MAX;

	/* B080 */
	intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
						clk_zero_cnt << 8 | prepare_cnt;

	/*
	 * LP to HS switch count = 4TLPX + PREP_COUNT * 2 + EXIT_ZERO_COUNT * 2
	 *					+ 10UI + Extra Byte Count
	 *
	 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
	 * Extra Byte Count is calculated according to number of lanes.
	 * High Low Switch Count is the Max of LP to HS and
	 * HS to LP switch count
	 *
	 */
	tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);

	/* B044 */
	/* FIXME:
	 * The comment above does not match with the code */
	lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * 2 +
						exit_zero_cnt * 2 + 10, 8);

	hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);

	intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
	intel_dsi->hs_to_lp_count += extra_byte_count;

	/* B088 */
	/* LP -> HS for clock lanes
	 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
	 *						extra byte count
	 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
	 *					2(in UI) + extra byte count
	 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
	 *					8 + extra byte count
	 */
	intel_dsi->clk_lp_to_hs_count =
		DIV_ROUND_UP(
			4 * tlpx_ui + prepare_cnt * 2 +
			clk_zero_cnt * 2,
			8);

	intel_dsi->clk_lp_to_hs_count += extra_byte_count;

	/* HS->LP for Clock Lanes
	 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
	 *						Extra byte count
	 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
	 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
	 *						Extra byte count
	 */
	intel_dsi->clk_hs_to_lp_count =
		DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
			8);
	intel_dsi->clk_hs_to_lp_count += extra_byte_count;

	DRM_DEBUG_KMS("Eot %s\n", intel_dsi->eotp_pkt ? "enabled" : "disabled");
	DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi->clock_stop ?
						"disabled" : "enabled");
	DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video");
	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
		DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
	else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
		DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
	else
		DRM_DEBUG_KMS("Dual link: NONE\n");
	DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
	DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
	DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout);
	DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val);
	DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi->init_count);
	DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count);
	DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi->lp_byte_clk);
	DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi->bw_timer);
	DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count);
	DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count);
	DRM_DEBUG_KMS("BTA %s\n",
			intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA ?
			"disabled" : "enabled");

	/* delays in VBT are in unit of 100us, so need to convert
	 * here in ms
	 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
	intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
	intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
	intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
	intel_dsi->panel_off_delay = pps->panel_off_delay / 10;
	intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;

	return true;
}

static void generic_panel_reset(struct intel_dsi_device *dsi)
{
	struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
	struct drm_device *dev = intel_dsi->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET];

	generic_exec_sequence(intel_dsi, sequence);

	sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];
	generic_exec_sequence(intel_dsi, sequence);
}

static void generic_disable_panel_power(struct intel_dsi_device *dsi)
{
	struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
	struct drm_device *dev = intel_dsi->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET];

	generic_exec_sequence(intel_dsi, sequence);
}

static void generic_enable(struct intel_dsi_device *dsi)
{
	struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
	struct drm_device *dev = intel_dsi->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_ON];

	generic_exec_sequence(intel_dsi, sequence);
}

static void generic_disable(struct intel_dsi_device *dsi)
{
	struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
	struct drm_device *dev = intel_dsi->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_OFF];

	generic_exec_sequence(intel_dsi, sequence);
}

static struct drm_display_mode *generic_get_modes(struct intel_dsi_device *dsi)
{
	struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
	struct drm_device *dev = intel_dsi->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	dev_priv->vbt.lfp_lvds_vbt_mode->type |= DRM_MODE_TYPE_PREFERRED;
	return dev_priv->vbt.lfp_lvds_vbt_mode;
}

struct intel_dsi_dev_ops vbt_generic_dsi_display_ops = {
	.init = generic_init,
	.panel_reset = generic_panel_reset,
	.disable_panel_power = generic_disable_panel_power,
	.enable = generic_enable,
	.disable = generic_disable,
	.get_modes = generic_get_modes,
};
Commit	Line	Data
2ab8b458 SK	1	/*
	2	* Copyright © 2014 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*
	23	* Author: Shobhit Kumar <shobhit.kumar@intel.com>
	24	*
	25	*/
	26
	27	#include <drm/drmP.h>
	28	#include <drm/drm_crtc.h>
	29	#include <drm/drm_edid.h>
	30	#include <drm/i915_drm.h>
	31	#include <linux/slab.h>
	32	#include <video/mipi_display.h>
	33	#include <asm/intel-mid.h>
	34	#include <video/mipi_display.h>
	35	#include "i915_drv.h"
	36	#include "intel_drv.h"
	37	#include "intel_dsi.h"
	38	#include "intel_dsi_cmd.h"
	39
	40	#define MIPI_TRANSFER_MODE_SHIFT 0
	41	#define MIPI_VIRTUAL_CHANNEL_SHIFT 1
	42	#define MIPI_PORT_SHIFT 3
	43
	44	#define PREPARE_CNT_MAX 0x3F
	45	#define EXIT_ZERO_CNT_MAX 0x3F
	46	#define CLK_ZERO_CNT_MAX 0xFF
	47	#define TRAIL_CNT_MAX 0x1F
	48
	49	#define NS_KHZ_RATIO 1000000
	50
	51	#define GPI0_NC_0_HV_DDI0_HPD 0x4130
	52	#define GPIO_NC_0_HV_DDI0_PAD 0x4138
	53	#define GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
	54	#define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD 0x4128
	55	#define GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
	56	#define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD 0x4118
	57	#define GPIO_NC_3_PANEL0_VDDEN 0x4140
	58	#define GPIO_NC_3_PANEL0_VDDEN_PAD 0x4148
	59	#define GPIO_NC_4_PANEL0_BLKEN 0x4150
	60	#define GPIO_NC_4_PANEL0_BLKEN_PAD 0x4158
	61	#define GPIO_NC_5_PANEL0_BLKCTL 0x4160
	62	#define GPIO_NC_5_PANEL0_BLKCTL_PAD 0x4168
	63	#define GPIO_NC_6_PCONF0 0x4180
	64	#define GPIO_NC_6_PAD 0x4188
65	#define GPIO_NC_7_PCONF0 0x4190
66	#define GPIO_NC_7_PAD 0x4198
67	#define GPIO_NC_8_PCONF0 0x4170
68	#define GPIO_NC_8_PAD 0x4178
69	#define GPIO_NC_9_PCONF0 0x4100
70	#define GPIO_NC_9_PAD 0x4108
71	#define GPIO_NC_10_PCONF0 0x40E0
72	#define GPIO_NC_10_PAD 0x40E8
73	#define GPIO_NC_11_PCONF0 0x40F0
74	#define GPIO_NC_11_PAD 0x40F8
75
76	struct gpio_table {
77	u16 function_reg;
78	u16 pad_reg;
79	u8 init;
80	};
81
82	static struct gpio_table gtable[] = {
83	{ GPI0_NC_0_HV_DDI0_HPD, GPIO_NC_0_HV_DDI0_PAD, 0 },
84	{ GPIO_NC_1_HV_DDI0_DDC_SDA, GPIO_NC_1_HV_DDI0_DDC_SDA_PAD, 0 },
85	{ GPIO_NC_2_HV_DDI0_DDC_SCL, GPIO_NC_2_HV_DDI0_DDC_SCL_PAD, 0 },
86	{ GPIO_NC_3_PANEL0_VDDEN, GPIO_NC_3_PANEL0_VDDEN_PAD, 0 },
87	{ GPIO_NC_4_PANEL0_BLKEN, GPIO_NC_4_PANEL0_BLKEN_PAD, 0 },
88	{ GPIO_NC_5_PANEL0_BLKCTL, GPIO_NC_5_PANEL0_BLKCTL_PAD, 0 },
89	{ GPIO_NC_6_PCONF0, GPIO_NC_6_PAD, 0 },
90	{ GPIO_NC_7_PCONF0, GPIO_NC_7_PAD, 0 },
91	{ GPIO_NC_8_PCONF0, GPIO_NC_8_PAD, 0 },
92	{ GPIO_NC_9_PCONF0, GPIO_NC_9_PAD, 0 },
93	{ GPIO_NC_10_PCONF0, GPIO_NC_10_PAD, 0},
94	{ GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0}
95	};
96
8f4d2683 GS	97	static inline enum port intel_dsi_seq_port_to_port(u8 port)
	98	{
	99	return port ? PORT_C : PORT_A;
	100	}
	101
2ab8b458 SK	102	static u8 mipi_exec_send_packet(struct intel_dsi intel_dsi, u8 *data)
2ab8b458 SK	103	{
8f4d2683	104	u8 type, byte, mode, vc, seq_port;
2ab8b458	105	u16 len;
8f4d2683	106	enum port port;
2ab8b458 SK	107
	108	byte = *data++;
	109	mode = (byte >> MIPI_TRANSFER_MODE_SHIFT) & 0x1;
	110	vc = (byte >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 0x3;
8f4d2683	111	seq_port = (byte >> MIPI_PORT_SHIFT) & 0x3;
2ab8b458	112
f915084e GS	113	/* For DSI single link on Port A & C, the seq_port value which is
	114	* parsed from Sequence Block#53 of VBT has been set to 0
	115	* Now, read/write of packets for the DSI single link on Port A and
	116	* Port C will based on the DVO port from VBT block 2.
	117	*/
	118	if (intel_dsi->ports == (1 << PORT_C))
	119	port = PORT_C;
	120	else
	121	port = intel_dsi_seq_port_to_port(seq_port);
2ab8b458 SK	122	/* LP or HS mode */
	123	intel_dsi->hs = mode;
	124
	125	/* get packet type and increment the pointer */
	126	type = *data++;
	127
	128	len = ((u16 ) data);
	129	data += 2;
	130
	131	switch (type) {
	132	case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
8f4d2683	133	dsi_vc_generic_write_0(intel_dsi, vc, port);
2ab8b458 SK	134	break;
2ab8b458 SK	135	case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
8f4d2683	136	dsi_vc_generic_write_1(intel_dsi, vc, *data, port);
2ab8b458 SK	137	break;
2ab8b458 SK	138	case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
8f4d2683	139	dsi_vc_generic_write_2(intel_dsi, vc, data, (data + 1), port);
2ab8b458 SK	140	break;
	141	case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
	142	case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
	143	case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
	144	DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n");
	145	break;
	146	case MIPI_DSI_GENERIC_LONG_WRITE:
8f4d2683	147	dsi_vc_generic_write(intel_dsi, vc, data, len, port);
2ab8b458 SK	148	break;
2ab8b458 SK	149	case MIPI_DSI_DCS_SHORT_WRITE:
8f4d2683	150	dsi_vc_dcs_write_0(intel_dsi, vc, *data, port);
2ab8b458 SK	151	break;
2ab8b458 SK	152	case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
8f4d2683	153	dsi_vc_dcs_write_1(intel_dsi, vc, data, (data + 1), port);
2ab8b458 SK	154	break;
	155	case MIPI_DSI_DCS_READ:
	156	DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n");
	157	break;
	158	case MIPI_DSI_DCS_LONG_WRITE:
8f4d2683	159	dsi_vc_dcs_write(intel_dsi, vc, data, len, port);
2ab8b458	160	break;
b5fbcd98	161	}
2ab8b458 SK	162
	163	data += len;
	164
	165	return data;
	166	}
	167
	168	static u8 mipi_exec_delay(struct intel_dsi intel_dsi, u8 *data)
	169	{
	170	u32 delay = ((u32 ) data);
	171
	172	usleep_range(delay, delay + 10);
	173	data += 4;
	174
	175	return data;
	176	}
	177
	178	static u8 mipi_exec_gpio(struct intel_dsi intel_dsi, u8 *data)
	179	{
	180	u8 gpio, action;
	181	u16 function, pad;
	182	u32 val;
	183	struct drm_device *dev = intel_dsi->base.base.dev;
	184	struct drm_i915_private *dev_priv = dev->dev_private;
	185
	186	gpio = *data++;
	187
	188	/* pull up/down */
	189	action = *data++;
	190
	191	function = gtable[gpio].function_reg;
	192	pad = gtable[gpio].pad_reg;
	193
	194	mutex_lock(&dev_priv->dpio_lock);
	195	if (!gtable[gpio].init) {
	196	/* program the function */
	197	/* FIXME: remove constant below */
	198	vlv_gpio_nc_write(dev_priv, function, 0x2000CC00);
	199	gtable[gpio].init = 1;
	200	}
	201
	202	val = 0x4 \| action;
	203
	204	/* pull up/down */
	205	vlv_gpio_nc_write(dev_priv, pad, val);
	206	mutex_unlock(&dev_priv->dpio_lock);
	207
	208	return data;
	209	}
	210
	211	typedef u8 * (fn_mipi_elem_exec)(struct intel_dsi intel_dsi, u8 *data);
	212	static const fn_mipi_elem_exec exec_elem[] = {
	213	NULL, /* reserved */
	214	mipi_exec_send_packet,
	215	mipi_exec_delay,
	216	mipi_exec_gpio,
	217	NULL, /* status read; later */
	218	};
	219
	220	/*
	221	* MIPI Sequence from VBT #53 parsing logic
	222	* We have already separated each seqence during bios parsing
	223	* Following is generic execution function for any sequence
	224	*/
	225
226	static const char * const seq_name[] = {
227	"UNDEFINED",
228	"MIPI_SEQ_ASSERT_RESET",
229	"MIPI_SEQ_INIT_OTP",
230	"MIPI_SEQ_DISPLAY_ON",
231	"MIPI_SEQ_DISPLAY_OFF",
232	"MIPI_SEQ_DEASSERT_RESET"
233	};
234
235	static void generic_exec_sequence(struct intel_dsi intel_dsi, char sequence)
236	{
237	u8 *data = sequence;
238	fn_mipi_elem_exec mipi_elem_exec;
239	int index;
240
241	if (!sequence)
242	return;
243
244	DRM_DEBUG_DRIVER("Starting MIPI sequence - %s\n", seq_name[*data]);
245
246	/* go to the first element of the sequence */
247	data++;
248
249	/* parse each byte till we reach end of sequence byte - 0x00 */
250	while (1) {
251	index = *data;
252	mipi_elem_exec = exec_elem[index];
253	if (!mipi_elem_exec) {
254	DRM_ERROR("Unsupported MIPI element, skipping sequence execution\n");
255	return;
256	}
257
258	/* goto element payload */
259	data++;
260
261	/* execute the element specific rotines */
262	data = mipi_elem_exec(intel_dsi, data);
263
264	/*
265	* After processing the element, data should point to
266	* next element or end of sequence
267	* check if have we reached end of sequence
268	*/
269	if (*data == 0x00)
270	break;
271	}
272	}
273
274	static bool generic_init(struct intel_dsi_device *dsi)
275	{
276	struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
277	struct drm_device *dev = intel_dsi->base.base.dev;
278	struct drm_i915_private *dev_priv = dev->dev_private;
279	struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
280	struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
281	struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
282	u32 bits_per_pixel = 24;
283	u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui;
284	u32 ui_num, ui_den;
285	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
286	u32 ths_prepare_ns, tclk_trail_ns;
287	u32 tclk_prepare_clkzero, ths_prepare_hszero;
288	u32 lp_to_hs_switch, hs_to_lp_switch;
7f0c8605 SK	289	u32 pclk, computed_ddr;
7f0c8605 SK	290	u16 burst_mode_ratio;
2ab8b458 SK	291
	292	DRM_DEBUG_KMS("\n");
	293
	294	intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
	295	intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
	296	intel_dsi->lane_count = mipi_config->lane_cnt + 1;
	297	intel_dsi->pixel_format = mipi_config->videomode_color_format << 7;
369602d3	298	intel_dsi->dual_link = mipi_config->dual_link;
a9da9bce	299	intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
369602d3 GS	300
	301	if (intel_dsi->dual_link)
	302	intel_dsi->ports = ((1 << PORT_A) \| (1 << PORT_C));
2ab8b458 SK	303
	304	if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666)
	305	bits_per_pixel = 18;
	306	else if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB565)
	307	bits_per_pixel = 16;
	308
2ab8b458 SK	309	intel_dsi->operation_mode = mipi_config->is_cmd_mode;
	310	intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
	311	intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
	312	intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
	313	intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
	314	intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
	315	intel_dsi->init_count = mipi_config->master_init_timer;
	316	intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
b5fbcd98 SK	317	intel_dsi->video_frmt_cfg_bits =
b5fbcd98 SK	318	mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
2ab8b458	319
7f0c8605 SK	320	pclk = mode->clock;
7f0c8605 SK	321
a9da9bce GS	322	/* In dual link mode each port needs half of pixel clock */
	323	if (intel_dsi->dual_link) {
	324	pclk = pclk / 2;
	325
	326	/* we can enable pixel_overlap if needed by panel. In this
	327	* case we need to increase the pixelclock for extra pixels
	328	*/
	329	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
	330	pclk += DIV_ROUND_UP(mode->vtotal *
	331	intel_dsi->pixel_overlap *
	332	60, 1000);
	333	}
	334	}
	335
7f0c8605 SK	336	/* Burst Mode Ratio
	337	* Target ddr frequency from VBT / non burst ddr freq
	338	* multiply by 100 to preserve remainder
	339	*/
	340	if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
	341	if (mipi_config->target_burst_mode_freq) {
	342	computed_ddr =
	343	(pclk * bits_per_pixel) / intel_dsi->lane_count;
	344
	345	if (mipi_config->target_burst_mode_freq <
	346	computed_ddr) {
	347	DRM_ERROR("Burst mode freq is less than computed\n");
	348	return false;
	349	}
	350
	351	burst_mode_ratio = DIV_ROUND_UP(
	352	mipi_config->target_burst_mode_freq * 100,
	353	computed_ddr);
	354
	355	pclk = DIV_ROUND_UP(pclk * burst_mode_ratio, 100);
	356	} else {
	357	DRM_ERROR("Burst mode target is not set\n");
	358	return false;
	359	}
	360	} else
	361	burst_mode_ratio = 100;
	362
	363	intel_dsi->burst_mode_ratio = burst_mode_ratio;
	364	intel_dsi->pclk = pclk;
	365
	366	bitrate = (pclk * bits_per_pixel) / intel_dsi->lane_count;
	367
2ab8b458 SK	368	switch (intel_dsi->escape_clk_div) {
	369	case 0:
	370	tlpx_ns = 50;
	371	break;
	372	case 1:
	373	tlpx_ns = 100;
	374	break;
	375
	376	case 2:
	377	tlpx_ns = 200;
	378	break;
	379	default:
	380	tlpx_ns = 50;
	381	break;
	382	}
	383
	384	switch (intel_dsi->lane_count) {
	385	case 1:
	386	case 2:
	387	extra_byte_count = 2;
	388	break;
	389	case 3:
	390	extra_byte_count = 4;
	391	break;
	392	case 4:
	393	default:
	394	extra_byte_count = 3;
	395	break;
	396	}
	397
	398	/*
	399	* ui(s) = 1/f [f in hz]
	400	* ui(ns) = 10^9 / (f*10^6) [f in Mhz] -> 10^3/f(Mhz)
	401	*/
	402
	403	/* in Kbps */
	404	ui_num = NS_KHZ_RATIO;
	405	ui_den = bitrate;
	406
	407	tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
	408	ths_prepare_hszero = mipi_config->ths_prepare_hszero;
	409
	410	/*
	411	* B060
	412	* LP byte clock = TLPX/ (8UI)
	413	*/
	414	intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num);
	415
	416	/* count values in UI = (ns value) * (bitrate / (2 * 10^6))
	417	*
	418	* Since txddrclkhs_i is 2xUI, all the count values programmed in
	419	* DPHY param register are divided by 2
	420	*
	421	* prepare count
	422	*/
b5fbcd98 SK	423	ths_prepare_ns = max(mipi_config->ths_prepare,
b5fbcd98 SK	424	mipi_config->tclk_prepare);
2ab8b458 SK	425	prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2);
	426
	427	/* exit zero count */
	428	exit_zero_cnt = DIV_ROUND_UP(
	429	(ths_prepare_hszero - ths_prepare_ns) * ui_den,
	430	ui_num * 2
	431	);
	432
	433	/*
	434	* Exit zero is unified val ths_zero and ths_exit
	435	* minimum value for ths_exit = 110ns
	436	* min (exit_zero_cnt * 2) = 110/UI
	437	* exit_zero_cnt = 55/UI
	438	*/
	439	if (exit_zero_cnt < (55 * ui_den / ui_num))
	440	if ((55 * ui_den) % ui_num)
	441	exit_zero_cnt += 1;
	442
	443	/* clk zero count */
	444	clk_zero_cnt = DIV_ROUND_UP(
	445	(tclk_prepare_clkzero - ths_prepare_ns)
	446	* ui_den, 2 * ui_num);
	447
	448	/* trail count */
	449	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
	450	trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);
	451
	452	if (prepare_cnt > PREPARE_CNT_MAX \|\|
	453	exit_zero_cnt > EXIT_ZERO_CNT_MAX \|\|
	454	clk_zero_cnt > CLK_ZERO_CNT_MAX \|\|
	455	trail_cnt > TRAIL_CNT_MAX)
	456	DRM_DEBUG_DRIVER("Values crossing maximum limits, restricting to max values\n");
	457
	458	if (prepare_cnt > PREPARE_CNT_MAX)
	459	prepare_cnt = PREPARE_CNT_MAX;
	460
	461	if (exit_zero_cnt > EXIT_ZERO_CNT_MAX)
	462	exit_zero_cnt = EXIT_ZERO_CNT_MAX;
	463
	464	if (clk_zero_cnt > CLK_ZERO_CNT_MAX)
	465	clk_zero_cnt = CLK_ZERO_CNT_MAX;
	466
	467	if (trail_cnt > TRAIL_CNT_MAX)
	468	trail_cnt = TRAIL_CNT_MAX;
	469
	470	/* B080 */
	471	intel_dsi->dphy_reg = exit_zero_cnt << 24 \| trail_cnt << 16 \|
	472	clk_zero_cnt << 8 \| prepare_cnt;
	473
	474	/*
	475	* LP to HS switch count = 4TLPX + PREP_COUNT * 2 + EXIT_ZERO_COUNT * 2
	476	* + 10UI + Extra Byte Count
	477	*
	478	* HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
	479	* Extra Byte Count is calculated according to number of lanes.
	480	* High Low Switch Count is the Max of LP to HS and
	481	* HS to LP switch count
	482	*
	483	*/
	484	tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num);
	485
	486	/* B044 */
	487	/* FIXME:
	488	* The comment above does not match with the code */
489	lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * 2 +
490	exit_zero_cnt * 2 + 10, 8);
491
492	hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8);
493
494	intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch);
495	intel_dsi->hs_to_lp_count += extra_byte_count;
496
497	/* B088 */
498	/* LP -> HS for clock lanes
499	* LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
500	* extra byte count
501	* 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
502	* 2(in UI) + extra byte count
503	* In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
504	* 8 + extra byte count
505	*/
506	intel_dsi->clk_lp_to_hs_count =
507	DIV_ROUND_UP(
508	4 * tlpx_ui + prepare_cnt * 2 +
509	clk_zero_cnt * 2,
510	8);
511
512	intel_dsi->clk_lp_to_hs_count += extra_byte_count;
513
514	/* HS->LP for Clock Lanes
515	* Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
516	* Extra byte count
517	* 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
518	* In byteclks = (2TLpx(in UI) + trail_count2 +8)(in UI)/8 +
519	* Extra byte count
520	*/
521	intel_dsi->clk_hs_to_lp_count =
522	DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,
523	8);
524	intel_dsi->clk_hs_to_lp_count += extra_byte_count;
525
526	DRM_DEBUG_KMS("Eot %s\n", intel_dsi->eotp_pkt ? "enabled" : "disabled");
527	DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi->clock_stop ?
528	"disabled" : "enabled");
529	DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video");
a9da9bce GS	530	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
	531	DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
	532	else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
	533	DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
	534	else
	535	DRM_DEBUG_KMS("Dual link: NONE\n");
2ab8b458 SK	536	DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
	537	DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
	538	DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout);
	539	DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val);
	540	DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi->init_count);
	541	DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count);
	542	DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi->lp_byte_clk);
	543	DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi->bw_timer);
	544	DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count);
	545	DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count);
	546	DRM_DEBUG_KMS("BTA %s\n",
	547	intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA ?
	548	"disabled" : "enabled");
	549
	550	/* delays in VBT are in unit of 100us, so need to convert
	551	* here in ms
	552	* Delay (100us) * 100 /1000 = Delay / 10 (ms) */
	553	intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
	554	intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
	555	intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
	556	intel_dsi->panel_off_delay = pps->panel_off_delay / 10;
	557	intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;
	558
	559	return true;
	560	}
	561
2ab8b458 SK	562	static void generic_panel_reset(struct intel_dsi_device *dsi)
	563	{
	564	struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
	565	struct drm_device *dev = intel_dsi->base.base.dev;
	566	struct drm_i915_private *dev_priv = dev->dev_private;
	567
	568	char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET];
	569
	570	generic_exec_sequence(intel_dsi, sequence);
2ab8b458	571
36d21f4c	572	sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];
2ab8b458 SK	573	generic_exec_sequence(intel_dsi, sequence);
	574	}
	575
36d21f4c	576	static void generic_disable_panel_power(struct intel_dsi_device *dsi)
2ab8b458 SK	577	{
	578	struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
	579	struct drm_device *dev = intel_dsi->base.base.dev;
	580	struct drm_i915_private *dev_priv = dev->dev_private;
	581
36d21f4c	582	char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET];
2ab8b458 SK	583
	584	generic_exec_sequence(intel_dsi, sequence);
	585	}
	586
	587	static void generic_enable(struct intel_dsi_device *dsi)
	588	{
	589	struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
	590	struct drm_device *dev = intel_dsi->base.base.dev;
	591	struct drm_i915_private *dev_priv = dev->dev_private;
	592
	593	char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_ON];
	594
	595	generic_exec_sequence(intel_dsi, sequence);
	596	}
	597
	598	static void generic_disable(struct intel_dsi_device *dsi)
	599	{
	600	struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
	601	struct drm_device *dev = intel_dsi->base.base.dev;
	602	struct drm_i915_private *dev_priv = dev->dev_private;
	603
	604	char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_OFF];
	605
	606	generic_exec_sequence(intel_dsi, sequence);
	607	}
	608
2ab8b458 SK	609	static struct drm_display_mode generic_get_modes(struct intel_dsi_device dsi)
	610	{
	611	struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
	612	struct drm_device *dev = intel_dsi->base.base.dev;
	613	struct drm_i915_private *dev_priv = dev->dev_private;
	614
	615	dev_priv->vbt.lfp_lvds_vbt_mode->type \|= DRM_MODE_TYPE_PREFERRED;
	616	return dev_priv->vbt.lfp_lvds_vbt_mode;
	617	}
	618
2ab8b458 SK	619	struct intel_dsi_dev_ops vbt_generic_dsi_display_ops = {
2ab8b458 SK	620	.init = generic_init,
2ab8b458 SK	621	.panel_reset = generic_panel_reset,
2ab8b458 SK	622	.disable_panel_power = generic_disable_panel_power,
2ab8b458 SK	623	.enable = generic_enable,
2ab8b458 SK	624	.disable = generic_disable,
2ab8b458	625	.get_modes = generic_get_modes,
2ab8b458	626	};