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2ab8b458 SK |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Author: Shobhit Kumar <shobhit.kumar@intel.com> | |
24 | * | |
25 | */ | |
26 | ||
27 | #include <drm/drmP.h> | |
28 | #include <drm/drm_crtc.h> | |
29 | #include <drm/drm_edid.h> | |
30 | #include <drm/i915_drm.h> | |
31 | #include <linux/slab.h> | |
32 | #include <video/mipi_display.h> | |
33 | #include <asm/intel-mid.h> | |
34 | #include <video/mipi_display.h> | |
35 | #include "i915_drv.h" | |
36 | #include "intel_drv.h" | |
37 | #include "intel_dsi.h" | |
38 | #include "intel_dsi_cmd.h" | |
39 | ||
40 | #define MIPI_TRANSFER_MODE_SHIFT 0 | |
41 | #define MIPI_VIRTUAL_CHANNEL_SHIFT 1 | |
42 | #define MIPI_PORT_SHIFT 3 | |
43 | ||
44 | #define PREPARE_CNT_MAX 0x3F | |
45 | #define EXIT_ZERO_CNT_MAX 0x3F | |
46 | #define CLK_ZERO_CNT_MAX 0xFF | |
47 | #define TRAIL_CNT_MAX 0x1F | |
48 | ||
49 | #define NS_KHZ_RATIO 1000000 | |
50 | ||
51 | #define GPI0_NC_0_HV_DDI0_HPD 0x4130 | |
52 | #define GPIO_NC_0_HV_DDI0_PAD 0x4138 | |
53 | #define GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120 | |
54 | #define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD 0x4128 | |
55 | #define GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110 | |
56 | #define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD 0x4118 | |
57 | #define GPIO_NC_3_PANEL0_VDDEN 0x4140 | |
58 | #define GPIO_NC_3_PANEL0_VDDEN_PAD 0x4148 | |
59 | #define GPIO_NC_4_PANEL0_BLKEN 0x4150 | |
60 | #define GPIO_NC_4_PANEL0_BLKEN_PAD 0x4158 | |
61 | #define GPIO_NC_5_PANEL0_BLKCTL 0x4160 | |
62 | #define GPIO_NC_5_PANEL0_BLKCTL_PAD 0x4168 | |
63 | #define GPIO_NC_6_PCONF0 0x4180 | |
64 | #define GPIO_NC_6_PAD 0x4188 | |
65 | #define GPIO_NC_7_PCONF0 0x4190 | |
66 | #define GPIO_NC_7_PAD 0x4198 | |
67 | #define GPIO_NC_8_PCONF0 0x4170 | |
68 | #define GPIO_NC_8_PAD 0x4178 | |
69 | #define GPIO_NC_9_PCONF0 0x4100 | |
70 | #define GPIO_NC_9_PAD 0x4108 | |
71 | #define GPIO_NC_10_PCONF0 0x40E0 | |
72 | #define GPIO_NC_10_PAD 0x40E8 | |
73 | #define GPIO_NC_11_PCONF0 0x40F0 | |
74 | #define GPIO_NC_11_PAD 0x40F8 | |
75 | ||
76 | struct gpio_table { | |
77 | u16 function_reg; | |
78 | u16 pad_reg; | |
79 | u8 init; | |
80 | }; | |
81 | ||
82 | static struct gpio_table gtable[] = { | |
83 | { GPI0_NC_0_HV_DDI0_HPD, GPIO_NC_0_HV_DDI0_PAD, 0 }, | |
84 | { GPIO_NC_1_HV_DDI0_DDC_SDA, GPIO_NC_1_HV_DDI0_DDC_SDA_PAD, 0 }, | |
85 | { GPIO_NC_2_HV_DDI0_DDC_SCL, GPIO_NC_2_HV_DDI0_DDC_SCL_PAD, 0 }, | |
86 | { GPIO_NC_3_PANEL0_VDDEN, GPIO_NC_3_PANEL0_VDDEN_PAD, 0 }, | |
87 | { GPIO_NC_4_PANEL0_BLKEN, GPIO_NC_4_PANEL0_BLKEN_PAD, 0 }, | |
88 | { GPIO_NC_5_PANEL0_BLKCTL, GPIO_NC_5_PANEL0_BLKCTL_PAD, 0 }, | |
89 | { GPIO_NC_6_PCONF0, GPIO_NC_6_PAD, 0 }, | |
90 | { GPIO_NC_7_PCONF0, GPIO_NC_7_PAD, 0 }, | |
91 | { GPIO_NC_8_PCONF0, GPIO_NC_8_PAD, 0 }, | |
92 | { GPIO_NC_9_PCONF0, GPIO_NC_9_PAD, 0 }, | |
93 | { GPIO_NC_10_PCONF0, GPIO_NC_10_PAD, 0}, | |
94 | { GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0} | |
95 | }; | |
96 | ||
8f4d2683 GS |
97 | static inline enum port intel_dsi_seq_port_to_port(u8 port) |
98 | { | |
99 | return port ? PORT_C : PORT_A; | |
100 | } | |
101 | ||
2ab8b458 SK |
102 | static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data) |
103 | { | |
8f4d2683 | 104 | u8 type, byte, mode, vc, seq_port; |
2ab8b458 | 105 | u16 len; |
8f4d2683 | 106 | enum port port; |
2ab8b458 SK |
107 | |
108 | byte = *data++; | |
109 | mode = (byte >> MIPI_TRANSFER_MODE_SHIFT) & 0x1; | |
110 | vc = (byte >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 0x3; | |
8f4d2683 | 111 | seq_port = (byte >> MIPI_PORT_SHIFT) & 0x3; |
2ab8b458 | 112 | |
8f4d2683 | 113 | port = intel_dsi_seq_port_to_port(seq_port); |
2ab8b458 SK |
114 | /* LP or HS mode */ |
115 | intel_dsi->hs = mode; | |
116 | ||
117 | /* get packet type and increment the pointer */ | |
118 | type = *data++; | |
119 | ||
120 | len = *((u16 *) data); | |
121 | data += 2; | |
122 | ||
123 | switch (type) { | |
124 | case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: | |
8f4d2683 | 125 | dsi_vc_generic_write_0(intel_dsi, vc, port); |
2ab8b458 SK |
126 | break; |
127 | case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: | |
8f4d2683 | 128 | dsi_vc_generic_write_1(intel_dsi, vc, *data, port); |
2ab8b458 SK |
129 | break; |
130 | case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: | |
8f4d2683 | 131 | dsi_vc_generic_write_2(intel_dsi, vc, *data, *(data + 1), port); |
2ab8b458 SK |
132 | break; |
133 | case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: | |
134 | case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: | |
135 | case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: | |
136 | DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n"); | |
137 | break; | |
138 | case MIPI_DSI_GENERIC_LONG_WRITE: | |
8f4d2683 | 139 | dsi_vc_generic_write(intel_dsi, vc, data, len, port); |
2ab8b458 SK |
140 | break; |
141 | case MIPI_DSI_DCS_SHORT_WRITE: | |
8f4d2683 | 142 | dsi_vc_dcs_write_0(intel_dsi, vc, *data, port); |
2ab8b458 SK |
143 | break; |
144 | case MIPI_DSI_DCS_SHORT_WRITE_PARAM: | |
8f4d2683 | 145 | dsi_vc_dcs_write_1(intel_dsi, vc, *data, *(data + 1), port); |
2ab8b458 SK |
146 | break; |
147 | case MIPI_DSI_DCS_READ: | |
148 | DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n"); | |
149 | break; | |
150 | case MIPI_DSI_DCS_LONG_WRITE: | |
8f4d2683 | 151 | dsi_vc_dcs_write(intel_dsi, vc, data, len, port); |
2ab8b458 | 152 | break; |
b5fbcd98 | 153 | } |
2ab8b458 SK |
154 | |
155 | data += len; | |
156 | ||
157 | return data; | |
158 | } | |
159 | ||
160 | static u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, u8 *data) | |
161 | { | |
162 | u32 delay = *((u32 *) data); | |
163 | ||
164 | usleep_range(delay, delay + 10); | |
165 | data += 4; | |
166 | ||
167 | return data; | |
168 | } | |
169 | ||
170 | static u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, u8 *data) | |
171 | { | |
172 | u8 gpio, action; | |
173 | u16 function, pad; | |
174 | u32 val; | |
175 | struct drm_device *dev = intel_dsi->base.base.dev; | |
176 | struct drm_i915_private *dev_priv = dev->dev_private; | |
177 | ||
178 | gpio = *data++; | |
179 | ||
180 | /* pull up/down */ | |
181 | action = *data++; | |
182 | ||
183 | function = gtable[gpio].function_reg; | |
184 | pad = gtable[gpio].pad_reg; | |
185 | ||
186 | mutex_lock(&dev_priv->dpio_lock); | |
187 | if (!gtable[gpio].init) { | |
188 | /* program the function */ | |
189 | /* FIXME: remove constant below */ | |
190 | vlv_gpio_nc_write(dev_priv, function, 0x2000CC00); | |
191 | gtable[gpio].init = 1; | |
192 | } | |
193 | ||
194 | val = 0x4 | action; | |
195 | ||
196 | /* pull up/down */ | |
197 | vlv_gpio_nc_write(dev_priv, pad, val); | |
198 | mutex_unlock(&dev_priv->dpio_lock); | |
199 | ||
200 | return data; | |
201 | } | |
202 | ||
203 | typedef u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi, u8 *data); | |
204 | static const fn_mipi_elem_exec exec_elem[] = { | |
205 | NULL, /* reserved */ | |
206 | mipi_exec_send_packet, | |
207 | mipi_exec_delay, | |
208 | mipi_exec_gpio, | |
209 | NULL, /* status read; later */ | |
210 | }; | |
211 | ||
212 | /* | |
213 | * MIPI Sequence from VBT #53 parsing logic | |
214 | * We have already separated each seqence during bios parsing | |
215 | * Following is generic execution function for any sequence | |
216 | */ | |
217 | ||
218 | static const char * const seq_name[] = { | |
219 | "UNDEFINED", | |
220 | "MIPI_SEQ_ASSERT_RESET", | |
221 | "MIPI_SEQ_INIT_OTP", | |
222 | "MIPI_SEQ_DISPLAY_ON", | |
223 | "MIPI_SEQ_DISPLAY_OFF", | |
224 | "MIPI_SEQ_DEASSERT_RESET" | |
225 | }; | |
226 | ||
227 | static void generic_exec_sequence(struct intel_dsi *intel_dsi, char *sequence) | |
228 | { | |
229 | u8 *data = sequence; | |
230 | fn_mipi_elem_exec mipi_elem_exec; | |
231 | int index; | |
232 | ||
233 | if (!sequence) | |
234 | return; | |
235 | ||
236 | DRM_DEBUG_DRIVER("Starting MIPI sequence - %s\n", seq_name[*data]); | |
237 | ||
238 | /* go to the first element of the sequence */ | |
239 | data++; | |
240 | ||
241 | /* parse each byte till we reach end of sequence byte - 0x00 */ | |
242 | while (1) { | |
243 | index = *data; | |
244 | mipi_elem_exec = exec_elem[index]; | |
245 | if (!mipi_elem_exec) { | |
246 | DRM_ERROR("Unsupported MIPI element, skipping sequence execution\n"); | |
247 | return; | |
248 | } | |
249 | ||
250 | /* goto element payload */ | |
251 | data++; | |
252 | ||
253 | /* execute the element specific rotines */ | |
254 | data = mipi_elem_exec(intel_dsi, data); | |
255 | ||
256 | /* | |
257 | * After processing the element, data should point to | |
258 | * next element or end of sequence | |
259 | * check if have we reached end of sequence | |
260 | */ | |
261 | if (*data == 0x00) | |
262 | break; | |
263 | } | |
264 | } | |
265 | ||
266 | static bool generic_init(struct intel_dsi_device *dsi) | |
267 | { | |
268 | struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev); | |
269 | struct drm_device *dev = intel_dsi->base.base.dev; | |
270 | struct drm_i915_private *dev_priv = dev->dev_private; | |
271 | struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; | |
272 | struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps; | |
273 | struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode; | |
274 | u32 bits_per_pixel = 24; | |
275 | u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui; | |
276 | u32 ui_num, ui_den; | |
277 | u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; | |
278 | u32 ths_prepare_ns, tclk_trail_ns; | |
279 | u32 tclk_prepare_clkzero, ths_prepare_hszero; | |
280 | u32 lp_to_hs_switch, hs_to_lp_switch; | |
7f0c8605 SK |
281 | u32 pclk, computed_ddr; |
282 | u16 burst_mode_ratio; | |
2ab8b458 SK |
283 | |
284 | DRM_DEBUG_KMS("\n"); | |
285 | ||
286 | intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1; | |
287 | intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0; | |
288 | intel_dsi->lane_count = mipi_config->lane_cnt + 1; | |
289 | intel_dsi->pixel_format = mipi_config->videomode_color_format << 7; | |
369602d3 | 290 | intel_dsi->dual_link = mipi_config->dual_link; |
a9da9bce | 291 | intel_dsi->pixel_overlap = mipi_config->pixel_overlap; |
369602d3 GS |
292 | |
293 | if (intel_dsi->dual_link) | |
294 | intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C)); | |
2ab8b458 SK |
295 | |
296 | if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666) | |
297 | bits_per_pixel = 18; | |
298 | else if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB565) | |
299 | bits_per_pixel = 16; | |
300 | ||
2ab8b458 SK |
301 | intel_dsi->operation_mode = mipi_config->is_cmd_mode; |
302 | intel_dsi->video_mode_format = mipi_config->video_transfer_mode; | |
303 | intel_dsi->escape_clk_div = mipi_config->byte_clk_sel; | |
304 | intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout; | |
305 | intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout; | |
306 | intel_dsi->rst_timer_val = mipi_config->device_reset_timer; | |
307 | intel_dsi->init_count = mipi_config->master_init_timer; | |
308 | intel_dsi->bw_timer = mipi_config->dbi_bw_timer; | |
b5fbcd98 SK |
309 | intel_dsi->video_frmt_cfg_bits = |
310 | mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0; | |
2ab8b458 | 311 | |
7f0c8605 SK |
312 | pclk = mode->clock; |
313 | ||
a9da9bce GS |
314 | /* In dual link mode each port needs half of pixel clock */ |
315 | if (intel_dsi->dual_link) { | |
316 | pclk = pclk / 2; | |
317 | ||
318 | /* we can enable pixel_overlap if needed by panel. In this | |
319 | * case we need to increase the pixelclock for extra pixels | |
320 | */ | |
321 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { | |
322 | pclk += DIV_ROUND_UP(mode->vtotal * | |
323 | intel_dsi->pixel_overlap * | |
324 | 60, 1000); | |
325 | } | |
326 | } | |
327 | ||
7f0c8605 SK |
328 | /* Burst Mode Ratio |
329 | * Target ddr frequency from VBT / non burst ddr freq | |
330 | * multiply by 100 to preserve remainder | |
331 | */ | |
332 | if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) { | |
333 | if (mipi_config->target_burst_mode_freq) { | |
334 | computed_ddr = | |
335 | (pclk * bits_per_pixel) / intel_dsi->lane_count; | |
336 | ||
337 | if (mipi_config->target_burst_mode_freq < | |
338 | computed_ddr) { | |
339 | DRM_ERROR("Burst mode freq is less than computed\n"); | |
340 | return false; | |
341 | } | |
342 | ||
343 | burst_mode_ratio = DIV_ROUND_UP( | |
344 | mipi_config->target_burst_mode_freq * 100, | |
345 | computed_ddr); | |
346 | ||
347 | pclk = DIV_ROUND_UP(pclk * burst_mode_ratio, 100); | |
348 | } else { | |
349 | DRM_ERROR("Burst mode target is not set\n"); | |
350 | return false; | |
351 | } | |
352 | } else | |
353 | burst_mode_ratio = 100; | |
354 | ||
355 | intel_dsi->burst_mode_ratio = burst_mode_ratio; | |
356 | intel_dsi->pclk = pclk; | |
357 | ||
358 | bitrate = (pclk * bits_per_pixel) / intel_dsi->lane_count; | |
359 | ||
2ab8b458 SK |
360 | switch (intel_dsi->escape_clk_div) { |
361 | case 0: | |
362 | tlpx_ns = 50; | |
363 | break; | |
364 | case 1: | |
365 | tlpx_ns = 100; | |
366 | break; | |
367 | ||
368 | case 2: | |
369 | tlpx_ns = 200; | |
370 | break; | |
371 | default: | |
372 | tlpx_ns = 50; | |
373 | break; | |
374 | } | |
375 | ||
376 | switch (intel_dsi->lane_count) { | |
377 | case 1: | |
378 | case 2: | |
379 | extra_byte_count = 2; | |
380 | break; | |
381 | case 3: | |
382 | extra_byte_count = 4; | |
383 | break; | |
384 | case 4: | |
385 | default: | |
386 | extra_byte_count = 3; | |
387 | break; | |
388 | } | |
389 | ||
390 | /* | |
391 | * ui(s) = 1/f [f in hz] | |
392 | * ui(ns) = 10^9 / (f*10^6) [f in Mhz] -> 10^3/f(Mhz) | |
393 | */ | |
394 | ||
395 | /* in Kbps */ | |
396 | ui_num = NS_KHZ_RATIO; | |
397 | ui_den = bitrate; | |
398 | ||
399 | tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero; | |
400 | ths_prepare_hszero = mipi_config->ths_prepare_hszero; | |
401 | ||
402 | /* | |
403 | * B060 | |
404 | * LP byte clock = TLPX/ (8UI) | |
405 | */ | |
406 | intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num); | |
407 | ||
408 | /* count values in UI = (ns value) * (bitrate / (2 * 10^6)) | |
409 | * | |
410 | * Since txddrclkhs_i is 2xUI, all the count values programmed in | |
411 | * DPHY param register are divided by 2 | |
412 | * | |
413 | * prepare count | |
414 | */ | |
b5fbcd98 SK |
415 | ths_prepare_ns = max(mipi_config->ths_prepare, |
416 | mipi_config->tclk_prepare); | |
2ab8b458 SK |
417 | prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2); |
418 | ||
419 | /* exit zero count */ | |
420 | exit_zero_cnt = DIV_ROUND_UP( | |
421 | (ths_prepare_hszero - ths_prepare_ns) * ui_den, | |
422 | ui_num * 2 | |
423 | ); | |
424 | ||
425 | /* | |
426 | * Exit zero is unified val ths_zero and ths_exit | |
427 | * minimum value for ths_exit = 110ns | |
428 | * min (exit_zero_cnt * 2) = 110/UI | |
429 | * exit_zero_cnt = 55/UI | |
430 | */ | |
431 | if (exit_zero_cnt < (55 * ui_den / ui_num)) | |
432 | if ((55 * ui_den) % ui_num) | |
433 | exit_zero_cnt += 1; | |
434 | ||
435 | /* clk zero count */ | |
436 | clk_zero_cnt = DIV_ROUND_UP( | |
437 | (tclk_prepare_clkzero - ths_prepare_ns) | |
438 | * ui_den, 2 * ui_num); | |
439 | ||
440 | /* trail count */ | |
441 | tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); | |
442 | trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num); | |
443 | ||
444 | if (prepare_cnt > PREPARE_CNT_MAX || | |
445 | exit_zero_cnt > EXIT_ZERO_CNT_MAX || | |
446 | clk_zero_cnt > CLK_ZERO_CNT_MAX || | |
447 | trail_cnt > TRAIL_CNT_MAX) | |
448 | DRM_DEBUG_DRIVER("Values crossing maximum limits, restricting to max values\n"); | |
449 | ||
450 | if (prepare_cnt > PREPARE_CNT_MAX) | |
451 | prepare_cnt = PREPARE_CNT_MAX; | |
452 | ||
453 | if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) | |
454 | exit_zero_cnt = EXIT_ZERO_CNT_MAX; | |
455 | ||
456 | if (clk_zero_cnt > CLK_ZERO_CNT_MAX) | |
457 | clk_zero_cnt = CLK_ZERO_CNT_MAX; | |
458 | ||
459 | if (trail_cnt > TRAIL_CNT_MAX) | |
460 | trail_cnt = TRAIL_CNT_MAX; | |
461 | ||
462 | /* B080 */ | |
463 | intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 | | |
464 | clk_zero_cnt << 8 | prepare_cnt; | |
465 | ||
466 | /* | |
467 | * LP to HS switch count = 4TLPX + PREP_COUNT * 2 + EXIT_ZERO_COUNT * 2 | |
468 | * + 10UI + Extra Byte Count | |
469 | * | |
470 | * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count | |
471 | * Extra Byte Count is calculated according to number of lanes. | |
472 | * High Low Switch Count is the Max of LP to HS and | |
473 | * HS to LP switch count | |
474 | * | |
475 | */ | |
476 | tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num); | |
477 | ||
478 | /* B044 */ | |
479 | /* FIXME: | |
480 | * The comment above does not match with the code */ | |
481 | lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * 2 + | |
482 | exit_zero_cnt * 2 + 10, 8); | |
483 | ||
484 | hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8); | |
485 | ||
486 | intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch); | |
487 | intel_dsi->hs_to_lp_count += extra_byte_count; | |
488 | ||
489 | /* B088 */ | |
490 | /* LP -> HS for clock lanes | |
491 | * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero + | |
492 | * extra byte count | |
493 | * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt * | |
494 | * 2(in UI) + extra byte count | |
495 | * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) / | |
496 | * 8 + extra byte count | |
497 | */ | |
498 | intel_dsi->clk_lp_to_hs_count = | |
499 | DIV_ROUND_UP( | |
500 | 4 * tlpx_ui + prepare_cnt * 2 + | |
501 | clk_zero_cnt * 2, | |
502 | 8); | |
503 | ||
504 | intel_dsi->clk_lp_to_hs_count += extra_byte_count; | |
505 | ||
506 | /* HS->LP for Clock Lanes | |
507 | * Low Power clock synchronisations + 1Tx byteclk + tclk_trail + | |
508 | * Extra byte count | |
509 | * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count | |
510 | * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 + | |
511 | * Extra byte count | |
512 | */ | |
513 | intel_dsi->clk_hs_to_lp_count = | |
514 | DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8, | |
515 | 8); | |
516 | intel_dsi->clk_hs_to_lp_count += extra_byte_count; | |
517 | ||
518 | DRM_DEBUG_KMS("Eot %s\n", intel_dsi->eotp_pkt ? "enabled" : "disabled"); | |
519 | DRM_DEBUG_KMS("Clockstop %s\n", intel_dsi->clock_stop ? | |
520 | "disabled" : "enabled"); | |
521 | DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video"); | |
a9da9bce GS |
522 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) |
523 | DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n"); | |
524 | else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT) | |
525 | DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n"); | |
526 | else | |
527 | DRM_DEBUG_KMS("Dual link: NONE\n"); | |
2ab8b458 SK |
528 | DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format); |
529 | DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div); | |
530 | DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout); | |
531 | DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val); | |
532 | DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi->init_count); | |
533 | DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count); | |
534 | DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi->lp_byte_clk); | |
535 | DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi->bw_timer); | |
536 | DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count); | |
537 | DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count); | |
538 | DRM_DEBUG_KMS("BTA %s\n", | |
539 | intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA ? | |
540 | "disabled" : "enabled"); | |
541 | ||
542 | /* delays in VBT are in unit of 100us, so need to convert | |
543 | * here in ms | |
544 | * Delay (100us) * 100 /1000 = Delay / 10 (ms) */ | |
545 | intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10; | |
546 | intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10; | |
547 | intel_dsi->panel_on_delay = pps->panel_on_delay / 10; | |
548 | intel_dsi->panel_off_delay = pps->panel_off_delay / 10; | |
549 | intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10; | |
550 | ||
551 | return true; | |
552 | } | |
553 | ||
554 | static int generic_mode_valid(struct intel_dsi_device *dsi, | |
555 | struct drm_display_mode *mode) | |
556 | { | |
557 | return MODE_OK; | |
558 | } | |
559 | ||
560 | static bool generic_mode_fixup(struct intel_dsi_device *dsi, | |
561 | const struct drm_display_mode *mode, | |
562 | struct drm_display_mode *adjusted_mode) { | |
563 | return true; | |
564 | } | |
565 | ||
566 | static void generic_panel_reset(struct intel_dsi_device *dsi) | |
567 | { | |
568 | struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev); | |
569 | struct drm_device *dev = intel_dsi->base.base.dev; | |
570 | struct drm_i915_private *dev_priv = dev->dev_private; | |
571 | ||
572 | char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET]; | |
573 | ||
574 | generic_exec_sequence(intel_dsi, sequence); | |
575 | } | |
576 | ||
577 | static void generic_disable_panel_power(struct intel_dsi_device *dsi) | |
578 | { | |
579 | struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev); | |
580 | struct drm_device *dev = intel_dsi->base.base.dev; | |
581 | struct drm_i915_private *dev_priv = dev->dev_private; | |
582 | ||
583 | char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET]; | |
584 | ||
585 | generic_exec_sequence(intel_dsi, sequence); | |
586 | } | |
587 | ||
588 | static void generic_send_otp_cmds(struct intel_dsi_device *dsi) | |
589 | { | |
590 | struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev); | |
591 | struct drm_device *dev = intel_dsi->base.base.dev; | |
592 | struct drm_i915_private *dev_priv = dev->dev_private; | |
593 | ||
594 | char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP]; | |
595 | ||
596 | generic_exec_sequence(intel_dsi, sequence); | |
597 | } | |
598 | ||
599 | static void generic_enable(struct intel_dsi_device *dsi) | |
600 | { | |
601 | struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev); | |
602 | struct drm_device *dev = intel_dsi->base.base.dev; | |
603 | struct drm_i915_private *dev_priv = dev->dev_private; | |
604 | ||
605 | char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_ON]; | |
606 | ||
607 | generic_exec_sequence(intel_dsi, sequence); | |
608 | } | |
609 | ||
610 | static void generic_disable(struct intel_dsi_device *dsi) | |
611 | { | |
612 | struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev); | |
613 | struct drm_device *dev = intel_dsi->base.base.dev; | |
614 | struct drm_i915_private *dev_priv = dev->dev_private; | |
615 | ||
616 | char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_OFF]; | |
617 | ||
618 | generic_exec_sequence(intel_dsi, sequence); | |
619 | } | |
620 | ||
621 | static enum drm_connector_status generic_detect(struct intel_dsi_device *dsi) | |
622 | { | |
623 | return connector_status_connected; | |
624 | } | |
625 | ||
626 | static bool generic_get_hw_state(struct intel_dsi_device *dev) | |
627 | { | |
628 | return true; | |
629 | } | |
630 | ||
631 | static struct drm_display_mode *generic_get_modes(struct intel_dsi_device *dsi) | |
632 | { | |
633 | struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev); | |
634 | struct drm_device *dev = intel_dsi->base.base.dev; | |
635 | struct drm_i915_private *dev_priv = dev->dev_private; | |
636 | ||
637 | dev_priv->vbt.lfp_lvds_vbt_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
638 | return dev_priv->vbt.lfp_lvds_vbt_mode; | |
639 | } | |
640 | ||
641 | static void generic_destroy(struct intel_dsi_device *dsi) { } | |
642 | ||
643 | /* Callbacks. We might not need them all. */ | |
644 | struct intel_dsi_dev_ops vbt_generic_dsi_display_ops = { | |
645 | .init = generic_init, | |
646 | .mode_valid = generic_mode_valid, | |
647 | .mode_fixup = generic_mode_fixup, | |
648 | .panel_reset = generic_panel_reset, | |
649 | .disable_panel_power = generic_disable_panel_power, | |
650 | .send_otp_cmds = generic_send_otp_cmds, | |
651 | .enable = generic_enable, | |
652 | .disable = generic_disable, | |
653 | .detect = generic_detect, | |
654 | .get_hw_state = generic_get_hw_state, | |
655 | .get_modes = generic_get_modes, | |
656 | .destroy = generic_destroy, | |
657 | }; |