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be4fc046 | 1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Shobhit Kumar <shobhit.kumar@intel.com> | |
25 | * Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com> | |
26 | */ | |
27 | ||
28 | #include <linux/kernel.h> | |
29 | #include "intel_drv.h" | |
30 | #include "i915_drv.h" | |
31 | #include "intel_dsi.h" | |
32 | ||
50dd63a2 | 33 | static const u16 lfsr_converts[] = { |
be4fc046 | 34 | 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */ |
35 | 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */ | |
3c5c6d88 GS |
36 | 106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */ |
37 | 71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */ | |
be4fc046 | 38 | }; |
39 | ||
44d4c6ee | 40 | /* Get DSI clock from pixel clock */ |
1e78aa01 JN |
41 | static u32 dsi_clk_from_pclk(u32 pclk, enum mipi_dsi_pixel_format fmt, |
42 | int lane_count) | |
be4fc046 | 43 | { |
44d4c6ee | 44 | u32 dsi_clk_khz; |
1e78aa01 | 45 | u32 bpp = mipi_dsi_pixel_format_to_bpp(fmt); |
be4fc046 | 46 | |
44d4c6ee SK |
47 | /* DSI data rate = pixel clock * bits per pixel / lane count |
48 | pixel clock is converted from KHz to Hz */ | |
7f0c8605 | 49 | dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); |
be4fc046 | 50 | |
44d4c6ee | 51 | return dsi_clk_khz; |
be4fc046 | 52 | } |
53 | ||
20dbe1a1 | 54 | static int dsi_calc_mnp(struct drm_i915_private *dev_priv, |
47eacbab VS |
55 | struct intel_crtc_state *config, |
56 | int target_dsi_clk) | |
be4fc046 | 57 | { |
7471bf4e | 58 | unsigned int calc_m = 0, calc_p = 0; |
20dbe1a1 GS |
59 | unsigned int m_min, m_max, p_min = 2, p_max = 6; |
60 | unsigned int m, n, p; | |
61 | int ref_clk; | |
7471bf4e | 62 | int delta = target_dsi_clk; |
be4fc046 | 63 | u32 m_seed; |
64 | ||
7471bf4e JN |
65 | /* target_dsi_clk is expected in kHz */ |
66 | if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) { | |
be4fc046 | 67 | DRM_ERROR("DSI CLK Out of Range\n"); |
68 | return -ECHRNG; | |
69 | } | |
70 | ||
20dbe1a1 GS |
71 | if (IS_CHERRYVIEW(dev_priv)) { |
72 | ref_clk = 100000; | |
73 | n = 4; | |
74 | m_min = 70; | |
75 | m_max = 96; | |
76 | } else { | |
77 | ref_clk = 25000; | |
78 | n = 1; | |
79 | m_min = 62; | |
80 | m_max = 92; | |
81 | } | |
82 | ||
83 | for (m = m_min; m <= m_max && delta; m++) { | |
84 | for (p = p_min; p <= p_max && delta; p++) { | |
7471bf4e JN |
85 | /* |
86 | * Find the optimal m and p divisors with minimal delta | |
87 | * +/- the required clock | |
88 | */ | |
a856c5bd | 89 | int calc_dsi_clk = (m * ref_clk) / (p * n); |
7471bf4e JN |
90 | int d = abs(target_dsi_clk - calc_dsi_clk); |
91 | if (d < delta) { | |
92 | delta = d; | |
8e1eed5a SK |
93 | calc_m = m; |
94 | calc_p = p; | |
be4fc046 | 95 | } |
96 | } | |
97 | } | |
98 | ||
a856c5bd JN |
99 | /* register has log2(N1), this works fine for powers of two */ |
100 | n = ffs(n) - 1; | |
be4fc046 | 101 | m_seed = lfsr_converts[calc_m - 62]; |
47eacbab VS |
102 | config->dsi_pll.ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2); |
103 | config->dsi_pll.div = n << DSI_PLL_N1_DIV_SHIFT | | |
be4fc046 | 104 | m_seed << DSI_PLL_M1_DIV_SHIFT; |
105 | ||
106 | return 0; | |
107 | } | |
108 | ||
be4fc046 | 109 | /* |
110 | * XXX: The muxing and gating is hard coded for now. Need to add support for | |
111 | * sharing PLLs with two DSI outputs. | |
112 | */ | |
47eacbab VS |
113 | static int vlv_compute_dsi_pll(struct intel_encoder *encoder, |
114 | struct intel_crtc_state *config) | |
be4fc046 | 115 | { |
116 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
be4fc046 | 117 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
118 | int ret; | |
be4fc046 | 119 | u32 dsi_clk; |
120 | ||
7f0c8605 | 121 | dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, |
7f3de833 | 122 | intel_dsi->lane_count); |
be4fc046 | 123 | |
47eacbab | 124 | ret = dsi_calc_mnp(dev_priv, config, dsi_clk); |
be4fc046 | 125 | if (ret) { |
126 | DRM_DEBUG_KMS("dsi_calc_mnp failed\n"); | |
47eacbab | 127 | return ret; |
be4fc046 | 128 | } |
129 | ||
3c860ab4 | 130 | if (intel_dsi->ports & (1 << PORT_A)) |
47eacbab | 131 | config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL; |
be4fc046 | 132 | |
3c860ab4 | 133 | if (intel_dsi->ports & (1 << PORT_C)) |
47eacbab VS |
134 | config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL; |
135 | ||
136 | config->dsi_pll.ctrl |= DSI_PLL_VCO_EN; | |
58cf8887 | 137 | |
be4fc046 | 138 | DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n", |
47eacbab VS |
139 | config->dsi_pll.div, config->dsi_pll.ctrl); |
140 | ||
141 | return 0; | |
142 | } | |
143 | ||
47eacbab VS |
144 | static void vlv_enable_dsi_pll(struct intel_encoder *encoder, |
145 | const struct intel_crtc_state *config) | |
be4fc046 | 146 | { |
47eacbab | 147 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
be4fc046 | 148 | |
149 | DRM_DEBUG_KMS("\n"); | |
150 | ||
a580516d | 151 | mutex_lock(&dev_priv->sb_lock); |
be4fc046 | 152 | |
062efa5d VS |
153 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0); |
154 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div); | |
155 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, | |
156 | config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN); | |
be4fc046 | 157 | |
158 | /* wait at least 0.5 us after ungating before enabling VCO */ | |
159 | usleep_range(1, 10); | |
160 | ||
47eacbab | 161 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl); |
be4fc046 | 162 | |
3770f0ee GS |
163 | if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) & |
164 | DSI_PLL_LOCK, 20)) { | |
be4fc046 | 165 | |
a580516d | 166 | mutex_unlock(&dev_priv->sb_lock); |
be4fc046 | 167 | DRM_ERROR("DSI PLL lock failed\n"); |
168 | return; | |
169 | } | |
a580516d | 170 | mutex_unlock(&dev_priv->sb_lock); |
be4fc046 | 171 | |
172 | DRM_DEBUG_KMS("DSI PLL locked\n"); | |
173 | } | |
174 | ||
fe88fc68 | 175 | static void vlv_disable_dsi_pll(struct intel_encoder *encoder) |
be4fc046 | 176 | { |
47eacbab | 177 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
be4fc046 | 178 | u32 tmp; |
179 | ||
180 | DRM_DEBUG_KMS("\n"); | |
181 | ||
a580516d | 182 | mutex_lock(&dev_priv->sb_lock); |
be4fc046 | 183 | |
184 | tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
185 | tmp &= ~DSI_PLL_VCO_EN; | |
186 | tmp |= DSI_PLL_LDO_GATE; | |
187 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); | |
188 | ||
a580516d | 189 | mutex_unlock(&dev_priv->sb_lock); |
be4fc046 | 190 | } |
f573de5a | 191 | |
db18b6a6 ID |
192 | static bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv) |
193 | { | |
194 | bool enabled; | |
195 | u32 val; | |
196 | u32 mask; | |
197 | ||
198 | mask = BXT_DSI_PLL_DO_ENABLE | BXT_DSI_PLL_LOCKED; | |
199 | val = I915_READ(BXT_DSI_PLL_ENABLE); | |
200 | enabled = (val & mask) == mask; | |
201 | ||
202 | if (!enabled) | |
203 | return false; | |
204 | ||
205 | /* | |
206 | * Both dividers must be programmed with valid values even if only one | |
207 | * of the PLL is used, see BSpec/Broxton Clocks. Check this here for | |
208 | * paranoia, since BIOS is known to misconfigure PLLs in this way at | |
209 | * times, and since accessing DSI registers with invalid dividers | |
210 | * causes a system hang. | |
211 | */ | |
212 | val = I915_READ(BXT_DSI_PLL_CTL); | |
213 | if (!(val & BXT_DSIA_16X_MASK) || !(val & BXT_DSIC_16X_MASK)) { | |
214 | DRM_DEBUG_DRIVER("PLL is enabled with invalid divider settings (%08x)\n", | |
215 | val); | |
216 | enabled = false; | |
217 | } | |
218 | ||
219 | return enabled; | |
220 | } | |
221 | ||
fe88fc68 SS |
222 | static void bxt_disable_dsi_pll(struct intel_encoder *encoder) |
223 | { | |
47eacbab | 224 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
fe88fc68 SS |
225 | u32 val; |
226 | ||
227 | DRM_DEBUG_KMS("\n"); | |
228 | ||
229 | val = I915_READ(BXT_DSI_PLL_ENABLE); | |
230 | val &= ~BXT_DSI_PLL_DO_ENABLE; | |
231 | I915_WRITE(BXT_DSI_PLL_ENABLE, val); | |
232 | ||
233 | /* | |
234 | * PLL lock should deassert within 200us. | |
235 | * Wait up to 1ms before timing out. | |
236 | */ | |
237 | if (wait_for((I915_READ(BXT_DSI_PLL_ENABLE) | |
238 | & BXT_DSI_PLL_LOCKED) == 0, 1)) | |
239 | DRM_ERROR("Timeout waiting for PLL lock deassertion\n"); | |
240 | } | |
241 | ||
1e78aa01 | 242 | static void assert_bpp_mismatch(enum mipi_dsi_pixel_format fmt, int pipe_bpp) |
f573de5a | 243 | { |
1e78aa01 | 244 | int bpp = mipi_dsi_pixel_format_to_bpp(fmt); |
f573de5a SK |
245 | |
246 | WARN(bpp != pipe_bpp, | |
7f3de833 DV |
247 | "bpp match assertion failure (expected %d, current %d)\n", |
248 | bpp, pipe_bpp); | |
f573de5a SK |
249 | } |
250 | ||
47eacbab VS |
251 | static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp, |
252 | struct intel_crtc_state *config) | |
f573de5a | 253 | { |
47eacbab | 254 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
f573de5a SK |
255 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
256 | u32 dsi_clock, pclk; | |
257 | u32 pll_ctl, pll_div; | |
a856c5bd | 258 | u32 m = 0, p = 0, n; |
ae9ec62b | 259 | int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000; |
f573de5a SK |
260 | int i; |
261 | ||
262 | DRM_DEBUG_KMS("\n"); | |
263 | ||
a580516d | 264 | mutex_lock(&dev_priv->sb_lock); |
f573de5a SK |
265 | pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
266 | pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER); | |
a580516d | 267 | mutex_unlock(&dev_priv->sb_lock); |
f573de5a | 268 | |
47eacbab VS |
269 | config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK; |
270 | config->dsi_pll.div = pll_div; | |
271 | ||
f573de5a SK |
272 | /* mask out other bits and extract the P1 divisor */ |
273 | pll_ctl &= DSI_PLL_P1_POST_DIV_MASK; | |
274 | pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2); | |
275 | ||
a856c5bd JN |
276 | /* N1 divisor */ |
277 | n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT; | |
278 | n = 1 << n; /* register has log2(N1) */ | |
279 | ||
f573de5a SK |
280 | /* mask out the other bits and extract the M1 divisor */ |
281 | pll_div &= DSI_PLL_M1_DIV_MASK; | |
282 | pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT; | |
283 | ||
284 | while (pll_ctl) { | |
285 | pll_ctl = pll_ctl >> 1; | |
286 | p++; | |
287 | } | |
288 | p--; | |
289 | ||
290 | if (!p) { | |
291 | DRM_ERROR("wrong P1 divisor\n"); | |
292 | return 0; | |
293 | } | |
294 | ||
295 | for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) { | |
296 | if (lfsr_converts[i] == pll_div) | |
297 | break; | |
298 | } | |
299 | ||
300 | if (i == ARRAY_SIZE(lfsr_converts)) { | |
301 | DRM_ERROR("wrong m_seed programmed\n"); | |
302 | return 0; | |
303 | } | |
304 | ||
305 | m = i + 62; | |
306 | ||
a856c5bd | 307 | dsi_clock = (m * refclk) / (p * n); |
f573de5a SK |
308 | |
309 | /* pixel_format and pipe_bpp should agree */ | |
310 | assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp); | |
311 | ||
312 | pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp); | |
313 | ||
314 | return pclk; | |
315 | } | |
cfe01a5e | 316 | |
47eacbab VS |
317 | static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp, |
318 | struct intel_crtc_state *config) | |
ce0c9821 SS |
319 | { |
320 | u32 pclk; | |
321 | u32 dsi_clk; | |
322 | u32 dsi_ratio; | |
323 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
324 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
325 | ||
326 | /* Divide by zero */ | |
327 | if (!pipe_bpp) { | |
328 | DRM_ERROR("Invalid BPP(0)\n"); | |
329 | return 0; | |
330 | } | |
331 | ||
47eacbab | 332 | config->dsi_pll.ctrl = I915_READ(BXT_DSI_PLL_CTL); |
ce0c9821 | 333 | |
47eacbab | 334 | dsi_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK; |
ce0c9821 SS |
335 | |
336 | dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2; | |
337 | ||
338 | /* pixel_format and pipe_bpp should agree */ | |
339 | assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp); | |
340 | ||
341 | pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp); | |
342 | ||
343 | DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk); | |
344 | return pclk; | |
345 | } | |
346 | ||
47eacbab VS |
347 | u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp, |
348 | struct intel_crtc_state *config) | |
d7d85d85 JN |
349 | { |
350 | if (IS_BROXTON(encoder->base.dev)) | |
47eacbab | 351 | return bxt_dsi_get_pclk(encoder, pipe_bpp, config); |
d7d85d85 | 352 | else |
47eacbab | 353 | return vlv_dsi_get_pclk(encoder, pipe_bpp, config); |
d7d85d85 JN |
354 | } |
355 | ||
b248e654 | 356 | static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) |
b389a45c SS |
357 | { |
358 | u32 temp; | |
359 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
360 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
361 | ||
362 | temp = I915_READ(MIPI_CTRL(port)); | |
363 | temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; | |
364 | I915_WRITE(MIPI_CTRL(port), temp | | |
365 | intel_dsi->escape_clk_div << | |
366 | ESCAPE_CLOCK_DIVIDER_SHIFT); | |
367 | } | |
368 | ||
11b8e4f5 | 369 | /* Program BXT Mipi clocks and dividers */ |
47eacbab VS |
370 | static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port, |
371 | const struct intel_crtc_state *config) | |
11b8e4f5 | 372 | { |
11b8e4f5 | 373 | struct drm_i915_private *dev_priv = dev->dev_private; |
782d25ca D |
374 | u32 tmp; |
375 | u32 dsi_rate = 0; | |
376 | u32 pll_ratio = 0; | |
377 | u32 rx_div; | |
378 | u32 tx_div; | |
379 | u32 rx_div_upper; | |
380 | u32 rx_div_lower; | |
381 | u32 mipi_8by3_divider; | |
11b8e4f5 SS |
382 | |
383 | /* Clear old configurations */ | |
384 | tmp = I915_READ(BXT_MIPI_CLOCK_CTL); | |
385 | tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); | |
782d25ca D |
386 | tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port)); |
387 | tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port)); | |
388 | tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port)); | |
11b8e4f5 SS |
389 | |
390 | /* Get the current DSI rate(actual) */ | |
47eacbab | 391 | pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK; |
11b8e4f5 SS |
392 | dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2; |
393 | ||
782d25ca D |
394 | /* |
395 | * tx clock should be <= 20MHz and the div value must be | |
396 | * subtracted by 1 as per bspec | |
397 | */ | |
398 | tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1; | |
399 | /* | |
400 | * rx clock should be <= 150MHz and the div value must be | |
401 | * subtracted by 1 as per bspec | |
402 | */ | |
403 | rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1; | |
11b8e4f5 SS |
404 | |
405 | /* | |
782d25ca D |
406 | * rx divider value needs to be updated in the |
407 | * two differnt bit fields in the register hence splitting the | |
408 | * rx divider value accordingly | |
11b8e4f5 | 409 | */ |
782d25ca D |
410 | rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2; |
411 | rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2; | |
412 | ||
413 | /* As per bpsec program the 8/3X clock divider to the below value */ | |
414 | if (dev_priv->vbt.dsi.config->is_cmd_mode) | |
415 | mipi_8by3_divider = 0x2; | |
416 | else | |
417 | mipi_8by3_divider = 0x3; | |
11b8e4f5 | 418 | |
782d25ca D |
419 | tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider); |
420 | tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div); | |
421 | tmp |= BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, rx_div_lower); | |
422 | tmp |= BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, rx_div_upper); | |
11b8e4f5 SS |
423 | |
424 | I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); | |
425 | } | |
426 | ||
47eacbab VS |
427 | static int bxt_compute_dsi_pll(struct intel_encoder *encoder, |
428 | struct intel_crtc_state *config) | |
cfe01a5e | 429 | { |
cfe01a5e SS |
430 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
431 | u8 dsi_ratio; | |
432 | u32 dsi_clk; | |
cfe01a5e SS |
433 | |
434 | dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, | |
47eacbab | 435 | intel_dsi->lane_count); |
cfe01a5e SS |
436 | |
437 | /* | |
438 | * From clock diagram, to get PLL ratio divider, divide double of DSI | |
439 | * link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to | |
440 | * round 'up' the result | |
441 | */ | |
442 | dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ); | |
443 | if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN || | |
47eacbab | 444 | dsi_ratio > BXT_DSI_PLL_RATIO_MAX) { |
cfe01a5e | 445 | DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n"); |
47eacbab | 446 | return -ECHRNG; |
cfe01a5e SS |
447 | } |
448 | ||
449 | /* | |
450 | * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x | |
451 | * Spec says both have to be programmed, even if one is not getting | |
452 | * used. Configure MIPI_CLOCK_CTL dividers in modeset | |
453 | */ | |
47eacbab | 454 | config->dsi_pll.ctrl = dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2; |
cfe01a5e SS |
455 | |
456 | /* As per recommendation from hardware team, | |
457 | * Prog PVD ratio =1 if dsi ratio <= 50 | |
458 | */ | |
47eacbab VS |
459 | if (dsi_ratio <= 50) |
460 | config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1; | |
cfe01a5e | 461 | |
47eacbab VS |
462 | return 0; |
463 | } | |
cfe01a5e | 464 | |
47eacbab VS |
465 | static void bxt_enable_dsi_pll(struct intel_encoder *encoder, |
466 | const struct intel_crtc_state *config) | |
cfe01a5e SS |
467 | { |
468 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
11b8e4f5 SS |
469 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
470 | enum port port; | |
cfe01a5e SS |
471 | u32 val; |
472 | ||
473 | DRM_DEBUG_KMS("\n"); | |
474 | ||
cfe01a5e | 475 | /* Configure PLL vales */ |
062efa5d VS |
476 | I915_WRITE(BXT_DSI_PLL_CTL, config->dsi_pll.ctrl); |
477 | POSTING_READ(BXT_DSI_PLL_CTL); | |
cfe01a5e | 478 | |
11b8e4f5 SS |
479 | /* Program TX, RX, Dphy clocks */ |
480 | for_each_dsi_port(port, intel_dsi->ports) | |
47eacbab | 481 | bxt_dsi_program_clocks(encoder->base.dev, port, config); |
11b8e4f5 | 482 | |
cfe01a5e SS |
483 | /* Enable DSI PLL */ |
484 | val = I915_READ(BXT_DSI_PLL_ENABLE); | |
485 | val |= BXT_DSI_PLL_DO_ENABLE; | |
486 | I915_WRITE(BXT_DSI_PLL_ENABLE, val); | |
487 | ||
488 | /* Timeout and fail if PLL not locked */ | |
489 | if (wait_for(I915_READ(BXT_DSI_PLL_ENABLE) & BXT_DSI_PLL_LOCKED, 1)) { | |
490 | DRM_ERROR("Timed out waiting for DSI PLL to lock\n"); | |
491 | return; | |
492 | } | |
493 | ||
494 | DRM_DEBUG_KMS("DSI PLL locked\n"); | |
495 | } | |
496 | ||
db18b6a6 ID |
497 | bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv) |
498 | { | |
499 | if (IS_BROXTON(dev_priv)) | |
500 | return bxt_dsi_pll_is_enabled(dev_priv); | |
501 | ||
502 | MISSING_CASE(INTEL_DEVID(dev_priv)); | |
503 | ||
504 | return false; | |
505 | } | |
506 | ||
47eacbab VS |
507 | int intel_compute_dsi_pll(struct intel_encoder *encoder, |
508 | struct intel_crtc_state *config) | |
509 | { | |
510 | struct drm_device *dev = encoder->base.dev; | |
511 | ||
512 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) | |
513 | return vlv_compute_dsi_pll(encoder, config); | |
514 | else if (IS_BROXTON(dev)) | |
515 | return bxt_compute_dsi_pll(encoder, config); | |
516 | ||
517 | return -ENODEV; | |
518 | } | |
519 | ||
520 | void intel_enable_dsi_pll(struct intel_encoder *encoder, | |
521 | const struct intel_crtc_state *config) | |
cfe01a5e SS |
522 | { |
523 | struct drm_device *dev = encoder->base.dev; | |
524 | ||
666a4537 | 525 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
47eacbab | 526 | vlv_enable_dsi_pll(encoder, config); |
cfe01a5e | 527 | else if (IS_BROXTON(dev)) |
47eacbab | 528 | bxt_enable_dsi_pll(encoder, config); |
cfe01a5e | 529 | } |
fe88fc68 SS |
530 | |
531 | void intel_disable_dsi_pll(struct intel_encoder *encoder) | |
532 | { | |
533 | struct drm_device *dev = encoder->base.dev; | |
534 | ||
666a4537 | 535 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
fe88fc68 SS |
536 | vlv_disable_dsi_pll(encoder); |
537 | else if (IS_BROXTON(dev)) | |
538 | bxt_disable_dsi_pll(encoder); | |
539 | } | |
b389a45c | 540 | |
b248e654 | 541 | static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) |
b389a45c SS |
542 | { |
543 | u32 tmp; | |
544 | struct drm_device *dev = encoder->base.dev; | |
545 | struct drm_i915_private *dev_priv = dev->dev_private; | |
546 | ||
547 | /* Clear old configurations */ | |
548 | tmp = I915_READ(BXT_MIPI_CLOCK_CTL); | |
549 | tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); | |
782d25ca D |
550 | tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port)); |
551 | tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port)); | |
552 | tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port)); | |
b389a45c SS |
553 | I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); |
554 | I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); | |
555 | } | |
556 | ||
557 | void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) | |
558 | { | |
559 | struct drm_device *dev = encoder->base.dev; | |
560 | ||
561 | if (IS_BROXTON(dev)) | |
562 | bxt_dsi_reset_clocks(encoder, port); | |
666a4537 | 563 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
b389a45c SS |
564 | vlv_dsi_reset_clocks(encoder, port); |
565 | } |