[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dsi_pll.c

/*
 * Copyright © 2013 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Shobhit Kumar <shobhit.kumar@intel.com>
 *	Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
 */

#include <linux/kernel.h>
#include "intel_drv.h"
#include "i915_drv.h"
#include "intel_dsi.h"

static const u16 lfsr_converts[] = {
	426, 469, 234, 373, 442, 221, 110, 311, 411,		/* 62 - 70 */
	461, 486, 243, 377, 188, 350, 175, 343, 427, 213,	/* 71 - 80 */
	106, 53, 282, 397, 454, 227, 113, 56, 284, 142,		/* 81 - 90 */
	71, 35, 273, 136, 324, 418, 465, 488, 500, 506		/* 91 - 100 */
};

/* Get DSI clock from pixel clock */
static u32 dsi_clk_from_pclk(u32 pclk, enum mipi_dsi_pixel_format fmt,
			     int lane_count)
{
	u32 dsi_clk_khz;
	u32 bpp = mipi_dsi_pixel_format_to_bpp(fmt);

	/* DSI data rate = pixel clock * bits per pixel / lane count
	   pixel clock is converted from KHz to Hz */
	dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count);

	return dsi_clk_khz;
}

static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
			struct intel_crtc_state *config,
			int target_dsi_clk)
{
	unsigned int m_min, m_max, p_min = 2, p_max = 6;
	unsigned int m, n, p;
	unsigned int calc_m, calc_p;
	int delta, ref_clk;

	/* target_dsi_clk is expected in kHz */
	if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) {
		DRM_ERROR("DSI CLK Out of Range\n");
		return -ECHRNG;
	}

	if (IS_CHERRYVIEW(dev_priv)) {
		ref_clk = 100000;
		n = 4;
		m_min = 70;
		m_max = 96;
	} else {
		ref_clk = 25000;
		n = 1;
		m_min = 62;
		m_max = 92;
	}

	calc_p = p_min;
	calc_m = m_min;
	delta = abs(target_dsi_clk - (m_min * ref_clk) / (p_min * n));

	for (m = m_min; m <= m_max && delta; m++) {
		for (p = p_min; p <= p_max && delta; p++) {
			/*
			 * Find the optimal m and p divisors with minimal delta
			 * +/- the required clock
			 */
			int calc_dsi_clk = (m * ref_clk) / (p * n);
			int d = abs(target_dsi_clk - calc_dsi_clk);
			if (d < delta) {
				delta = d;
				calc_m = m;
				calc_p = p;
			}
		}
	}

	/* register has log2(N1), this works fine for powers of two */
	config->dsi_pll.ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
	config->dsi_pll.div =
		(ffs(n) - 1) << DSI_PLL_N1_DIV_SHIFT |
		(u32)lfsr_converts[calc_m - 62] << DSI_PLL_M1_DIV_SHIFT;

	return 0;
}

/*
 * XXX: The muxing and gating is hard coded for now. Need to add support for
 * sharing PLLs with two DSI outputs.
 */
static int vlv_compute_dsi_pll(struct intel_encoder *encoder,
			       struct intel_crtc_state *config)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
	int ret;
	u32 dsi_clk;

	dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
				    intel_dsi->lane_count);

	ret = dsi_calc_mnp(dev_priv, config, dsi_clk);
	if (ret) {
		DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
		return ret;
	}

	if (intel_dsi->ports & (1 << PORT_A))
		config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;

	if (intel_dsi->ports & (1 << PORT_C))
		config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;

	config->dsi_pll.ctrl |= DSI_PLL_VCO_EN;

	DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
		      config->dsi_pll.div, config->dsi_pll.ctrl);

	return 0;
}

static void vlv_enable_dsi_pll(struct intel_encoder *encoder,
			       const struct intel_crtc_state *config)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	DRM_DEBUG_KMS("\n");

	mutex_lock(&dev_priv->sb_lock);

	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div);
	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL,
		      config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN);

	/* wait at least 0.5 us after ungating before enabling VCO */
	usleep_range(1, 10);

	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl);

	if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &
						DSI_PLL_LOCK, 20)) {

		mutex_unlock(&dev_priv->sb_lock);
		DRM_ERROR("DSI PLL lock failed\n");
		return;
	}
	mutex_unlock(&dev_priv->sb_lock);

	DRM_DEBUG_KMS("DSI PLL locked\n");
}

static void vlv_disable_dsi_pll(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	u32 tmp;

	DRM_DEBUG_KMS("\n");

	mutex_lock(&dev_priv->sb_lock);

	tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
	tmp &= ~DSI_PLL_VCO_EN;
	tmp |= DSI_PLL_LDO_GATE;
	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);

	mutex_unlock(&dev_priv->sb_lock);
}

static bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
{
	bool enabled;
	u32 val;
	u32 mask;

	mask = BXT_DSI_PLL_DO_ENABLE | BXT_DSI_PLL_LOCKED;
	val = I915_READ(BXT_DSI_PLL_ENABLE);
	enabled = (val & mask) == mask;

	if (!enabled)
		return false;

	/*
	 * Both dividers must be programmed with valid values even if only one
	 * of the PLL is used, see BSpec/Broxton Clocks. Check this here for
	 * paranoia, since BIOS is known to misconfigure PLLs in this way at
	 * times, and since accessing DSI registers with invalid dividers
	 * causes a system hang.
	 */
	val = I915_READ(BXT_DSI_PLL_CTL);
	if (!(val & BXT_DSIA_16X_MASK) || !(val & BXT_DSIC_16X_MASK)) {
		DRM_DEBUG_DRIVER("PLL is enabled with invalid divider settings (%08x)\n",
				 val);
		enabled = false;
	}

	return enabled;
}

static void bxt_disable_dsi_pll(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	u32 val;

	DRM_DEBUG_KMS("\n");

	val = I915_READ(BXT_DSI_PLL_ENABLE);
	val &= ~BXT_DSI_PLL_DO_ENABLE;
	I915_WRITE(BXT_DSI_PLL_ENABLE, val);

	/*
	 * PLL lock should deassert within 200us.
	 * Wait up to 1ms before timing out.
	 */
	if (intel_wait_for_register(dev_priv,
				    BXT_DSI_PLL_ENABLE,
				    BXT_DSI_PLL_LOCKED,
				    0,
				    1))
		DRM_ERROR("Timeout waiting for PLL lock deassertion\n");
}

static void assert_bpp_mismatch(enum mipi_dsi_pixel_format fmt, int pipe_bpp)
{
	int bpp = mipi_dsi_pixel_format_to_bpp(fmt);

	WARN(bpp != pipe_bpp,
	     "bpp match assertion failure (expected %d, current %d)\n",
	     bpp, pipe_bpp);
}

static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
			    struct intel_crtc_state *config)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
	u32 dsi_clock, pclk;
	u32 pll_ctl, pll_div;
	u32 m = 0, p = 0, n;
	int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000;
	int i;

	DRM_DEBUG_KMS("\n");

	mutex_lock(&dev_priv->sb_lock);
	pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
	pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER);
	mutex_unlock(&dev_priv->sb_lock);

	config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK;
	config->dsi_pll.div = pll_div;

	/* mask out other bits and extract the P1 divisor */
	pll_ctl &= DSI_PLL_P1_POST_DIV_MASK;
	pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2);

	/* N1 divisor */
	n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT;
	n = 1 << n; /* register has log2(N1) */

	/* mask out the other bits and extract the M1 divisor */
	pll_div &= DSI_PLL_M1_DIV_MASK;
	pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT;

	while (pll_ctl) {
		pll_ctl = pll_ctl >> 1;
		p++;
	}
	p--;

	if (!p) {
		DRM_ERROR("wrong P1 divisor\n");
		return 0;
	}

	for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) {
		if (lfsr_converts[i] == pll_div)
			break;
	}

	if (i == ARRAY_SIZE(lfsr_converts)) {
		DRM_ERROR("wrong m_seed programmed\n");
		return 0;
	}

	m = i + 62;

	dsi_clock = (m * refclk) / (p * n);

	/* pixel_format and pipe_bpp should agree */
	assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);

	pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp);

	return pclk;
}

static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
			    struct intel_crtc_state *config)
{
	u32 pclk;
	u32 dsi_clk;
	u32 dsi_ratio;
	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	/* Divide by zero */
	if (!pipe_bpp) {
		DRM_ERROR("Invalid BPP(0)\n");
		return 0;
	}

	config->dsi_pll.ctrl = I915_READ(BXT_DSI_PLL_CTL);

	dsi_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;

	dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2;

	/* pixel_format and pipe_bpp should agree */
	assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);

	pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp);

	DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk);
	return pclk;
}

u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
		       struct intel_crtc_state *config)
{
	if (IS_BROXTON(encoder->base.dev))
		return bxt_dsi_get_pclk(encoder, pipe_bpp, config);
	else
		return vlv_dsi_get_pclk(encoder, pipe_bpp, config);
}

static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
{
	u32 temp;
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);

	temp = I915_READ(MIPI_CTRL(port));
	temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
	I915_WRITE(MIPI_CTRL(port), temp |
			intel_dsi->escape_clk_div <<
			ESCAPE_CLOCK_DIVIDER_SHIFT);
}

/* Program BXT Mipi clocks and dividers */
static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,
				   const struct intel_crtc_state *config)
{
	struct drm_i915_private *dev_priv = to_i915(dev);
	u32 tmp;
	u32 dsi_rate = 0;
	u32 pll_ratio = 0;
	u32 rx_div;
	u32 tx_div;
	u32 rx_div_upper;
	u32 rx_div_lower;
	u32 mipi_8by3_divider;

	/* Clear old configurations */
	tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
	tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
	tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
	tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
	tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));

	/* Get the current DSI rate(actual) */
	pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
	dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;

	/*
	 * tx clock should be <= 20MHz and the div value must be
	 * subtracted by 1 as per bspec
	 */
	tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1;
	/*
	 * rx clock should be <= 150MHz and the div value must be
	 * subtracted by 1 as per bspec
	 */
	rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1;

	/*
	 * rx divider value needs to be updated in the
	 * two differnt bit fields in the register hence splitting the
	 * rx divider value accordingly
	 */
	rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
	rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;

	/* As per bpsec program the 8/3X clock divider to the below value */
	if (dev_priv->vbt.dsi.config->is_cmd_mode)
		mipi_8by3_divider = 0x2;
	else
		mipi_8by3_divider = 0x3;

	tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);
	tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div);
	tmp |= BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, rx_div_lower);
	tmp |= BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, rx_div_upper);

	I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
}

static int bxt_compute_dsi_pll(struct intel_encoder *encoder,
			       struct intel_crtc_state *config)
{
	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
	u8 dsi_ratio;
	u32 dsi_clk;

	dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
				    intel_dsi->lane_count);

	/*
	 * From clock diagram, to get PLL ratio divider, divide double of DSI
	 * link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to
	 * round 'up' the result
	 */
	dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);
	if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
	    dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
		DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");
		return -ECHRNG;
	}

	/*
	 * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x
	 * Spec says both have to be programmed, even if one is not getting
	 * used. Configure MIPI_CLOCK_CTL dividers in modeset
	 */
	config->dsi_pll.ctrl = dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2;

	/* As per recommendation from hardware team,
	 * Prog PVD ratio =1 if dsi ratio <= 50
	 */
	if (dsi_ratio <= 50)
		config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1;

	return 0;
}

static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
			       const struct intel_crtc_state *config)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
	enum port port;
	u32 val;

	DRM_DEBUG_KMS("\n");

	/* Configure PLL vales */
	I915_WRITE(BXT_DSI_PLL_CTL, config->dsi_pll.ctrl);
	POSTING_READ(BXT_DSI_PLL_CTL);

	/* Program TX, RX, Dphy clocks */
	for_each_dsi_port(port, intel_dsi->ports)
		bxt_dsi_program_clocks(encoder->base.dev, port, config);

	/* Enable DSI PLL */
	val = I915_READ(BXT_DSI_PLL_ENABLE);
	val |= BXT_DSI_PLL_DO_ENABLE;
	I915_WRITE(BXT_DSI_PLL_ENABLE, val);

	/* Timeout and fail if PLL not locked */
	if (intel_wait_for_register(dev_priv,
				    BXT_DSI_PLL_ENABLE,
				    BXT_DSI_PLL_LOCKED,
				    BXT_DSI_PLL_LOCKED,
				    1)) {
		DRM_ERROR("Timed out waiting for DSI PLL to lock\n");
		return;
	}

	DRM_DEBUG_KMS("DSI PLL locked\n");
}

bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
{
	if (IS_BROXTON(dev_priv))
		return bxt_dsi_pll_is_enabled(dev_priv);

	MISSING_CASE(INTEL_DEVID(dev_priv));

	return false;
}

int intel_compute_dsi_pll(struct intel_encoder *encoder,
			  struct intel_crtc_state *config)
{
	struct drm_device *dev = encoder->base.dev;

	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
		return vlv_compute_dsi_pll(encoder, config);
	else if (IS_BROXTON(dev))
		return bxt_compute_dsi_pll(encoder, config);

	return -ENODEV;
}

void intel_enable_dsi_pll(struct intel_encoder *encoder,
			  const struct intel_crtc_state *config)
{
	struct drm_device *dev = encoder->base.dev;

	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
		vlv_enable_dsi_pll(encoder, config);
	else if (IS_BROXTON(dev))
		bxt_enable_dsi_pll(encoder, config);
}

void intel_disable_dsi_pll(struct intel_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;

	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
		vlv_disable_dsi_pll(encoder);
	else if (IS_BROXTON(dev))
		bxt_disable_dsi_pll(encoder);
}

static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
{
	u32 tmp;
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = to_i915(dev);

	/* Clear old configurations */
	tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
	tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
	tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
	tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
	tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
	I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
	I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
}

void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
{
	struct drm_device *dev = encoder->base.dev;

	if (IS_BROXTON(dev))
		bxt_dsi_reset_clocks(encoder, port);
	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
		vlv_dsi_reset_clocks(encoder, port);
}
Commit	Line	Data
be4fc046	1	/*
	2	* Copyright © 2013 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* Shobhit Kumar <shobhit.kumar@intel.com>
	25	* Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
	26	*/
	27
	28	#include <linux/kernel.h>
	29	#include "intel_drv.h"
	30	#include "i915_drv.h"
	31	#include "intel_dsi.h"
	32
50dd63a2	33	static const u16 lfsr_converts[] = {
be4fc046	34	426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */
be4fc046	35	461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */
3c5c6d88 GS	36	106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */
3c5c6d88 GS	37	71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */
be4fc046	38	};
be4fc046	39
44d4c6ee	40	/* Get DSI clock from pixel clock */
1e78aa01 JN	41	static u32 dsi_clk_from_pclk(u32 pclk, enum mipi_dsi_pixel_format fmt,
1e78aa01 JN	42	int lane_count)
be4fc046	43	{
44d4c6ee	44	u32 dsi_clk_khz;
1e78aa01	45	u32 bpp = mipi_dsi_pixel_format_to_bpp(fmt);
be4fc046	46
44d4c6ee SK	47	/* DSI data rate = pixel clock * bits per pixel / lane count
44d4c6ee SK	48	pixel clock is converted from KHz to Hz */
7f0c8605	49	dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count);
be4fc046	50
44d4c6ee	51	return dsi_clk_khz;
be4fc046	52	}
be4fc046	53
20dbe1a1	54	static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
47eacbab VS	55	struct intel_crtc_state *config,
47eacbab VS	56	int target_dsi_clk)
be4fc046	57	{
20dbe1a1 GS	58	unsigned int m_min, m_max, p_min = 2, p_max = 6;
20dbe1a1 GS	59	unsigned int m, n, p;
1bbea16a CW	60	unsigned int calc_m, calc_p;
1bbea16a CW	61	int delta, ref_clk;
be4fc046	62
7471bf4e JN	63	/* target_dsi_clk is expected in kHz */
7471bf4e JN	64	if (target_dsi_clk < 300000 \|\| target_dsi_clk > 1150000) {
be4fc046	65	DRM_ERROR("DSI CLK Out of Range\n");
	66	return -ECHRNG;
	67	}
	68
20dbe1a1 GS	69	if (IS_CHERRYVIEW(dev_priv)) {
	70	ref_clk = 100000;
	71	n = 4;
	72	m_min = 70;
	73	m_max = 96;
	74	} else {
	75	ref_clk = 25000;
	76	n = 1;
	77	m_min = 62;
	78	m_max = 92;
	79	}
	80
1bbea16a CW	81	calc_p = p_min;
	82	calc_m = m_min;
	83	delta = abs(target_dsi_clk - (m_min * ref_clk) / (p_min * n));
	84
20dbe1a1 GS	85	for (m = m_min; m <= m_max && delta; m++) {
20dbe1a1 GS	86	for (p = p_min; p <= p_max && delta; p++) {
7471bf4e JN	87	/*
	88	* Find the optimal m and p divisors with minimal delta
	89	* +/- the required clock
	90	*/
a856c5bd	91	int calc_dsi_clk = (m * ref_clk) / (p * n);
7471bf4e JN	92	int d = abs(target_dsi_clk - calc_dsi_clk);
	93	if (d < delta) {
	94	delta = d;
8e1eed5a SK	95	calc_m = m;
8e1eed5a SK	96	calc_p = p;
be4fc046	97	}
	98	}
	99	}
	100
a856c5bd	101	/* register has log2(N1), this works fine for powers of two */
47eacbab	102	config->dsi_pll.ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
1bbea16a CW	103	config->dsi_pll.div =
	104	(ffs(n) - 1) << DSI_PLL_N1_DIV_SHIFT \|
	105	(u32)lfsr_converts[calc_m - 62] << DSI_PLL_M1_DIV_SHIFT;
be4fc046	106
	107	return 0;
	108	}
	109
be4fc046	110	/*
	111	* XXX: The muxing and gating is hard coded for now. Need to add support for
	112	* sharing PLLs with two DSI outputs.
	113	*/
47eacbab VS	114	static int vlv_compute_dsi_pll(struct intel_encoder *encoder,
47eacbab VS	115	struct intel_crtc_state *config)
be4fc046	116	{
fac5e23e	117	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
be4fc046	118	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
be4fc046	119	int ret;
be4fc046	120	u32 dsi_clk;
be4fc046	121
7f0c8605	122	dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
7f3de833	123	intel_dsi->lane_count);
be4fc046	124
47eacbab	125	ret = dsi_calc_mnp(dev_priv, config, dsi_clk);
be4fc046	126	if (ret) {
be4fc046	127	DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
47eacbab	128	return ret;
be4fc046	129	}
be4fc046	130
3c860ab4	131	if (intel_dsi->ports & (1 << PORT_A))
47eacbab	132	config->dsi_pll.ctrl \|= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
be4fc046	133
3c860ab4	134	if (intel_dsi->ports & (1 << PORT_C))
47eacbab VS	135	config->dsi_pll.ctrl \|= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
	136
	137	config->dsi_pll.ctrl \|= DSI_PLL_VCO_EN;
58cf8887	138
be4fc046	139	DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
47eacbab VS	140	config->dsi_pll.div, config->dsi_pll.ctrl);
	141
	142	return 0;
	143	}
	144
47eacbab VS	145	static void vlv_enable_dsi_pll(struct intel_encoder *encoder,
47eacbab VS	146	const struct intel_crtc_state *config)
be4fc046	147	{
47eacbab	148	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
be4fc046	149
	150	DRM_DEBUG_KMS("\n");
	151
a580516d	152	mutex_lock(&dev_priv->sb_lock);
be4fc046	153
062efa5d VS	154	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
	155	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div);
	156	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL,
	157	config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN);
be4fc046	158
	159	/* wait at least 0.5 us after ungating before enabling VCO */
	160	usleep_range(1, 10);
	161
47eacbab	162	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl);
be4fc046	163
3770f0ee GS	164	if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &
3770f0ee GS	165	DSI_PLL_LOCK, 20)) {
be4fc046	166
a580516d	167	mutex_unlock(&dev_priv->sb_lock);
be4fc046	168	DRM_ERROR("DSI PLL lock failed\n");
	169	return;
	170	}
a580516d	171	mutex_unlock(&dev_priv->sb_lock);
be4fc046	172
	173	DRM_DEBUG_KMS("DSI PLL locked\n");
	174	}
	175
fe88fc68	176	static void vlv_disable_dsi_pll(struct intel_encoder *encoder)
be4fc046	177	{
47eacbab	178	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
be4fc046	179	u32 tmp;
	180
	181	DRM_DEBUG_KMS("\n");
	182
a580516d	183	mutex_lock(&dev_priv->sb_lock);
be4fc046	184
	185	tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
	186	tmp &= ~DSI_PLL_VCO_EN;
	187	tmp \|= DSI_PLL_LDO_GATE;
	188	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
	189
a580516d	190	mutex_unlock(&dev_priv->sb_lock);
be4fc046	191	}
f573de5a	192
db18b6a6 ID	193	static bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
	194	{
	195	bool enabled;
	196	u32 val;
	197	u32 mask;
	198
	199	mask = BXT_DSI_PLL_DO_ENABLE \| BXT_DSI_PLL_LOCKED;
	200	val = I915_READ(BXT_DSI_PLL_ENABLE);
	201	enabled = (val & mask) == mask;
	202
	203	if (!enabled)
	204	return false;
	205
	206	/*
	207	* Both dividers must be programmed with valid values even if only one
	208	* of the PLL is used, see BSpec/Broxton Clocks. Check this here for
	209	* paranoia, since BIOS is known to misconfigure PLLs in this way at
	210	* times, and since accessing DSI registers with invalid dividers
	211	* causes a system hang.
	212	*/
	213	val = I915_READ(BXT_DSI_PLL_CTL);
	214	if (!(val & BXT_DSIA_16X_MASK) \|\| !(val & BXT_DSIC_16X_MASK)) {
	215	DRM_DEBUG_DRIVER("PLL is enabled with invalid divider settings (%08x)\n",
	216	val);
	217	enabled = false;
	218	}
	219
	220	return enabled;
	221	}
	222
fe88fc68 SS	223	static void bxt_disable_dsi_pll(struct intel_encoder *encoder)
fe88fc68 SS	224	{
47eacbab	225	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
fe88fc68 SS	226	u32 val;
	227
	228	DRM_DEBUG_KMS("\n");
	229
	230	val = I915_READ(BXT_DSI_PLL_ENABLE);
	231	val &= ~BXT_DSI_PLL_DO_ENABLE;
	232	I915_WRITE(BXT_DSI_PLL_ENABLE, val);
	233
	234	/*
	235	* PLL lock should deassert within 200us.
	236	* Wait up to 1ms before timing out.
	237	*/
90a392c6 CW	238	if (intel_wait_for_register(dev_priv,
	239	BXT_DSI_PLL_ENABLE,
	240	BXT_DSI_PLL_LOCKED,
	241	0,
	242	1))
fe88fc68 SS	243	DRM_ERROR("Timeout waiting for PLL lock deassertion\n");
	244	}
	245
1e78aa01	246	static void assert_bpp_mismatch(enum mipi_dsi_pixel_format fmt, int pipe_bpp)
f573de5a	247	{
1e78aa01	248	int bpp = mipi_dsi_pixel_format_to_bpp(fmt);
f573de5a SK	249
f573de5a SK	250	WARN(bpp != pipe_bpp,
7f3de833 DV	251	"bpp match assertion failure (expected %d, current %d)\n",
7f3de833 DV	252	bpp, pipe_bpp);
f573de5a SK	253	}
f573de5a SK	254
47eacbab VS	255	static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
47eacbab VS	256	struct intel_crtc_state *config)
f573de5a	257	{
47eacbab	258	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
f573de5a SK	259	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
	260	u32 dsi_clock, pclk;
	261	u32 pll_ctl, pll_div;
a856c5bd	262	u32 m = 0, p = 0, n;
ae9ec62b	263	int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000;
f573de5a SK	264	int i;
	265
	266	DRM_DEBUG_KMS("\n");
	267
a580516d	268	mutex_lock(&dev_priv->sb_lock);
f573de5a SK	269	pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
f573de5a SK	270	pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER);
a580516d	271	mutex_unlock(&dev_priv->sb_lock);
f573de5a	272
47eacbab VS	273	config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK;
	274	config->dsi_pll.div = pll_div;
	275
f573de5a SK	276	/* mask out other bits and extract the P1 divisor */
	277	pll_ctl &= DSI_PLL_P1_POST_DIV_MASK;
	278	pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2);
	279
a856c5bd JN	280	/* N1 divisor */
	281	n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT;
	282	n = 1 << n; /* register has log2(N1) */
	283
f573de5a SK	284	/* mask out the other bits and extract the M1 divisor */
	285	pll_div &= DSI_PLL_M1_DIV_MASK;
	286	pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT;
	287
	288	while (pll_ctl) {
	289	pll_ctl = pll_ctl >> 1;
	290	p++;
	291	}
	292	p--;
	293
	294	if (!p) {
	295	DRM_ERROR("wrong P1 divisor\n");
	296	return 0;
	297	}
	298
	299	for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) {
	300	if (lfsr_converts[i] == pll_div)
	301	break;
	302	}
	303
	304	if (i == ARRAY_SIZE(lfsr_converts)) {
	305	DRM_ERROR("wrong m_seed programmed\n");
	306	return 0;
	307	}
	308
	309	m = i + 62;
	310
a856c5bd	311	dsi_clock = (m * refclk) / (p * n);
f573de5a SK	312
	313	/* pixel_format and pipe_bpp should agree */
	314	assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);
	315
	316	pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp);
	317
	318	return pclk;
	319	}
cfe01a5e	320
47eacbab VS	321	static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
47eacbab VS	322	struct intel_crtc_state *config)
ce0c9821 SS	323	{
	324	u32 pclk;
	325	u32 dsi_clk;
	326	u32 dsi_ratio;
	327	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
fac5e23e	328	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
ce0c9821 SS	329
	330	/* Divide by zero */
	331	if (!pipe_bpp) {
	332	DRM_ERROR("Invalid BPP(0)\n");
	333	return 0;
	334	}
	335
47eacbab	336	config->dsi_pll.ctrl = I915_READ(BXT_DSI_PLL_CTL);
ce0c9821	337
47eacbab	338	dsi_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
ce0c9821 SS	339
	340	dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2;
	341
	342	/* pixel_format and pipe_bpp should agree */
	343	assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);
	344
	345	pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp);
	346
	347	DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk);
	348	return pclk;
	349	}
	350
47eacbab VS	351	u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
47eacbab VS	352	struct intel_crtc_state *config)
d7d85d85 JN	353	{
d7d85d85 JN	354	if (IS_BROXTON(encoder->base.dev))
47eacbab	355	return bxt_dsi_get_pclk(encoder, pipe_bpp, config);
d7d85d85	356	else
47eacbab	357	return vlv_dsi_get_pclk(encoder, pipe_bpp, config);
d7d85d85 JN	358	}
d7d85d85 JN	359
b248e654	360	static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
b389a45c SS	361	{
b389a45c SS	362	u32 temp;
fac5e23e	363	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
b389a45c SS	364	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
	365
	366	temp = I915_READ(MIPI_CTRL(port));
	367	temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
	368	I915_WRITE(MIPI_CTRL(port), temp \|
	369	intel_dsi->escape_clk_div <<
	370	ESCAPE_CLOCK_DIVIDER_SHIFT);
	371	}
	372
11b8e4f5	373	/* Program BXT Mipi clocks and dividers */
47eacbab VS	374	static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,
47eacbab VS	375	const struct intel_crtc_state *config)
11b8e4f5	376	{
fac5e23e	377	struct drm_i915_private *dev_priv = to_i915(dev);
782d25ca D	378	u32 tmp;
	379	u32 dsi_rate = 0;
	380	u32 pll_ratio = 0;
	381	u32 rx_div;
	382	u32 tx_div;
	383	u32 rx_div_upper;
	384	u32 rx_div_lower;
	385	u32 mipi_8by3_divider;
11b8e4f5 SS	386
	387	/* Clear old configurations */
	388	tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
	389	tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
782d25ca D	390	tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
	391	tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
	392	tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
11b8e4f5 SS	393
11b8e4f5 SS	394	/* Get the current DSI rate(actual) */
47eacbab	395	pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
11b8e4f5 SS	396	dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
11b8e4f5 SS	397
782d25ca D	398	/*
	399	* tx clock should be <= 20MHz and the div value must be
	400	* subtracted by 1 as per bspec
	401	*/
	402	tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1;
	403	/*
	404	* rx clock should be <= 150MHz and the div value must be
	405	* subtracted by 1 as per bspec
	406	*/
	407	rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1;
11b8e4f5 SS	408
11b8e4f5 SS	409	/*
782d25ca D	410	* rx divider value needs to be updated in the
	411	* two differnt bit fields in the register hence splitting the
	412	* rx divider value accordingly
11b8e4f5	413	*/
782d25ca D	414	rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
	415	rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;
	416
	417	/* As per bpsec program the 8/3X clock divider to the below value */
	418	if (dev_priv->vbt.dsi.config->is_cmd_mode)
	419	mipi_8by3_divider = 0x2;
	420	else
	421	mipi_8by3_divider = 0x3;
11b8e4f5	422
782d25ca D	423	tmp \|= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);
	424	tmp \|= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div);
	425	tmp \|= BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, rx_div_lower);
	426	tmp \|= BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, rx_div_upper);
11b8e4f5 SS	427
	428	I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
	429	}
	430
47eacbab VS	431	static int bxt_compute_dsi_pll(struct intel_encoder *encoder,
47eacbab VS	432	struct intel_crtc_state *config)
cfe01a5e	433	{
cfe01a5e SS	434	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
	435	u8 dsi_ratio;
	436	u32 dsi_clk;
cfe01a5e SS	437
cfe01a5e SS	438	dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
47eacbab	439	intel_dsi->lane_count);
cfe01a5e SS	440
	441	/*
	442	* From clock diagram, to get PLL ratio divider, divide double of DSI
	443	* link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to
	444	* round 'up' the result
	445	*/
	446	dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);
	447	if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN \|\|
47eacbab	448	dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
cfe01a5e	449	DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");
47eacbab	450	return -ECHRNG;
cfe01a5e SS	451	}
	452
	453	/*
	454	* Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x
	455	* Spec says both have to be programmed, even if one is not getting
	456	* used. Configure MIPI_CLOCK_CTL dividers in modeset
	457	*/
47eacbab	458	config->dsi_pll.ctrl = dsi_ratio \| BXT_DSIA_16X_BY2 \| BXT_DSIC_16X_BY2;
cfe01a5e SS	459
	460	/* As per recommendation from hardware team,
	461	* Prog PVD ratio =1 if dsi ratio <= 50
	462	*/
47eacbab VS	463	if (dsi_ratio <= 50)
47eacbab VS	464	config->dsi_pll.ctrl \|= BXT_DSI_PLL_PVD_RATIO_1;
cfe01a5e	465
47eacbab VS	466	return 0;
47eacbab VS	467	}
cfe01a5e	468
47eacbab VS	469	static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
47eacbab VS	470	const struct intel_crtc_state *config)
cfe01a5e	471	{
fac5e23e	472	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
11b8e4f5 SS	473	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
11b8e4f5 SS	474	enum port port;
cfe01a5e SS	475	u32 val;
	476
	477	DRM_DEBUG_KMS("\n");
	478
cfe01a5e	479	/* Configure PLL vales */
062efa5d VS	480	I915_WRITE(BXT_DSI_PLL_CTL, config->dsi_pll.ctrl);
062efa5d VS	481	POSTING_READ(BXT_DSI_PLL_CTL);
cfe01a5e	482
11b8e4f5 SS	483	/* Program TX, RX, Dphy clocks */
11b8e4f5 SS	484	for_each_dsi_port(port, intel_dsi->ports)
47eacbab	485	bxt_dsi_program_clocks(encoder->base.dev, port, config);
11b8e4f5	486
cfe01a5e SS	487	/* Enable DSI PLL */
	488	val = I915_READ(BXT_DSI_PLL_ENABLE);
	489	val \|= BXT_DSI_PLL_DO_ENABLE;
	490	I915_WRITE(BXT_DSI_PLL_ENABLE, val);
	491
	492	/* Timeout and fail if PLL not locked */
186f1c5d CW	493	if (intel_wait_for_register(dev_priv,
	494	BXT_DSI_PLL_ENABLE,
	495	BXT_DSI_PLL_LOCKED,
	496	BXT_DSI_PLL_LOCKED,
	497	1)) {
cfe01a5e SS	498	DRM_ERROR("Timed out waiting for DSI PLL to lock\n");
	499	return;
	500	}
	501
	502	DRM_DEBUG_KMS("DSI PLL locked\n");
	503	}
	504
db18b6a6 ID	505	bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
	506	{
	507	if (IS_BROXTON(dev_priv))
	508	return bxt_dsi_pll_is_enabled(dev_priv);
	509
	510	MISSING_CASE(INTEL_DEVID(dev_priv));
	511
	512	return false;
	513	}
	514
47eacbab VS	515	int intel_compute_dsi_pll(struct intel_encoder *encoder,
	516	struct intel_crtc_state *config)
	517	{
	518	struct drm_device *dev = encoder->base.dev;
	519
	520	if (IS_VALLEYVIEW(dev) \|\| IS_CHERRYVIEW(dev))
	521	return vlv_compute_dsi_pll(encoder, config);
	522	else if (IS_BROXTON(dev))
	523	return bxt_compute_dsi_pll(encoder, config);
	524
	525	return -ENODEV;
	526	}
	527
	528	void intel_enable_dsi_pll(struct intel_encoder *encoder,
	529	const struct intel_crtc_state *config)
cfe01a5e SS	530	{
	531	struct drm_device *dev = encoder->base.dev;
	532
666a4537	533	if (IS_VALLEYVIEW(dev) \|\| IS_CHERRYVIEW(dev))
47eacbab	534	vlv_enable_dsi_pll(encoder, config);
cfe01a5e	535	else if (IS_BROXTON(dev))
47eacbab	536	bxt_enable_dsi_pll(encoder, config);
cfe01a5e	537	}
fe88fc68 SS	538
	539	void intel_disable_dsi_pll(struct intel_encoder *encoder)
	540	{
	541	struct drm_device *dev = encoder->base.dev;
	542
666a4537	543	if (IS_VALLEYVIEW(dev) \|\| IS_CHERRYVIEW(dev))
fe88fc68 SS	544	vlv_disable_dsi_pll(encoder);
	545	else if (IS_BROXTON(dev))
	546	bxt_disable_dsi_pll(encoder);
	547	}
b389a45c	548
b248e654	549	static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
b389a45c SS	550	{
	551	u32 tmp;
	552	struct drm_device *dev = encoder->base.dev;
fac5e23e	553	struct drm_i915_private *dev_priv = to_i915(dev);
b389a45c SS	554
	555	/* Clear old configurations */
	556	tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
	557	tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
782d25ca D	558	tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
	559	tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
	560	tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
b389a45c SS	561	I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
	562	I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
	563	}
	564
	565	void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
	566	{
	567	struct drm_device *dev = encoder->base.dev;
	568
	569	if (IS_BROXTON(dev))
	570	bxt_dsi_reset_clocks(encoder, port);
666a4537	571	else if (IS_VALLEYVIEW(dev) \|\| IS_CHERRYVIEW(dev))
b389a45c SS	572	vlv_dsi_reset_clocks(encoder, port);
b389a45c SS	573	}