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be4fc046 | 1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Shobhit Kumar <shobhit.kumar@intel.com> | |
25 | * Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com> | |
26 | */ | |
27 | ||
28 | #include <linux/kernel.h> | |
29 | #include "intel_drv.h" | |
30 | #include "i915_drv.h" | |
31 | #include "intel_dsi.h" | |
32 | ||
be4fc046 | 33 | struct dsi_mnp { |
34 | u32 dsi_pll_ctrl; | |
35 | u32 dsi_pll_div; | |
36 | }; | |
37 | ||
50dd63a2 | 38 | static const u16 lfsr_converts[] = { |
be4fc046 | 39 | 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */ |
40 | 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */ | |
3c5c6d88 GS |
41 | 106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */ |
42 | 71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */ | |
be4fc046 | 43 | }; |
44 | ||
44d4c6ee | 45 | /* Get DSI clock from pixel clock */ |
1e78aa01 JN |
46 | static u32 dsi_clk_from_pclk(u32 pclk, enum mipi_dsi_pixel_format fmt, |
47 | int lane_count) | |
be4fc046 | 48 | { |
44d4c6ee | 49 | u32 dsi_clk_khz; |
1e78aa01 | 50 | u32 bpp = mipi_dsi_pixel_format_to_bpp(fmt); |
be4fc046 | 51 | |
44d4c6ee SK |
52 | /* DSI data rate = pixel clock * bits per pixel / lane count |
53 | pixel clock is converted from KHz to Hz */ | |
7f0c8605 | 54 | dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); |
be4fc046 | 55 | |
44d4c6ee | 56 | return dsi_clk_khz; |
be4fc046 | 57 | } |
58 | ||
20dbe1a1 GS |
59 | static int dsi_calc_mnp(struct drm_i915_private *dev_priv, |
60 | struct dsi_mnp *dsi_mnp, int target_dsi_clk) | |
be4fc046 | 61 | { |
7471bf4e | 62 | unsigned int calc_m = 0, calc_p = 0; |
20dbe1a1 GS |
63 | unsigned int m_min, m_max, p_min = 2, p_max = 6; |
64 | unsigned int m, n, p; | |
65 | int ref_clk; | |
7471bf4e | 66 | int delta = target_dsi_clk; |
be4fc046 | 67 | u32 m_seed; |
68 | ||
7471bf4e JN |
69 | /* target_dsi_clk is expected in kHz */ |
70 | if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) { | |
be4fc046 | 71 | DRM_ERROR("DSI CLK Out of Range\n"); |
72 | return -ECHRNG; | |
73 | } | |
74 | ||
20dbe1a1 GS |
75 | if (IS_CHERRYVIEW(dev_priv)) { |
76 | ref_clk = 100000; | |
77 | n = 4; | |
78 | m_min = 70; | |
79 | m_max = 96; | |
80 | } else { | |
81 | ref_clk = 25000; | |
82 | n = 1; | |
83 | m_min = 62; | |
84 | m_max = 92; | |
85 | } | |
86 | ||
87 | for (m = m_min; m <= m_max && delta; m++) { | |
88 | for (p = p_min; p <= p_max && delta; p++) { | |
7471bf4e JN |
89 | /* |
90 | * Find the optimal m and p divisors with minimal delta | |
91 | * +/- the required clock | |
92 | */ | |
a856c5bd | 93 | int calc_dsi_clk = (m * ref_clk) / (p * n); |
7471bf4e JN |
94 | int d = abs(target_dsi_clk - calc_dsi_clk); |
95 | if (d < delta) { | |
96 | delta = d; | |
8e1eed5a SK |
97 | calc_m = m; |
98 | calc_p = p; | |
be4fc046 | 99 | } |
100 | } | |
101 | } | |
102 | ||
a856c5bd JN |
103 | /* register has log2(N1), this works fine for powers of two */ |
104 | n = ffs(n) - 1; | |
be4fc046 | 105 | m_seed = lfsr_converts[calc_m - 62]; |
be4fc046 | 106 | dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2); |
a856c5bd | 107 | dsi_mnp->dsi_pll_div = n << DSI_PLL_N1_DIV_SHIFT | |
be4fc046 | 108 | m_seed << DSI_PLL_M1_DIV_SHIFT; |
109 | ||
110 | return 0; | |
111 | } | |
112 | ||
be4fc046 | 113 | /* |
114 | * XXX: The muxing and gating is hard coded for now. Need to add support for | |
115 | * sharing PLLs with two DSI outputs. | |
116 | */ | |
117 | static void vlv_configure_dsi_pll(struct intel_encoder *encoder) | |
118 | { | |
119 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
be4fc046 | 120 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
121 | int ret; | |
122 | struct dsi_mnp dsi_mnp; | |
123 | u32 dsi_clk; | |
124 | ||
7f0c8605 | 125 | dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, |
7f3de833 | 126 | intel_dsi->lane_count); |
be4fc046 | 127 | |
20dbe1a1 | 128 | ret = dsi_calc_mnp(dev_priv, &dsi_mnp, dsi_clk); |
be4fc046 | 129 | if (ret) { |
130 | DRM_DEBUG_KMS("dsi_calc_mnp failed\n"); | |
131 | return; | |
132 | } | |
133 | ||
3c860ab4 GS |
134 | if (intel_dsi->ports & (1 << PORT_A)) |
135 | dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL; | |
be4fc046 | 136 | |
3c860ab4 | 137 | if (intel_dsi->ports & (1 << PORT_C)) |
58cf8887 GS |
138 | dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL; |
139 | ||
be4fc046 | 140 | DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n", |
141 | dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl); | |
142 | ||
143 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0); | |
144 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, dsi_mnp.dsi_pll_div); | |
145 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, dsi_mnp.dsi_pll_ctrl); | |
146 | } | |
147 | ||
cfe01a5e | 148 | static void vlv_enable_dsi_pll(struct intel_encoder *encoder) |
be4fc046 | 149 | { |
150 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
151 | u32 tmp; | |
152 | ||
153 | DRM_DEBUG_KMS("\n"); | |
154 | ||
a580516d | 155 | mutex_lock(&dev_priv->sb_lock); |
be4fc046 | 156 | |
157 | vlv_configure_dsi_pll(encoder); | |
158 | ||
159 | /* wait at least 0.5 us after ungating before enabling VCO */ | |
160 | usleep_range(1, 10); | |
161 | ||
162 | tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
163 | tmp |= DSI_PLL_VCO_EN; | |
164 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); | |
165 | ||
3770f0ee GS |
166 | if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) & |
167 | DSI_PLL_LOCK, 20)) { | |
be4fc046 | 168 | |
a580516d | 169 | mutex_unlock(&dev_priv->sb_lock); |
be4fc046 | 170 | DRM_ERROR("DSI PLL lock failed\n"); |
171 | return; | |
172 | } | |
a580516d | 173 | mutex_unlock(&dev_priv->sb_lock); |
be4fc046 | 174 | |
175 | DRM_DEBUG_KMS("DSI PLL locked\n"); | |
176 | } | |
177 | ||
fe88fc68 | 178 | static void vlv_disable_dsi_pll(struct intel_encoder *encoder) |
be4fc046 | 179 | { |
180 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
181 | u32 tmp; | |
182 | ||
183 | DRM_DEBUG_KMS("\n"); | |
184 | ||
a580516d | 185 | mutex_lock(&dev_priv->sb_lock); |
be4fc046 | 186 | |
187 | tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
188 | tmp &= ~DSI_PLL_VCO_EN; | |
189 | tmp |= DSI_PLL_LDO_GATE; | |
190 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); | |
191 | ||
a580516d | 192 | mutex_unlock(&dev_priv->sb_lock); |
be4fc046 | 193 | } |
f573de5a | 194 | |
db18b6a6 ID |
195 | static bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv) |
196 | { | |
197 | bool enabled; | |
198 | u32 val; | |
199 | u32 mask; | |
200 | ||
201 | mask = BXT_DSI_PLL_DO_ENABLE | BXT_DSI_PLL_LOCKED; | |
202 | val = I915_READ(BXT_DSI_PLL_ENABLE); | |
203 | enabled = (val & mask) == mask; | |
204 | ||
205 | if (!enabled) | |
206 | return false; | |
207 | ||
208 | /* | |
209 | * Both dividers must be programmed with valid values even if only one | |
210 | * of the PLL is used, see BSpec/Broxton Clocks. Check this here for | |
211 | * paranoia, since BIOS is known to misconfigure PLLs in this way at | |
212 | * times, and since accessing DSI registers with invalid dividers | |
213 | * causes a system hang. | |
214 | */ | |
215 | val = I915_READ(BXT_DSI_PLL_CTL); | |
216 | if (!(val & BXT_DSIA_16X_MASK) || !(val & BXT_DSIC_16X_MASK)) { | |
217 | DRM_DEBUG_DRIVER("PLL is enabled with invalid divider settings (%08x)\n", | |
218 | val); | |
219 | enabled = false; | |
220 | } | |
221 | ||
222 | return enabled; | |
223 | } | |
224 | ||
fe88fc68 SS |
225 | static void bxt_disable_dsi_pll(struct intel_encoder *encoder) |
226 | { | |
227 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
228 | u32 val; | |
229 | ||
230 | DRM_DEBUG_KMS("\n"); | |
231 | ||
232 | val = I915_READ(BXT_DSI_PLL_ENABLE); | |
233 | val &= ~BXT_DSI_PLL_DO_ENABLE; | |
234 | I915_WRITE(BXT_DSI_PLL_ENABLE, val); | |
235 | ||
236 | /* | |
237 | * PLL lock should deassert within 200us. | |
238 | * Wait up to 1ms before timing out. | |
239 | */ | |
240 | if (wait_for((I915_READ(BXT_DSI_PLL_ENABLE) | |
241 | & BXT_DSI_PLL_LOCKED) == 0, 1)) | |
242 | DRM_ERROR("Timeout waiting for PLL lock deassertion\n"); | |
243 | } | |
244 | ||
1e78aa01 | 245 | static void assert_bpp_mismatch(enum mipi_dsi_pixel_format fmt, int pipe_bpp) |
f573de5a | 246 | { |
1e78aa01 | 247 | int bpp = mipi_dsi_pixel_format_to_bpp(fmt); |
f573de5a SK |
248 | |
249 | WARN(bpp != pipe_bpp, | |
7f3de833 DV |
250 | "bpp match assertion failure (expected %d, current %d)\n", |
251 | bpp, pipe_bpp); | |
f573de5a SK |
252 | } |
253 | ||
d7d85d85 | 254 | static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp) |
f573de5a SK |
255 | { |
256 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
257 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
258 | u32 dsi_clock, pclk; | |
259 | u32 pll_ctl, pll_div; | |
a856c5bd | 260 | u32 m = 0, p = 0, n; |
ae9ec62b | 261 | int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000; |
f573de5a SK |
262 | int i; |
263 | ||
264 | DRM_DEBUG_KMS("\n"); | |
265 | ||
a580516d | 266 | mutex_lock(&dev_priv->sb_lock); |
f573de5a SK |
267 | pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
268 | pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER); | |
a580516d | 269 | mutex_unlock(&dev_priv->sb_lock); |
f573de5a SK |
270 | |
271 | /* mask out other bits and extract the P1 divisor */ | |
272 | pll_ctl &= DSI_PLL_P1_POST_DIV_MASK; | |
273 | pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2); | |
274 | ||
a856c5bd JN |
275 | /* N1 divisor */ |
276 | n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT; | |
277 | n = 1 << n; /* register has log2(N1) */ | |
278 | ||
f573de5a SK |
279 | /* mask out the other bits and extract the M1 divisor */ |
280 | pll_div &= DSI_PLL_M1_DIV_MASK; | |
281 | pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT; | |
282 | ||
283 | while (pll_ctl) { | |
284 | pll_ctl = pll_ctl >> 1; | |
285 | p++; | |
286 | } | |
287 | p--; | |
288 | ||
289 | if (!p) { | |
290 | DRM_ERROR("wrong P1 divisor\n"); | |
291 | return 0; | |
292 | } | |
293 | ||
294 | for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) { | |
295 | if (lfsr_converts[i] == pll_div) | |
296 | break; | |
297 | } | |
298 | ||
299 | if (i == ARRAY_SIZE(lfsr_converts)) { | |
300 | DRM_ERROR("wrong m_seed programmed\n"); | |
301 | return 0; | |
302 | } | |
303 | ||
304 | m = i + 62; | |
305 | ||
a856c5bd | 306 | dsi_clock = (m * refclk) / (p * n); |
f573de5a SK |
307 | |
308 | /* pixel_format and pipe_bpp should agree */ | |
309 | assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp); | |
310 | ||
311 | pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp); | |
312 | ||
313 | return pclk; | |
314 | } | |
cfe01a5e | 315 | |
d7d85d85 | 316 | static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp) |
ce0c9821 SS |
317 | { |
318 | u32 pclk; | |
319 | u32 dsi_clk; | |
320 | u32 dsi_ratio; | |
321 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
322 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
323 | ||
324 | /* Divide by zero */ | |
325 | if (!pipe_bpp) { | |
326 | DRM_ERROR("Invalid BPP(0)\n"); | |
327 | return 0; | |
328 | } | |
329 | ||
330 | dsi_ratio = I915_READ(BXT_DSI_PLL_CTL) & | |
331 | BXT_DSI_PLL_RATIO_MASK; | |
332 | ||
333 | /* Invalid DSI ratio ? */ | |
334 | if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN || | |
335 | dsi_ratio > BXT_DSI_PLL_RATIO_MAX) { | |
336 | DRM_ERROR("Invalid DSI pll ratio(%u) programmed\n", dsi_ratio); | |
337 | return 0; | |
338 | } | |
339 | ||
340 | dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2; | |
341 | ||
342 | /* pixel_format and pipe_bpp should agree */ | |
343 | assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp); | |
344 | ||
345 | pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp); | |
346 | ||
347 | DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk); | |
348 | return pclk; | |
349 | } | |
350 | ||
d7d85d85 JN |
351 | u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp) |
352 | { | |
353 | if (IS_BROXTON(encoder->base.dev)) | |
354 | return bxt_dsi_get_pclk(encoder, pipe_bpp); | |
355 | else | |
356 | return vlv_dsi_get_pclk(encoder, pipe_bpp); | |
357 | } | |
358 | ||
b248e654 | 359 | static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) |
b389a45c SS |
360 | { |
361 | u32 temp; | |
362 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
363 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
364 | ||
365 | temp = I915_READ(MIPI_CTRL(port)); | |
366 | temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; | |
367 | I915_WRITE(MIPI_CTRL(port), temp | | |
368 | intel_dsi->escape_clk_div << | |
369 | ESCAPE_CLOCK_DIVIDER_SHIFT); | |
370 | } | |
371 | ||
11b8e4f5 SS |
372 | /* Program BXT Mipi clocks and dividers */ |
373 | static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port) | |
374 | { | |
11b8e4f5 | 375 | struct drm_i915_private *dev_priv = dev->dev_private; |
782d25ca D |
376 | u32 tmp; |
377 | u32 dsi_rate = 0; | |
378 | u32 pll_ratio = 0; | |
379 | u32 rx_div; | |
380 | u32 tx_div; | |
381 | u32 rx_div_upper; | |
382 | u32 rx_div_lower; | |
383 | u32 mipi_8by3_divider; | |
11b8e4f5 SS |
384 | |
385 | /* Clear old configurations */ | |
386 | tmp = I915_READ(BXT_MIPI_CLOCK_CTL); | |
387 | tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); | |
782d25ca D |
388 | tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port)); |
389 | tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port)); | |
390 | tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port)); | |
11b8e4f5 SS |
391 | |
392 | /* Get the current DSI rate(actual) */ | |
393 | pll_ratio = I915_READ(BXT_DSI_PLL_CTL) & | |
394 | BXT_DSI_PLL_RATIO_MASK; | |
395 | dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2; | |
396 | ||
782d25ca D |
397 | /* |
398 | * tx clock should be <= 20MHz and the div value must be | |
399 | * subtracted by 1 as per bspec | |
400 | */ | |
401 | tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1; | |
402 | /* | |
403 | * rx clock should be <= 150MHz and the div value must be | |
404 | * subtracted by 1 as per bspec | |
405 | */ | |
406 | rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1; | |
11b8e4f5 SS |
407 | |
408 | /* | |
782d25ca D |
409 | * rx divider value needs to be updated in the |
410 | * two differnt bit fields in the register hence splitting the | |
411 | * rx divider value accordingly | |
11b8e4f5 | 412 | */ |
782d25ca D |
413 | rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2; |
414 | rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2; | |
415 | ||
416 | /* As per bpsec program the 8/3X clock divider to the below value */ | |
417 | if (dev_priv->vbt.dsi.config->is_cmd_mode) | |
418 | mipi_8by3_divider = 0x2; | |
419 | else | |
420 | mipi_8by3_divider = 0x3; | |
11b8e4f5 | 421 | |
782d25ca D |
422 | tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider); |
423 | tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div); | |
424 | tmp |= BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, rx_div_lower); | |
425 | tmp |= BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, rx_div_upper); | |
11b8e4f5 SS |
426 | |
427 | I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); | |
428 | } | |
429 | ||
cfe01a5e SS |
430 | static bool bxt_configure_dsi_pll(struct intel_encoder *encoder) |
431 | { | |
432 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
433 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
434 | u8 dsi_ratio; | |
435 | u32 dsi_clk; | |
436 | u32 val; | |
437 | ||
438 | dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, | |
439 | intel_dsi->lane_count); | |
440 | ||
441 | /* | |
442 | * From clock diagram, to get PLL ratio divider, divide double of DSI | |
443 | * link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to | |
444 | * round 'up' the result | |
445 | */ | |
446 | dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ); | |
447 | if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN || | |
448 | dsi_ratio > BXT_DSI_PLL_RATIO_MAX) { | |
449 | DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n"); | |
450 | return false; | |
451 | } | |
452 | ||
453 | /* | |
454 | * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x | |
455 | * Spec says both have to be programmed, even if one is not getting | |
456 | * used. Configure MIPI_CLOCK_CTL dividers in modeset | |
457 | */ | |
458 | val = I915_READ(BXT_DSI_PLL_CTL); | |
459 | val &= ~BXT_DSI_PLL_PVD_RATIO_MASK; | |
460 | val &= ~BXT_DSI_FREQ_SEL_MASK; | |
461 | val &= ~BXT_DSI_PLL_RATIO_MASK; | |
462 | val |= (dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2); | |
463 | ||
464 | /* As per recommendation from hardware team, | |
465 | * Prog PVD ratio =1 if dsi ratio <= 50 | |
466 | */ | |
467 | if (dsi_ratio <= 50) { | |
468 | val &= ~BXT_DSI_PLL_PVD_RATIO_MASK; | |
469 | val |= BXT_DSI_PLL_PVD_RATIO_1; | |
470 | } | |
471 | ||
472 | I915_WRITE(BXT_DSI_PLL_CTL, val); | |
473 | POSTING_READ(BXT_DSI_PLL_CTL); | |
474 | ||
475 | return true; | |
476 | } | |
477 | ||
478 | static void bxt_enable_dsi_pll(struct intel_encoder *encoder) | |
479 | { | |
480 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
11b8e4f5 SS |
481 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
482 | enum port port; | |
cfe01a5e SS |
483 | u32 val; |
484 | ||
485 | DRM_DEBUG_KMS("\n"); | |
486 | ||
cfe01a5e SS |
487 | /* Configure PLL vales */ |
488 | if (!bxt_configure_dsi_pll(encoder)) { | |
489 | DRM_ERROR("Configure DSI PLL failed, abort PLL enable\n"); | |
490 | return; | |
491 | } | |
492 | ||
11b8e4f5 SS |
493 | /* Program TX, RX, Dphy clocks */ |
494 | for_each_dsi_port(port, intel_dsi->ports) | |
495 | bxt_dsi_program_clocks(encoder->base.dev, port); | |
496 | ||
cfe01a5e SS |
497 | /* Enable DSI PLL */ |
498 | val = I915_READ(BXT_DSI_PLL_ENABLE); | |
499 | val |= BXT_DSI_PLL_DO_ENABLE; | |
500 | I915_WRITE(BXT_DSI_PLL_ENABLE, val); | |
501 | ||
502 | /* Timeout and fail if PLL not locked */ | |
503 | if (wait_for(I915_READ(BXT_DSI_PLL_ENABLE) & BXT_DSI_PLL_LOCKED, 1)) { | |
504 | DRM_ERROR("Timed out waiting for DSI PLL to lock\n"); | |
505 | return; | |
506 | } | |
507 | ||
508 | DRM_DEBUG_KMS("DSI PLL locked\n"); | |
509 | } | |
510 | ||
db18b6a6 ID |
511 | bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv) |
512 | { | |
513 | if (IS_BROXTON(dev_priv)) | |
514 | return bxt_dsi_pll_is_enabled(dev_priv); | |
515 | ||
516 | MISSING_CASE(INTEL_DEVID(dev_priv)); | |
517 | ||
518 | return false; | |
519 | } | |
520 | ||
cfe01a5e SS |
521 | void intel_enable_dsi_pll(struct intel_encoder *encoder) |
522 | { | |
523 | struct drm_device *dev = encoder->base.dev; | |
524 | ||
666a4537 | 525 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
cfe01a5e SS |
526 | vlv_enable_dsi_pll(encoder); |
527 | else if (IS_BROXTON(dev)) | |
528 | bxt_enable_dsi_pll(encoder); | |
529 | } | |
fe88fc68 SS |
530 | |
531 | void intel_disable_dsi_pll(struct intel_encoder *encoder) | |
532 | { | |
533 | struct drm_device *dev = encoder->base.dev; | |
534 | ||
666a4537 | 535 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
fe88fc68 SS |
536 | vlv_disable_dsi_pll(encoder); |
537 | else if (IS_BROXTON(dev)) | |
538 | bxt_disable_dsi_pll(encoder); | |
539 | } | |
b389a45c | 540 | |
b248e654 | 541 | static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) |
b389a45c SS |
542 | { |
543 | u32 tmp; | |
544 | struct drm_device *dev = encoder->base.dev; | |
545 | struct drm_i915_private *dev_priv = dev->dev_private; | |
546 | ||
547 | /* Clear old configurations */ | |
548 | tmp = I915_READ(BXT_MIPI_CLOCK_CTL); | |
549 | tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); | |
782d25ca D |
550 | tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port)); |
551 | tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port)); | |
552 | tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port)); | |
b389a45c SS |
553 | I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); |
554 | I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); | |
555 | } | |
556 | ||
557 | void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) | |
558 | { | |
559 | struct drm_device *dev = encoder->base.dev; | |
560 | ||
561 | if (IS_BROXTON(dev)) | |
562 | bxt_dsi_reset_clocks(encoder, port); | |
666a4537 | 563 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
b389a45c SS |
564 | vlv_dsi_reset_clocks(encoder, port); |
565 | } |