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be4fc046 | 1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Shobhit Kumar <shobhit.kumar@intel.com> | |
25 | * Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com> | |
26 | */ | |
27 | ||
28 | #include <linux/kernel.h> | |
29 | #include "intel_drv.h" | |
30 | #include "i915_drv.h" | |
31 | #include "intel_dsi.h" | |
32 | ||
33 | #define DSI_HSS_PACKET_SIZE 4 | |
34 | #define DSI_HSE_PACKET_SIZE 4 | |
35 | #define DSI_HSA_PACKET_EXTRA_SIZE 6 | |
36 | #define DSI_HBP_PACKET_EXTRA_SIZE 6 | |
37 | #define DSI_HACTIVE_PACKET_EXTRA_SIZE 6 | |
38 | #define DSI_HFP_PACKET_EXTRA_SIZE 6 | |
39 | #define DSI_EOTP_PACKET_SIZE 4 | |
40 | ||
260c1ad1 JN |
41 | static int dsi_pixel_format_bpp(int pixel_format) |
42 | { | |
43 | int bpp; | |
44 | ||
45 | switch (pixel_format) { | |
46 | default: | |
47 | case VID_MODE_FORMAT_RGB888: | |
48 | case VID_MODE_FORMAT_RGB666_LOOSE: | |
49 | bpp = 24; | |
50 | break; | |
51 | case VID_MODE_FORMAT_RGB666: | |
52 | bpp = 18; | |
53 | break; | |
54 | case VID_MODE_FORMAT_RGB565: | |
55 | bpp = 16; | |
56 | break; | |
57 | } | |
58 | ||
59 | return bpp; | |
60 | } | |
61 | ||
be4fc046 | 62 | struct dsi_mnp { |
63 | u32 dsi_pll_ctrl; | |
64 | u32 dsi_pll_div; | |
65 | }; | |
66 | ||
67 | static const u32 lfsr_converts[] = { | |
68 | 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */ | |
69 | 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */ | |
3c5c6d88 GS |
70 | 106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */ |
71 | 71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */ | |
be4fc046 | 72 | }; |
73 | ||
44d4c6ee SK |
74 | #ifdef DSI_CLK_FROM_RR |
75 | ||
a7482145 | 76 | static u32 dsi_rr_formula(const struct drm_display_mode *mode, |
be4fc046 | 77 | int pixel_format, int video_mode_format, |
78 | int lane_count, bool eotp) | |
79 | { | |
80 | u32 bpp; | |
81 | u32 hactive, vactive, hfp, hsync, hbp, vfp, vsync, vbp; | |
82 | u32 hsync_bytes, hbp_bytes, hactive_bytes, hfp_bytes; | |
83 | u32 bytes_per_line, bytes_per_frame; | |
84 | u32 num_frames; | |
85 | u32 bytes_per_x_frames, bytes_per_x_frames_x_lanes; | |
86 | u32 dsi_bit_clock_hz; | |
87 | u32 dsi_clk; | |
88 | ||
260c1ad1 | 89 | bpp = dsi_pixel_format_bpp(pixel_format); |
be4fc046 | 90 | |
91 | hactive = mode->hdisplay; | |
92 | vactive = mode->vdisplay; | |
93 | hfp = mode->hsync_start - mode->hdisplay; | |
94 | hsync = mode->hsync_end - mode->hsync_start; | |
95 | hbp = mode->htotal - mode->hsync_end; | |
96 | ||
97 | vfp = mode->vsync_start - mode->vdisplay; | |
98 | vsync = mode->vsync_end - mode->vsync_start; | |
99 | vbp = mode->vtotal - mode->vsync_end; | |
100 | ||
101 | hsync_bytes = DIV_ROUND_UP(hsync * bpp, 8); | |
102 | hbp_bytes = DIV_ROUND_UP(hbp * bpp, 8); | |
103 | hactive_bytes = DIV_ROUND_UP(hactive * bpp, 8); | |
104 | hfp_bytes = DIV_ROUND_UP(hfp * bpp, 8); | |
105 | ||
106 | bytes_per_line = DSI_HSS_PACKET_SIZE + hsync_bytes + | |
107 | DSI_HSA_PACKET_EXTRA_SIZE + DSI_HSE_PACKET_SIZE + | |
108 | hbp_bytes + DSI_HBP_PACKET_EXTRA_SIZE + | |
109 | hactive_bytes + DSI_HACTIVE_PACKET_EXTRA_SIZE + | |
110 | hfp_bytes + DSI_HFP_PACKET_EXTRA_SIZE; | |
111 | ||
112 | /* | |
113 | * XXX: Need to accurately calculate LP to HS transition timeout and add | |
114 | * it to bytes_per_line/bytes_per_frame. | |
115 | */ | |
116 | ||
117 | if (eotp && video_mode_format == VIDEO_MODE_BURST) | |
118 | bytes_per_line += DSI_EOTP_PACKET_SIZE; | |
119 | ||
120 | bytes_per_frame = vsync * bytes_per_line + vbp * bytes_per_line + | |
121 | vactive * bytes_per_line + vfp * bytes_per_line; | |
122 | ||
123 | if (eotp && | |
124 | (video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE || | |
125 | video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS)) | |
126 | bytes_per_frame += DSI_EOTP_PACKET_SIZE; | |
127 | ||
128 | num_frames = drm_mode_vrefresh(mode); | |
129 | bytes_per_x_frames = num_frames * bytes_per_frame; | |
130 | ||
131 | bytes_per_x_frames_x_lanes = bytes_per_x_frames / lane_count; | |
132 | ||
133 | /* the dsi clock is divided by 2 in the hardware to get dsi ddr clock */ | |
134 | dsi_bit_clock_hz = bytes_per_x_frames_x_lanes * 8; | |
44d4c6ee | 135 | dsi_clk = dsi_bit_clock_hz / 1000; |
be4fc046 | 136 | |
137 | if (eotp && video_mode_format == VIDEO_MODE_BURST) | |
138 | dsi_clk *= 2; | |
139 | ||
140 | return dsi_clk; | |
141 | } | |
142 | ||
44d4c6ee | 143 | #else |
be4fc046 | 144 | |
44d4c6ee | 145 | /* Get DSI clock from pixel clock */ |
7f0c8605 | 146 | static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count) |
be4fc046 | 147 | { |
44d4c6ee | 148 | u32 dsi_clk_khz; |
260c1ad1 | 149 | u32 bpp = dsi_pixel_format_bpp(pixel_format); |
be4fc046 | 150 | |
44d4c6ee SK |
151 | /* DSI data rate = pixel clock * bits per pixel / lane count |
152 | pixel clock is converted from KHz to Hz */ | |
7f0c8605 | 153 | dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); |
be4fc046 | 154 | |
44d4c6ee | 155 | return dsi_clk_khz; |
be4fc046 | 156 | } |
157 | ||
44d4c6ee | 158 | #endif |
be4fc046 | 159 | |
20dbe1a1 GS |
160 | static int dsi_calc_mnp(struct drm_i915_private *dev_priv, |
161 | struct dsi_mnp *dsi_mnp, int target_dsi_clk) | |
be4fc046 | 162 | { |
7471bf4e | 163 | unsigned int calc_m = 0, calc_p = 0; |
20dbe1a1 GS |
164 | unsigned int m_min, m_max, p_min = 2, p_max = 6; |
165 | unsigned int m, n, p; | |
166 | int ref_clk; | |
7471bf4e | 167 | int delta = target_dsi_clk; |
be4fc046 | 168 | u32 m_seed; |
169 | ||
7471bf4e JN |
170 | /* target_dsi_clk is expected in kHz */ |
171 | if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) { | |
be4fc046 | 172 | DRM_ERROR("DSI CLK Out of Range\n"); |
173 | return -ECHRNG; | |
174 | } | |
175 | ||
20dbe1a1 GS |
176 | if (IS_CHERRYVIEW(dev_priv)) { |
177 | ref_clk = 100000; | |
178 | n = 4; | |
179 | m_min = 70; | |
180 | m_max = 96; | |
181 | } else { | |
182 | ref_clk = 25000; | |
183 | n = 1; | |
184 | m_min = 62; | |
185 | m_max = 92; | |
186 | } | |
187 | ||
188 | for (m = m_min; m <= m_max && delta; m++) { | |
189 | for (p = p_min; p <= p_max && delta; p++) { | |
7471bf4e JN |
190 | /* |
191 | * Find the optimal m and p divisors with minimal delta | |
192 | * +/- the required clock | |
193 | */ | |
a856c5bd | 194 | int calc_dsi_clk = (m * ref_clk) / (p * n); |
7471bf4e JN |
195 | int d = abs(target_dsi_clk - calc_dsi_clk); |
196 | if (d < delta) { | |
197 | delta = d; | |
8e1eed5a SK |
198 | calc_m = m; |
199 | calc_p = p; | |
be4fc046 | 200 | } |
201 | } | |
202 | } | |
203 | ||
a856c5bd JN |
204 | /* register has log2(N1), this works fine for powers of two */ |
205 | n = ffs(n) - 1; | |
be4fc046 | 206 | m_seed = lfsr_converts[calc_m - 62]; |
be4fc046 | 207 | dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2); |
a856c5bd | 208 | dsi_mnp->dsi_pll_div = n << DSI_PLL_N1_DIV_SHIFT | |
be4fc046 | 209 | m_seed << DSI_PLL_M1_DIV_SHIFT; |
210 | ||
211 | return 0; | |
212 | } | |
213 | ||
be4fc046 | 214 | /* |
215 | * XXX: The muxing and gating is hard coded for now. Need to add support for | |
216 | * sharing PLLs with two DSI outputs. | |
217 | */ | |
218 | static void vlv_configure_dsi_pll(struct intel_encoder *encoder) | |
219 | { | |
220 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
be4fc046 | 221 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
222 | int ret; | |
223 | struct dsi_mnp dsi_mnp; | |
224 | u32 dsi_clk; | |
225 | ||
7f0c8605 | 226 | dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, |
7f3de833 | 227 | intel_dsi->lane_count); |
be4fc046 | 228 | |
20dbe1a1 | 229 | ret = dsi_calc_mnp(dev_priv, &dsi_mnp, dsi_clk); |
be4fc046 | 230 | if (ret) { |
231 | DRM_DEBUG_KMS("dsi_calc_mnp failed\n"); | |
232 | return; | |
233 | } | |
234 | ||
3c860ab4 GS |
235 | if (intel_dsi->ports & (1 << PORT_A)) |
236 | dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL; | |
be4fc046 | 237 | |
3c860ab4 | 238 | if (intel_dsi->ports & (1 << PORT_C)) |
58cf8887 GS |
239 | dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL; |
240 | ||
be4fc046 | 241 | DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n", |
242 | dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl); | |
243 | ||
244 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0); | |
245 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, dsi_mnp.dsi_pll_div); | |
246 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, dsi_mnp.dsi_pll_ctrl); | |
247 | } | |
248 | ||
cfe01a5e | 249 | static void vlv_enable_dsi_pll(struct intel_encoder *encoder) |
be4fc046 | 250 | { |
251 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
252 | u32 tmp; | |
253 | ||
254 | DRM_DEBUG_KMS("\n"); | |
255 | ||
a580516d | 256 | mutex_lock(&dev_priv->sb_lock); |
be4fc046 | 257 | |
258 | vlv_configure_dsi_pll(encoder); | |
259 | ||
260 | /* wait at least 0.5 us after ungating before enabling VCO */ | |
261 | usleep_range(1, 10); | |
262 | ||
263 | tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
264 | tmp |= DSI_PLL_VCO_EN; | |
265 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); | |
266 | ||
3770f0ee GS |
267 | if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) & |
268 | DSI_PLL_LOCK, 20)) { | |
be4fc046 | 269 | |
a580516d | 270 | mutex_unlock(&dev_priv->sb_lock); |
be4fc046 | 271 | DRM_ERROR("DSI PLL lock failed\n"); |
272 | return; | |
273 | } | |
a580516d | 274 | mutex_unlock(&dev_priv->sb_lock); |
be4fc046 | 275 | |
276 | DRM_DEBUG_KMS("DSI PLL locked\n"); | |
277 | } | |
278 | ||
fe88fc68 | 279 | static void vlv_disable_dsi_pll(struct intel_encoder *encoder) |
be4fc046 | 280 | { |
281 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
282 | u32 tmp; | |
283 | ||
284 | DRM_DEBUG_KMS("\n"); | |
285 | ||
a580516d | 286 | mutex_lock(&dev_priv->sb_lock); |
be4fc046 | 287 | |
288 | tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
289 | tmp &= ~DSI_PLL_VCO_EN; | |
290 | tmp |= DSI_PLL_LDO_GATE; | |
291 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); | |
292 | ||
a580516d | 293 | mutex_unlock(&dev_priv->sb_lock); |
be4fc046 | 294 | } |
f573de5a | 295 | |
fe88fc68 SS |
296 | static void bxt_disable_dsi_pll(struct intel_encoder *encoder) |
297 | { | |
298 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
299 | u32 val; | |
300 | ||
301 | DRM_DEBUG_KMS("\n"); | |
302 | ||
303 | val = I915_READ(BXT_DSI_PLL_ENABLE); | |
304 | val &= ~BXT_DSI_PLL_DO_ENABLE; | |
305 | I915_WRITE(BXT_DSI_PLL_ENABLE, val); | |
306 | ||
307 | /* | |
308 | * PLL lock should deassert within 200us. | |
309 | * Wait up to 1ms before timing out. | |
310 | */ | |
311 | if (wait_for((I915_READ(BXT_DSI_PLL_ENABLE) | |
312 | & BXT_DSI_PLL_LOCKED) == 0, 1)) | |
313 | DRM_ERROR("Timeout waiting for PLL lock deassertion\n"); | |
314 | } | |
315 | ||
f573de5a SK |
316 | static void assert_bpp_mismatch(int pixel_format, int pipe_bpp) |
317 | { | |
260c1ad1 | 318 | int bpp = dsi_pixel_format_bpp(pixel_format); |
f573de5a SK |
319 | |
320 | WARN(bpp != pipe_bpp, | |
7f3de833 DV |
321 | "bpp match assertion failure (expected %d, current %d)\n", |
322 | bpp, pipe_bpp); | |
f573de5a SK |
323 | } |
324 | ||
325 | u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp) | |
326 | { | |
327 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
328 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
329 | u32 dsi_clock, pclk; | |
330 | u32 pll_ctl, pll_div; | |
a856c5bd | 331 | u32 m = 0, p = 0, n; |
f573de5a SK |
332 | int refclk = 25000; |
333 | int i; | |
334 | ||
335 | DRM_DEBUG_KMS("\n"); | |
336 | ||
a580516d | 337 | mutex_lock(&dev_priv->sb_lock); |
f573de5a SK |
338 | pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
339 | pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER); | |
a580516d | 340 | mutex_unlock(&dev_priv->sb_lock); |
f573de5a SK |
341 | |
342 | /* mask out other bits and extract the P1 divisor */ | |
343 | pll_ctl &= DSI_PLL_P1_POST_DIV_MASK; | |
344 | pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2); | |
345 | ||
a856c5bd JN |
346 | /* N1 divisor */ |
347 | n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT; | |
348 | n = 1 << n; /* register has log2(N1) */ | |
349 | ||
f573de5a SK |
350 | /* mask out the other bits and extract the M1 divisor */ |
351 | pll_div &= DSI_PLL_M1_DIV_MASK; | |
352 | pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT; | |
353 | ||
354 | while (pll_ctl) { | |
355 | pll_ctl = pll_ctl >> 1; | |
356 | p++; | |
357 | } | |
358 | p--; | |
359 | ||
360 | if (!p) { | |
361 | DRM_ERROR("wrong P1 divisor\n"); | |
362 | return 0; | |
363 | } | |
364 | ||
365 | for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) { | |
366 | if (lfsr_converts[i] == pll_div) | |
367 | break; | |
368 | } | |
369 | ||
370 | if (i == ARRAY_SIZE(lfsr_converts)) { | |
371 | DRM_ERROR("wrong m_seed programmed\n"); | |
372 | return 0; | |
373 | } | |
374 | ||
375 | m = i + 62; | |
376 | ||
a856c5bd | 377 | dsi_clock = (m * refclk) / (p * n); |
f573de5a SK |
378 | |
379 | /* pixel_format and pipe_bpp should agree */ | |
380 | assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp); | |
381 | ||
382 | pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp); | |
383 | ||
384 | return pclk; | |
385 | } | |
cfe01a5e | 386 | |
ce0c9821 SS |
387 | u32 bxt_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp) |
388 | { | |
389 | u32 pclk; | |
390 | u32 dsi_clk; | |
391 | u32 dsi_ratio; | |
392 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
393 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
394 | ||
395 | /* Divide by zero */ | |
396 | if (!pipe_bpp) { | |
397 | DRM_ERROR("Invalid BPP(0)\n"); | |
398 | return 0; | |
399 | } | |
400 | ||
401 | dsi_ratio = I915_READ(BXT_DSI_PLL_CTL) & | |
402 | BXT_DSI_PLL_RATIO_MASK; | |
403 | ||
404 | /* Invalid DSI ratio ? */ | |
405 | if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN || | |
406 | dsi_ratio > BXT_DSI_PLL_RATIO_MAX) { | |
407 | DRM_ERROR("Invalid DSI pll ratio(%u) programmed\n", dsi_ratio); | |
408 | return 0; | |
409 | } | |
410 | ||
411 | dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2; | |
412 | ||
413 | /* pixel_format and pipe_bpp should agree */ | |
414 | assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp); | |
415 | ||
416 | pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp); | |
417 | ||
418 | DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk); | |
419 | return pclk; | |
420 | } | |
421 | ||
b248e654 | 422 | static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) |
b389a45c SS |
423 | { |
424 | u32 temp; | |
425 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
426 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
427 | ||
428 | temp = I915_READ(MIPI_CTRL(port)); | |
429 | temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; | |
430 | I915_WRITE(MIPI_CTRL(port), temp | | |
431 | intel_dsi->escape_clk_div << | |
432 | ESCAPE_CLOCK_DIVIDER_SHIFT); | |
433 | } | |
434 | ||
11b8e4f5 SS |
435 | /* Program BXT Mipi clocks and dividers */ |
436 | static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port) | |
437 | { | |
438 | u32 tmp; | |
439 | u32 divider; | |
440 | u32 dsi_rate; | |
441 | u32 pll_ratio; | |
442 | struct drm_i915_private *dev_priv = dev->dev_private; | |
443 | ||
444 | /* Clear old configurations */ | |
445 | tmp = I915_READ(BXT_MIPI_CLOCK_CTL); | |
446 | tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); | |
447 | tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port)); | |
448 | tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port)); | |
449 | tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port)); | |
450 | ||
451 | /* Get the current DSI rate(actual) */ | |
452 | pll_ratio = I915_READ(BXT_DSI_PLL_CTL) & | |
453 | BXT_DSI_PLL_RATIO_MASK; | |
454 | dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2; | |
455 | ||
456 | /* Max possible output of clock is 39.5 MHz, program value -1 */ | |
457 | divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1; | |
458 | tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider); | |
459 | ||
460 | /* | |
461 | * Tx escape clock must be as close to 20MHz possible, but should | |
462 | * not exceed it. Hence select divide by 2 | |
463 | */ | |
464 | tmp |= BXT_MIPI_TX_ESCLK_8XDIV_BY2(port); | |
465 | ||
466 | tmp |= BXT_MIPI_RX_ESCLK_8X_BY3(port); | |
467 | ||
468 | I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); | |
469 | } | |
470 | ||
cfe01a5e SS |
471 | static bool bxt_configure_dsi_pll(struct intel_encoder *encoder) |
472 | { | |
473 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
474 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
475 | u8 dsi_ratio; | |
476 | u32 dsi_clk; | |
477 | u32 val; | |
478 | ||
479 | dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, | |
480 | intel_dsi->lane_count); | |
481 | ||
482 | /* | |
483 | * From clock diagram, to get PLL ratio divider, divide double of DSI | |
484 | * link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to | |
485 | * round 'up' the result | |
486 | */ | |
487 | dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ); | |
488 | if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN || | |
489 | dsi_ratio > BXT_DSI_PLL_RATIO_MAX) { | |
490 | DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n"); | |
491 | return false; | |
492 | } | |
493 | ||
494 | /* | |
495 | * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x | |
496 | * Spec says both have to be programmed, even if one is not getting | |
497 | * used. Configure MIPI_CLOCK_CTL dividers in modeset | |
498 | */ | |
499 | val = I915_READ(BXT_DSI_PLL_CTL); | |
500 | val &= ~BXT_DSI_PLL_PVD_RATIO_MASK; | |
501 | val &= ~BXT_DSI_FREQ_SEL_MASK; | |
502 | val &= ~BXT_DSI_PLL_RATIO_MASK; | |
503 | val |= (dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2); | |
504 | ||
505 | /* As per recommendation from hardware team, | |
506 | * Prog PVD ratio =1 if dsi ratio <= 50 | |
507 | */ | |
508 | if (dsi_ratio <= 50) { | |
509 | val &= ~BXT_DSI_PLL_PVD_RATIO_MASK; | |
510 | val |= BXT_DSI_PLL_PVD_RATIO_1; | |
511 | } | |
512 | ||
513 | I915_WRITE(BXT_DSI_PLL_CTL, val); | |
514 | POSTING_READ(BXT_DSI_PLL_CTL); | |
515 | ||
516 | return true; | |
517 | } | |
518 | ||
519 | static void bxt_enable_dsi_pll(struct intel_encoder *encoder) | |
520 | { | |
521 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
11b8e4f5 SS |
522 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
523 | enum port port; | |
cfe01a5e SS |
524 | u32 val; |
525 | ||
526 | DRM_DEBUG_KMS("\n"); | |
527 | ||
528 | val = I915_READ(BXT_DSI_PLL_ENABLE); | |
529 | ||
530 | if (val & BXT_DSI_PLL_DO_ENABLE) { | |
531 | WARN(1, "DSI PLL already enabled. Disabling it.\n"); | |
532 | val &= ~BXT_DSI_PLL_DO_ENABLE; | |
533 | I915_WRITE(BXT_DSI_PLL_ENABLE, val); | |
534 | } | |
535 | ||
536 | /* Configure PLL vales */ | |
537 | if (!bxt_configure_dsi_pll(encoder)) { | |
538 | DRM_ERROR("Configure DSI PLL failed, abort PLL enable\n"); | |
539 | return; | |
540 | } | |
541 | ||
11b8e4f5 SS |
542 | /* Program TX, RX, Dphy clocks */ |
543 | for_each_dsi_port(port, intel_dsi->ports) | |
544 | bxt_dsi_program_clocks(encoder->base.dev, port); | |
545 | ||
cfe01a5e SS |
546 | /* Enable DSI PLL */ |
547 | val = I915_READ(BXT_DSI_PLL_ENABLE); | |
548 | val |= BXT_DSI_PLL_DO_ENABLE; | |
549 | I915_WRITE(BXT_DSI_PLL_ENABLE, val); | |
550 | ||
551 | /* Timeout and fail if PLL not locked */ | |
552 | if (wait_for(I915_READ(BXT_DSI_PLL_ENABLE) & BXT_DSI_PLL_LOCKED, 1)) { | |
553 | DRM_ERROR("Timed out waiting for DSI PLL to lock\n"); | |
554 | return; | |
555 | } | |
556 | ||
557 | DRM_DEBUG_KMS("DSI PLL locked\n"); | |
558 | } | |
559 | ||
560 | void intel_enable_dsi_pll(struct intel_encoder *encoder) | |
561 | { | |
562 | struct drm_device *dev = encoder->base.dev; | |
563 | ||
564 | if (IS_VALLEYVIEW(dev)) | |
565 | vlv_enable_dsi_pll(encoder); | |
566 | else if (IS_BROXTON(dev)) | |
567 | bxt_enable_dsi_pll(encoder); | |
568 | } | |
fe88fc68 SS |
569 | |
570 | void intel_disable_dsi_pll(struct intel_encoder *encoder) | |
571 | { | |
572 | struct drm_device *dev = encoder->base.dev; | |
573 | ||
574 | if (IS_VALLEYVIEW(dev)) | |
575 | vlv_disable_dsi_pll(encoder); | |
576 | else if (IS_BROXTON(dev)) | |
577 | bxt_disable_dsi_pll(encoder); | |
578 | } | |
b389a45c | 579 | |
b248e654 | 580 | static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) |
b389a45c SS |
581 | { |
582 | u32 tmp; | |
583 | struct drm_device *dev = encoder->base.dev; | |
584 | struct drm_i915_private *dev_priv = dev->dev_private; | |
585 | ||
586 | /* Clear old configurations */ | |
587 | tmp = I915_READ(BXT_MIPI_CLOCK_CTL); | |
588 | tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); | |
589 | tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port)); | |
590 | tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port)); | |
591 | tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port)); | |
592 | I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); | |
593 | I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); | |
594 | } | |
595 | ||
596 | void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) | |
597 | { | |
598 | struct drm_device *dev = encoder->base.dev; | |
599 | ||
600 | if (IS_BROXTON(dev)) | |
601 | bxt_dsi_reset_clocks(encoder, port); | |
602 | else if (IS_VALLEYVIEW(dev)) | |
603 | vlv_dsi_reset_clocks(encoder, port); | |
604 | } |