[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dsi_pll.c

/*
 * Copyright © 2013 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Shobhit Kumar <shobhit.kumar@intel.com>
 *	Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
 */

#include <linux/kernel.h>
#include "intel_drv.h"
#include "i915_drv.h"
#include "intel_dsi.h"

#define DSI_HSS_PACKET_SIZE		4
#define DSI_HSE_PACKET_SIZE		4
#define DSI_HSA_PACKET_EXTRA_SIZE	6
#define DSI_HBP_PACKET_EXTRA_SIZE	6
#define DSI_HACTIVE_PACKET_EXTRA_SIZE	6
#define DSI_HFP_PACKET_EXTRA_SIZE	6
#define DSI_EOTP_PACKET_SIZE		4

static int dsi_pixel_format_bpp(int pixel_format)
{
	int bpp;

	switch (pixel_format) {
	default:
	case VID_MODE_FORMAT_RGB888:
	case VID_MODE_FORMAT_RGB666_LOOSE:
		bpp = 24;
		break;
	case VID_MODE_FORMAT_RGB666:
		bpp = 18;
		break;
	case VID_MODE_FORMAT_RGB565:
		bpp = 16;
		break;
	}

	return bpp;
}

struct dsi_mnp {
	u32 dsi_pll_ctrl;
	u32 dsi_pll_div;
};

static const u32 lfsr_converts[] = {
	426, 469, 234, 373, 442, 221, 110, 311, 411,		/* 62 - 70 */
	461, 486, 243, 377, 188, 350, 175, 343, 427, 213,	/* 71 - 80 */
	106, 53, 282, 397, 454, 227, 113, 56, 284, 142,		/* 81 - 90 */
	71, 35, 273, 136, 324, 418, 465, 488, 500, 506		/* 91 - 100 */
};

#ifdef DSI_CLK_FROM_RR

static u32 dsi_rr_formula(const struct drm_display_mode *mode,
			  int pixel_format, int video_mode_format,
			  int lane_count, bool eotp)
{
	u32 bpp;
	u32 hactive, vactive, hfp, hsync, hbp, vfp, vsync, vbp;
	u32 hsync_bytes, hbp_bytes, hactive_bytes, hfp_bytes;
	u32 bytes_per_line, bytes_per_frame;
	u32 num_frames;
	u32 bytes_per_x_frames, bytes_per_x_frames_x_lanes;
	u32 dsi_bit_clock_hz;
	u32 dsi_clk;

	bpp = dsi_pixel_format_bpp(pixel_format);

	hactive = mode->hdisplay;
	vactive = mode->vdisplay;
	hfp = mode->hsync_start - mode->hdisplay;
	hsync = mode->hsync_end - mode->hsync_start;
	hbp = mode->htotal - mode->hsync_end;

	vfp = mode->vsync_start - mode->vdisplay;
	vsync = mode->vsync_end - mode->vsync_start;
	vbp = mode->vtotal - mode->vsync_end;

	hsync_bytes = DIV_ROUND_UP(hsync * bpp, 8);
	hbp_bytes = DIV_ROUND_UP(hbp * bpp, 8);
	hactive_bytes = DIV_ROUND_UP(hactive * bpp, 8);
	hfp_bytes = DIV_ROUND_UP(hfp * bpp, 8);

	bytes_per_line = DSI_HSS_PACKET_SIZE + hsync_bytes +
		DSI_HSA_PACKET_EXTRA_SIZE + DSI_HSE_PACKET_SIZE +
		hbp_bytes + DSI_HBP_PACKET_EXTRA_SIZE +
		hactive_bytes + DSI_HACTIVE_PACKET_EXTRA_SIZE +
		hfp_bytes + DSI_HFP_PACKET_EXTRA_SIZE;

	/*
	 * XXX: Need to accurately calculate LP to HS transition timeout and add
	 * it to bytes_per_line/bytes_per_frame.
	 */

	if (eotp && video_mode_format == VIDEO_MODE_BURST)
		bytes_per_line += DSI_EOTP_PACKET_SIZE;

	bytes_per_frame = vsync * bytes_per_line + vbp * bytes_per_line +
		vactive * bytes_per_line + vfp * bytes_per_line;

	if (eotp &&
	    (video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE ||
	     video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS))
		bytes_per_frame += DSI_EOTP_PACKET_SIZE;

	num_frames = drm_mode_vrefresh(mode);
	bytes_per_x_frames = num_frames * bytes_per_frame;

	bytes_per_x_frames_x_lanes = bytes_per_x_frames / lane_count;

	/* the dsi clock is divided by 2 in the hardware to get dsi ddr clock */
	dsi_bit_clock_hz = bytes_per_x_frames_x_lanes * 8;
	dsi_clk = dsi_bit_clock_hz / 1000;

	if (eotp && video_mode_format == VIDEO_MODE_BURST)
		dsi_clk *= 2;

	return dsi_clk;
}

#else

/* Get DSI clock from pixel clock */
static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count)
{
	u32 dsi_clk_khz;
	u32 bpp = dsi_pixel_format_bpp(pixel_format);

	/* DSI data rate = pixel clock * bits per pixel / lane count
	   pixel clock is converted from KHz to Hz */
	dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count);

	return dsi_clk_khz;
}

#endif

static int dsi_calc_mnp(int target_dsi_clk, struct dsi_mnp *dsi_mnp)
{
	unsigned int calc_m = 0, calc_p = 0;
	unsigned int m, n = 1, p;
	int ref_clk = 25000;
	int delta = target_dsi_clk;
	u32 m_seed;

	/* target_dsi_clk is expected in kHz */
	if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) {
		DRM_ERROR("DSI CLK Out of Range\n");
		return -ECHRNG;
	}

	for (m = 62; m <= 92 && delta; m++) {
		for (p = 2; p <= 6 && delta; p++) {
			/*
			 * Find the optimal m and p divisors with minimal delta
			 * +/- the required clock
			 */
			int calc_dsi_clk = (m * ref_clk) / (p * n);
			int d = abs(target_dsi_clk - calc_dsi_clk);
			if (d < delta) {
				delta = d;
				calc_m = m;
				calc_p = p;
			}
		}
	}

	/* register has log2(N1), this works fine for powers of two */
	n = ffs(n) - 1;
	m_seed = lfsr_converts[calc_m - 62];
	dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
	dsi_mnp->dsi_pll_div = n << DSI_PLL_N1_DIV_SHIFT |
		m_seed << DSI_PLL_M1_DIV_SHIFT;

	return 0;
}

/*
 * XXX: The muxing and gating is hard coded for now. Need to add support for
 * sharing PLLs with two DSI outputs.
 */
static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
	int ret;
	struct dsi_mnp dsi_mnp;
	u32 dsi_clk;

	dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
				    intel_dsi->lane_count);

	ret = dsi_calc_mnp(dsi_clk, &dsi_mnp);
	if (ret) {
		DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
		return;
	}

	if (intel_dsi->ports & (1 << PORT_A))
		dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;

	if (intel_dsi->ports & (1 << PORT_C))
		dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;

	DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
		      dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl);

	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, dsi_mnp.dsi_pll_div);
	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, dsi_mnp.dsi_pll_ctrl);
}

void vlv_enable_dsi_pll(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	u32 tmp;

	DRM_DEBUG_KMS("\n");

	mutex_lock(&dev_priv->sb_lock);

	vlv_configure_dsi_pll(encoder);

	/* wait at least 0.5 us after ungating before enabling VCO */
	usleep_range(1, 10);

	tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
	tmp |= DSI_PLL_VCO_EN;
	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);

	if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &
						DSI_PLL_LOCK, 20)) {

		mutex_unlock(&dev_priv->sb_lock);
		DRM_ERROR("DSI PLL lock failed\n");
		return;
	}
	mutex_unlock(&dev_priv->sb_lock);

	DRM_DEBUG_KMS("DSI PLL locked\n");
}

void vlv_disable_dsi_pll(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	u32 tmp;

	DRM_DEBUG_KMS("\n");

	mutex_lock(&dev_priv->sb_lock);

	tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
	tmp &= ~DSI_PLL_VCO_EN;
	tmp |= DSI_PLL_LDO_GATE;
	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);

	mutex_unlock(&dev_priv->sb_lock);
}

static void assert_bpp_mismatch(int pixel_format, int pipe_bpp)
{
	int bpp = dsi_pixel_format_bpp(pixel_format);

	WARN(bpp != pipe_bpp,
	     "bpp match assertion failure (expected %d, current %d)\n",
	     bpp, pipe_bpp);
}

u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
	u32 dsi_clock, pclk;
	u32 pll_ctl, pll_div;
	u32 m = 0, p = 0, n;
	int refclk = 25000;
	int i;

	DRM_DEBUG_KMS("\n");

	mutex_lock(&dev_priv->sb_lock);
	pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
	pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER);
	mutex_unlock(&dev_priv->sb_lock);

	/* mask out other bits and extract the P1 divisor */
	pll_ctl &= DSI_PLL_P1_POST_DIV_MASK;
	pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2);

	/* N1 divisor */
	n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT;
	n = 1 << n; /* register has log2(N1) */

	/* mask out the other bits and extract the M1 divisor */
	pll_div &= DSI_PLL_M1_DIV_MASK;
	pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT;

	while (pll_ctl) {
		pll_ctl = pll_ctl >> 1;
		p++;
	}
	p--;

	if (!p) {
		DRM_ERROR("wrong P1 divisor\n");
		return 0;
	}

	for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) {
		if (lfsr_converts[i] == pll_div)
			break;
	}

	if (i == ARRAY_SIZE(lfsr_converts)) {
		DRM_ERROR("wrong m_seed programmed\n");
		return 0;
	}

	m = i + 62;

	dsi_clock = (m * refclk) / (p * n);

	/* pixel_format and pipe_bpp should agree */
	assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);

	pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp);

	return pclk;
}
Commit	Line	Data
be4fc046	1	/*
	2	* Copyright © 2013 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* Shobhit Kumar <shobhit.kumar@intel.com>
	25	* Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
	26	*/
	27
	28	#include <linux/kernel.h>
	29	#include "intel_drv.h"
	30	#include "i915_drv.h"
	31	#include "intel_dsi.h"
	32
	33	#define DSI_HSS_PACKET_SIZE 4
	34	#define DSI_HSE_PACKET_SIZE 4
	35	#define DSI_HSA_PACKET_EXTRA_SIZE 6
	36	#define DSI_HBP_PACKET_EXTRA_SIZE 6
	37	#define DSI_HACTIVE_PACKET_EXTRA_SIZE 6
	38	#define DSI_HFP_PACKET_EXTRA_SIZE 6
	39	#define DSI_EOTP_PACKET_SIZE 4
	40
260c1ad1 JN	41	static int dsi_pixel_format_bpp(int pixel_format)
	42	{
	43	int bpp;
	44
	45	switch (pixel_format) {
	46	default:
	47	case VID_MODE_FORMAT_RGB888:
	48	case VID_MODE_FORMAT_RGB666_LOOSE:
	49	bpp = 24;
	50	break;
	51	case VID_MODE_FORMAT_RGB666:
	52	bpp = 18;
	53	break;
	54	case VID_MODE_FORMAT_RGB565:
	55	bpp = 16;
	56	break;
	57	}
	58
	59	return bpp;
	60	}
	61
be4fc046	62	struct dsi_mnp {
	63	u32 dsi_pll_ctrl;
	64	u32 dsi_pll_div;
	65	};
	66
	67	static const u32 lfsr_converts[] = {
	68	426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */
	69	461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */
3c5c6d88 GS	70	106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */
3c5c6d88 GS	71	71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */
be4fc046	72	};
be4fc046	73
44d4c6ee SK	74	#ifdef DSI_CLK_FROM_RR
44d4c6ee SK	75
a7482145	76	static u32 dsi_rr_formula(const struct drm_display_mode *mode,
be4fc046	77	int pixel_format, int video_mode_format,
	78	int lane_count, bool eotp)
	79	{
	80	u32 bpp;
	81	u32 hactive, vactive, hfp, hsync, hbp, vfp, vsync, vbp;
	82	u32 hsync_bytes, hbp_bytes, hactive_bytes, hfp_bytes;
	83	u32 bytes_per_line, bytes_per_frame;
	84	u32 num_frames;
	85	u32 bytes_per_x_frames, bytes_per_x_frames_x_lanes;
	86	u32 dsi_bit_clock_hz;
	87	u32 dsi_clk;
	88
260c1ad1	89	bpp = dsi_pixel_format_bpp(pixel_format);
be4fc046	90
	91	hactive = mode->hdisplay;
	92	vactive = mode->vdisplay;
	93	hfp = mode->hsync_start - mode->hdisplay;
	94	hsync = mode->hsync_end - mode->hsync_start;
	95	hbp = mode->htotal - mode->hsync_end;
	96
	97	vfp = mode->vsync_start - mode->vdisplay;
	98	vsync = mode->vsync_end - mode->vsync_start;
	99	vbp = mode->vtotal - mode->vsync_end;
	100
	101	hsync_bytes = DIV_ROUND_UP(hsync * bpp, 8);
	102	hbp_bytes = DIV_ROUND_UP(hbp * bpp, 8);
	103	hactive_bytes = DIV_ROUND_UP(hactive * bpp, 8);
	104	hfp_bytes = DIV_ROUND_UP(hfp * bpp, 8);
	105
	106	bytes_per_line = DSI_HSS_PACKET_SIZE + hsync_bytes +
	107	DSI_HSA_PACKET_EXTRA_SIZE + DSI_HSE_PACKET_SIZE +
	108	hbp_bytes + DSI_HBP_PACKET_EXTRA_SIZE +
	109	hactive_bytes + DSI_HACTIVE_PACKET_EXTRA_SIZE +
	110	hfp_bytes + DSI_HFP_PACKET_EXTRA_SIZE;
	111
	112	/*
	113	* XXX: Need to accurately calculate LP to HS transition timeout and add
	114	* it to bytes_per_line/bytes_per_frame.
	115	*/
	116
	117	if (eotp && video_mode_format == VIDEO_MODE_BURST)
	118	bytes_per_line += DSI_EOTP_PACKET_SIZE;
	119
	120	bytes_per_frame = vsync * bytes_per_line + vbp * bytes_per_line +
	121	vactive * bytes_per_line + vfp * bytes_per_line;
	122
	123	if (eotp &&
	124	(video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE \|\|
	125	video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS))
	126	bytes_per_frame += DSI_EOTP_PACKET_SIZE;
	127
	128	num_frames = drm_mode_vrefresh(mode);
	129	bytes_per_x_frames = num_frames * bytes_per_frame;
	130
	131	bytes_per_x_frames_x_lanes = bytes_per_x_frames / lane_count;
	132
	133	/* the dsi clock is divided by 2 in the hardware to get dsi ddr clock */
	134	dsi_bit_clock_hz = bytes_per_x_frames_x_lanes * 8;
44d4c6ee	135	dsi_clk = dsi_bit_clock_hz / 1000;
be4fc046	136
	137	if (eotp && video_mode_format == VIDEO_MODE_BURST)
	138	dsi_clk *= 2;
	139
	140	return dsi_clk;
	141	}
	142
44d4c6ee	143	#else
be4fc046	144
44d4c6ee	145	/* Get DSI clock from pixel clock */
7f0c8605	146	static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count)
be4fc046	147	{
44d4c6ee	148	u32 dsi_clk_khz;
260c1ad1	149	u32 bpp = dsi_pixel_format_bpp(pixel_format);
be4fc046	150
44d4c6ee SK	151	/* DSI data rate = pixel clock * bits per pixel / lane count
44d4c6ee SK	152	pixel clock is converted from KHz to Hz */
7f0c8605	153	dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count);
be4fc046	154
44d4c6ee	155	return dsi_clk_khz;
be4fc046	156	}
be4fc046	157
44d4c6ee	158	#endif
be4fc046	159
7471bf4e	160	static int dsi_calc_mnp(int target_dsi_clk, struct dsi_mnp *dsi_mnp)
be4fc046	161	{
7471bf4e	162	unsigned int calc_m = 0, calc_p = 0;
a856c5bd	163	unsigned int m, n = 1, p;
7471bf4e JN	164	int ref_clk = 25000;
7471bf4e JN	165	int delta = target_dsi_clk;
be4fc046	166	u32 m_seed;
be4fc046	167
7471bf4e JN	168	/* target_dsi_clk is expected in kHz */
7471bf4e JN	169	if (target_dsi_clk < 300000 \|\| target_dsi_clk > 1150000) {
be4fc046	170	DRM_ERROR("DSI CLK Out of Range\n");
	171	return -ECHRNG;
	172	}
	173
7471bf4e JN	174	for (m = 62; m <= 92 && delta; m++) {
	175	for (p = 2; p <= 6 && delta; p++) {
	176	/*
	177	* Find the optimal m and p divisors with minimal delta
	178	* +/- the required clock
	179	*/
a856c5bd	180	int calc_dsi_clk = (m * ref_clk) / (p * n);
7471bf4e JN	181	int d = abs(target_dsi_clk - calc_dsi_clk);
	182	if (d < delta) {
	183	delta = d;
8e1eed5a SK	184	calc_m = m;
8e1eed5a SK	185	calc_p = p;
be4fc046	186	}
	187	}
	188	}
	189
a856c5bd JN	190	/* register has log2(N1), this works fine for powers of two */
a856c5bd JN	191	n = ffs(n) - 1;
be4fc046	192	m_seed = lfsr_converts[calc_m - 62];
be4fc046	193	dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
a856c5bd	194	dsi_mnp->dsi_pll_div = n << DSI_PLL_N1_DIV_SHIFT \|
be4fc046	195	m_seed << DSI_PLL_M1_DIV_SHIFT;
	196
	197	return 0;
	198	}
	199
be4fc046	200	/*
	201	* XXX: The muxing and gating is hard coded for now. Need to add support for
	202	* sharing PLLs with two DSI outputs.
	203	*/
	204	static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
	205	{
	206	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
be4fc046	207	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
	208	int ret;
	209	struct dsi_mnp dsi_mnp;
	210	u32 dsi_clk;
	211
7f0c8605	212	dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
7f3de833	213	intel_dsi->lane_count);
be4fc046	214
	215	ret = dsi_calc_mnp(dsi_clk, &dsi_mnp);
	216	if (ret) {
	217	DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
	218	return;
	219	}
	220
3c860ab4 GS	221	if (intel_dsi->ports & (1 << PORT_A))
3c860ab4 GS	222	dsi_mnp.dsi_pll_ctrl \|= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
be4fc046	223
3c860ab4	224	if (intel_dsi->ports & (1 << PORT_C))
58cf8887 GS	225	dsi_mnp.dsi_pll_ctrl \|= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
58cf8887 GS	226
be4fc046	227	DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
	228	dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl);
	229
	230	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
	231	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, dsi_mnp.dsi_pll_div);
	232	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, dsi_mnp.dsi_pll_ctrl);
	233	}
	234
	235	void vlv_enable_dsi_pll(struct intel_encoder *encoder)
	236	{
	237	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	238	u32 tmp;
	239
	240	DRM_DEBUG_KMS("\n");
	241
a580516d	242	mutex_lock(&dev_priv->sb_lock);
be4fc046	243
	244	vlv_configure_dsi_pll(encoder);
	245
	246	/* wait at least 0.5 us after ungating before enabling VCO */
	247	usleep_range(1, 10);
	248
	249	tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
	250	tmp \|= DSI_PLL_VCO_EN;
	251	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
	252
3770f0ee GS	253	if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &
3770f0ee GS	254	DSI_PLL_LOCK, 20)) {
be4fc046	255
a580516d	256	mutex_unlock(&dev_priv->sb_lock);
be4fc046	257	DRM_ERROR("DSI PLL lock failed\n");
	258	return;
	259	}
a580516d	260	mutex_unlock(&dev_priv->sb_lock);
be4fc046	261
	262	DRM_DEBUG_KMS("DSI PLL locked\n");
	263	}
	264
	265	void vlv_disable_dsi_pll(struct intel_encoder *encoder)
	266	{
	267	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	268	u32 tmp;
	269
	270	DRM_DEBUG_KMS("\n");
	271
a580516d	272	mutex_lock(&dev_priv->sb_lock);
be4fc046	273
	274	tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
	275	tmp &= ~DSI_PLL_VCO_EN;
	276	tmp \|= DSI_PLL_LDO_GATE;
	277	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
	278
a580516d	279	mutex_unlock(&dev_priv->sb_lock);
be4fc046	280	}
f573de5a SK	281
	282	static void assert_bpp_mismatch(int pixel_format, int pipe_bpp)
	283	{
260c1ad1	284	int bpp = dsi_pixel_format_bpp(pixel_format);
f573de5a SK	285
f573de5a SK	286	WARN(bpp != pipe_bpp,
7f3de833 DV	287	"bpp match assertion failure (expected %d, current %d)\n",
7f3de833 DV	288	bpp, pipe_bpp);
f573de5a SK	289	}
	290
	291	u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
	292	{
	293	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	294	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
	295	u32 dsi_clock, pclk;
	296	u32 pll_ctl, pll_div;
a856c5bd	297	u32 m = 0, p = 0, n;
f573de5a SK	298	int refclk = 25000;
	299	int i;
	300
	301	DRM_DEBUG_KMS("\n");
	302
a580516d	303	mutex_lock(&dev_priv->sb_lock);
f573de5a SK	304	pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
f573de5a SK	305	pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER);
a580516d	306	mutex_unlock(&dev_priv->sb_lock);
f573de5a SK	307
	308	/* mask out other bits and extract the P1 divisor */
	309	pll_ctl &= DSI_PLL_P1_POST_DIV_MASK;
	310	pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2);
	311
a856c5bd JN	312	/* N1 divisor */
	313	n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT;
	314	n = 1 << n; /* register has log2(N1) */
	315
f573de5a SK	316	/* mask out the other bits and extract the M1 divisor */
	317	pll_div &= DSI_PLL_M1_DIV_MASK;
	318	pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT;
	319
	320	while (pll_ctl) {
	321	pll_ctl = pll_ctl >> 1;
	322	p++;
	323	}
	324	p--;
	325
	326	if (!p) {
	327	DRM_ERROR("wrong P1 divisor\n");
	328	return 0;
	329	}
	330
	331	for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) {
	332	if (lfsr_converts[i] == pll_div)
	333	break;
	334	}
	335
	336	if (i == ARRAY_SIZE(lfsr_converts)) {
	337	DRM_ERROR("wrong m_seed programmed\n");
	338	return 0;
	339	}
	340
	341	m = i + 62;
	342
a856c5bd	343	dsi_clock = (m * refclk) / (p * n);
f573de5a SK	344
	345	/* pixel_format and pipe_bpp should agree */
	346	assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);
	347
	348	pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp);
	349
	350	return pclk;
	351	}