Commit | Line | Data |
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be4fc046 | 1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Shobhit Kumar <shobhit.kumar@intel.com> | |
25 | * Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com> | |
26 | */ | |
27 | ||
28 | #include <linux/kernel.h> | |
29 | #include "intel_drv.h" | |
30 | #include "i915_drv.h" | |
31 | #include "intel_dsi.h" | |
32 | ||
0aa8bdf2 | 33 | int dsi_pixel_format_bpp(int pixel_format) |
260c1ad1 JN |
34 | { |
35 | int bpp; | |
36 | ||
37 | switch (pixel_format) { | |
38 | default: | |
39 | case VID_MODE_FORMAT_RGB888: | |
42c151e6 | 40 | case VID_MODE_FORMAT_RGB666: |
260c1ad1 JN |
41 | bpp = 24; |
42 | break; | |
42c151e6 | 43 | case VID_MODE_FORMAT_RGB666_PACKED: |
260c1ad1 JN |
44 | bpp = 18; |
45 | break; | |
46 | case VID_MODE_FORMAT_RGB565: | |
47 | bpp = 16; | |
48 | break; | |
49 | } | |
50 | ||
51 | return bpp; | |
52 | } | |
53 | ||
be4fc046 | 54 | struct dsi_mnp { |
55 | u32 dsi_pll_ctrl; | |
56 | u32 dsi_pll_div; | |
57 | }; | |
58 | ||
59 | static const u32 lfsr_converts[] = { | |
60 | 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */ | |
61 | 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */ | |
3c5c6d88 GS |
62 | 106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */ |
63 | 71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */ | |
be4fc046 | 64 | }; |
65 | ||
44d4c6ee | 66 | /* Get DSI clock from pixel clock */ |
7f0c8605 | 67 | static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count) |
be4fc046 | 68 | { |
44d4c6ee | 69 | u32 dsi_clk_khz; |
260c1ad1 | 70 | u32 bpp = dsi_pixel_format_bpp(pixel_format); |
be4fc046 | 71 | |
44d4c6ee SK |
72 | /* DSI data rate = pixel clock * bits per pixel / lane count |
73 | pixel clock is converted from KHz to Hz */ | |
7f0c8605 | 74 | dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); |
be4fc046 | 75 | |
44d4c6ee | 76 | return dsi_clk_khz; |
be4fc046 | 77 | } |
78 | ||
20dbe1a1 GS |
79 | static int dsi_calc_mnp(struct drm_i915_private *dev_priv, |
80 | struct dsi_mnp *dsi_mnp, int target_dsi_clk) | |
be4fc046 | 81 | { |
7471bf4e | 82 | unsigned int calc_m = 0, calc_p = 0; |
20dbe1a1 GS |
83 | unsigned int m_min, m_max, p_min = 2, p_max = 6; |
84 | unsigned int m, n, p; | |
85 | int ref_clk; | |
7471bf4e | 86 | int delta = target_dsi_clk; |
be4fc046 | 87 | u32 m_seed; |
88 | ||
7471bf4e JN |
89 | /* target_dsi_clk is expected in kHz */ |
90 | if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) { | |
be4fc046 | 91 | DRM_ERROR("DSI CLK Out of Range\n"); |
92 | return -ECHRNG; | |
93 | } | |
94 | ||
20dbe1a1 GS |
95 | if (IS_CHERRYVIEW(dev_priv)) { |
96 | ref_clk = 100000; | |
97 | n = 4; | |
98 | m_min = 70; | |
99 | m_max = 96; | |
100 | } else { | |
101 | ref_clk = 25000; | |
102 | n = 1; | |
103 | m_min = 62; | |
104 | m_max = 92; | |
105 | } | |
106 | ||
107 | for (m = m_min; m <= m_max && delta; m++) { | |
108 | for (p = p_min; p <= p_max && delta; p++) { | |
7471bf4e JN |
109 | /* |
110 | * Find the optimal m and p divisors with minimal delta | |
111 | * +/- the required clock | |
112 | */ | |
a856c5bd | 113 | int calc_dsi_clk = (m * ref_clk) / (p * n); |
7471bf4e JN |
114 | int d = abs(target_dsi_clk - calc_dsi_clk); |
115 | if (d < delta) { | |
116 | delta = d; | |
8e1eed5a SK |
117 | calc_m = m; |
118 | calc_p = p; | |
be4fc046 | 119 | } |
120 | } | |
121 | } | |
122 | ||
a856c5bd JN |
123 | /* register has log2(N1), this works fine for powers of two */ |
124 | n = ffs(n) - 1; | |
be4fc046 | 125 | m_seed = lfsr_converts[calc_m - 62]; |
be4fc046 | 126 | dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2); |
a856c5bd | 127 | dsi_mnp->dsi_pll_div = n << DSI_PLL_N1_DIV_SHIFT | |
be4fc046 | 128 | m_seed << DSI_PLL_M1_DIV_SHIFT; |
129 | ||
130 | return 0; | |
131 | } | |
132 | ||
be4fc046 | 133 | /* |
134 | * XXX: The muxing and gating is hard coded for now. Need to add support for | |
135 | * sharing PLLs with two DSI outputs. | |
136 | */ | |
137 | static void vlv_configure_dsi_pll(struct intel_encoder *encoder) | |
138 | { | |
139 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
be4fc046 | 140 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
141 | int ret; | |
142 | struct dsi_mnp dsi_mnp; | |
143 | u32 dsi_clk; | |
144 | ||
7f0c8605 | 145 | dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, |
7f3de833 | 146 | intel_dsi->lane_count); |
be4fc046 | 147 | |
20dbe1a1 | 148 | ret = dsi_calc_mnp(dev_priv, &dsi_mnp, dsi_clk); |
be4fc046 | 149 | if (ret) { |
150 | DRM_DEBUG_KMS("dsi_calc_mnp failed\n"); | |
151 | return; | |
152 | } | |
153 | ||
3c860ab4 GS |
154 | if (intel_dsi->ports & (1 << PORT_A)) |
155 | dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL; | |
be4fc046 | 156 | |
3c860ab4 | 157 | if (intel_dsi->ports & (1 << PORT_C)) |
58cf8887 GS |
158 | dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL; |
159 | ||
be4fc046 | 160 | DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n", |
161 | dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl); | |
162 | ||
163 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0); | |
164 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, dsi_mnp.dsi_pll_div); | |
165 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, dsi_mnp.dsi_pll_ctrl); | |
166 | } | |
167 | ||
cfe01a5e | 168 | static void vlv_enable_dsi_pll(struct intel_encoder *encoder) |
be4fc046 | 169 | { |
170 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
171 | u32 tmp; | |
172 | ||
173 | DRM_DEBUG_KMS("\n"); | |
174 | ||
a580516d | 175 | mutex_lock(&dev_priv->sb_lock); |
be4fc046 | 176 | |
177 | vlv_configure_dsi_pll(encoder); | |
178 | ||
179 | /* wait at least 0.5 us after ungating before enabling VCO */ | |
180 | usleep_range(1, 10); | |
181 | ||
182 | tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
183 | tmp |= DSI_PLL_VCO_EN; | |
184 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); | |
185 | ||
3770f0ee GS |
186 | if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) & |
187 | DSI_PLL_LOCK, 20)) { | |
be4fc046 | 188 | |
a580516d | 189 | mutex_unlock(&dev_priv->sb_lock); |
be4fc046 | 190 | DRM_ERROR("DSI PLL lock failed\n"); |
191 | return; | |
192 | } | |
a580516d | 193 | mutex_unlock(&dev_priv->sb_lock); |
be4fc046 | 194 | |
195 | DRM_DEBUG_KMS("DSI PLL locked\n"); | |
196 | } | |
197 | ||
fe88fc68 | 198 | static void vlv_disable_dsi_pll(struct intel_encoder *encoder) |
be4fc046 | 199 | { |
200 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
201 | u32 tmp; | |
202 | ||
203 | DRM_DEBUG_KMS("\n"); | |
204 | ||
a580516d | 205 | mutex_lock(&dev_priv->sb_lock); |
be4fc046 | 206 | |
207 | tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
208 | tmp &= ~DSI_PLL_VCO_EN; | |
209 | tmp |= DSI_PLL_LDO_GATE; | |
210 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); | |
211 | ||
a580516d | 212 | mutex_unlock(&dev_priv->sb_lock); |
be4fc046 | 213 | } |
f573de5a | 214 | |
fe88fc68 SS |
215 | static void bxt_disable_dsi_pll(struct intel_encoder *encoder) |
216 | { | |
217 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
218 | u32 val; | |
219 | ||
220 | DRM_DEBUG_KMS("\n"); | |
221 | ||
222 | val = I915_READ(BXT_DSI_PLL_ENABLE); | |
223 | val &= ~BXT_DSI_PLL_DO_ENABLE; | |
224 | I915_WRITE(BXT_DSI_PLL_ENABLE, val); | |
225 | ||
226 | /* | |
227 | * PLL lock should deassert within 200us. | |
228 | * Wait up to 1ms before timing out. | |
229 | */ | |
230 | if (wait_for((I915_READ(BXT_DSI_PLL_ENABLE) | |
231 | & BXT_DSI_PLL_LOCKED) == 0, 1)) | |
232 | DRM_ERROR("Timeout waiting for PLL lock deassertion\n"); | |
233 | } | |
234 | ||
f573de5a SK |
235 | static void assert_bpp_mismatch(int pixel_format, int pipe_bpp) |
236 | { | |
260c1ad1 | 237 | int bpp = dsi_pixel_format_bpp(pixel_format); |
f573de5a SK |
238 | |
239 | WARN(bpp != pipe_bpp, | |
7f3de833 DV |
240 | "bpp match assertion failure (expected %d, current %d)\n", |
241 | bpp, pipe_bpp); | |
f573de5a SK |
242 | } |
243 | ||
d7d85d85 | 244 | static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp) |
f573de5a SK |
245 | { |
246 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
247 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
248 | u32 dsi_clock, pclk; | |
249 | u32 pll_ctl, pll_div; | |
a856c5bd | 250 | u32 m = 0, p = 0, n; |
f573de5a SK |
251 | int refclk = 25000; |
252 | int i; | |
253 | ||
254 | DRM_DEBUG_KMS("\n"); | |
255 | ||
a580516d | 256 | mutex_lock(&dev_priv->sb_lock); |
f573de5a SK |
257 | pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
258 | pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER); | |
a580516d | 259 | mutex_unlock(&dev_priv->sb_lock); |
f573de5a SK |
260 | |
261 | /* mask out other bits and extract the P1 divisor */ | |
262 | pll_ctl &= DSI_PLL_P1_POST_DIV_MASK; | |
263 | pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2); | |
264 | ||
a856c5bd JN |
265 | /* N1 divisor */ |
266 | n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT; | |
267 | n = 1 << n; /* register has log2(N1) */ | |
268 | ||
f573de5a SK |
269 | /* mask out the other bits and extract the M1 divisor */ |
270 | pll_div &= DSI_PLL_M1_DIV_MASK; | |
271 | pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT; | |
272 | ||
273 | while (pll_ctl) { | |
274 | pll_ctl = pll_ctl >> 1; | |
275 | p++; | |
276 | } | |
277 | p--; | |
278 | ||
279 | if (!p) { | |
280 | DRM_ERROR("wrong P1 divisor\n"); | |
281 | return 0; | |
282 | } | |
283 | ||
284 | for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) { | |
285 | if (lfsr_converts[i] == pll_div) | |
286 | break; | |
287 | } | |
288 | ||
289 | if (i == ARRAY_SIZE(lfsr_converts)) { | |
290 | DRM_ERROR("wrong m_seed programmed\n"); | |
291 | return 0; | |
292 | } | |
293 | ||
294 | m = i + 62; | |
295 | ||
a856c5bd | 296 | dsi_clock = (m * refclk) / (p * n); |
f573de5a SK |
297 | |
298 | /* pixel_format and pipe_bpp should agree */ | |
299 | assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp); | |
300 | ||
301 | pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp); | |
302 | ||
303 | return pclk; | |
304 | } | |
cfe01a5e | 305 | |
d7d85d85 | 306 | static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp) |
ce0c9821 SS |
307 | { |
308 | u32 pclk; | |
309 | u32 dsi_clk; | |
310 | u32 dsi_ratio; | |
311 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
312 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
313 | ||
314 | /* Divide by zero */ | |
315 | if (!pipe_bpp) { | |
316 | DRM_ERROR("Invalid BPP(0)\n"); | |
317 | return 0; | |
318 | } | |
319 | ||
320 | dsi_ratio = I915_READ(BXT_DSI_PLL_CTL) & | |
321 | BXT_DSI_PLL_RATIO_MASK; | |
322 | ||
323 | /* Invalid DSI ratio ? */ | |
324 | if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN || | |
325 | dsi_ratio > BXT_DSI_PLL_RATIO_MAX) { | |
326 | DRM_ERROR("Invalid DSI pll ratio(%u) programmed\n", dsi_ratio); | |
327 | return 0; | |
328 | } | |
329 | ||
330 | dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2; | |
331 | ||
332 | /* pixel_format and pipe_bpp should agree */ | |
333 | assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp); | |
334 | ||
335 | pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp); | |
336 | ||
337 | DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk); | |
338 | return pclk; | |
339 | } | |
340 | ||
d7d85d85 JN |
341 | u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp) |
342 | { | |
343 | if (IS_BROXTON(encoder->base.dev)) | |
344 | return bxt_dsi_get_pclk(encoder, pipe_bpp); | |
345 | else | |
346 | return vlv_dsi_get_pclk(encoder, pipe_bpp); | |
347 | } | |
348 | ||
b248e654 | 349 | static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) |
b389a45c SS |
350 | { |
351 | u32 temp; | |
352 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
353 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
354 | ||
355 | temp = I915_READ(MIPI_CTRL(port)); | |
356 | temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; | |
357 | I915_WRITE(MIPI_CTRL(port), temp | | |
358 | intel_dsi->escape_clk_div << | |
359 | ESCAPE_CLOCK_DIVIDER_SHIFT); | |
360 | } | |
361 | ||
11b8e4f5 SS |
362 | /* Program BXT Mipi clocks and dividers */ |
363 | static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port) | |
364 | { | |
11b8e4f5 | 365 | struct drm_i915_private *dev_priv = dev->dev_private; |
782d25ca D |
366 | u32 tmp; |
367 | u32 dsi_rate = 0; | |
368 | u32 pll_ratio = 0; | |
369 | u32 rx_div; | |
370 | u32 tx_div; | |
371 | u32 rx_div_upper; | |
372 | u32 rx_div_lower; | |
373 | u32 mipi_8by3_divider; | |
11b8e4f5 SS |
374 | |
375 | /* Clear old configurations */ | |
376 | tmp = I915_READ(BXT_MIPI_CLOCK_CTL); | |
377 | tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); | |
782d25ca D |
378 | tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port)); |
379 | tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port)); | |
380 | tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port)); | |
11b8e4f5 SS |
381 | |
382 | /* Get the current DSI rate(actual) */ | |
383 | pll_ratio = I915_READ(BXT_DSI_PLL_CTL) & | |
384 | BXT_DSI_PLL_RATIO_MASK; | |
385 | dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2; | |
386 | ||
782d25ca D |
387 | /* |
388 | * tx clock should be <= 20MHz and the div value must be | |
389 | * subtracted by 1 as per bspec | |
390 | */ | |
391 | tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1; | |
392 | /* | |
393 | * rx clock should be <= 150MHz and the div value must be | |
394 | * subtracted by 1 as per bspec | |
395 | */ | |
396 | rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1; | |
11b8e4f5 SS |
397 | |
398 | /* | |
782d25ca D |
399 | * rx divider value needs to be updated in the |
400 | * two differnt bit fields in the register hence splitting the | |
401 | * rx divider value accordingly | |
11b8e4f5 | 402 | */ |
782d25ca D |
403 | rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2; |
404 | rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2; | |
405 | ||
406 | /* As per bpsec program the 8/3X clock divider to the below value */ | |
407 | if (dev_priv->vbt.dsi.config->is_cmd_mode) | |
408 | mipi_8by3_divider = 0x2; | |
409 | else | |
410 | mipi_8by3_divider = 0x3; | |
11b8e4f5 | 411 | |
782d25ca D |
412 | tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider); |
413 | tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div); | |
414 | tmp |= BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, rx_div_lower); | |
415 | tmp |= BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, rx_div_upper); | |
11b8e4f5 SS |
416 | |
417 | I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); | |
418 | } | |
419 | ||
cfe01a5e SS |
420 | static bool bxt_configure_dsi_pll(struct intel_encoder *encoder) |
421 | { | |
422 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
423 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
424 | u8 dsi_ratio; | |
425 | u32 dsi_clk; | |
426 | u32 val; | |
427 | ||
428 | dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, | |
429 | intel_dsi->lane_count); | |
430 | ||
431 | /* | |
432 | * From clock diagram, to get PLL ratio divider, divide double of DSI | |
433 | * link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to | |
434 | * round 'up' the result | |
435 | */ | |
436 | dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ); | |
437 | if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN || | |
438 | dsi_ratio > BXT_DSI_PLL_RATIO_MAX) { | |
439 | DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n"); | |
440 | return false; | |
441 | } | |
442 | ||
443 | /* | |
444 | * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x | |
445 | * Spec says both have to be programmed, even if one is not getting | |
446 | * used. Configure MIPI_CLOCK_CTL dividers in modeset | |
447 | */ | |
448 | val = I915_READ(BXT_DSI_PLL_CTL); | |
449 | val &= ~BXT_DSI_PLL_PVD_RATIO_MASK; | |
450 | val &= ~BXT_DSI_FREQ_SEL_MASK; | |
451 | val &= ~BXT_DSI_PLL_RATIO_MASK; | |
452 | val |= (dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2); | |
453 | ||
454 | /* As per recommendation from hardware team, | |
455 | * Prog PVD ratio =1 if dsi ratio <= 50 | |
456 | */ | |
457 | if (dsi_ratio <= 50) { | |
458 | val &= ~BXT_DSI_PLL_PVD_RATIO_MASK; | |
459 | val |= BXT_DSI_PLL_PVD_RATIO_1; | |
460 | } | |
461 | ||
462 | I915_WRITE(BXT_DSI_PLL_CTL, val); | |
463 | POSTING_READ(BXT_DSI_PLL_CTL); | |
464 | ||
465 | return true; | |
466 | } | |
467 | ||
468 | static void bxt_enable_dsi_pll(struct intel_encoder *encoder) | |
469 | { | |
470 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
11b8e4f5 SS |
471 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
472 | enum port port; | |
cfe01a5e SS |
473 | u32 val; |
474 | ||
475 | DRM_DEBUG_KMS("\n"); | |
476 | ||
477 | val = I915_READ(BXT_DSI_PLL_ENABLE); | |
478 | ||
479 | if (val & BXT_DSI_PLL_DO_ENABLE) { | |
480 | WARN(1, "DSI PLL already enabled. Disabling it.\n"); | |
481 | val &= ~BXT_DSI_PLL_DO_ENABLE; | |
482 | I915_WRITE(BXT_DSI_PLL_ENABLE, val); | |
483 | } | |
484 | ||
485 | /* Configure PLL vales */ | |
486 | if (!bxt_configure_dsi_pll(encoder)) { | |
487 | DRM_ERROR("Configure DSI PLL failed, abort PLL enable\n"); | |
488 | return; | |
489 | } | |
490 | ||
11b8e4f5 SS |
491 | /* Program TX, RX, Dphy clocks */ |
492 | for_each_dsi_port(port, intel_dsi->ports) | |
493 | bxt_dsi_program_clocks(encoder->base.dev, port); | |
494 | ||
cfe01a5e SS |
495 | /* Enable DSI PLL */ |
496 | val = I915_READ(BXT_DSI_PLL_ENABLE); | |
497 | val |= BXT_DSI_PLL_DO_ENABLE; | |
498 | I915_WRITE(BXT_DSI_PLL_ENABLE, val); | |
499 | ||
500 | /* Timeout and fail if PLL not locked */ | |
501 | if (wait_for(I915_READ(BXT_DSI_PLL_ENABLE) & BXT_DSI_PLL_LOCKED, 1)) { | |
502 | DRM_ERROR("Timed out waiting for DSI PLL to lock\n"); | |
503 | return; | |
504 | } | |
505 | ||
506 | DRM_DEBUG_KMS("DSI PLL locked\n"); | |
507 | } | |
508 | ||
509 | void intel_enable_dsi_pll(struct intel_encoder *encoder) | |
510 | { | |
511 | struct drm_device *dev = encoder->base.dev; | |
512 | ||
666a4537 | 513 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
cfe01a5e SS |
514 | vlv_enable_dsi_pll(encoder); |
515 | else if (IS_BROXTON(dev)) | |
516 | bxt_enable_dsi_pll(encoder); | |
517 | } | |
fe88fc68 SS |
518 | |
519 | void intel_disable_dsi_pll(struct intel_encoder *encoder) | |
520 | { | |
521 | struct drm_device *dev = encoder->base.dev; | |
522 | ||
666a4537 | 523 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
fe88fc68 SS |
524 | vlv_disable_dsi_pll(encoder); |
525 | else if (IS_BROXTON(dev)) | |
526 | bxt_disable_dsi_pll(encoder); | |
527 | } | |
b389a45c | 528 | |
b248e654 | 529 | static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) |
b389a45c SS |
530 | { |
531 | u32 tmp; | |
532 | struct drm_device *dev = encoder->base.dev; | |
533 | struct drm_i915_private *dev_priv = dev->dev_private; | |
534 | ||
535 | /* Clear old configurations */ | |
536 | tmp = I915_READ(BXT_MIPI_CLOCK_CTL); | |
537 | tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); | |
782d25ca D |
538 | tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port)); |
539 | tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port)); | |
540 | tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port)); | |
b389a45c SS |
541 | I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); |
542 | I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); | |
543 | } | |
544 | ||
545 | void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) | |
546 | { | |
547 | struct drm_device *dev = encoder->base.dev; | |
548 | ||
549 | if (IS_BROXTON(dev)) | |
550 | bxt_dsi_reset_clocks(encoder, port); | |
666a4537 | 551 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
b389a45c SS |
552 | vlv_dsi_reset_clocks(encoder, port); |
553 | } |