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be4fc046 | 1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Shobhit Kumar <shobhit.kumar@intel.com> | |
25 | * Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com> | |
26 | */ | |
27 | ||
28 | #include <linux/kernel.h> | |
29 | #include "intel_drv.h" | |
30 | #include "i915_drv.h" | |
31 | #include "intel_dsi.h" | |
32 | ||
33 | #define DSI_HSS_PACKET_SIZE 4 | |
34 | #define DSI_HSE_PACKET_SIZE 4 | |
35 | #define DSI_HSA_PACKET_EXTRA_SIZE 6 | |
36 | #define DSI_HBP_PACKET_EXTRA_SIZE 6 | |
37 | #define DSI_HACTIVE_PACKET_EXTRA_SIZE 6 | |
38 | #define DSI_HFP_PACKET_EXTRA_SIZE 6 | |
39 | #define DSI_EOTP_PACKET_SIZE 4 | |
40 | ||
260c1ad1 JN |
41 | static int dsi_pixel_format_bpp(int pixel_format) |
42 | { | |
43 | int bpp; | |
44 | ||
45 | switch (pixel_format) { | |
46 | default: | |
47 | case VID_MODE_FORMAT_RGB888: | |
48 | case VID_MODE_FORMAT_RGB666_LOOSE: | |
49 | bpp = 24; | |
50 | break; | |
51 | case VID_MODE_FORMAT_RGB666: | |
52 | bpp = 18; | |
53 | break; | |
54 | case VID_MODE_FORMAT_RGB565: | |
55 | bpp = 16; | |
56 | break; | |
57 | } | |
58 | ||
59 | return bpp; | |
60 | } | |
61 | ||
be4fc046 | 62 | struct dsi_mnp { |
63 | u32 dsi_pll_ctrl; | |
64 | u32 dsi_pll_div; | |
65 | }; | |
66 | ||
67 | static const u32 lfsr_converts[] = { | |
68 | 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */ | |
69 | 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */ | |
3c5c6d88 GS |
70 | 106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */ |
71 | 71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */ | |
be4fc046 | 72 | }; |
73 | ||
44d4c6ee SK |
74 | #ifdef DSI_CLK_FROM_RR |
75 | ||
a7482145 | 76 | static u32 dsi_rr_formula(const struct drm_display_mode *mode, |
be4fc046 | 77 | int pixel_format, int video_mode_format, |
78 | int lane_count, bool eotp) | |
79 | { | |
80 | u32 bpp; | |
81 | u32 hactive, vactive, hfp, hsync, hbp, vfp, vsync, vbp; | |
82 | u32 hsync_bytes, hbp_bytes, hactive_bytes, hfp_bytes; | |
83 | u32 bytes_per_line, bytes_per_frame; | |
84 | u32 num_frames; | |
85 | u32 bytes_per_x_frames, bytes_per_x_frames_x_lanes; | |
86 | u32 dsi_bit_clock_hz; | |
87 | u32 dsi_clk; | |
88 | ||
260c1ad1 | 89 | bpp = dsi_pixel_format_bpp(pixel_format); |
be4fc046 | 90 | |
91 | hactive = mode->hdisplay; | |
92 | vactive = mode->vdisplay; | |
93 | hfp = mode->hsync_start - mode->hdisplay; | |
94 | hsync = mode->hsync_end - mode->hsync_start; | |
95 | hbp = mode->htotal - mode->hsync_end; | |
96 | ||
97 | vfp = mode->vsync_start - mode->vdisplay; | |
98 | vsync = mode->vsync_end - mode->vsync_start; | |
99 | vbp = mode->vtotal - mode->vsync_end; | |
100 | ||
101 | hsync_bytes = DIV_ROUND_UP(hsync * bpp, 8); | |
102 | hbp_bytes = DIV_ROUND_UP(hbp * bpp, 8); | |
103 | hactive_bytes = DIV_ROUND_UP(hactive * bpp, 8); | |
104 | hfp_bytes = DIV_ROUND_UP(hfp * bpp, 8); | |
105 | ||
106 | bytes_per_line = DSI_HSS_PACKET_SIZE + hsync_bytes + | |
107 | DSI_HSA_PACKET_EXTRA_SIZE + DSI_HSE_PACKET_SIZE + | |
108 | hbp_bytes + DSI_HBP_PACKET_EXTRA_SIZE + | |
109 | hactive_bytes + DSI_HACTIVE_PACKET_EXTRA_SIZE + | |
110 | hfp_bytes + DSI_HFP_PACKET_EXTRA_SIZE; | |
111 | ||
112 | /* | |
113 | * XXX: Need to accurately calculate LP to HS transition timeout and add | |
114 | * it to bytes_per_line/bytes_per_frame. | |
115 | */ | |
116 | ||
117 | if (eotp && video_mode_format == VIDEO_MODE_BURST) | |
118 | bytes_per_line += DSI_EOTP_PACKET_SIZE; | |
119 | ||
120 | bytes_per_frame = vsync * bytes_per_line + vbp * bytes_per_line + | |
121 | vactive * bytes_per_line + vfp * bytes_per_line; | |
122 | ||
123 | if (eotp && | |
124 | (video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE || | |
125 | video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS)) | |
126 | bytes_per_frame += DSI_EOTP_PACKET_SIZE; | |
127 | ||
128 | num_frames = drm_mode_vrefresh(mode); | |
129 | bytes_per_x_frames = num_frames * bytes_per_frame; | |
130 | ||
131 | bytes_per_x_frames_x_lanes = bytes_per_x_frames / lane_count; | |
132 | ||
133 | /* the dsi clock is divided by 2 in the hardware to get dsi ddr clock */ | |
134 | dsi_bit_clock_hz = bytes_per_x_frames_x_lanes * 8; | |
44d4c6ee | 135 | dsi_clk = dsi_bit_clock_hz / 1000; |
be4fc046 | 136 | |
137 | if (eotp && video_mode_format == VIDEO_MODE_BURST) | |
138 | dsi_clk *= 2; | |
139 | ||
140 | return dsi_clk; | |
141 | } | |
142 | ||
44d4c6ee | 143 | #else |
be4fc046 | 144 | |
44d4c6ee | 145 | /* Get DSI clock from pixel clock */ |
7f0c8605 | 146 | static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count) |
be4fc046 | 147 | { |
44d4c6ee | 148 | u32 dsi_clk_khz; |
260c1ad1 | 149 | u32 bpp = dsi_pixel_format_bpp(pixel_format); |
be4fc046 | 150 | |
44d4c6ee SK |
151 | /* DSI data rate = pixel clock * bits per pixel / lane count |
152 | pixel clock is converted from KHz to Hz */ | |
7f0c8605 | 153 | dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); |
be4fc046 | 154 | |
44d4c6ee | 155 | return dsi_clk_khz; |
be4fc046 | 156 | } |
157 | ||
44d4c6ee | 158 | #endif |
be4fc046 | 159 | |
20dbe1a1 GS |
160 | static int dsi_calc_mnp(struct drm_i915_private *dev_priv, |
161 | struct dsi_mnp *dsi_mnp, int target_dsi_clk) | |
be4fc046 | 162 | { |
7471bf4e | 163 | unsigned int calc_m = 0, calc_p = 0; |
20dbe1a1 GS |
164 | unsigned int m_min, m_max, p_min = 2, p_max = 6; |
165 | unsigned int m, n, p; | |
166 | int ref_clk; | |
7471bf4e | 167 | int delta = target_dsi_clk; |
be4fc046 | 168 | u32 m_seed; |
169 | ||
7471bf4e JN |
170 | /* target_dsi_clk is expected in kHz */ |
171 | if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) { | |
be4fc046 | 172 | DRM_ERROR("DSI CLK Out of Range\n"); |
173 | return -ECHRNG; | |
174 | } | |
175 | ||
20dbe1a1 GS |
176 | if (IS_CHERRYVIEW(dev_priv)) { |
177 | ref_clk = 100000; | |
178 | n = 4; | |
179 | m_min = 70; | |
180 | m_max = 96; | |
181 | } else { | |
182 | ref_clk = 25000; | |
183 | n = 1; | |
184 | m_min = 62; | |
185 | m_max = 92; | |
186 | } | |
187 | ||
188 | for (m = m_min; m <= m_max && delta; m++) { | |
189 | for (p = p_min; p <= p_max && delta; p++) { | |
7471bf4e JN |
190 | /* |
191 | * Find the optimal m and p divisors with minimal delta | |
192 | * +/- the required clock | |
193 | */ | |
a856c5bd | 194 | int calc_dsi_clk = (m * ref_clk) / (p * n); |
7471bf4e JN |
195 | int d = abs(target_dsi_clk - calc_dsi_clk); |
196 | if (d < delta) { | |
197 | delta = d; | |
8e1eed5a SK |
198 | calc_m = m; |
199 | calc_p = p; | |
be4fc046 | 200 | } |
201 | } | |
202 | } | |
203 | ||
a856c5bd JN |
204 | /* register has log2(N1), this works fine for powers of two */ |
205 | n = ffs(n) - 1; | |
be4fc046 | 206 | m_seed = lfsr_converts[calc_m - 62]; |
be4fc046 | 207 | dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2); |
a856c5bd | 208 | dsi_mnp->dsi_pll_div = n << DSI_PLL_N1_DIV_SHIFT | |
be4fc046 | 209 | m_seed << DSI_PLL_M1_DIV_SHIFT; |
210 | ||
211 | return 0; | |
212 | } | |
213 | ||
be4fc046 | 214 | /* |
215 | * XXX: The muxing and gating is hard coded for now. Need to add support for | |
216 | * sharing PLLs with two DSI outputs. | |
217 | */ | |
218 | static void vlv_configure_dsi_pll(struct intel_encoder *encoder) | |
219 | { | |
220 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
be4fc046 | 221 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
222 | int ret; | |
223 | struct dsi_mnp dsi_mnp; | |
224 | u32 dsi_clk; | |
225 | ||
7f0c8605 | 226 | dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, |
7f3de833 | 227 | intel_dsi->lane_count); |
be4fc046 | 228 | |
20dbe1a1 | 229 | ret = dsi_calc_mnp(dev_priv, &dsi_mnp, dsi_clk); |
be4fc046 | 230 | if (ret) { |
231 | DRM_DEBUG_KMS("dsi_calc_mnp failed\n"); | |
232 | return; | |
233 | } | |
234 | ||
3c860ab4 GS |
235 | if (intel_dsi->ports & (1 << PORT_A)) |
236 | dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL; | |
be4fc046 | 237 | |
3c860ab4 | 238 | if (intel_dsi->ports & (1 << PORT_C)) |
58cf8887 GS |
239 | dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL; |
240 | ||
be4fc046 | 241 | DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n", |
242 | dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl); | |
243 | ||
244 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0); | |
245 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, dsi_mnp.dsi_pll_div); | |
246 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, dsi_mnp.dsi_pll_ctrl); | |
247 | } | |
248 | ||
cfe01a5e | 249 | static void vlv_enable_dsi_pll(struct intel_encoder *encoder) |
be4fc046 | 250 | { |
251 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
252 | u32 tmp; | |
253 | ||
254 | DRM_DEBUG_KMS("\n"); | |
255 | ||
a580516d | 256 | mutex_lock(&dev_priv->sb_lock); |
be4fc046 | 257 | |
258 | vlv_configure_dsi_pll(encoder); | |
259 | ||
260 | /* wait at least 0.5 us after ungating before enabling VCO */ | |
261 | usleep_range(1, 10); | |
262 | ||
263 | tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
264 | tmp |= DSI_PLL_VCO_EN; | |
265 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); | |
266 | ||
3770f0ee GS |
267 | if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) & |
268 | DSI_PLL_LOCK, 20)) { | |
be4fc046 | 269 | |
a580516d | 270 | mutex_unlock(&dev_priv->sb_lock); |
be4fc046 | 271 | DRM_ERROR("DSI PLL lock failed\n"); |
272 | return; | |
273 | } | |
a580516d | 274 | mutex_unlock(&dev_priv->sb_lock); |
be4fc046 | 275 | |
276 | DRM_DEBUG_KMS("DSI PLL locked\n"); | |
277 | } | |
278 | ||
279 | void vlv_disable_dsi_pll(struct intel_encoder *encoder) | |
280 | { | |
281 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
282 | u32 tmp; | |
283 | ||
284 | DRM_DEBUG_KMS("\n"); | |
285 | ||
a580516d | 286 | mutex_lock(&dev_priv->sb_lock); |
be4fc046 | 287 | |
288 | tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
289 | tmp &= ~DSI_PLL_VCO_EN; | |
290 | tmp |= DSI_PLL_LDO_GATE; | |
291 | vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); | |
292 | ||
a580516d | 293 | mutex_unlock(&dev_priv->sb_lock); |
be4fc046 | 294 | } |
f573de5a SK |
295 | |
296 | static void assert_bpp_mismatch(int pixel_format, int pipe_bpp) | |
297 | { | |
260c1ad1 | 298 | int bpp = dsi_pixel_format_bpp(pixel_format); |
f573de5a SK |
299 | |
300 | WARN(bpp != pipe_bpp, | |
7f3de833 DV |
301 | "bpp match assertion failure (expected %d, current %d)\n", |
302 | bpp, pipe_bpp); | |
f573de5a SK |
303 | } |
304 | ||
305 | u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp) | |
306 | { | |
307 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
308 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
309 | u32 dsi_clock, pclk; | |
310 | u32 pll_ctl, pll_div; | |
a856c5bd | 311 | u32 m = 0, p = 0, n; |
f573de5a SK |
312 | int refclk = 25000; |
313 | int i; | |
314 | ||
315 | DRM_DEBUG_KMS("\n"); | |
316 | ||
a580516d | 317 | mutex_lock(&dev_priv->sb_lock); |
f573de5a SK |
318 | pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
319 | pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER); | |
a580516d | 320 | mutex_unlock(&dev_priv->sb_lock); |
f573de5a SK |
321 | |
322 | /* mask out other bits and extract the P1 divisor */ | |
323 | pll_ctl &= DSI_PLL_P1_POST_DIV_MASK; | |
324 | pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2); | |
325 | ||
a856c5bd JN |
326 | /* N1 divisor */ |
327 | n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT; | |
328 | n = 1 << n; /* register has log2(N1) */ | |
329 | ||
f573de5a SK |
330 | /* mask out the other bits and extract the M1 divisor */ |
331 | pll_div &= DSI_PLL_M1_DIV_MASK; | |
332 | pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT; | |
333 | ||
334 | while (pll_ctl) { | |
335 | pll_ctl = pll_ctl >> 1; | |
336 | p++; | |
337 | } | |
338 | p--; | |
339 | ||
340 | if (!p) { | |
341 | DRM_ERROR("wrong P1 divisor\n"); | |
342 | return 0; | |
343 | } | |
344 | ||
345 | for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) { | |
346 | if (lfsr_converts[i] == pll_div) | |
347 | break; | |
348 | } | |
349 | ||
350 | if (i == ARRAY_SIZE(lfsr_converts)) { | |
351 | DRM_ERROR("wrong m_seed programmed\n"); | |
352 | return 0; | |
353 | } | |
354 | ||
355 | m = i + 62; | |
356 | ||
a856c5bd | 357 | dsi_clock = (m * refclk) / (p * n); |
f573de5a SK |
358 | |
359 | /* pixel_format and pipe_bpp should agree */ | |
360 | assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp); | |
361 | ||
362 | pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp); | |
363 | ||
364 | return pclk; | |
365 | } | |
cfe01a5e SS |
366 | |
367 | static bool bxt_configure_dsi_pll(struct intel_encoder *encoder) | |
368 | { | |
369 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
370 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
371 | u8 dsi_ratio; | |
372 | u32 dsi_clk; | |
373 | u32 val; | |
374 | ||
375 | dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, | |
376 | intel_dsi->lane_count); | |
377 | ||
378 | /* | |
379 | * From clock diagram, to get PLL ratio divider, divide double of DSI | |
380 | * link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to | |
381 | * round 'up' the result | |
382 | */ | |
383 | dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ); | |
384 | if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN || | |
385 | dsi_ratio > BXT_DSI_PLL_RATIO_MAX) { | |
386 | DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n"); | |
387 | return false; | |
388 | } | |
389 | ||
390 | /* | |
391 | * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x | |
392 | * Spec says both have to be programmed, even if one is not getting | |
393 | * used. Configure MIPI_CLOCK_CTL dividers in modeset | |
394 | */ | |
395 | val = I915_READ(BXT_DSI_PLL_CTL); | |
396 | val &= ~BXT_DSI_PLL_PVD_RATIO_MASK; | |
397 | val &= ~BXT_DSI_FREQ_SEL_MASK; | |
398 | val &= ~BXT_DSI_PLL_RATIO_MASK; | |
399 | val |= (dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2); | |
400 | ||
401 | /* As per recommendation from hardware team, | |
402 | * Prog PVD ratio =1 if dsi ratio <= 50 | |
403 | */ | |
404 | if (dsi_ratio <= 50) { | |
405 | val &= ~BXT_DSI_PLL_PVD_RATIO_MASK; | |
406 | val |= BXT_DSI_PLL_PVD_RATIO_1; | |
407 | } | |
408 | ||
409 | I915_WRITE(BXT_DSI_PLL_CTL, val); | |
410 | POSTING_READ(BXT_DSI_PLL_CTL); | |
411 | ||
412 | return true; | |
413 | } | |
414 | ||
415 | static void bxt_enable_dsi_pll(struct intel_encoder *encoder) | |
416 | { | |
417 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
418 | u32 val; | |
419 | ||
420 | DRM_DEBUG_KMS("\n"); | |
421 | ||
422 | val = I915_READ(BXT_DSI_PLL_ENABLE); | |
423 | ||
424 | if (val & BXT_DSI_PLL_DO_ENABLE) { | |
425 | WARN(1, "DSI PLL already enabled. Disabling it.\n"); | |
426 | val &= ~BXT_DSI_PLL_DO_ENABLE; | |
427 | I915_WRITE(BXT_DSI_PLL_ENABLE, val); | |
428 | } | |
429 | ||
430 | /* Configure PLL vales */ | |
431 | if (!bxt_configure_dsi_pll(encoder)) { | |
432 | DRM_ERROR("Configure DSI PLL failed, abort PLL enable\n"); | |
433 | return; | |
434 | } | |
435 | ||
436 | /* Enable DSI PLL */ | |
437 | val = I915_READ(BXT_DSI_PLL_ENABLE); | |
438 | val |= BXT_DSI_PLL_DO_ENABLE; | |
439 | I915_WRITE(BXT_DSI_PLL_ENABLE, val); | |
440 | ||
441 | /* Timeout and fail if PLL not locked */ | |
442 | if (wait_for(I915_READ(BXT_DSI_PLL_ENABLE) & BXT_DSI_PLL_LOCKED, 1)) { | |
443 | DRM_ERROR("Timed out waiting for DSI PLL to lock\n"); | |
444 | return; | |
445 | } | |
446 | ||
447 | DRM_DEBUG_KMS("DSI PLL locked\n"); | |
448 | } | |
449 | ||
450 | void intel_enable_dsi_pll(struct intel_encoder *encoder) | |
451 | { | |
452 | struct drm_device *dev = encoder->base.dev; | |
453 | ||
454 | if (IS_VALLEYVIEW(dev)) | |
455 | vlv_enable_dsi_pll(encoder); | |
456 | else if (IS_BROXTON(dev)) | |
457 | bxt_enable_dsi_pll(encoder); | |
458 | } |