[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dvo.c

/*
 * Copyright 2006 Dave Airlie <airlied@linux.ie>
 * Copyright © 2006-2007 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 */
#include <linux/i2c.h>
#include <linux/slab.h>
#include <drm/drmP.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
#include "intel_drv.h"
#include <drm/i915_drm.h>
#include "i915_drv.h"
#include "dvo.h"

#define SIL164_ADDR	0x38
#define CH7xxx_ADDR	0x76
#define TFP410_ADDR	0x38
#define NS2501_ADDR     0x38

static const struct intel_dvo_device intel_dvo_devices[] = {
	{
		.type = INTEL_DVO_CHIP_TMDS,
		.name = "sil164",
		.dvo_reg = DVOC,
		.slave_addr = SIL164_ADDR,
		.dev_ops = &sil164_ops,
	},
	{
		.type = INTEL_DVO_CHIP_TMDS,
		.name = "ch7xxx",
		.dvo_reg = DVOC,
		.slave_addr = CH7xxx_ADDR,
		.dev_ops = &ch7xxx_ops,
	},
	{
		.type = INTEL_DVO_CHIP_TMDS,
		.name = "ch7xxx",
		.dvo_reg = DVOC,
		.slave_addr = 0x75, /* For some ch7010 */
		.dev_ops = &ch7xxx_ops,
	},
	{
		.type = INTEL_DVO_CHIP_LVDS,
		.name = "ivch",
		.dvo_reg = DVOA,
		.slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */
		.dev_ops = &ivch_ops,
	},
	{
		.type = INTEL_DVO_CHIP_TMDS,
		.name = "tfp410",
		.dvo_reg = DVOC,
		.slave_addr = TFP410_ADDR,
		.dev_ops = &tfp410_ops,
	},
	{
		.type = INTEL_DVO_CHIP_LVDS,
		.name = "ch7017",
		.dvo_reg = DVOC,
		.slave_addr = 0x75,
		.gpio = GMBUS_PIN_DPB,
		.dev_ops = &ch7017_ops,
	},
	{
	        .type = INTEL_DVO_CHIP_TMDS,
		.name = "ns2501",
		.dvo_reg = DVOB,
		.slave_addr = NS2501_ADDR,
		.dev_ops = &ns2501_ops,
       }
};

struct intel_dvo {
	struct intel_encoder base;

	struct intel_dvo_device dev;

	struct drm_display_mode *panel_fixed_mode;
	bool panel_wants_dither;
};

static struct intel_dvo *enc_to_dvo(struct intel_encoder *encoder)
{
	return container_of(encoder, struct intel_dvo, base);
}

static struct intel_dvo *intel_attached_dvo(struct drm_connector *connector)
{
	return enc_to_dvo(intel_attached_encoder(connector));
}

static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector)
{
	struct drm_device *dev = connector->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_dvo *intel_dvo = intel_attached_dvo(&connector->base);
	u32 tmp;

	tmp = I915_READ(intel_dvo->dev.dvo_reg);

	if (!(tmp & DVO_ENABLE))
		return false;

	return intel_dvo->dev.dev_ops->get_hw_state(&intel_dvo->dev);
}

static bool intel_dvo_get_hw_state(struct intel_encoder *encoder,
				   enum pipe *pipe)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
	u32 tmp;

	tmp = I915_READ(intel_dvo->dev.dvo_reg);

	if (!(tmp & DVO_ENABLE))
		return false;

	*pipe = PORT_TO_PIPE(tmp);

	return true;
}

static void intel_dvo_get_config(struct intel_encoder *encoder,
				 struct intel_crtc_state *pipe_config)
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
	u32 tmp, flags = 0;

	tmp = I915_READ(intel_dvo->dev.dvo_reg);
	if (tmp & DVO_HSYNC_ACTIVE_HIGH)
		flags |= DRM_MODE_FLAG_PHSYNC;
	else
		flags |= DRM_MODE_FLAG_NHSYNC;
	if (tmp & DVO_VSYNC_ACTIVE_HIGH)
		flags |= DRM_MODE_FLAG_PVSYNC;
	else
		flags |= DRM_MODE_FLAG_NVSYNC;

	pipe_config->base.adjusted_mode.flags |= flags;

	pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
}

static void intel_disable_dvo(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
	u32 dvo_reg = intel_dvo->dev.dvo_reg;
	u32 temp = I915_READ(dvo_reg);

	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);
	I915_WRITE(dvo_reg, temp & ~DVO_ENABLE);
	I915_READ(dvo_reg);
}

static void intel_enable_dvo(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
	u32 dvo_reg = intel_dvo->dev.dvo_reg;
	u32 temp = I915_READ(dvo_reg);

	intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
					 &crtc->config->base.mode,
					 &crtc->config->base.adjusted_mode);

	I915_WRITE(dvo_reg, temp | DVO_ENABLE);
	I915_READ(dvo_reg);

	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true);
}

static enum drm_mode_status
intel_dvo_mode_valid(struct drm_connector *connector,
		     struct drm_display_mode *mode)
{
	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
	int target_clock = mode->clock;

	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		return MODE_NO_DBLESCAN;

	/* XXX: Validate clock range */

	if (intel_dvo->panel_fixed_mode) {
		if (mode->hdisplay > intel_dvo->panel_fixed_mode->hdisplay)
			return MODE_PANEL;
		if (mode->vdisplay > intel_dvo->panel_fixed_mode->vdisplay)
			return MODE_PANEL;

		target_clock = intel_dvo->panel_fixed_mode->clock;
	}

	if (target_clock > max_dotclk)
		return MODE_CLOCK_HIGH;

	return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode);
}

static bool intel_dvo_compute_config(struct intel_encoder *encoder,
				     struct intel_crtc_state *pipe_config)
{
	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;

	/* If we have timings from the BIOS for the panel, put them in
	 * to the adjusted mode.  The CRTC will be set up for this mode,
	 * with the panel scaling set up to source from the H/VDisplay
	 * of the original mode.
	 */
	if (intel_dvo->panel_fixed_mode != NULL) {
#define C(x) adjusted_mode->x = intel_dvo->panel_fixed_mode->x
		C(hdisplay);
		C(hsync_start);
		C(hsync_end);
		C(htotal);
		C(vdisplay);
		C(vsync_start);
		C(vsync_end);
		C(vtotal);
		C(clock);
#undef C

		drm_mode_set_crtcinfo(adjusted_mode, 0);
	}

	return true;
}

static void intel_dvo_pre_enable(struct intel_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
	struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
	int pipe = crtc->pipe;
	u32 dvo_val;
	u32 dvo_reg = intel_dvo->dev.dvo_reg, dvo_srcdim_reg;

	switch (dvo_reg) {
	case DVOA:
	default:
		dvo_srcdim_reg = DVOA_SRCDIM;
		break;
	case DVOB:
		dvo_srcdim_reg = DVOB_SRCDIM;
		break;
	case DVOC:
		dvo_srcdim_reg = DVOC_SRCDIM;
		break;
	}

	/* Save the data order, since I don't know what it should be set to. */
	dvo_val = I915_READ(dvo_reg) &
		  (DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG);
	dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE |
		   DVO_BLANK_ACTIVE_HIGH;

	if (pipe == 1)
		dvo_val |= DVO_PIPE_B_SELECT;
	dvo_val |= DVO_PIPE_STALL;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
		dvo_val |= DVO_HSYNC_ACTIVE_HIGH;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
		dvo_val |= DVO_VSYNC_ACTIVE_HIGH;

	/*I915_WRITE(DVOB_SRCDIM,
	  (adjusted_mode->hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) |
	  (adjusted_mode->VDisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/
	I915_WRITE(dvo_srcdim_reg,
		   (adjusted_mode->hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) |
		   (adjusted_mode->vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));
	/*I915_WRITE(DVOB, dvo_val);*/
	I915_WRITE(dvo_reg, dvo_val);
}

/**
 * Detect the output connection on our DVO device.
 *
 * Unimplemented.
 */
static enum drm_connector_status
intel_dvo_detect(struct drm_connector *connector, bool force)
{
	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		      connector->base.id, connector->name);
	return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev);
}

static int intel_dvo_get_modes(struct drm_connector *connector)
{
	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
	struct drm_i915_private *dev_priv = connector->dev->dev_private;

	/* We should probably have an i2c driver get_modes function for those
	 * devices which will have a fixed set of modes determined by the chip
	 * (TV-out, for example), but for now with just TMDS and LVDS,
	 * that's not the case.
	 */
	intel_ddc_get_modes(connector,
			    intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPC));
	if (!list_empty(&connector->probed_modes))
		return 1;

	if (intel_dvo->panel_fixed_mode != NULL) {
		struct drm_display_mode *mode;
		mode = drm_mode_duplicate(connector->dev, intel_dvo->panel_fixed_mode);
		if (mode) {
			drm_mode_probed_add(connector, mode);
			return 1;
		}
	}

	return 0;
}

static void intel_dvo_destroy(struct drm_connector *connector)
{
	drm_connector_cleanup(connector);
	kfree(connector);
}

static const struct drm_connector_funcs intel_dvo_connector_funcs = {
	.dpms = drm_atomic_helper_connector_dpms,
	.detect = intel_dvo_detect,
	.destroy = intel_dvo_destroy,
	.fill_modes = drm_helper_probe_single_connector_modes,
	.atomic_get_property = intel_connector_atomic_get_property,
	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
};

static const struct drm_connector_helper_funcs intel_dvo_connector_helper_funcs = {
	.mode_valid = intel_dvo_mode_valid,
	.get_modes = intel_dvo_get_modes,
	.best_encoder = intel_best_encoder,
};

static void intel_dvo_enc_destroy(struct drm_encoder *encoder)
{
	struct intel_dvo *intel_dvo = enc_to_dvo(to_intel_encoder(encoder));

	if (intel_dvo->dev.dev_ops->destroy)
		intel_dvo->dev.dev_ops->destroy(&intel_dvo->dev);

	kfree(intel_dvo->panel_fixed_mode);

	intel_encoder_destroy(encoder);
}

static const struct drm_encoder_funcs intel_dvo_enc_funcs = {
	.destroy = intel_dvo_enc_destroy,
};

/**
 * Attempts to get a fixed panel timing for LVDS (currently only the i830).
 *
 * Other chips with DVO LVDS will need to extend this to deal with the LVDS
 * chip being on DVOB/C and having multiple pipes.
 */
static struct drm_display_mode *
intel_dvo_get_current_mode(struct drm_connector *connector)
{
	struct drm_device *dev = connector->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
	uint32_t dvo_val = I915_READ(intel_dvo->dev.dvo_reg);
	struct drm_display_mode *mode = NULL;

	/* If the DVO port is active, that'll be the LVDS, so we can pull out
	 * its timings to get how the BIOS set up the panel.
	 */
	if (dvo_val & DVO_ENABLE) {
		struct drm_crtc *crtc;
		int pipe = (dvo_val & DVO_PIPE_B_SELECT) ? 1 : 0;

		crtc = intel_get_crtc_for_pipe(dev, pipe);
		if (crtc) {
			mode = intel_crtc_mode_get(dev, crtc);
			if (mode) {
				mode->type |= DRM_MODE_TYPE_PREFERRED;
				if (dvo_val & DVO_HSYNC_ACTIVE_HIGH)
					mode->flags |= DRM_MODE_FLAG_PHSYNC;
				if (dvo_val & DVO_VSYNC_ACTIVE_HIGH)
					mode->flags |= DRM_MODE_FLAG_PVSYNC;
			}
		}
	}

	return mode;
}

void intel_dvo_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *intel_encoder;
	struct intel_dvo *intel_dvo;
	struct intel_connector *intel_connector;
	int i;
	int encoder_type = DRM_MODE_ENCODER_NONE;

	intel_dvo = kzalloc(sizeof(*intel_dvo), GFP_KERNEL);
	if (!intel_dvo)
		return;

	intel_connector = intel_connector_alloc();
	if (!intel_connector) {
		kfree(intel_dvo);
		return;
	}

	intel_encoder = &intel_dvo->base;
	drm_encoder_init(dev, &intel_encoder->base,
			 &intel_dvo_enc_funcs, encoder_type);

	intel_encoder->disable = intel_disable_dvo;
	intel_encoder->enable = intel_enable_dvo;
	intel_encoder->get_hw_state = intel_dvo_get_hw_state;
	intel_encoder->get_config = intel_dvo_get_config;
	intel_encoder->compute_config = intel_dvo_compute_config;
	intel_encoder->pre_enable = intel_dvo_pre_enable;
	intel_connector->get_hw_state = intel_dvo_connector_get_hw_state;
	intel_connector->unregister = intel_connector_unregister;

	/* Now, try to find a controller */
	for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) {
		struct drm_connector *connector = &intel_connector->base;
		const struct intel_dvo_device *dvo = &intel_dvo_devices[i];
		struct i2c_adapter *i2c;
		int gpio;
		bool dvoinit;
		enum pipe pipe;
		uint32_t dpll[I915_MAX_PIPES];

		/* Allow the I2C driver info to specify the GPIO to be used in
		 * special cases, but otherwise default to what's defined
		 * in the spec.
		 */
		if (intel_gmbus_is_valid_pin(dev_priv, dvo->gpio))
			gpio = dvo->gpio;
		else if (dvo->type == INTEL_DVO_CHIP_LVDS)
			gpio = GMBUS_PIN_SSC;
		else
			gpio = GMBUS_PIN_DPB;

		/* Set up the I2C bus necessary for the chip we're probing.
		 * It appears that everything is on GPIOE except for panels
		 * on i830 laptops, which are on GPIOB (DVOA).
		 */
		i2c = intel_gmbus_get_adapter(dev_priv, gpio);

		intel_dvo->dev = *dvo;

		/* GMBUS NAK handling seems to be unstable, hence let the
		 * transmitter detection run in bit banging mode for now.
		 */
		intel_gmbus_force_bit(i2c, true);

		/* ns2501 requires the DVO 2x clock before it will
		 * respond to i2c accesses, so make sure we have
		 * have the clock enabled before we attempt to
		 * initialize the device.
		 */
		for_each_pipe(dev_priv, pipe) {
			dpll[pipe] = I915_READ(DPLL(pipe));
			I915_WRITE(DPLL(pipe), dpll[pipe] | DPLL_DVO_2X_MODE);
		}

		dvoinit = dvo->dev_ops->init(&intel_dvo->dev, i2c);

		/* restore the DVO 2x clock state to original */
		for_each_pipe(dev_priv, pipe) {
			I915_WRITE(DPLL(pipe), dpll[pipe]);
		}

		intel_gmbus_force_bit(i2c, false);

		if (!dvoinit)
			continue;

		intel_encoder->type = INTEL_OUTPUT_DVO;
		intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
		switch (dvo->type) {
		case INTEL_DVO_CHIP_TMDS:
			intel_encoder->cloneable = (1 << INTEL_OUTPUT_ANALOG) |
				(1 << INTEL_OUTPUT_DVO);
			drm_connector_init(dev, connector,
					   &intel_dvo_connector_funcs,
					   DRM_MODE_CONNECTOR_DVII);
			encoder_type = DRM_MODE_ENCODER_TMDS;
			break;
		case INTEL_DVO_CHIP_LVDS:
			intel_encoder->cloneable = 0;
			drm_connector_init(dev, connector,
					   &intel_dvo_connector_funcs,
					   DRM_MODE_CONNECTOR_LVDS);
			encoder_type = DRM_MODE_ENCODER_LVDS;
			break;
		}

		drm_connector_helper_add(connector,
					 &intel_dvo_connector_helper_funcs);
		connector->display_info.subpixel_order = SubPixelHorizontalRGB;
		connector->interlace_allowed = false;
		connector->doublescan_allowed = false;

		intel_connector_attach_encoder(intel_connector, intel_encoder);
		if (dvo->type == INTEL_DVO_CHIP_LVDS) {
			/* For our LVDS chipsets, we should hopefully be able
			 * to dig the fixed panel mode out of the BIOS data.
			 * However, it's in a different format from the BIOS
			 * data on chipsets with integrated LVDS (stored in AIM
			 * headers, likely), so for now, just get the current
			 * mode being output through DVO.
			 */
			intel_dvo->panel_fixed_mode =
				intel_dvo_get_current_mode(connector);
			intel_dvo->panel_wants_dither = true;
		}

		drm_connector_register(connector);
		return;
	}

	drm_encoder_cleanup(&intel_encoder->base);
	kfree(intel_dvo);
	kfree(intel_connector);
}
Commit	Line	Data
79e53945 JB	1	/*
	2	* Copyright 2006 Dave Airlie <airlied@linux.ie>
	3	* Copyright © 2006-2007 Intel Corporation
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice (including the next
	13	* paragraph) shall be included in all copies or substantial portions of the
	14	* Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	21	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	22	* DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors:
	25	* Eric Anholt <eric@anholt.net>
	26	*/
	27	#include <linux/i2c.h>
5a0e3ad6	28	#include <linux/slab.h>
760285e7	29	#include <drm/drmP.h>
c6f95f27	30	#include <drm/drm_atomic_helper.h>
760285e7	31	#include <drm/drm_crtc.h>
79e53945	32	#include "intel_drv.h"
760285e7	33	#include <drm/i915_drm.h>
79e53945 JB	34	#include "i915_drv.h"
	35	#include "dvo.h"
	36
	37	#define SIL164_ADDR 0x38
	38	#define CH7xxx_ADDR 0x76
	39	#define TFP410_ADDR 0x38
7434a255	40	#define NS2501_ADDR 0x38
79e53945	41
ea5b213a	42	static const struct intel_dvo_device intel_dvo_devices[] = {
79e53945 JB	43	{
	44	.type = INTEL_DVO_CHIP_TMDS,
	45	.name = "sil164",
	46	.dvo_reg = DVOC,
	47	.slave_addr = SIL164_ADDR,
	48	.dev_ops = &sil164_ops,
	49	},
	50	{
	51	.type = INTEL_DVO_CHIP_TMDS,
	52	.name = "ch7xxx",
	53	.dvo_reg = DVOC,
	54	.slave_addr = CH7xxx_ADDR,
	55	.dev_ops = &ch7xxx_ops,
	56	},
98304ad1	57	{
	58	.type = INTEL_DVO_CHIP_TMDS,
	59	.name = "ch7xxx",
	60	.dvo_reg = DVOC,
	61	.slave_addr = 0x75, /* For some ch7010 */
	62	.dev_ops = &ch7xxx_ops,
	63	},
79e53945 JB	64	{
	65	.type = INTEL_DVO_CHIP_LVDS,
	66	.name = "ivch",
	67	.dvo_reg = DVOA,
	68	.slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */
	69	.dev_ops = &ivch_ops,
	70	},
	71	{
	72	.type = INTEL_DVO_CHIP_TMDS,
	73	.name = "tfp410",
	74	.dvo_reg = DVOC,
	75	.slave_addr = TFP410_ADDR,
	76	.dev_ops = &tfp410_ops,
	77	},
	78	{
	79	.type = INTEL_DVO_CHIP_LVDS,
	80	.name = "ch7017",
	81	.dvo_reg = DVOC,
	82	.slave_addr = 0x75,
988c7015	83	.gpio = GMBUS_PIN_DPB,
79e53945	84	.dev_ops = &ch7017_ops,
7434a255 TR	85	},
	86	{
	87	.type = INTEL_DVO_CHIP_TMDS,
	88	.name = "ns2501",
316e0157	89	.dvo_reg = DVOB,
7434a255 TR	90	.slave_addr = NS2501_ADDR,
	91	.dev_ops = &ns2501_ops,
	92	}
79e53945 JB	93	};
79e53945 JB	94
ea5b213a CW	95	struct intel_dvo {
	96	struct intel_encoder base;
	97
	98	struct intel_dvo_device dev;
	99
	100	struct drm_display_mode *panel_fixed_mode;
	101	bool panel_wants_dither;
	102	};
	103
69438e64	104	static struct intel_dvo enc_to_dvo(struct intel_encoder encoder)
ea5b213a	105	{
69438e64	106	return container_of(encoder, struct intel_dvo, base);
ea5b213a CW	107	}
ea5b213a CW	108
df0e9248 CW	109	static struct intel_dvo intel_attached_dvo(struct drm_connector connector)
df0e9248 CW	110	{
79fde301	111	return enc_to_dvo(intel_attached_encoder(connector));
df0e9248 CW	112	}
df0e9248 CW	113
732ce74f	114	static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector)
79e53945	115	{
f417c11b VS	116	struct drm_device *dev = connector->base.dev;
f417c11b VS	117	struct drm_i915_private *dev_priv = dev->dev_private;
732ce74f	118	struct intel_dvo *intel_dvo = intel_attached_dvo(&connector->base);
f417c11b VS	119	u32 tmp;
	120
	121	tmp = I915_READ(intel_dvo->dev.dvo_reg);
	122
	123	if (!(tmp & DVO_ENABLE))
	124	return false;
732ce74f DV	125
	126	return intel_dvo->dev.dev_ops->get_hw_state(&intel_dvo->dev);
	127	}
	128
	129	static bool intel_dvo_get_hw_state(struct intel_encoder *encoder,
	130	enum pipe *pipe)
	131	{
	132	struct drm_device *dev = encoder->base.dev;
	133	struct drm_i915_private *dev_priv = dev->dev_private;
69438e64	134	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
732ce74f DV	135	u32 tmp;
	136
	137	tmp = I915_READ(intel_dvo->dev.dvo_reg);
	138
	139	if (!(tmp & DVO_ENABLE))
	140	return false;
	141
	142	*pipe = PORT_TO_PIPE(tmp);
	143
	144	return true;
	145	}
	146
045ac3b5	147	static void intel_dvo_get_config(struct intel_encoder *encoder,
5cec258b	148	struct intel_crtc_state *pipe_config)
045ac3b5 JB	149	{
045ac3b5 JB	150	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
69438e64	151	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
045ac3b5 JB	152	u32 tmp, flags = 0;
	153
	154	tmp = I915_READ(intel_dvo->dev.dvo_reg);
	155	if (tmp & DVO_HSYNC_ACTIVE_HIGH)
	156	flags \|= DRM_MODE_FLAG_PHSYNC;
	157	else
	158	flags \|= DRM_MODE_FLAG_NHSYNC;
	159	if (tmp & DVO_VSYNC_ACTIVE_HIGH)
	160	flags \|= DRM_MODE_FLAG_PVSYNC;
	161	else
	162	flags \|= DRM_MODE_FLAG_NVSYNC;
	163
2d112de7	164	pipe_config->base.adjusted_mode.flags \|= flags;
18442d08	165
2d112de7	166	pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
045ac3b5 JB	167	}
045ac3b5 JB	168
19c63fa8 DV	169	static void intel_disable_dvo(struct intel_encoder *encoder)
	170	{
	171	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
69438e64	172	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
19c63fa8 DV	173	u32 dvo_reg = intel_dvo->dev.dvo_reg;
	174	u32 temp = I915_READ(dvo_reg);
	175
	176	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);
	177	I915_WRITE(dvo_reg, temp & ~DVO_ENABLE);
	178	I915_READ(dvo_reg);
	179	}
	180
	181	static void intel_enable_dvo(struct intel_encoder *encoder)
	182	{
	183	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
69438e64	184	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
48f34e10	185	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
ea5b213a	186	u32 dvo_reg = intel_dvo->dev.dvo_reg;
79e53945 JB	187	u32 temp = I915_READ(dvo_reg);
79e53945 JB	188
48f34e10	189	intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
6e3c9717 ACO	190	&crtc->config->base.mode,
6e3c9717 ACO	191	&crtc->config->base.adjusted_mode);
48f34e10	192
c9c054c2 VS	193	I915_WRITE(dvo_reg, temp \| DVO_ENABLE);
	194	I915_READ(dvo_reg);
	195
19c63fa8 DV	196	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true);
	197	}
	198
c19de8eb DL	199	static enum drm_mode_status
	200	intel_dvo_mode_valid(struct drm_connector *connector,
	201	struct drm_display_mode *mode)
79e53945	202	{
df0e9248	203	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
26a91555 MK	204	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
26a91555 MK	205	int target_clock = mode->clock;
79e53945 JB	206
	207	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
	208	return MODE_NO_DBLESCAN;
	209
	210	/* XXX: Validate clock range */
	211
ea5b213a CW	212	if (intel_dvo->panel_fixed_mode) {
ea5b213a CW	213	if (mode->hdisplay > intel_dvo->panel_fixed_mode->hdisplay)
79e53945	214	return MODE_PANEL;
ea5b213a	215	if (mode->vdisplay > intel_dvo->panel_fixed_mode->vdisplay)
79e53945	216	return MODE_PANEL;
26a91555 MK	217
26a91555 MK	218	target_clock = intel_dvo->panel_fixed_mode->clock;
79e53945 JB	219	}
79e53945 JB	220
26a91555 MK	221	if (target_clock > max_dotclk)
	222	return MODE_CLOCK_HIGH;
	223
ea5b213a	224	return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode);
79e53945 JB	225	}
79e53945 JB	226
a3470375	227	static bool intel_dvo_compute_config(struct intel_encoder *encoder,
5cec258b	228	struct intel_crtc_state *pipe_config)
79e53945	229	{
a3470375	230	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
2d112de7	231	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
79e53945 JB	232
	233	/* If we have timings from the BIOS for the panel, put them in
	234	* to the adjusted mode. The CRTC will be set up for this mode,
	235	* with the panel scaling set up to source from the H/VDisplay
	236	* of the original mode.
	237	*/
ea5b213a CW	238	if (intel_dvo->panel_fixed_mode != NULL) {
ea5b213a CW	239	#define C(x) adjusted_mode->x = intel_dvo->panel_fixed_mode->x
79e53945 JB	240	C(hdisplay);
	241	C(hsync_start);
	242	C(hsync_end);
	243	C(htotal);
	244	C(vdisplay);
	245	C(vsync_start);
	246	C(vsync_end);
	247	C(vtotal);
	248	C(clock);
79e53945	249	#undef C
0d971748 DV	250
0d971748 DV	251	drm_mode_set_crtcinfo(adjusted_mode, 0);
79e53945 JB	252	}
79e53945 JB	253
79e53945 JB	254	return true;
	255	}
	256
912b0e2d	257	static void intel_dvo_pre_enable(struct intel_encoder *encoder)
79e53945	258	{
79fde301	259	struct drm_device *dev = encoder->base.dev;
79e53945	260	struct drm_i915_private *dev_priv = dev->dev_private;
79fde301	261	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
6e3c9717	262	struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
79fde301 DV	263	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
79fde301 DV	264	int pipe = crtc->pipe;
79e53945	265	u32 dvo_val;
ea5b213a	266	u32 dvo_reg = intel_dvo->dev.dvo_reg, dvo_srcdim_reg;
79e53945 JB	267
	268	switch (dvo_reg) {
	269	case DVOA:
	270	default:
	271	dvo_srcdim_reg = DVOA_SRCDIM;
	272	break;
	273	case DVOB:
	274	dvo_srcdim_reg = DVOB_SRCDIM;
	275	break;
	276	case DVOC:
	277	dvo_srcdim_reg = DVOC_SRCDIM;
	278	break;
	279	}
	280
79e53945 JB	281	/* Save the data order, since I don't know what it should be set to. */
	282	dvo_val = I915_READ(dvo_reg) &
	283	(DVO_PRESERVE_MASK \| DVO_DATA_ORDER_GBRG);
	284	dvo_val \|= DVO_DATA_ORDER_FP \| DVO_BORDER_ENABLE \|
	285	DVO_BLANK_ACTIVE_HIGH;
	286
	287	if (pipe == 1)
	288	dvo_val \|= DVO_PIPE_B_SELECT;
	289	dvo_val \|= DVO_PIPE_STALL;
	290	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
	291	dvo_val \|= DVO_HSYNC_ACTIVE_HIGH;
	292	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
	293	dvo_val \|= DVO_VSYNC_ACTIVE_HIGH;
	294
79e53945 JB	295	/*I915_WRITE(DVOB_SRCDIM,
	296	(adjusted_mode->hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) \|
	297	(adjusted_mode->VDisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/
	298	I915_WRITE(dvo_srcdim_reg,
	299	(adjusted_mode->hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) \|
	300	(adjusted_mode->vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));
	301	/I915_WRITE(DVOB, dvo_val);/
	302	I915_WRITE(dvo_reg, dvo_val);
	303	}
	304
	305	/**
	306	* Detect the output connection on our DVO device.
	307	*
	308	* Unimplemented.
	309	*/
7b334fcb	310	static enum drm_connector_status
930a9e28	311	intel_dvo_detect(struct drm_connector *connector, bool force)
79e53945	312	{
df0e9248	313	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
164c8598	314	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417	315	connector->base.id, connector->name);
ea5b213a	316	return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev);
79e53945 JB	317	}
	318
	319	static int intel_dvo_get_modes(struct drm_connector *connector)
	320	{
df0e9248	321	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
f899fc64	322	struct drm_i915_private *dev_priv = connector->dev->dev_private;
79e53945 JB	323
	324	/* We should probably have an i2c driver get_modes function for those
	325	* devices which will have a fixed set of modes determined by the chip
	326	* (TV-out, for example), but for now with just TMDS and LVDS,
	327	* that's not the case.
	328	*/
f899fc64	329	intel_ddc_get_modes(connector,
988c7015	330	intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPC));
79e53945 JB	331	if (!list_empty(&connector->probed_modes))
	332	return 1;
	333
ea5b213a	334	if (intel_dvo->panel_fixed_mode != NULL) {
79e53945	335	struct drm_display_mode *mode;
ea5b213a	336	mode = drm_mode_duplicate(connector->dev, intel_dvo->panel_fixed_mode);
79e53945 JB	337	if (mode) {
	338	drm_mode_probed_add(connector, mode);
	339	return 1;
	340	}
	341	}
ea5b213a	342
79e53945 JB	343	return 0;
	344	}
	345
ea5b213a	346	static void intel_dvo_destroy(struct drm_connector *connector)
79e53945	347	{
79e53945	348	drm_connector_cleanup(connector);
599be16c	349	kfree(connector);
79e53945	350	}
79e53945	351
79e53945	352	static const struct drm_connector_funcs intel_dvo_connector_funcs = {
4d688a2a	353	.dpms = drm_atomic_helper_connector_dpms,
79e53945 JB	354	.detect = intel_dvo_detect,
	355	.destroy = intel_dvo_destroy,
	356	.fill_modes = drm_helper_probe_single_connector_modes,
2545e4a6	357	.atomic_get_property = intel_connector_atomic_get_property,
c6f95f27	358	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
98969725	359	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
79e53945 JB	360	};
	361
	362	static const struct drm_connector_helper_funcs intel_dvo_connector_helper_funcs = {
	363	.mode_valid = intel_dvo_mode_valid,
	364	.get_modes = intel_dvo_get_modes,
df0e9248	365	.best_encoder = intel_best_encoder,
79e53945 JB	366	};
79e53945 JB	367
b358d0a6	368	static void intel_dvo_enc_destroy(struct drm_encoder *encoder)
79e53945	369	{
69438e64	370	struct intel_dvo *intel_dvo = enc_to_dvo(to_intel_encoder(encoder));
ea5b213a CW	371
	372	if (intel_dvo->dev.dev_ops->destroy)
	373	intel_dvo->dev.dev_ops->destroy(&intel_dvo->dev);
	374
	375	kfree(intel_dvo->panel_fixed_mode);
	376
	377	intel_encoder_destroy(encoder);
79e53945 JB	378	}
	379
	380	static const struct drm_encoder_funcs intel_dvo_enc_funcs = {
	381	.destroy = intel_dvo_enc_destroy,
	382	};
	383
79e53945 JB	384	/**
	385	* Attempts to get a fixed panel timing for LVDS (currently only the i830).
	386	*
	387	* Other chips with DVO LVDS will need to extend this to deal with the LVDS
	388	* chip being on DVOB/C and having multiple pipes.
	389	*/
	390	static struct drm_display_mode *
ea5b213a	391	intel_dvo_get_current_mode(struct drm_connector *connector)
79e53945 JB	392	{
	393	struct drm_device *dev = connector->dev;
	394	struct drm_i915_private *dev_priv = dev->dev_private;
df0e9248	395	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
ea5b213a	396	uint32_t dvo_val = I915_READ(intel_dvo->dev.dvo_reg);
79e53945 JB	397	struct drm_display_mode *mode = NULL;
	398
	399	/* If the DVO port is active, that'll be the LVDS, so we can pull out
	400	* its timings to get how the BIOS set up the panel.
	401	*/
	402	if (dvo_val & DVO_ENABLE) {
	403	struct drm_crtc *crtc;
	404	int pipe = (dvo_val & DVO_PIPE_B_SELECT) ? 1 : 0;
	405
f875c15a	406	crtc = intel_get_crtc_for_pipe(dev, pipe);
79e53945 JB	407	if (crtc) {
79e53945 JB	408	mode = intel_crtc_mode_get(dev, crtc);
79e53945 JB	409	if (mode) {
	410	mode->type \|= DRM_MODE_TYPE_PREFERRED;
	411	if (dvo_val & DVO_HSYNC_ACTIVE_HIGH)
	412	mode->flags \|= DRM_MODE_FLAG_PHSYNC;
	413	if (dvo_val & DVO_VSYNC_ACTIVE_HIGH)
	414	mode->flags \|= DRM_MODE_FLAG_PVSYNC;
	415	}
	416	}
	417	}
ea5b213a	418
79e53945 JB	419	return mode;
	420	}
	421
	422	void intel_dvo_init(struct drm_device *dev)
	423	{
f899fc64	424	struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37	425	struct intel_encoder *intel_encoder;
ea5b213a	426	struct intel_dvo *intel_dvo;
599be16c	427	struct intel_connector *intel_connector;
79e53945	428	int i;
79e53945	429	int encoder_type = DRM_MODE_ENCODER_NONE;
ea5b213a	430
b14c5679	431	intel_dvo = kzalloc(sizeof(*intel_dvo), GFP_KERNEL);
ea5b213a	432	if (!intel_dvo)
79e53945 JB	433	return;
79e53945 JB	434
9bdbd0b9	435	intel_connector = intel_connector_alloc();
599be16c	436	if (!intel_connector) {
ea5b213a	437	kfree(intel_dvo);
599be16c ZW	438	return;
	439	}
	440
ea5b213a	441	intel_encoder = &intel_dvo->base;
373a3cf7 CW	442	drm_encoder_init(dev, &intel_encoder->base,
373a3cf7 CW	443	&intel_dvo_enc_funcs, encoder_type);
ea5b213a	444
19c63fa8 DV	445	intel_encoder->disable = intel_disable_dvo;
19c63fa8 DV	446	intel_encoder->enable = intel_enable_dvo;
732ce74f	447	intel_encoder->get_hw_state = intel_dvo_get_hw_state;
045ac3b5	448	intel_encoder->get_config = intel_dvo_get_config;
a3470375	449	intel_encoder->compute_config = intel_dvo_compute_config;
912b0e2d	450	intel_encoder->pre_enable = intel_dvo_pre_enable;
732ce74f	451	intel_connector->get_hw_state = intel_dvo_connector_get_hw_state;
4932e2c3	452	intel_connector->unregister = intel_connector_unregister;
19c63fa8	453
79e53945 JB	454	/* Now, try to find a controller */
79e53945 JB	455	for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) {
599be16c	456	struct drm_connector *connector = &intel_connector->base;
ea5b213a	457	const struct intel_dvo_device *dvo = &intel_dvo_devices[i];
f899fc64	458	struct i2c_adapter *i2c;
79e53945	459	int gpio;
e4bfff54	460	bool dvoinit;
46509475	461	enum pipe pipe;
699ab787	462	uint32_t dpll[I915_MAX_PIPES];
79e53945	463
79e53945 JB	464	/* Allow the I2C driver info to specify the GPIO to be used in
	465	* special cases, but otherwise default to what's defined
	466	* in the spec.
	467	*/
88ac7939	468	if (intel_gmbus_is_valid_pin(dev_priv, dvo->gpio))
79e53945 JB	469	gpio = dvo->gpio;
79e53945 JB	470	else if (dvo->type == INTEL_DVO_CHIP_LVDS)
988c7015	471	gpio = GMBUS_PIN_SSC;
79e53945	472	else
988c7015	473	gpio = GMBUS_PIN_DPB;
79e53945 JB	474
	475	/* Set up the I2C bus necessary for the chip we're probing.
	476	* It appears that everything is on GPIOE except for panels
	477	* on i830 laptops, which are on GPIOB (DVOA).
	478	*/
3bd7d909	479	i2c = intel_gmbus_get_adapter(dev_priv, gpio);
79e53945	480
ea5b213a	481	intel_dvo->dev = *dvo;
e4bfff54 DMEA	482
	483	/* GMBUS NAK handling seems to be unstable, hence let the
	484	* transmitter detection run in bit banging mode for now.
	485	*/
	486	intel_gmbus_force_bit(i2c, true);
	487
46509475 VS	488	/* ns2501 requires the DVO 2x clock before it will
	489	* respond to i2c accesses, so make sure we have
	490	* have the clock enabled before we attempt to
	491	* initialize the device.
	492	*/
	493	for_each_pipe(dev_priv, pipe) {
	494	dpll[pipe] = I915_READ(DPLL(pipe));
	495	I915_WRITE(DPLL(pipe), dpll[pipe] \| DPLL_DVO_2X_MODE);
	496	}
	497
e4bfff54 DMEA	498	dvoinit = dvo->dev_ops->init(&intel_dvo->dev, i2c);
e4bfff54 DMEA	499
46509475 VS	500	/* restore the DVO 2x clock state to original */
	501	for_each_pipe(dev_priv, pipe) {
	502	I915_WRITE(DPLL(pipe), dpll[pipe]);
	503	}
	504
e4bfff54 DMEA	505	intel_gmbus_force_bit(i2c, false);
	506
	507	if (!dvoinit)
79e53945 JB	508	continue;
79e53945 JB	509
21d40d37 EA	510	intel_encoder->type = INTEL_OUTPUT_DVO;
21d40d37 EA	511	intel_encoder->crtc_mask = (1 << 0) \| (1 << 1);
79e53945 JB	512	switch (dvo->type) {
79e53945 JB	513	case INTEL_DVO_CHIP_TMDS:
bc079e8b VS	514	intel_encoder->cloneable = (1 << INTEL_OUTPUT_ANALOG) \|
bc079e8b VS	515	(1 << INTEL_OUTPUT_DVO);
79e53945 JB	516	drm_connector_init(dev, connector,
	517	&intel_dvo_connector_funcs,
	518	DRM_MODE_CONNECTOR_DVII);
	519	encoder_type = DRM_MODE_ENCODER_TMDS;
	520	break;
	521	case INTEL_DVO_CHIP_LVDS:
bc079e8b	522	intel_encoder->cloneable = 0;
79e53945 JB	523	drm_connector_init(dev, connector,
	524	&intel_dvo_connector_funcs,
	525	DRM_MODE_CONNECTOR_LVDS);
	526	encoder_type = DRM_MODE_ENCODER_LVDS;
	527	break;
	528	}
	529
	530	drm_connector_helper_add(connector,
	531	&intel_dvo_connector_helper_funcs);
	532	connector->display_info.subpixel_order = SubPixelHorizontalRGB;
	533	connector->interlace_allowed = false;
	534	connector->doublescan_allowed = false;
	535
df0e9248	536	intel_connector_attach_encoder(intel_connector, intel_encoder);
79e53945 JB	537	if (dvo->type == INTEL_DVO_CHIP_LVDS) {
	538	/* For our LVDS chipsets, we should hopefully be able
	539	* to dig the fixed panel mode out of the BIOS data.
	540	* However, it's in a different format from the BIOS
	541	* data on chipsets with integrated LVDS (stored in AIM
	542	* headers, likely), so for now, just get the current
	543	* mode being output through DVO.
	544	*/
ea5b213a	545	intel_dvo->panel_fixed_mode =
79e53945	546	intel_dvo_get_current_mode(connector);
ea5b213a	547	intel_dvo->panel_wants_dither = true;
79e53945 JB	548	}
79e53945 JB	549
34ea3d38	550	drm_connector_register(connector);
79e53945 JB	551	return;
	552	}
	553
373a3cf7	554	drm_encoder_cleanup(&intel_encoder->base);
ea5b213a	555	kfree(intel_dvo);
599be16c	556	kfree(intel_connector);
79e53945	557	}