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79e53945 JB |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2007 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | */ | |
27 | #include <linux/i2c.h> | |
5a0e3ad6 | 28 | #include <linux/slab.h> |
760285e7 DH |
29 | #include <drm/drmP.h> |
30 | #include <drm/drm_crtc.h> | |
79e53945 | 31 | #include "intel_drv.h" |
760285e7 | 32 | #include <drm/i915_drm.h> |
79e53945 JB |
33 | #include "i915_drv.h" |
34 | #include "dvo.h" | |
35 | ||
36 | #define SIL164_ADDR 0x38 | |
37 | #define CH7xxx_ADDR 0x76 | |
38 | #define TFP410_ADDR 0x38 | |
7434a255 | 39 | #define NS2501_ADDR 0x38 |
79e53945 | 40 | |
ea5b213a | 41 | static const struct intel_dvo_device intel_dvo_devices[] = { |
79e53945 JB |
42 | { |
43 | .type = INTEL_DVO_CHIP_TMDS, | |
44 | .name = "sil164", | |
45 | .dvo_reg = DVOC, | |
46 | .slave_addr = SIL164_ADDR, | |
47 | .dev_ops = &sil164_ops, | |
48 | }, | |
49 | { | |
50 | .type = INTEL_DVO_CHIP_TMDS, | |
51 | .name = "ch7xxx", | |
52 | .dvo_reg = DVOC, | |
53 | .slave_addr = CH7xxx_ADDR, | |
54 | .dev_ops = &ch7xxx_ops, | |
55 | }, | |
98304ad1 | 56 | { |
57 | .type = INTEL_DVO_CHIP_TMDS, | |
58 | .name = "ch7xxx", | |
59 | .dvo_reg = DVOC, | |
60 | .slave_addr = 0x75, /* For some ch7010 */ | |
61 | .dev_ops = &ch7xxx_ops, | |
62 | }, | |
79e53945 JB |
63 | { |
64 | .type = INTEL_DVO_CHIP_LVDS, | |
65 | .name = "ivch", | |
66 | .dvo_reg = DVOA, | |
67 | .slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */ | |
68 | .dev_ops = &ivch_ops, | |
69 | }, | |
70 | { | |
71 | .type = INTEL_DVO_CHIP_TMDS, | |
72 | .name = "tfp410", | |
73 | .dvo_reg = DVOC, | |
74 | .slave_addr = TFP410_ADDR, | |
75 | .dev_ops = &tfp410_ops, | |
76 | }, | |
77 | { | |
78 | .type = INTEL_DVO_CHIP_LVDS, | |
79 | .name = "ch7017", | |
80 | .dvo_reg = DVOC, | |
81 | .slave_addr = 0x75, | |
a6b17b43 | 82 | .gpio = GMBUS_PORT_DPB, |
79e53945 | 83 | .dev_ops = &ch7017_ops, |
7434a255 TR |
84 | }, |
85 | { | |
86 | .type = INTEL_DVO_CHIP_TMDS, | |
87 | .name = "ns2501", | |
88 | .dvo_reg = DVOC, | |
89 | .slave_addr = NS2501_ADDR, | |
90 | .dev_ops = &ns2501_ops, | |
91 | } | |
79e53945 JB |
92 | }; |
93 | ||
ea5b213a CW |
94 | struct intel_dvo { |
95 | struct intel_encoder base; | |
96 | ||
97 | struct intel_dvo_device dev; | |
98 | ||
99 | struct drm_display_mode *panel_fixed_mode; | |
100 | bool panel_wants_dither; | |
101 | }; | |
102 | ||
69438e64 | 103 | static struct intel_dvo *enc_to_dvo(struct intel_encoder *encoder) |
ea5b213a | 104 | { |
69438e64 | 105 | return container_of(encoder, struct intel_dvo, base); |
ea5b213a CW |
106 | } |
107 | ||
df0e9248 CW |
108 | static struct intel_dvo *intel_attached_dvo(struct drm_connector *connector) |
109 | { | |
79fde301 | 110 | return enc_to_dvo(intel_attached_encoder(connector)); |
df0e9248 CW |
111 | } |
112 | ||
732ce74f | 113 | static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector) |
79e53945 | 114 | { |
732ce74f DV |
115 | struct intel_dvo *intel_dvo = intel_attached_dvo(&connector->base); |
116 | ||
117 | return intel_dvo->dev.dev_ops->get_hw_state(&intel_dvo->dev); | |
118 | } | |
119 | ||
120 | static bool intel_dvo_get_hw_state(struct intel_encoder *encoder, | |
121 | enum pipe *pipe) | |
122 | { | |
123 | struct drm_device *dev = encoder->base.dev; | |
124 | struct drm_i915_private *dev_priv = dev->dev_private; | |
69438e64 | 125 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
732ce74f DV |
126 | u32 tmp; |
127 | ||
128 | tmp = I915_READ(intel_dvo->dev.dvo_reg); | |
129 | ||
130 | if (!(tmp & DVO_ENABLE)) | |
131 | return false; | |
132 | ||
133 | *pipe = PORT_TO_PIPE(tmp); | |
134 | ||
135 | return true; | |
136 | } | |
137 | ||
045ac3b5 JB |
138 | static void intel_dvo_get_config(struct intel_encoder *encoder, |
139 | struct intel_crtc_config *pipe_config) | |
140 | { | |
141 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
69438e64 | 142 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
045ac3b5 JB |
143 | u32 tmp, flags = 0; |
144 | ||
145 | tmp = I915_READ(intel_dvo->dev.dvo_reg); | |
146 | if (tmp & DVO_HSYNC_ACTIVE_HIGH) | |
147 | flags |= DRM_MODE_FLAG_PHSYNC; | |
148 | else | |
149 | flags |= DRM_MODE_FLAG_NHSYNC; | |
150 | if (tmp & DVO_VSYNC_ACTIVE_HIGH) | |
151 | flags |= DRM_MODE_FLAG_PVSYNC; | |
152 | else | |
153 | flags |= DRM_MODE_FLAG_NVSYNC; | |
154 | ||
155 | pipe_config->adjusted_mode.flags |= flags; | |
156 | } | |
157 | ||
19c63fa8 DV |
158 | static void intel_disable_dvo(struct intel_encoder *encoder) |
159 | { | |
160 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
69438e64 | 161 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
19c63fa8 DV |
162 | u32 dvo_reg = intel_dvo->dev.dvo_reg; |
163 | u32 temp = I915_READ(dvo_reg); | |
164 | ||
165 | intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false); | |
166 | I915_WRITE(dvo_reg, temp & ~DVO_ENABLE); | |
167 | I915_READ(dvo_reg); | |
168 | } | |
169 | ||
170 | static void intel_enable_dvo(struct intel_encoder *encoder) | |
171 | { | |
172 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
69438e64 | 173 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
ea5b213a | 174 | u32 dvo_reg = intel_dvo->dev.dvo_reg; |
79e53945 JB |
175 | u32 temp = I915_READ(dvo_reg); |
176 | ||
19c63fa8 DV |
177 | I915_WRITE(dvo_reg, temp | DVO_ENABLE); |
178 | I915_READ(dvo_reg); | |
179 | intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true); | |
180 | } | |
181 | ||
6b1c087b | 182 | /* Special dpms function to support cloning between dvo/sdvo/crt. */ |
b2cabb0e | 183 | static void intel_dvo_dpms(struct drm_connector *connector, int mode) |
79e53945 | 184 | { |
b2cabb0e DV |
185 | struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
186 | struct drm_crtc *crtc; | |
187 | ||
188 | /* dvo supports only 2 dpms states. */ | |
189 | if (mode != DRM_MODE_DPMS_ON) | |
190 | mode = DRM_MODE_DPMS_OFF; | |
191 | ||
192 | if (mode == connector->dpms) | |
193 | return; | |
194 | ||
195 | connector->dpms = mode; | |
196 | ||
197 | /* Only need to change hw state when actually enabled */ | |
198 | crtc = intel_dvo->base.base.crtc; | |
199 | if (!crtc) { | |
200 | intel_dvo->base.connectors_active = false; | |
201 | return; | |
202 | } | |
79e53945 | 203 | |
6b1c087b JN |
204 | /* We call connector dpms manually below in case pipe dpms doesn't |
205 | * change due to cloning. */ | |
79e53945 | 206 | if (mode == DRM_MODE_DPMS_ON) { |
b2cabb0e DV |
207 | intel_dvo->base.connectors_active = true; |
208 | ||
209 | intel_crtc_update_dpms(crtc); | |
210 | ||
fac3274c | 211 | intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true); |
79e53945 | 212 | } else { |
fac3274c | 213 | intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false); |
b2cabb0e DV |
214 | |
215 | intel_dvo->base.connectors_active = false; | |
216 | ||
217 | intel_crtc_update_dpms(crtc); | |
79e53945 | 218 | } |
0a91ca29 | 219 | |
b980514c | 220 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
221 | } |
222 | ||
79e53945 JB |
223 | static int intel_dvo_mode_valid(struct drm_connector *connector, |
224 | struct drm_display_mode *mode) | |
225 | { | |
df0e9248 | 226 | struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
79e53945 JB |
227 | |
228 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
229 | return MODE_NO_DBLESCAN; | |
230 | ||
231 | /* XXX: Validate clock range */ | |
232 | ||
ea5b213a CW |
233 | if (intel_dvo->panel_fixed_mode) { |
234 | if (mode->hdisplay > intel_dvo->panel_fixed_mode->hdisplay) | |
79e53945 | 235 | return MODE_PANEL; |
ea5b213a | 236 | if (mode->vdisplay > intel_dvo->panel_fixed_mode->vdisplay) |
79e53945 JB |
237 | return MODE_PANEL; |
238 | } | |
239 | ||
ea5b213a | 240 | return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode); |
79e53945 JB |
241 | } |
242 | ||
a3470375 DV |
243 | static bool intel_dvo_compute_config(struct intel_encoder *encoder, |
244 | struct intel_crtc_config *pipe_config) | |
79e53945 | 245 | { |
a3470375 DV |
246 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
247 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; | |
79e53945 JB |
248 | |
249 | /* If we have timings from the BIOS for the panel, put them in | |
250 | * to the adjusted mode. The CRTC will be set up for this mode, | |
251 | * with the panel scaling set up to source from the H/VDisplay | |
252 | * of the original mode. | |
253 | */ | |
ea5b213a CW |
254 | if (intel_dvo->panel_fixed_mode != NULL) { |
255 | #define C(x) adjusted_mode->x = intel_dvo->panel_fixed_mode->x | |
79e53945 JB |
256 | C(hdisplay); |
257 | C(hsync_start); | |
258 | C(hsync_end); | |
259 | C(htotal); | |
260 | C(vdisplay); | |
261 | C(vsync_start); | |
262 | C(vsync_end); | |
263 | C(vtotal); | |
264 | C(clock); | |
79e53945 | 265 | #undef C |
0d971748 DV |
266 | |
267 | drm_mode_set_crtcinfo(adjusted_mode, 0); | |
79e53945 JB |
268 | } |
269 | ||
ea5b213a | 270 | if (intel_dvo->dev.dev_ops->mode_fixup) |
a3470375 DV |
271 | return intel_dvo->dev.dev_ops->mode_fixup(&intel_dvo->dev, |
272 | &pipe_config->requested_mode, | |
273 | adjusted_mode); | |
79e53945 JB |
274 | |
275 | return true; | |
276 | } | |
277 | ||
79fde301 | 278 | static void intel_dvo_mode_set(struct intel_encoder *encoder) |
79e53945 | 279 | { |
79fde301 | 280 | struct drm_device *dev = encoder->base.dev; |
79e53945 | 281 | struct drm_i915_private *dev_priv = dev->dev_private; |
79fde301 DV |
282 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
283 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; | |
284 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); | |
285 | int pipe = crtc->pipe; | |
79e53945 | 286 | u32 dvo_val; |
ea5b213a | 287 | u32 dvo_reg = intel_dvo->dev.dvo_reg, dvo_srcdim_reg; |
79e53945 JB |
288 | |
289 | switch (dvo_reg) { | |
290 | case DVOA: | |
291 | default: | |
292 | dvo_srcdim_reg = DVOA_SRCDIM; | |
293 | break; | |
294 | case DVOB: | |
295 | dvo_srcdim_reg = DVOB_SRCDIM; | |
296 | break; | |
297 | case DVOC: | |
298 | dvo_srcdim_reg = DVOC_SRCDIM; | |
299 | break; | |
300 | } | |
301 | ||
79fde301 DV |
302 | intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev, |
303 | &crtc->config.requested_mode, | |
304 | adjusted_mode); | |
79e53945 JB |
305 | |
306 | /* Save the data order, since I don't know what it should be set to. */ | |
307 | dvo_val = I915_READ(dvo_reg) & | |
308 | (DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG); | |
309 | dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE | | |
310 | DVO_BLANK_ACTIVE_HIGH; | |
311 | ||
312 | if (pipe == 1) | |
313 | dvo_val |= DVO_PIPE_B_SELECT; | |
314 | dvo_val |= DVO_PIPE_STALL; | |
315 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
316 | dvo_val |= DVO_HSYNC_ACTIVE_HIGH; | |
317 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
318 | dvo_val |= DVO_VSYNC_ACTIVE_HIGH; | |
319 | ||
79e53945 JB |
320 | /*I915_WRITE(DVOB_SRCDIM, |
321 | (adjusted_mode->hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | | |
322 | (adjusted_mode->VDisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/ | |
323 | I915_WRITE(dvo_srcdim_reg, | |
324 | (adjusted_mode->hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | | |
325 | (adjusted_mode->vdisplay << DVO_SRCDIM_VERTICAL_SHIFT)); | |
326 | /*I915_WRITE(DVOB, dvo_val);*/ | |
327 | I915_WRITE(dvo_reg, dvo_val); | |
328 | } | |
329 | ||
330 | /** | |
331 | * Detect the output connection on our DVO device. | |
332 | * | |
333 | * Unimplemented. | |
334 | */ | |
7b334fcb | 335 | static enum drm_connector_status |
930a9e28 | 336 | intel_dvo_detect(struct drm_connector *connector, bool force) |
79e53945 | 337 | { |
df0e9248 | 338 | struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
164c8598 CW |
339 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
340 | connector->base.id, drm_get_connector_name(connector)); | |
ea5b213a | 341 | return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev); |
79e53945 JB |
342 | } |
343 | ||
344 | static int intel_dvo_get_modes(struct drm_connector *connector) | |
345 | { | |
df0e9248 | 346 | struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
f899fc64 | 347 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
79e53945 JB |
348 | |
349 | /* We should probably have an i2c driver get_modes function for those | |
350 | * devices which will have a fixed set of modes determined by the chip | |
351 | * (TV-out, for example), but for now with just TMDS and LVDS, | |
352 | * that's not the case. | |
353 | */ | |
f899fc64 | 354 | intel_ddc_get_modes(connector, |
3bd7d909 | 355 | intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPC)); |
79e53945 JB |
356 | if (!list_empty(&connector->probed_modes)) |
357 | return 1; | |
358 | ||
ea5b213a | 359 | if (intel_dvo->panel_fixed_mode != NULL) { |
79e53945 | 360 | struct drm_display_mode *mode; |
ea5b213a | 361 | mode = drm_mode_duplicate(connector->dev, intel_dvo->panel_fixed_mode); |
79e53945 JB |
362 | if (mode) { |
363 | drm_mode_probed_add(connector, mode); | |
364 | return 1; | |
365 | } | |
366 | } | |
ea5b213a | 367 | |
79e53945 JB |
368 | return 0; |
369 | } | |
370 | ||
ea5b213a | 371 | static void intel_dvo_destroy(struct drm_connector *connector) |
79e53945 | 372 | { |
79e53945 JB |
373 | drm_sysfs_connector_remove(connector); |
374 | drm_connector_cleanup(connector); | |
599be16c | 375 | kfree(connector); |
79e53945 | 376 | } |
79e53945 | 377 | |
79e53945 | 378 | static const struct drm_connector_funcs intel_dvo_connector_funcs = { |
b2cabb0e | 379 | .dpms = intel_dvo_dpms, |
79e53945 JB |
380 | .detect = intel_dvo_detect, |
381 | .destroy = intel_dvo_destroy, | |
382 | .fill_modes = drm_helper_probe_single_connector_modes, | |
383 | }; | |
384 | ||
385 | static const struct drm_connector_helper_funcs intel_dvo_connector_helper_funcs = { | |
386 | .mode_valid = intel_dvo_mode_valid, | |
387 | .get_modes = intel_dvo_get_modes, | |
df0e9248 | 388 | .best_encoder = intel_best_encoder, |
79e53945 JB |
389 | }; |
390 | ||
b358d0a6 | 391 | static void intel_dvo_enc_destroy(struct drm_encoder *encoder) |
79e53945 | 392 | { |
69438e64 | 393 | struct intel_dvo *intel_dvo = enc_to_dvo(to_intel_encoder(encoder)); |
ea5b213a CW |
394 | |
395 | if (intel_dvo->dev.dev_ops->destroy) | |
396 | intel_dvo->dev.dev_ops->destroy(&intel_dvo->dev); | |
397 | ||
398 | kfree(intel_dvo->panel_fixed_mode); | |
399 | ||
400 | intel_encoder_destroy(encoder); | |
79e53945 JB |
401 | } |
402 | ||
403 | static const struct drm_encoder_funcs intel_dvo_enc_funcs = { | |
404 | .destroy = intel_dvo_enc_destroy, | |
405 | }; | |
406 | ||
79e53945 JB |
407 | /** |
408 | * Attempts to get a fixed panel timing for LVDS (currently only the i830). | |
409 | * | |
410 | * Other chips with DVO LVDS will need to extend this to deal with the LVDS | |
411 | * chip being on DVOB/C and having multiple pipes. | |
412 | */ | |
413 | static struct drm_display_mode * | |
ea5b213a | 414 | intel_dvo_get_current_mode(struct drm_connector *connector) |
79e53945 JB |
415 | { |
416 | struct drm_device *dev = connector->dev; | |
417 | struct drm_i915_private *dev_priv = dev->dev_private; | |
df0e9248 | 418 | struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
ea5b213a | 419 | uint32_t dvo_val = I915_READ(intel_dvo->dev.dvo_reg); |
79e53945 JB |
420 | struct drm_display_mode *mode = NULL; |
421 | ||
422 | /* If the DVO port is active, that'll be the LVDS, so we can pull out | |
423 | * its timings to get how the BIOS set up the panel. | |
424 | */ | |
425 | if (dvo_val & DVO_ENABLE) { | |
426 | struct drm_crtc *crtc; | |
427 | int pipe = (dvo_val & DVO_PIPE_B_SELECT) ? 1 : 0; | |
428 | ||
f875c15a | 429 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
79e53945 JB |
430 | if (crtc) { |
431 | mode = intel_crtc_mode_get(dev, crtc); | |
79e53945 JB |
432 | if (mode) { |
433 | mode->type |= DRM_MODE_TYPE_PREFERRED; | |
434 | if (dvo_val & DVO_HSYNC_ACTIVE_HIGH) | |
435 | mode->flags |= DRM_MODE_FLAG_PHSYNC; | |
436 | if (dvo_val & DVO_VSYNC_ACTIVE_HIGH) | |
437 | mode->flags |= DRM_MODE_FLAG_PVSYNC; | |
438 | } | |
439 | } | |
440 | } | |
ea5b213a | 441 | |
79e53945 JB |
442 | return mode; |
443 | } | |
444 | ||
445 | void intel_dvo_init(struct drm_device *dev) | |
446 | { | |
f899fc64 | 447 | struct drm_i915_private *dev_priv = dev->dev_private; |
21d40d37 | 448 | struct intel_encoder *intel_encoder; |
ea5b213a | 449 | struct intel_dvo *intel_dvo; |
599be16c | 450 | struct intel_connector *intel_connector; |
79e53945 | 451 | int i; |
79e53945 | 452 | int encoder_type = DRM_MODE_ENCODER_NONE; |
ea5b213a CW |
453 | |
454 | intel_dvo = kzalloc(sizeof(struct intel_dvo), GFP_KERNEL); | |
455 | if (!intel_dvo) | |
79e53945 JB |
456 | return; |
457 | ||
599be16c ZW |
458 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
459 | if (!intel_connector) { | |
ea5b213a | 460 | kfree(intel_dvo); |
599be16c ZW |
461 | return; |
462 | } | |
463 | ||
ea5b213a | 464 | intel_encoder = &intel_dvo->base; |
373a3cf7 CW |
465 | drm_encoder_init(dev, &intel_encoder->base, |
466 | &intel_dvo_enc_funcs, encoder_type); | |
ea5b213a | 467 | |
19c63fa8 DV |
468 | intel_encoder->disable = intel_disable_dvo; |
469 | intel_encoder->enable = intel_enable_dvo; | |
732ce74f | 470 | intel_encoder->get_hw_state = intel_dvo_get_hw_state; |
045ac3b5 | 471 | intel_encoder->get_config = intel_dvo_get_config; |
a3470375 | 472 | intel_encoder->compute_config = intel_dvo_compute_config; |
79fde301 | 473 | intel_encoder->mode_set = intel_dvo_mode_set; |
732ce74f | 474 | intel_connector->get_hw_state = intel_dvo_connector_get_hw_state; |
19c63fa8 | 475 | |
79e53945 JB |
476 | /* Now, try to find a controller */ |
477 | for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) { | |
599be16c | 478 | struct drm_connector *connector = &intel_connector->base; |
ea5b213a | 479 | const struct intel_dvo_device *dvo = &intel_dvo_devices[i]; |
f899fc64 | 480 | struct i2c_adapter *i2c; |
79e53945 | 481 | int gpio; |
e4bfff54 | 482 | bool dvoinit; |
79e53945 | 483 | |
79e53945 JB |
484 | /* Allow the I2C driver info to specify the GPIO to be used in |
485 | * special cases, but otherwise default to what's defined | |
486 | * in the spec. | |
487 | */ | |
3bd7d909 | 488 | if (intel_gmbus_is_port_valid(dvo->gpio)) |
79e53945 JB |
489 | gpio = dvo->gpio; |
490 | else if (dvo->type == INTEL_DVO_CHIP_LVDS) | |
f573c660 | 491 | gpio = GMBUS_PORT_SSC; |
79e53945 | 492 | else |
a6b17b43 | 493 | gpio = GMBUS_PORT_DPB; |
79e53945 JB |
494 | |
495 | /* Set up the I2C bus necessary for the chip we're probing. | |
496 | * It appears that everything is on GPIOE except for panels | |
497 | * on i830 laptops, which are on GPIOB (DVOA). | |
498 | */ | |
3bd7d909 | 499 | i2c = intel_gmbus_get_adapter(dev_priv, gpio); |
79e53945 | 500 | |
ea5b213a | 501 | intel_dvo->dev = *dvo; |
e4bfff54 DMEA |
502 | |
503 | /* GMBUS NAK handling seems to be unstable, hence let the | |
504 | * transmitter detection run in bit banging mode for now. | |
505 | */ | |
506 | intel_gmbus_force_bit(i2c, true); | |
507 | ||
508 | dvoinit = dvo->dev_ops->init(&intel_dvo->dev, i2c); | |
509 | ||
510 | intel_gmbus_force_bit(i2c, false); | |
511 | ||
512 | if (!dvoinit) | |
79e53945 JB |
513 | continue; |
514 | ||
21d40d37 EA |
515 | intel_encoder->type = INTEL_OUTPUT_DVO; |
516 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
79e53945 JB |
517 | switch (dvo->type) { |
518 | case INTEL_DVO_CHIP_TMDS: | |
66a9278e | 519 | intel_encoder->cloneable = true; |
79e53945 JB |
520 | drm_connector_init(dev, connector, |
521 | &intel_dvo_connector_funcs, | |
522 | DRM_MODE_CONNECTOR_DVII); | |
523 | encoder_type = DRM_MODE_ENCODER_TMDS; | |
524 | break; | |
525 | case INTEL_DVO_CHIP_LVDS: | |
66a9278e | 526 | intel_encoder->cloneable = false; |
79e53945 JB |
527 | drm_connector_init(dev, connector, |
528 | &intel_dvo_connector_funcs, | |
529 | DRM_MODE_CONNECTOR_LVDS); | |
530 | encoder_type = DRM_MODE_ENCODER_LVDS; | |
531 | break; | |
532 | } | |
533 | ||
534 | drm_connector_helper_add(connector, | |
535 | &intel_dvo_connector_helper_funcs); | |
536 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
537 | connector->interlace_allowed = false; | |
538 | connector->doublescan_allowed = false; | |
539 | ||
df0e9248 | 540 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
79e53945 JB |
541 | if (dvo->type == INTEL_DVO_CHIP_LVDS) { |
542 | /* For our LVDS chipsets, we should hopefully be able | |
543 | * to dig the fixed panel mode out of the BIOS data. | |
544 | * However, it's in a different format from the BIOS | |
545 | * data on chipsets with integrated LVDS (stored in AIM | |
546 | * headers, likely), so for now, just get the current | |
547 | * mode being output through DVO. | |
548 | */ | |
ea5b213a | 549 | intel_dvo->panel_fixed_mode = |
79e53945 | 550 | intel_dvo_get_current_mode(connector); |
ea5b213a | 551 | intel_dvo->panel_wants_dither = true; |
79e53945 JB |
552 | } |
553 | ||
554 | drm_sysfs_connector_add(connector); | |
555 | return; | |
556 | } | |
557 | ||
373a3cf7 | 558 | drm_encoder_cleanup(&intel_encoder->base); |
ea5b213a | 559 | kfree(intel_dvo); |
599be16c | 560 | kfree(intel_connector); |
79e53945 | 561 | } |