[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dvo.c

/*
 * Copyright 2006 Dave Airlie <airlied@linux.ie>
 * Copyright © 2006-2007 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 */
#include <linux/i2c.h>
#include <linux/slab.h>
#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include "intel_drv.h"
#include <drm/i915_drm.h>
#include "i915_drv.h"
#include "dvo.h"

#define SIL164_ADDR	0x38
#define CH7xxx_ADDR	0x76
#define TFP410_ADDR	0x38
#define NS2501_ADDR     0x38

static const struct intel_dvo_device intel_dvo_devices[] = {
	{
		.type = INTEL_DVO_CHIP_TMDS,
		.name = "sil164",
		.dvo_reg = DVOC,
		.slave_addr = SIL164_ADDR,
		.dev_ops = &sil164_ops,
	},
	{
		.type = INTEL_DVO_CHIP_TMDS,
		.name = "ch7xxx",
		.dvo_reg = DVOC,
		.slave_addr = CH7xxx_ADDR,
		.dev_ops = &ch7xxx_ops,
	},
	{
		.type = INTEL_DVO_CHIP_TMDS,
		.name = "ch7xxx",
		.dvo_reg = DVOC,
		.slave_addr = 0x75, /* For some ch7010 */
		.dev_ops = &ch7xxx_ops,
	},
	{
		.type = INTEL_DVO_CHIP_LVDS,
		.name = "ivch",
		.dvo_reg = DVOA,
		.slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */
		.dev_ops = &ivch_ops,
	},
	{
		.type = INTEL_DVO_CHIP_TMDS,
		.name = "tfp410",
		.dvo_reg = DVOC,
		.slave_addr = TFP410_ADDR,
		.dev_ops = &tfp410_ops,
	},
	{
		.type = INTEL_DVO_CHIP_LVDS,
		.name = "ch7017",
		.dvo_reg = DVOC,
		.slave_addr = 0x75,
		.gpio = GMBUS_PORT_DPB,
		.dev_ops = &ch7017_ops,
	},
	{
	        .type = INTEL_DVO_CHIP_TMDS,
		.name = "ns2501",
		.dvo_reg = DVOC,
		.slave_addr = NS2501_ADDR,
		.dev_ops = &ns2501_ops,
       }
};

struct intel_dvo {
	struct intel_encoder base;

	struct intel_dvo_device dev;

	struct drm_display_mode *panel_fixed_mode;
	bool panel_wants_dither;
};

static struct intel_dvo *enc_to_dvo(struct intel_encoder *encoder)
{
	return container_of(encoder, struct intel_dvo, base);
}

static struct intel_dvo *intel_attached_dvo(struct drm_connector *connector)
{
	return enc_to_dvo(intel_attached_encoder(connector));
}

static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector)
{
	struct intel_dvo *intel_dvo = intel_attached_dvo(&connector->base);

	return intel_dvo->dev.dev_ops->get_hw_state(&intel_dvo->dev);
}

static bool intel_dvo_get_hw_state(struct intel_encoder *encoder,
				   enum pipe *pipe)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
	u32 tmp;

	tmp = I915_READ(intel_dvo->dev.dvo_reg);

	if (!(tmp & DVO_ENABLE))
		return false;

	*pipe = PORT_TO_PIPE(tmp);

	return true;
}

static void intel_dvo_get_config(struct intel_encoder *encoder,
				 struct intel_crtc_config *pipe_config)
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
	u32 tmp, flags = 0;

	tmp = I915_READ(intel_dvo->dev.dvo_reg);
	if (tmp & DVO_HSYNC_ACTIVE_HIGH)
		flags |= DRM_MODE_FLAG_PHSYNC;
	else
		flags |= DRM_MODE_FLAG_NHSYNC;
	if (tmp & DVO_VSYNC_ACTIVE_HIGH)
		flags |= DRM_MODE_FLAG_PVSYNC;
	else
		flags |= DRM_MODE_FLAG_NVSYNC;

	pipe_config->adjusted_mode.flags |= flags;

	pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
}

static void intel_disable_dvo(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
	u32 dvo_reg = intel_dvo->dev.dvo_reg;
	u32 temp = I915_READ(dvo_reg);

	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);
	I915_WRITE(dvo_reg, temp & ~DVO_ENABLE);
	I915_READ(dvo_reg);
}

static void intel_enable_dvo(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
	u32 dvo_reg = intel_dvo->dev.dvo_reg;
	u32 temp = I915_READ(dvo_reg);

	I915_WRITE(dvo_reg, temp | DVO_ENABLE);
	I915_READ(dvo_reg);
	intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
					 &crtc->config.requested_mode,
					 &crtc->config.adjusted_mode);

	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true);
}

/* Special dpms function to support cloning between dvo/sdvo/crt. */
static void intel_dvo_dpms(struct drm_connector *connector, int mode)
{
	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
	struct drm_crtc *crtc;
	struct intel_crtc_config *config;

	/* dvo supports only 2 dpms states. */
	if (mode != DRM_MODE_DPMS_ON)
		mode = DRM_MODE_DPMS_OFF;

	if (mode == connector->dpms)
		return;

	connector->dpms = mode;

	/* Only need to change hw state when actually enabled */
	crtc = intel_dvo->base.base.crtc;
	if (!crtc) {
		intel_dvo->base.connectors_active = false;
		return;
	}

	/* We call connector dpms manually below in case pipe dpms doesn't
	 * change due to cloning. */
	if (mode == DRM_MODE_DPMS_ON) {
		config = &to_intel_crtc(crtc)->config;

		intel_dvo->base.connectors_active = true;

		intel_crtc_update_dpms(crtc);

		intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
						 &config->requested_mode,
						 &config->adjusted_mode);

		intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true);
	} else {
		intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);

		intel_dvo->base.connectors_active = false;

		intel_crtc_update_dpms(crtc);
	}

	intel_modeset_check_state(connector->dev);
}

static enum drm_mode_status
intel_dvo_mode_valid(struct drm_connector *connector,
		     struct drm_display_mode *mode)
{
	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);

	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		return MODE_NO_DBLESCAN;

	/* XXX: Validate clock range */

	if (intel_dvo->panel_fixed_mode) {
		if (mode->hdisplay > intel_dvo->panel_fixed_mode->hdisplay)
			return MODE_PANEL;
		if (mode->vdisplay > intel_dvo->panel_fixed_mode->vdisplay)
			return MODE_PANEL;
	}

	return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode);
}

static bool intel_dvo_compute_config(struct intel_encoder *encoder,
				     struct intel_crtc_config *pipe_config)
{
	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;

	/* If we have timings from the BIOS for the panel, put them in
	 * to the adjusted mode.  The CRTC will be set up for this mode,
	 * with the panel scaling set up to source from the H/VDisplay
	 * of the original mode.
	 */
	if (intel_dvo->panel_fixed_mode != NULL) {
#define C(x) adjusted_mode->x = intel_dvo->panel_fixed_mode->x
		C(hdisplay);
		C(hsync_start);
		C(hsync_end);
		C(htotal);
		C(vdisplay);
		C(vsync_start);
		C(vsync_end);
		C(vtotal);
		C(clock);
#undef C

		drm_mode_set_crtcinfo(adjusted_mode, 0);
	}

	return true;
}

static void intel_dvo_pre_enable(struct intel_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
	struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
	int pipe = crtc->pipe;
	u32 dvo_val;
	u32 dvo_reg = intel_dvo->dev.dvo_reg, dvo_srcdim_reg;

	switch (dvo_reg) {
	case DVOA:
	default:
		dvo_srcdim_reg = DVOA_SRCDIM;
		break;
	case DVOB:
		dvo_srcdim_reg = DVOB_SRCDIM;
		break;
	case DVOC:
		dvo_srcdim_reg = DVOC_SRCDIM;
		break;
	}

	/* Save the data order, since I don't know what it should be set to. */
	dvo_val = I915_READ(dvo_reg) &
		  (DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG);
	dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE |
		   DVO_BLANK_ACTIVE_HIGH;

	if (pipe == 1)
		dvo_val |= DVO_PIPE_B_SELECT;
	dvo_val |= DVO_PIPE_STALL;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
		dvo_val |= DVO_HSYNC_ACTIVE_HIGH;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
		dvo_val |= DVO_VSYNC_ACTIVE_HIGH;

	/*I915_WRITE(DVOB_SRCDIM,
	  (adjusted_mode->hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) |
	  (adjusted_mode->VDisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/
	I915_WRITE(dvo_srcdim_reg,
		   (adjusted_mode->hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) |
		   (adjusted_mode->vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));
	/*I915_WRITE(DVOB, dvo_val);*/
	I915_WRITE(dvo_reg, dvo_val);
}

/**
 * Detect the output connection on our DVO device.
 *
 * Unimplemented.
 */
static enum drm_connector_status
intel_dvo_detect(struct drm_connector *connector, bool force)
{
	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		      connector->base.id, drm_get_connector_name(connector));
	return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev);
}

static int intel_dvo_get_modes(struct drm_connector *connector)
{
	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
	struct drm_i915_private *dev_priv = connector->dev->dev_private;

	/* We should probably have an i2c driver get_modes function for those
	 * devices which will have a fixed set of modes determined by the chip
	 * (TV-out, for example), but for now with just TMDS and LVDS,
	 * that's not the case.
	 */
	intel_ddc_get_modes(connector,
			    intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPC));
	if (!list_empty(&connector->probed_modes))
		return 1;

	if (intel_dvo->panel_fixed_mode != NULL) {
		struct drm_display_mode *mode;
		mode = drm_mode_duplicate(connector->dev, intel_dvo->panel_fixed_mode);
		if (mode) {
			drm_mode_probed_add(connector, mode);
			return 1;
		}
	}

	return 0;
}

static void intel_dvo_destroy(struct drm_connector *connector)
{
	drm_connector_cleanup(connector);
	kfree(connector);
}

static const struct drm_connector_funcs intel_dvo_connector_funcs = {
	.dpms = intel_dvo_dpms,
	.detect = intel_dvo_detect,
	.destroy = intel_dvo_destroy,
	.fill_modes = drm_helper_probe_single_connector_modes,
};

static const struct drm_connector_helper_funcs intel_dvo_connector_helper_funcs = {
	.mode_valid = intel_dvo_mode_valid,
	.get_modes = intel_dvo_get_modes,
	.best_encoder = intel_best_encoder,
};

static void intel_dvo_enc_destroy(struct drm_encoder *encoder)
{
	struct intel_dvo *intel_dvo = enc_to_dvo(to_intel_encoder(encoder));

	if (intel_dvo->dev.dev_ops->destroy)
		intel_dvo->dev.dev_ops->destroy(&intel_dvo->dev);

	kfree(intel_dvo->panel_fixed_mode);

	intel_encoder_destroy(encoder);
}

static const struct drm_encoder_funcs intel_dvo_enc_funcs = {
	.destroy = intel_dvo_enc_destroy,
};

/**
 * Attempts to get a fixed panel timing for LVDS (currently only the i830).
 *
 * Other chips with DVO LVDS will need to extend this to deal with the LVDS
 * chip being on DVOB/C and having multiple pipes.
 */
static struct drm_display_mode *
intel_dvo_get_current_mode(struct drm_connector *connector)
{
	struct drm_device *dev = connector->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
	uint32_t dvo_val = I915_READ(intel_dvo->dev.dvo_reg);
	struct drm_display_mode *mode = NULL;

	/* If the DVO port is active, that'll be the LVDS, so we can pull out
	 * its timings to get how the BIOS set up the panel.
	 */
	if (dvo_val & DVO_ENABLE) {
		struct drm_crtc *crtc;
		int pipe = (dvo_val & DVO_PIPE_B_SELECT) ? 1 : 0;

		crtc = intel_get_crtc_for_pipe(dev, pipe);
		if (crtc) {
			mode = intel_crtc_mode_get(dev, crtc);
			if (mode) {
				mode->type |= DRM_MODE_TYPE_PREFERRED;
				if (dvo_val & DVO_HSYNC_ACTIVE_HIGH)
					mode->flags |= DRM_MODE_FLAG_PHSYNC;
				if (dvo_val & DVO_VSYNC_ACTIVE_HIGH)
					mode->flags |= DRM_MODE_FLAG_PVSYNC;
			}
		}
	}

	return mode;
}

void intel_dvo_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *intel_encoder;
	struct intel_dvo *intel_dvo;
	struct intel_connector *intel_connector;
	int i;
	int encoder_type = DRM_MODE_ENCODER_NONE;

	intel_dvo = kzalloc(sizeof(*intel_dvo), GFP_KERNEL);
	if (!intel_dvo)
		return;

	intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
	if (!intel_connector) {
		kfree(intel_dvo);
		return;
	}

	intel_encoder = &intel_dvo->base;
	drm_encoder_init(dev, &intel_encoder->base,
			 &intel_dvo_enc_funcs, encoder_type);

	intel_encoder->disable = intel_disable_dvo;
	intel_encoder->enable = intel_enable_dvo;
	intel_encoder->get_hw_state = intel_dvo_get_hw_state;
	intel_encoder->get_config = intel_dvo_get_config;
	intel_encoder->compute_config = intel_dvo_compute_config;
	intel_encoder->pre_enable = intel_dvo_pre_enable;
	intel_connector->get_hw_state = intel_dvo_connector_get_hw_state;
	intel_connector->unregister = intel_connector_unregister;

	/* Now, try to find a controller */
	for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) {
		struct drm_connector *connector = &intel_connector->base;
		const struct intel_dvo_device *dvo = &intel_dvo_devices[i];
		struct i2c_adapter *i2c;
		int gpio;
		bool dvoinit;

		/* Allow the I2C driver info to specify the GPIO to be used in
		 * special cases, but otherwise default to what's defined
		 * in the spec.
		 */
		if (intel_gmbus_is_port_valid(dvo->gpio))
			gpio = dvo->gpio;
		else if (dvo->type == INTEL_DVO_CHIP_LVDS)
			gpio = GMBUS_PORT_SSC;
		else
			gpio = GMBUS_PORT_DPB;

		/* Set up the I2C bus necessary for the chip we're probing.
		 * It appears that everything is on GPIOE except for panels
		 * on i830 laptops, which are on GPIOB (DVOA).
		 */
		i2c = intel_gmbus_get_adapter(dev_priv, gpio);

		intel_dvo->dev = *dvo;

		/* GMBUS NAK handling seems to be unstable, hence let the
		 * transmitter detection run in bit banging mode for now.
		 */
		intel_gmbus_force_bit(i2c, true);

		dvoinit = dvo->dev_ops->init(&intel_dvo->dev, i2c);

		intel_gmbus_force_bit(i2c, false);

		if (!dvoinit)
			continue;

		intel_encoder->type = INTEL_OUTPUT_DVO;
		intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
		switch (dvo->type) {
		case INTEL_DVO_CHIP_TMDS:
			intel_encoder->cloneable = (1 << INTEL_OUTPUT_ANALOG) |
				(1 << INTEL_OUTPUT_DVO);
			drm_connector_init(dev, connector,
					   &intel_dvo_connector_funcs,
					   DRM_MODE_CONNECTOR_DVII);
			encoder_type = DRM_MODE_ENCODER_TMDS;
			break;
		case INTEL_DVO_CHIP_LVDS:
			intel_encoder->cloneable = 0;
			drm_connector_init(dev, connector,
					   &intel_dvo_connector_funcs,
					   DRM_MODE_CONNECTOR_LVDS);
			encoder_type = DRM_MODE_ENCODER_LVDS;
			break;
		}

		drm_connector_helper_add(connector,
					 &intel_dvo_connector_helper_funcs);
		connector->display_info.subpixel_order = SubPixelHorizontalRGB;
		connector->interlace_allowed = false;
		connector->doublescan_allowed = false;

		intel_connector_attach_encoder(intel_connector, intel_encoder);
		if (dvo->type == INTEL_DVO_CHIP_LVDS) {
			/* For our LVDS chipsets, we should hopefully be able
			 * to dig the fixed panel mode out of the BIOS data.
			 * However, it's in a different format from the BIOS
			 * data on chipsets with integrated LVDS (stored in AIM
			 * headers, likely), so for now, just get the current
			 * mode being output through DVO.
			 */
			intel_dvo->panel_fixed_mode =
				intel_dvo_get_current_mode(connector);
			intel_dvo->panel_wants_dither = true;
		}

		drm_sysfs_connector_add(connector);
		return;
	}

	drm_encoder_cleanup(&intel_encoder->base);
	kfree(intel_dvo);
	kfree(intel_connector);
}
Commit	Line	Data
79e53945 JB	1	/*
	2	* Copyright 2006 Dave Airlie <airlied@linux.ie>
	3	* Copyright © 2006-2007 Intel Corporation
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice (including the next
	13	* paragraph) shall be included in all copies or substantial portions of the
	14	* Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	21	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	22	* DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors:
	25	* Eric Anholt <eric@anholt.net>
	26	*/
	27	#include <linux/i2c.h>
5a0e3ad6	28	#include <linux/slab.h>
760285e7 DH	29	#include <drm/drmP.h>
760285e7 DH	30	#include <drm/drm_crtc.h>
79e53945	31	#include "intel_drv.h"
760285e7	32	#include <drm/i915_drm.h>
79e53945 JB	33	#include "i915_drv.h"
	34	#include "dvo.h"
	35
	36	#define SIL164_ADDR 0x38
	37	#define CH7xxx_ADDR 0x76
	38	#define TFP410_ADDR 0x38
7434a255	39	#define NS2501_ADDR 0x38
79e53945	40
ea5b213a	41	static const struct intel_dvo_device intel_dvo_devices[] = {
79e53945 JB	42	{
	43	.type = INTEL_DVO_CHIP_TMDS,
	44	.name = "sil164",
	45	.dvo_reg = DVOC,
	46	.slave_addr = SIL164_ADDR,
	47	.dev_ops = &sil164_ops,
	48	},
	49	{
	50	.type = INTEL_DVO_CHIP_TMDS,
	51	.name = "ch7xxx",
	52	.dvo_reg = DVOC,
	53	.slave_addr = CH7xxx_ADDR,
	54	.dev_ops = &ch7xxx_ops,
	55	},
98304ad1	56	{
	57	.type = INTEL_DVO_CHIP_TMDS,
	58	.name = "ch7xxx",
	59	.dvo_reg = DVOC,
	60	.slave_addr = 0x75, /* For some ch7010 */
	61	.dev_ops = &ch7xxx_ops,
	62	},
79e53945 JB	63	{
	64	.type = INTEL_DVO_CHIP_LVDS,
	65	.name = "ivch",
	66	.dvo_reg = DVOA,
	67	.slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */
	68	.dev_ops = &ivch_ops,
	69	},
	70	{
	71	.type = INTEL_DVO_CHIP_TMDS,
	72	.name = "tfp410",
	73	.dvo_reg = DVOC,
	74	.slave_addr = TFP410_ADDR,
	75	.dev_ops = &tfp410_ops,
	76	},
	77	{
	78	.type = INTEL_DVO_CHIP_LVDS,
	79	.name = "ch7017",
	80	.dvo_reg = DVOC,
	81	.slave_addr = 0x75,
a6b17b43	82	.gpio = GMBUS_PORT_DPB,
79e53945	83	.dev_ops = &ch7017_ops,
7434a255 TR	84	},
	85	{
	86	.type = INTEL_DVO_CHIP_TMDS,
	87	.name = "ns2501",
	88	.dvo_reg = DVOC,
	89	.slave_addr = NS2501_ADDR,
	90	.dev_ops = &ns2501_ops,
	91	}
79e53945 JB	92	};
79e53945 JB	93
ea5b213a CW	94	struct intel_dvo {
	95	struct intel_encoder base;
	96
	97	struct intel_dvo_device dev;
	98
	99	struct drm_display_mode *panel_fixed_mode;
	100	bool panel_wants_dither;
	101	};
	102
69438e64	103	static struct intel_dvo enc_to_dvo(struct intel_encoder encoder)
ea5b213a	104	{
69438e64	105	return container_of(encoder, struct intel_dvo, base);
ea5b213a CW	106	}
ea5b213a CW	107
df0e9248 CW	108	static struct intel_dvo intel_attached_dvo(struct drm_connector connector)
df0e9248 CW	109	{
79fde301	110	return enc_to_dvo(intel_attached_encoder(connector));
df0e9248 CW	111	}
df0e9248 CW	112
732ce74f	113	static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector)
79e53945	114	{
732ce74f DV	115	struct intel_dvo *intel_dvo = intel_attached_dvo(&connector->base);
	116
	117	return intel_dvo->dev.dev_ops->get_hw_state(&intel_dvo->dev);
	118	}
	119
	120	static bool intel_dvo_get_hw_state(struct intel_encoder *encoder,
	121	enum pipe *pipe)
	122	{
	123	struct drm_device *dev = encoder->base.dev;
	124	struct drm_i915_private *dev_priv = dev->dev_private;
69438e64	125	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
732ce74f DV	126	u32 tmp;
	127
	128	tmp = I915_READ(intel_dvo->dev.dvo_reg);
	129
	130	if (!(tmp & DVO_ENABLE))
	131	return false;
	132
	133	*pipe = PORT_TO_PIPE(tmp);
	134
	135	return true;
	136	}
	137
045ac3b5 JB	138	static void intel_dvo_get_config(struct intel_encoder *encoder,
	139	struct intel_crtc_config *pipe_config)
	140	{
	141	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
69438e64	142	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
045ac3b5 JB	143	u32 tmp, flags = 0;
	144
	145	tmp = I915_READ(intel_dvo->dev.dvo_reg);
	146	if (tmp & DVO_HSYNC_ACTIVE_HIGH)
	147	flags \|= DRM_MODE_FLAG_PHSYNC;
	148	else
	149	flags \|= DRM_MODE_FLAG_NHSYNC;
	150	if (tmp & DVO_VSYNC_ACTIVE_HIGH)
	151	flags \|= DRM_MODE_FLAG_PVSYNC;
	152	else
	153	flags \|= DRM_MODE_FLAG_NVSYNC;
	154
	155	pipe_config->adjusted_mode.flags \|= flags;
18442d08	156
241bfc38	157	pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
045ac3b5 JB	158	}
045ac3b5 JB	159
19c63fa8 DV	160	static void intel_disable_dvo(struct intel_encoder *encoder)
	161	{
	162	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
69438e64	163	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
19c63fa8 DV	164	u32 dvo_reg = intel_dvo->dev.dvo_reg;
	165	u32 temp = I915_READ(dvo_reg);
	166
	167	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);
	168	I915_WRITE(dvo_reg, temp & ~DVO_ENABLE);
	169	I915_READ(dvo_reg);
	170	}
	171
	172	static void intel_enable_dvo(struct intel_encoder *encoder)
	173	{
	174	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
69438e64	175	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
48f34e10	176	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
ea5b213a	177	u32 dvo_reg = intel_dvo->dev.dvo_reg;
79e53945 JB	178	u32 temp = I915_READ(dvo_reg);
79e53945 JB	179
19c63fa8 DV	180	I915_WRITE(dvo_reg, temp \| DVO_ENABLE);
19c63fa8 DV	181	I915_READ(dvo_reg);
48f34e10 DV	182	intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
	183	&crtc->config.requested_mode,
	184	&crtc->config.adjusted_mode);
	185
19c63fa8 DV	186	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true);
	187	}
	188
6b1c087b	189	/* Special dpms function to support cloning between dvo/sdvo/crt. */
b2cabb0e	190	static void intel_dvo_dpms(struct drm_connector *connector, int mode)
79e53945	191	{
b2cabb0e DV	192	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
b2cabb0e DV	193	struct drm_crtc *crtc;
48f34e10	194	struct intel_crtc_config *config;
b2cabb0e DV	195
	196	/* dvo supports only 2 dpms states. */
	197	if (mode != DRM_MODE_DPMS_ON)
	198	mode = DRM_MODE_DPMS_OFF;
	199
	200	if (mode == connector->dpms)
	201	return;
	202
	203	connector->dpms = mode;
	204
	205	/* Only need to change hw state when actually enabled */
	206	crtc = intel_dvo->base.base.crtc;
	207	if (!crtc) {
	208	intel_dvo->base.connectors_active = false;
	209	return;
	210	}
79e53945	211
6b1c087b JN	212	/* We call connector dpms manually below in case pipe dpms doesn't
6b1c087b JN	213	* change due to cloning. */
79e53945	214	if (mode == DRM_MODE_DPMS_ON) {
48f34e10 DV	215	config = &to_intel_crtc(crtc)->config;
48f34e10 DV	216
b2cabb0e DV	217	intel_dvo->base.connectors_active = true;
	218
	219	intel_crtc_update_dpms(crtc);
	220
48f34e10 DV	221	intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
	222	&config->requested_mode,
	223	&config->adjusted_mode);
	224
fac3274c	225	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true);
79e53945	226	} else {
fac3274c	227	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);
b2cabb0e DV	228
	229	intel_dvo->base.connectors_active = false;
	230
	231	intel_crtc_update_dpms(crtc);
79e53945	232	}
0a91ca29	233
b980514c	234	intel_modeset_check_state(connector->dev);
79e53945 JB	235	}
79e53945 JB	236
c19de8eb DL	237	static enum drm_mode_status
	238	intel_dvo_mode_valid(struct drm_connector *connector,
	239	struct drm_display_mode *mode)
79e53945	240	{
df0e9248	241	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
79e53945 JB	242
	243	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
	244	return MODE_NO_DBLESCAN;
	245
	246	/* XXX: Validate clock range */
	247
ea5b213a CW	248	if (intel_dvo->panel_fixed_mode) {
ea5b213a CW	249	if (mode->hdisplay > intel_dvo->panel_fixed_mode->hdisplay)
79e53945	250	return MODE_PANEL;
ea5b213a	251	if (mode->vdisplay > intel_dvo->panel_fixed_mode->vdisplay)
79e53945 JB	252	return MODE_PANEL;
	253	}
	254
ea5b213a	255	return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode);
79e53945 JB	256	}
79e53945 JB	257
a3470375 DV	258	static bool intel_dvo_compute_config(struct intel_encoder *encoder,
a3470375 DV	259	struct intel_crtc_config *pipe_config)
79e53945	260	{
a3470375 DV	261	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
a3470375 DV	262	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
79e53945 JB	263
	264	/* If we have timings from the BIOS for the panel, put them in
	265	* to the adjusted mode. The CRTC will be set up for this mode,
	266	* with the panel scaling set up to source from the H/VDisplay
	267	* of the original mode.
	268	*/
ea5b213a CW	269	if (intel_dvo->panel_fixed_mode != NULL) {
ea5b213a CW	270	#define C(x) adjusted_mode->x = intel_dvo->panel_fixed_mode->x
79e53945 JB	271	C(hdisplay);
	272	C(hsync_start);
	273	C(hsync_end);
	274	C(htotal);
	275	C(vdisplay);
	276	C(vsync_start);
	277	C(vsync_end);
	278	C(vtotal);
	279	C(clock);
79e53945	280	#undef C
0d971748 DV	281
0d971748 DV	282	drm_mode_set_crtcinfo(adjusted_mode, 0);
79e53945 JB	283	}
79e53945 JB	284
79e53945 JB	285	return true;
	286	}
	287
912b0e2d	288	static void intel_dvo_pre_enable(struct intel_encoder *encoder)
79e53945	289	{
79fde301	290	struct drm_device *dev = encoder->base.dev;
79e53945	291	struct drm_i915_private *dev_priv = dev->dev_private;
79fde301 DV	292	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
	293	struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
	294	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
	295	int pipe = crtc->pipe;
79e53945	296	u32 dvo_val;
ea5b213a	297	u32 dvo_reg = intel_dvo->dev.dvo_reg, dvo_srcdim_reg;
79e53945 JB	298
	299	switch (dvo_reg) {
	300	case DVOA:
	301	default:
	302	dvo_srcdim_reg = DVOA_SRCDIM;
	303	break;
	304	case DVOB:
	305	dvo_srcdim_reg = DVOB_SRCDIM;
	306	break;
	307	case DVOC:
	308	dvo_srcdim_reg = DVOC_SRCDIM;
	309	break;
	310	}
	311
79e53945 JB	312	/* Save the data order, since I don't know what it should be set to. */
	313	dvo_val = I915_READ(dvo_reg) &
	314	(DVO_PRESERVE_MASK \| DVO_DATA_ORDER_GBRG);
	315	dvo_val \|= DVO_DATA_ORDER_FP \| DVO_BORDER_ENABLE \|
	316	DVO_BLANK_ACTIVE_HIGH;
	317
	318	if (pipe == 1)
	319	dvo_val \|= DVO_PIPE_B_SELECT;
	320	dvo_val \|= DVO_PIPE_STALL;
	321	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
	322	dvo_val \|= DVO_HSYNC_ACTIVE_HIGH;
	323	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
	324	dvo_val \|= DVO_VSYNC_ACTIVE_HIGH;
	325
79e53945 JB	326	/*I915_WRITE(DVOB_SRCDIM,
	327	(adjusted_mode->hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) \|
	328	(adjusted_mode->VDisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/
	329	I915_WRITE(dvo_srcdim_reg,
	330	(adjusted_mode->hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) \|
	331	(adjusted_mode->vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));
	332	/I915_WRITE(DVOB, dvo_val);/
	333	I915_WRITE(dvo_reg, dvo_val);
	334	}
	335
	336	/**
	337	* Detect the output connection on our DVO device.
	338	*
	339	* Unimplemented.
	340	*/
7b334fcb	341	static enum drm_connector_status
930a9e28	342	intel_dvo_detect(struct drm_connector *connector, bool force)
79e53945	343	{
df0e9248	344	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
164c8598 CW	345	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
164c8598 CW	346	connector->base.id, drm_get_connector_name(connector));
ea5b213a	347	return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev);
79e53945 JB	348	}
	349
	350	static int intel_dvo_get_modes(struct drm_connector *connector)
	351	{
df0e9248	352	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
f899fc64	353	struct drm_i915_private *dev_priv = connector->dev->dev_private;
79e53945 JB	354
	355	/* We should probably have an i2c driver get_modes function for those
	356	* devices which will have a fixed set of modes determined by the chip
	357	* (TV-out, for example), but for now with just TMDS and LVDS,
	358	* that's not the case.
	359	*/
f899fc64	360	intel_ddc_get_modes(connector,
3bd7d909	361	intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPC));
79e53945 JB	362	if (!list_empty(&connector->probed_modes))
	363	return 1;
	364
ea5b213a	365	if (intel_dvo->panel_fixed_mode != NULL) {
79e53945	366	struct drm_display_mode *mode;
ea5b213a	367	mode = drm_mode_duplicate(connector->dev, intel_dvo->panel_fixed_mode);
79e53945 JB	368	if (mode) {
	369	drm_mode_probed_add(connector, mode);
	370	return 1;
	371	}
	372	}
ea5b213a	373
79e53945 JB	374	return 0;
	375	}
	376
ea5b213a	377	static void intel_dvo_destroy(struct drm_connector *connector)
79e53945	378	{
79e53945	379	drm_connector_cleanup(connector);
599be16c	380	kfree(connector);
79e53945	381	}
79e53945	382
79e53945	383	static const struct drm_connector_funcs intel_dvo_connector_funcs = {
b2cabb0e	384	.dpms = intel_dvo_dpms,
79e53945 JB	385	.detect = intel_dvo_detect,
	386	.destroy = intel_dvo_destroy,
	387	.fill_modes = drm_helper_probe_single_connector_modes,
	388	};
	389
	390	static const struct drm_connector_helper_funcs intel_dvo_connector_helper_funcs = {
	391	.mode_valid = intel_dvo_mode_valid,
	392	.get_modes = intel_dvo_get_modes,
df0e9248	393	.best_encoder = intel_best_encoder,
79e53945 JB	394	};
79e53945 JB	395
b358d0a6	396	static void intel_dvo_enc_destroy(struct drm_encoder *encoder)
79e53945	397	{
69438e64	398	struct intel_dvo *intel_dvo = enc_to_dvo(to_intel_encoder(encoder));
ea5b213a CW	399
	400	if (intel_dvo->dev.dev_ops->destroy)
	401	intel_dvo->dev.dev_ops->destroy(&intel_dvo->dev);
	402
	403	kfree(intel_dvo->panel_fixed_mode);
	404
	405	intel_encoder_destroy(encoder);
79e53945 JB	406	}
	407
	408	static const struct drm_encoder_funcs intel_dvo_enc_funcs = {
	409	.destroy = intel_dvo_enc_destroy,
	410	};
	411
79e53945 JB	412	/**
	413	* Attempts to get a fixed panel timing for LVDS (currently only the i830).
	414	*
	415	* Other chips with DVO LVDS will need to extend this to deal with the LVDS
	416	* chip being on DVOB/C and having multiple pipes.
	417	*/
	418	static struct drm_display_mode *
ea5b213a	419	intel_dvo_get_current_mode(struct drm_connector *connector)
79e53945 JB	420	{
	421	struct drm_device *dev = connector->dev;
	422	struct drm_i915_private *dev_priv = dev->dev_private;
df0e9248	423	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
ea5b213a	424	uint32_t dvo_val = I915_READ(intel_dvo->dev.dvo_reg);
79e53945 JB	425	struct drm_display_mode *mode = NULL;
	426
	427	/* If the DVO port is active, that'll be the LVDS, so we can pull out
	428	* its timings to get how the BIOS set up the panel.
	429	*/
	430	if (dvo_val & DVO_ENABLE) {
	431	struct drm_crtc *crtc;
	432	int pipe = (dvo_val & DVO_PIPE_B_SELECT) ? 1 : 0;
	433
f875c15a	434	crtc = intel_get_crtc_for_pipe(dev, pipe);
79e53945 JB	435	if (crtc) {
79e53945 JB	436	mode = intel_crtc_mode_get(dev, crtc);
79e53945 JB	437	if (mode) {
	438	mode->type \|= DRM_MODE_TYPE_PREFERRED;
	439	if (dvo_val & DVO_HSYNC_ACTIVE_HIGH)
	440	mode->flags \|= DRM_MODE_FLAG_PHSYNC;
	441	if (dvo_val & DVO_VSYNC_ACTIVE_HIGH)
	442	mode->flags \|= DRM_MODE_FLAG_PVSYNC;
	443	}
	444	}
	445	}
ea5b213a	446
79e53945 JB	447	return mode;
	448	}
	449
	450	void intel_dvo_init(struct drm_device *dev)
	451	{
f899fc64	452	struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37	453	struct intel_encoder *intel_encoder;
ea5b213a	454	struct intel_dvo *intel_dvo;
599be16c	455	struct intel_connector *intel_connector;
79e53945	456	int i;
79e53945	457	int encoder_type = DRM_MODE_ENCODER_NONE;
ea5b213a	458
b14c5679	459	intel_dvo = kzalloc(sizeof(*intel_dvo), GFP_KERNEL);
ea5b213a	460	if (!intel_dvo)
79e53945 JB	461	return;
79e53945 JB	462
b14c5679	463	intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
599be16c	464	if (!intel_connector) {
ea5b213a	465	kfree(intel_dvo);
599be16c ZW	466	return;
	467	}
	468
ea5b213a	469	intel_encoder = &intel_dvo->base;
373a3cf7 CW	470	drm_encoder_init(dev, &intel_encoder->base,
373a3cf7 CW	471	&intel_dvo_enc_funcs, encoder_type);
ea5b213a	472
19c63fa8 DV	473	intel_encoder->disable = intel_disable_dvo;
19c63fa8 DV	474	intel_encoder->enable = intel_enable_dvo;
732ce74f	475	intel_encoder->get_hw_state = intel_dvo_get_hw_state;
045ac3b5	476	intel_encoder->get_config = intel_dvo_get_config;
a3470375	477	intel_encoder->compute_config = intel_dvo_compute_config;
912b0e2d	478	intel_encoder->pre_enable = intel_dvo_pre_enable;
732ce74f	479	intel_connector->get_hw_state = intel_dvo_connector_get_hw_state;
4932e2c3	480	intel_connector->unregister = intel_connector_unregister;
19c63fa8	481
79e53945 JB	482	/* Now, try to find a controller */
79e53945 JB	483	for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) {
599be16c	484	struct drm_connector *connector = &intel_connector->base;
ea5b213a	485	const struct intel_dvo_device *dvo = &intel_dvo_devices[i];
f899fc64	486	struct i2c_adapter *i2c;
79e53945	487	int gpio;
e4bfff54	488	bool dvoinit;
79e53945	489
79e53945 JB	490	/* Allow the I2C driver info to specify the GPIO to be used in
	491	* special cases, but otherwise default to what's defined
	492	* in the spec.
	493	*/
3bd7d909	494	if (intel_gmbus_is_port_valid(dvo->gpio))
79e53945 JB	495	gpio = dvo->gpio;
79e53945 JB	496	else if (dvo->type == INTEL_DVO_CHIP_LVDS)
f573c660	497	gpio = GMBUS_PORT_SSC;
79e53945	498	else
a6b17b43	499	gpio = GMBUS_PORT_DPB;
79e53945 JB	500
	501	/* Set up the I2C bus necessary for the chip we're probing.
	502	* It appears that everything is on GPIOE except for panels
	503	* on i830 laptops, which are on GPIOB (DVOA).
	504	*/
3bd7d909	505	i2c = intel_gmbus_get_adapter(dev_priv, gpio);
79e53945	506
ea5b213a	507	intel_dvo->dev = *dvo;
e4bfff54 DMEA	508
	509	/* GMBUS NAK handling seems to be unstable, hence let the
	510	* transmitter detection run in bit banging mode for now.
	511	*/
	512	intel_gmbus_force_bit(i2c, true);
	513
	514	dvoinit = dvo->dev_ops->init(&intel_dvo->dev, i2c);
	515
	516	intel_gmbus_force_bit(i2c, false);
	517
	518	if (!dvoinit)
79e53945 JB	519	continue;
79e53945 JB	520
21d40d37 EA	521	intel_encoder->type = INTEL_OUTPUT_DVO;
21d40d37 EA	522	intel_encoder->crtc_mask = (1 << 0) \| (1 << 1);
79e53945 JB	523	switch (dvo->type) {
79e53945 JB	524	case INTEL_DVO_CHIP_TMDS:
bc079e8b VS	525	intel_encoder->cloneable = (1 << INTEL_OUTPUT_ANALOG) \|
bc079e8b VS	526	(1 << INTEL_OUTPUT_DVO);
79e53945 JB	527	drm_connector_init(dev, connector,
	528	&intel_dvo_connector_funcs,
	529	DRM_MODE_CONNECTOR_DVII);
	530	encoder_type = DRM_MODE_ENCODER_TMDS;
	531	break;
	532	case INTEL_DVO_CHIP_LVDS:
bc079e8b	533	intel_encoder->cloneable = 0;
79e53945 JB	534	drm_connector_init(dev, connector,
	535	&intel_dvo_connector_funcs,
	536	DRM_MODE_CONNECTOR_LVDS);
	537	encoder_type = DRM_MODE_ENCODER_LVDS;
	538	break;
	539	}
	540
	541	drm_connector_helper_add(connector,
	542	&intel_dvo_connector_helper_funcs);
	543	connector->display_info.subpixel_order = SubPixelHorizontalRGB;
	544	connector->interlace_allowed = false;
	545	connector->doublescan_allowed = false;
	546
df0e9248	547	intel_connector_attach_encoder(intel_connector, intel_encoder);
79e53945 JB	548	if (dvo->type == INTEL_DVO_CHIP_LVDS) {
	549	/* For our LVDS chipsets, we should hopefully be able
	550	* to dig the fixed panel mode out of the BIOS data.
	551	* However, it's in a different format from the BIOS
	552	* data on chipsets with integrated LVDS (stored in AIM
	553	* headers, likely), so for now, just get the current
	554	* mode being output through DVO.
	555	*/
ea5b213a	556	intel_dvo->panel_fixed_mode =
79e53945	557	intel_dvo_get_current_mode(connector);
ea5b213a	558	intel_dvo->panel_wants_dither = true;
79e53945 JB	559	}
	560
	561	drm_sysfs_connector_add(connector);
	562	return;
	563	}
	564
373a3cf7	565	drm_encoder_cleanup(&intel_encoder->base);
ea5b213a	566	kfree(intel_dvo);
599be16c	567	kfree(intel_connector);
79e53945	568	}