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79e53945 JB |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2007 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | */ | |
27 | #include <linux/i2c.h> | |
5a0e3ad6 | 28 | #include <linux/slab.h> |
79e53945 JB |
29 | #include "drmP.h" |
30 | #include "drm.h" | |
31 | #include "drm_crtc.h" | |
32 | #include "intel_drv.h" | |
33 | #include "i915_drm.h" | |
34 | #include "i915_drv.h" | |
35 | #include "dvo.h" | |
36 | ||
37 | #define SIL164_ADDR 0x38 | |
38 | #define CH7xxx_ADDR 0x76 | |
39 | #define TFP410_ADDR 0x38 | |
40 | ||
ea5b213a | 41 | static const struct intel_dvo_device intel_dvo_devices[] = { |
79e53945 JB |
42 | { |
43 | .type = INTEL_DVO_CHIP_TMDS, | |
44 | .name = "sil164", | |
45 | .dvo_reg = DVOC, | |
46 | .slave_addr = SIL164_ADDR, | |
47 | .dev_ops = &sil164_ops, | |
48 | }, | |
49 | { | |
50 | .type = INTEL_DVO_CHIP_TMDS, | |
51 | .name = "ch7xxx", | |
52 | .dvo_reg = DVOC, | |
53 | .slave_addr = CH7xxx_ADDR, | |
54 | .dev_ops = &ch7xxx_ops, | |
55 | }, | |
56 | { | |
57 | .type = INTEL_DVO_CHIP_LVDS, | |
58 | .name = "ivch", | |
59 | .dvo_reg = DVOA, | |
60 | .slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */ | |
61 | .dev_ops = &ivch_ops, | |
62 | }, | |
63 | { | |
64 | .type = INTEL_DVO_CHIP_TMDS, | |
65 | .name = "tfp410", | |
66 | .dvo_reg = DVOC, | |
67 | .slave_addr = TFP410_ADDR, | |
68 | .dev_ops = &tfp410_ops, | |
69 | }, | |
70 | { | |
71 | .type = INTEL_DVO_CHIP_LVDS, | |
72 | .name = "ch7017", | |
73 | .dvo_reg = DVOC, | |
74 | .slave_addr = 0x75, | |
a6b17b43 | 75 | .gpio = GMBUS_PORT_DPB, |
79e53945 JB |
76 | .dev_ops = &ch7017_ops, |
77 | } | |
78 | }; | |
79 | ||
ea5b213a CW |
80 | struct intel_dvo { |
81 | struct intel_encoder base; | |
82 | ||
83 | struct intel_dvo_device dev; | |
84 | ||
85 | struct drm_display_mode *panel_fixed_mode; | |
86 | bool panel_wants_dither; | |
87 | }; | |
88 | ||
89 | static struct intel_dvo *enc_to_intel_dvo(struct drm_encoder *encoder) | |
90 | { | |
4ef69c7a | 91 | return container_of(encoder, struct intel_dvo, base.base); |
ea5b213a CW |
92 | } |
93 | ||
df0e9248 CW |
94 | static struct intel_dvo *intel_attached_dvo(struct drm_connector *connector) |
95 | { | |
96 | return container_of(intel_attached_encoder(connector), | |
97 | struct intel_dvo, base); | |
98 | } | |
99 | ||
79e53945 JB |
100 | static void intel_dvo_dpms(struct drm_encoder *encoder, int mode) |
101 | { | |
102 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; | |
ea5b213a CW |
103 | struct intel_dvo *intel_dvo = enc_to_intel_dvo(encoder); |
104 | u32 dvo_reg = intel_dvo->dev.dvo_reg; | |
79e53945 JB |
105 | u32 temp = I915_READ(dvo_reg); |
106 | ||
107 | if (mode == DRM_MODE_DPMS_ON) { | |
108 | I915_WRITE(dvo_reg, temp | DVO_ENABLE); | |
109 | I915_READ(dvo_reg); | |
ea5b213a | 110 | intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, mode); |
79e53945 | 111 | } else { |
ea5b213a | 112 | intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, mode); |
79e53945 JB |
113 | I915_WRITE(dvo_reg, temp & ~DVO_ENABLE); |
114 | I915_READ(dvo_reg); | |
115 | } | |
116 | } | |
117 | ||
79e53945 JB |
118 | static int intel_dvo_mode_valid(struct drm_connector *connector, |
119 | struct drm_display_mode *mode) | |
120 | { | |
df0e9248 | 121 | struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
79e53945 JB |
122 | |
123 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
124 | return MODE_NO_DBLESCAN; | |
125 | ||
126 | /* XXX: Validate clock range */ | |
127 | ||
ea5b213a CW |
128 | if (intel_dvo->panel_fixed_mode) { |
129 | if (mode->hdisplay > intel_dvo->panel_fixed_mode->hdisplay) | |
79e53945 | 130 | return MODE_PANEL; |
ea5b213a | 131 | if (mode->vdisplay > intel_dvo->panel_fixed_mode->vdisplay) |
79e53945 JB |
132 | return MODE_PANEL; |
133 | } | |
134 | ||
ea5b213a | 135 | return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode); |
79e53945 JB |
136 | } |
137 | ||
138 | static bool intel_dvo_mode_fixup(struct drm_encoder *encoder, | |
e811f5ae | 139 | const struct drm_display_mode *mode, |
79e53945 JB |
140 | struct drm_display_mode *adjusted_mode) |
141 | { | |
ea5b213a | 142 | struct intel_dvo *intel_dvo = enc_to_intel_dvo(encoder); |
79e53945 JB |
143 | |
144 | /* If we have timings from the BIOS for the panel, put them in | |
145 | * to the adjusted mode. The CRTC will be set up for this mode, | |
146 | * with the panel scaling set up to source from the H/VDisplay | |
147 | * of the original mode. | |
148 | */ | |
ea5b213a CW |
149 | if (intel_dvo->panel_fixed_mode != NULL) { |
150 | #define C(x) adjusted_mode->x = intel_dvo->panel_fixed_mode->x | |
79e53945 JB |
151 | C(hdisplay); |
152 | C(hsync_start); | |
153 | C(hsync_end); | |
154 | C(htotal); | |
155 | C(vdisplay); | |
156 | C(vsync_start); | |
157 | C(vsync_end); | |
158 | C(vtotal); | |
159 | C(clock); | |
79e53945 JB |
160 | #undef C |
161 | } | |
162 | ||
ea5b213a CW |
163 | if (intel_dvo->dev.dev_ops->mode_fixup) |
164 | return intel_dvo->dev.dev_ops->mode_fixup(&intel_dvo->dev, mode, adjusted_mode); | |
79e53945 JB |
165 | |
166 | return true; | |
167 | } | |
168 | ||
169 | static void intel_dvo_mode_set(struct drm_encoder *encoder, | |
170 | struct drm_display_mode *mode, | |
171 | struct drm_display_mode *adjusted_mode) | |
172 | { | |
173 | struct drm_device *dev = encoder->dev; | |
174 | struct drm_i915_private *dev_priv = dev->dev_private; | |
175 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
ea5b213a | 176 | struct intel_dvo *intel_dvo = enc_to_intel_dvo(encoder); |
79e53945 JB |
177 | int pipe = intel_crtc->pipe; |
178 | u32 dvo_val; | |
ea5b213a | 179 | u32 dvo_reg = intel_dvo->dev.dvo_reg, dvo_srcdim_reg; |
9db4a9c7 | 180 | int dpll_reg = DPLL(pipe); |
79e53945 JB |
181 | |
182 | switch (dvo_reg) { | |
183 | case DVOA: | |
184 | default: | |
185 | dvo_srcdim_reg = DVOA_SRCDIM; | |
186 | break; | |
187 | case DVOB: | |
188 | dvo_srcdim_reg = DVOB_SRCDIM; | |
189 | break; | |
190 | case DVOC: | |
191 | dvo_srcdim_reg = DVOC_SRCDIM; | |
192 | break; | |
193 | } | |
194 | ||
ea5b213a | 195 | intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev, mode, adjusted_mode); |
79e53945 JB |
196 | |
197 | /* Save the data order, since I don't know what it should be set to. */ | |
198 | dvo_val = I915_READ(dvo_reg) & | |
199 | (DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG); | |
200 | dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE | | |
201 | DVO_BLANK_ACTIVE_HIGH; | |
202 | ||
203 | if (pipe == 1) | |
204 | dvo_val |= DVO_PIPE_B_SELECT; | |
205 | dvo_val |= DVO_PIPE_STALL; | |
206 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
207 | dvo_val |= DVO_HSYNC_ACTIVE_HIGH; | |
208 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
209 | dvo_val |= DVO_VSYNC_ACTIVE_HIGH; | |
210 | ||
211 | I915_WRITE(dpll_reg, I915_READ(dpll_reg) | DPLL_DVO_HIGH_SPEED); | |
212 | ||
213 | /*I915_WRITE(DVOB_SRCDIM, | |
214 | (adjusted_mode->hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | | |
215 | (adjusted_mode->VDisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/ | |
216 | I915_WRITE(dvo_srcdim_reg, | |
217 | (adjusted_mode->hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | | |
218 | (adjusted_mode->vdisplay << DVO_SRCDIM_VERTICAL_SHIFT)); | |
219 | /*I915_WRITE(DVOB, dvo_val);*/ | |
220 | I915_WRITE(dvo_reg, dvo_val); | |
221 | } | |
222 | ||
223 | /** | |
224 | * Detect the output connection on our DVO device. | |
225 | * | |
226 | * Unimplemented. | |
227 | */ | |
7b334fcb | 228 | static enum drm_connector_status |
930a9e28 | 229 | intel_dvo_detect(struct drm_connector *connector, bool force) |
79e53945 | 230 | { |
df0e9248 | 231 | struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
ea5b213a | 232 | return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev); |
79e53945 JB |
233 | } |
234 | ||
235 | static int intel_dvo_get_modes(struct drm_connector *connector) | |
236 | { | |
df0e9248 | 237 | struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
f899fc64 | 238 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
79e53945 JB |
239 | |
240 | /* We should probably have an i2c driver get_modes function for those | |
241 | * devices which will have a fixed set of modes determined by the chip | |
242 | * (TV-out, for example), but for now with just TMDS and LVDS, | |
243 | * that's not the case. | |
244 | */ | |
f899fc64 | 245 | intel_ddc_get_modes(connector, |
3bd7d909 | 246 | intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPC)); |
79e53945 JB |
247 | if (!list_empty(&connector->probed_modes)) |
248 | return 1; | |
249 | ||
ea5b213a | 250 | if (intel_dvo->panel_fixed_mode != NULL) { |
79e53945 | 251 | struct drm_display_mode *mode; |
ea5b213a | 252 | mode = drm_mode_duplicate(connector->dev, intel_dvo->panel_fixed_mode); |
79e53945 JB |
253 | if (mode) { |
254 | drm_mode_probed_add(connector, mode); | |
255 | return 1; | |
256 | } | |
257 | } | |
ea5b213a | 258 | |
79e53945 JB |
259 | return 0; |
260 | } | |
261 | ||
ea5b213a | 262 | static void intel_dvo_destroy(struct drm_connector *connector) |
79e53945 | 263 | { |
79e53945 JB |
264 | drm_sysfs_connector_remove(connector); |
265 | drm_connector_cleanup(connector); | |
599be16c | 266 | kfree(connector); |
79e53945 | 267 | } |
79e53945 JB |
268 | |
269 | static const struct drm_encoder_helper_funcs intel_dvo_helper_funcs = { | |
270 | .dpms = intel_dvo_dpms, | |
271 | .mode_fixup = intel_dvo_mode_fixup, | |
272 | .prepare = intel_encoder_prepare, | |
273 | .mode_set = intel_dvo_mode_set, | |
274 | .commit = intel_encoder_commit, | |
275 | }; | |
276 | ||
277 | static const struct drm_connector_funcs intel_dvo_connector_funcs = { | |
c9fb15f6 | 278 | .dpms = drm_helper_connector_dpms, |
79e53945 JB |
279 | .detect = intel_dvo_detect, |
280 | .destroy = intel_dvo_destroy, | |
281 | .fill_modes = drm_helper_probe_single_connector_modes, | |
282 | }; | |
283 | ||
284 | static const struct drm_connector_helper_funcs intel_dvo_connector_helper_funcs = { | |
285 | .mode_valid = intel_dvo_mode_valid, | |
286 | .get_modes = intel_dvo_get_modes, | |
df0e9248 | 287 | .best_encoder = intel_best_encoder, |
79e53945 JB |
288 | }; |
289 | ||
b358d0a6 | 290 | static void intel_dvo_enc_destroy(struct drm_encoder *encoder) |
79e53945 | 291 | { |
ea5b213a CW |
292 | struct intel_dvo *intel_dvo = enc_to_intel_dvo(encoder); |
293 | ||
294 | if (intel_dvo->dev.dev_ops->destroy) | |
295 | intel_dvo->dev.dev_ops->destroy(&intel_dvo->dev); | |
296 | ||
297 | kfree(intel_dvo->panel_fixed_mode); | |
298 | ||
299 | intel_encoder_destroy(encoder); | |
79e53945 JB |
300 | } |
301 | ||
302 | static const struct drm_encoder_funcs intel_dvo_enc_funcs = { | |
303 | .destroy = intel_dvo_enc_destroy, | |
304 | }; | |
305 | ||
79e53945 JB |
306 | /** |
307 | * Attempts to get a fixed panel timing for LVDS (currently only the i830). | |
308 | * | |
309 | * Other chips with DVO LVDS will need to extend this to deal with the LVDS | |
310 | * chip being on DVOB/C and having multiple pipes. | |
311 | */ | |
312 | static struct drm_display_mode * | |
ea5b213a | 313 | intel_dvo_get_current_mode(struct drm_connector *connector) |
79e53945 JB |
314 | { |
315 | struct drm_device *dev = connector->dev; | |
316 | struct drm_i915_private *dev_priv = dev->dev_private; | |
df0e9248 | 317 | struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
ea5b213a | 318 | uint32_t dvo_val = I915_READ(intel_dvo->dev.dvo_reg); |
79e53945 JB |
319 | struct drm_display_mode *mode = NULL; |
320 | ||
321 | /* If the DVO port is active, that'll be the LVDS, so we can pull out | |
322 | * its timings to get how the BIOS set up the panel. | |
323 | */ | |
324 | if (dvo_val & DVO_ENABLE) { | |
325 | struct drm_crtc *crtc; | |
326 | int pipe = (dvo_val & DVO_PIPE_B_SELECT) ? 1 : 0; | |
327 | ||
f875c15a | 328 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
79e53945 JB |
329 | if (crtc) { |
330 | mode = intel_crtc_mode_get(dev, crtc); | |
79e53945 JB |
331 | if (mode) { |
332 | mode->type |= DRM_MODE_TYPE_PREFERRED; | |
333 | if (dvo_val & DVO_HSYNC_ACTIVE_HIGH) | |
334 | mode->flags |= DRM_MODE_FLAG_PHSYNC; | |
335 | if (dvo_val & DVO_VSYNC_ACTIVE_HIGH) | |
336 | mode->flags |= DRM_MODE_FLAG_PVSYNC; | |
337 | } | |
338 | } | |
339 | } | |
ea5b213a | 340 | |
79e53945 JB |
341 | return mode; |
342 | } | |
343 | ||
344 | void intel_dvo_init(struct drm_device *dev) | |
345 | { | |
f899fc64 | 346 | struct drm_i915_private *dev_priv = dev->dev_private; |
21d40d37 | 347 | struct intel_encoder *intel_encoder; |
ea5b213a | 348 | struct intel_dvo *intel_dvo; |
599be16c | 349 | struct intel_connector *intel_connector; |
79e53945 | 350 | int i; |
79e53945 | 351 | int encoder_type = DRM_MODE_ENCODER_NONE; |
ea5b213a CW |
352 | |
353 | intel_dvo = kzalloc(sizeof(struct intel_dvo), GFP_KERNEL); | |
354 | if (!intel_dvo) | |
79e53945 JB |
355 | return; |
356 | ||
599be16c ZW |
357 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
358 | if (!intel_connector) { | |
ea5b213a | 359 | kfree(intel_dvo); |
599be16c ZW |
360 | return; |
361 | } | |
362 | ||
ea5b213a | 363 | intel_encoder = &intel_dvo->base; |
373a3cf7 CW |
364 | drm_encoder_init(dev, &intel_encoder->base, |
365 | &intel_dvo_enc_funcs, encoder_type); | |
ea5b213a | 366 | |
79e53945 JB |
367 | /* Now, try to find a controller */ |
368 | for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) { | |
599be16c | 369 | struct drm_connector *connector = &intel_connector->base; |
ea5b213a | 370 | const struct intel_dvo_device *dvo = &intel_dvo_devices[i]; |
f899fc64 | 371 | struct i2c_adapter *i2c; |
79e53945 JB |
372 | int gpio; |
373 | ||
79e53945 JB |
374 | /* Allow the I2C driver info to specify the GPIO to be used in |
375 | * special cases, but otherwise default to what's defined | |
376 | * in the spec. | |
377 | */ | |
3bd7d909 | 378 | if (intel_gmbus_is_port_valid(dvo->gpio)) |
79e53945 JB |
379 | gpio = dvo->gpio; |
380 | else if (dvo->type == INTEL_DVO_CHIP_LVDS) | |
f573c660 | 381 | gpio = GMBUS_PORT_SSC; |
79e53945 | 382 | else |
a6b17b43 | 383 | gpio = GMBUS_PORT_DPB; |
79e53945 JB |
384 | |
385 | /* Set up the I2C bus necessary for the chip we're probing. | |
386 | * It appears that everything is on GPIOE except for panels | |
387 | * on i830 laptops, which are on GPIOB (DVOA). | |
388 | */ | |
3bd7d909 | 389 | i2c = intel_gmbus_get_adapter(dev_priv, gpio); |
79e53945 | 390 | |
ea5b213a | 391 | intel_dvo->dev = *dvo; |
f573c660 | 392 | if (!dvo->dev_ops->init(&intel_dvo->dev, i2c)) |
79e53945 JB |
393 | continue; |
394 | ||
21d40d37 EA |
395 | intel_encoder->type = INTEL_OUTPUT_DVO; |
396 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
79e53945 JB |
397 | switch (dvo->type) { |
398 | case INTEL_DVO_CHIP_TMDS: | |
21d40d37 | 399 | intel_encoder->clone_mask = |
f8aed700 ML |
400 | (1 << INTEL_DVO_TMDS_CLONE_BIT) | |
401 | (1 << INTEL_ANALOG_CLONE_BIT); | |
79e53945 JB |
402 | drm_connector_init(dev, connector, |
403 | &intel_dvo_connector_funcs, | |
404 | DRM_MODE_CONNECTOR_DVII); | |
405 | encoder_type = DRM_MODE_ENCODER_TMDS; | |
406 | break; | |
407 | case INTEL_DVO_CHIP_LVDS: | |
21d40d37 | 408 | intel_encoder->clone_mask = |
f8aed700 | 409 | (1 << INTEL_DVO_LVDS_CLONE_BIT); |
79e53945 JB |
410 | drm_connector_init(dev, connector, |
411 | &intel_dvo_connector_funcs, | |
412 | DRM_MODE_CONNECTOR_LVDS); | |
413 | encoder_type = DRM_MODE_ENCODER_LVDS; | |
414 | break; | |
415 | } | |
416 | ||
417 | drm_connector_helper_add(connector, | |
418 | &intel_dvo_connector_helper_funcs); | |
419 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
420 | connector->interlace_allowed = false; | |
421 | connector->doublescan_allowed = false; | |
422 | ||
4ef69c7a | 423 | drm_encoder_helper_add(&intel_encoder->base, |
79e53945 JB |
424 | &intel_dvo_helper_funcs); |
425 | ||
df0e9248 | 426 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
79e53945 JB |
427 | if (dvo->type == INTEL_DVO_CHIP_LVDS) { |
428 | /* For our LVDS chipsets, we should hopefully be able | |
429 | * to dig the fixed panel mode out of the BIOS data. | |
430 | * However, it's in a different format from the BIOS | |
431 | * data on chipsets with integrated LVDS (stored in AIM | |
432 | * headers, likely), so for now, just get the current | |
433 | * mode being output through DVO. | |
434 | */ | |
ea5b213a | 435 | intel_dvo->panel_fixed_mode = |
79e53945 | 436 | intel_dvo_get_current_mode(connector); |
ea5b213a | 437 | intel_dvo->panel_wants_dither = true; |
79e53945 JB |
438 | } |
439 | ||
440 | drm_sysfs_connector_add(connector); | |
441 | return; | |
442 | } | |
443 | ||
373a3cf7 | 444 | drm_encoder_cleanup(&intel_encoder->base); |
ea5b213a | 445 | kfree(intel_dvo); |
599be16c | 446 | kfree(intel_connector); |
79e53945 | 447 | } |