Commit | Line | Data |
---|---|---|
7ff0ebcc RV |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
94b83957 RV |
24 | /** |
25 | * DOC: Frame Buffer Compression (FBC) | |
26 | * | |
27 | * FBC tries to save memory bandwidth (and so power consumption) by | |
28 | * compressing the amount of memory used by the display. It is total | |
29 | * transparent to user space and completely handled in the kernel. | |
7ff0ebcc RV |
30 | * |
31 | * The benefits of FBC are mostly visible with solid backgrounds and | |
94b83957 RV |
32 | * variation-less patterns. It comes from keeping the memory footprint small |
33 | * and having fewer memory pages opened and accessed for refreshing the display. | |
7ff0ebcc | 34 | * |
94b83957 RV |
35 | * i915 is responsible to reserve stolen memory for FBC and configure its |
36 | * offset on proper registers. The hardware takes care of all | |
37 | * compress/decompress. However there are many known cases where we have to | |
38 | * forcibly disable it to allow proper screen updates. | |
7ff0ebcc RV |
39 | */ |
40 | ||
94b83957 RV |
41 | #include "intel_drv.h" |
42 | #include "i915_drv.h" | |
43 | ||
7ff0ebcc RV |
44 | static void i8xx_fbc_disable(struct drm_device *dev) |
45 | { | |
46 | struct drm_i915_private *dev_priv = dev->dev_private; | |
47 | u32 fbc_ctl; | |
48 | ||
49 | dev_priv->fbc.enabled = false; | |
50 | ||
51 | /* Disable compression */ | |
52 | fbc_ctl = I915_READ(FBC_CONTROL); | |
53 | if ((fbc_ctl & FBC_CTL_EN) == 0) | |
54 | return; | |
55 | ||
56 | fbc_ctl &= ~FBC_CTL_EN; | |
57 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
58 | ||
59 | /* Wait for compressing bit to clear */ | |
60 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { | |
61 | DRM_DEBUG_KMS("FBC idle timed out\n"); | |
62 | return; | |
63 | } | |
64 | ||
65 | DRM_DEBUG_KMS("disabled FBC\n"); | |
66 | } | |
67 | ||
68 | static void i8xx_fbc_enable(struct drm_crtc *crtc) | |
69 | { | |
70 | struct drm_device *dev = crtc->dev; | |
71 | struct drm_i915_private *dev_priv = dev->dev_private; | |
72 | struct drm_framebuffer *fb = crtc->primary->fb; | |
73 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
74 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
75 | int cfb_pitch; | |
76 | int i; | |
77 | u32 fbc_ctl; | |
78 | ||
79 | dev_priv->fbc.enabled = true; | |
80 | ||
81 | cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE; | |
82 | if (fb->pitches[0] < cfb_pitch) | |
83 | cfb_pitch = fb->pitches[0]; | |
84 | ||
85 | /* FBC_CTL wants 32B or 64B units */ | |
86 | if (IS_GEN2(dev)) | |
87 | cfb_pitch = (cfb_pitch / 32) - 1; | |
88 | else | |
89 | cfb_pitch = (cfb_pitch / 64) - 1; | |
90 | ||
91 | /* Clear old tags */ | |
92 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) | |
93 | I915_WRITE(FBC_TAG + (i * 4), 0); | |
94 | ||
95 | if (IS_GEN4(dev)) { | |
96 | u32 fbc_ctl2; | |
97 | ||
98 | /* Set it up... */ | |
99 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; | |
100 | fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane); | |
101 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); | |
102 | I915_WRITE(FBC_FENCE_OFF, crtc->y); | |
103 | } | |
104 | ||
105 | /* enable it... */ | |
106 | fbc_ctl = I915_READ(FBC_CONTROL); | |
107 | fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT; | |
108 | fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC; | |
109 | if (IS_I945GM(dev)) | |
110 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ | |
111 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; | |
112 | fbc_ctl |= obj->fence_reg; | |
113 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
114 | ||
115 | DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n", | |
116 | cfb_pitch, crtc->y, plane_name(intel_crtc->plane)); | |
117 | } | |
118 | ||
119 | static bool i8xx_fbc_enabled(struct drm_device *dev) | |
120 | { | |
121 | struct drm_i915_private *dev_priv = dev->dev_private; | |
122 | ||
123 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; | |
124 | } | |
125 | ||
126 | static void g4x_fbc_enable(struct drm_crtc *crtc) | |
127 | { | |
128 | struct drm_device *dev = crtc->dev; | |
129 | struct drm_i915_private *dev_priv = dev->dev_private; | |
130 | struct drm_framebuffer *fb = crtc->primary->fb; | |
131 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
132 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
133 | u32 dpfc_ctl; | |
134 | ||
135 | dev_priv->fbc.enabled = true; | |
136 | ||
137 | dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN; | |
138 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) | |
139 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
140 | else | |
141 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
142 | dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; | |
143 | ||
144 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); | |
145 | ||
146 | /* enable it... */ | |
147 | I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
148 | ||
149 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); | |
150 | } | |
151 | ||
152 | static void g4x_fbc_disable(struct drm_device *dev) | |
153 | { | |
154 | struct drm_i915_private *dev_priv = dev->dev_private; | |
155 | u32 dpfc_ctl; | |
156 | ||
157 | dev_priv->fbc.enabled = false; | |
158 | ||
159 | /* Disable compression */ | |
160 | dpfc_ctl = I915_READ(DPFC_CONTROL); | |
161 | if (dpfc_ctl & DPFC_CTL_EN) { | |
162 | dpfc_ctl &= ~DPFC_CTL_EN; | |
163 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); | |
164 | ||
165 | DRM_DEBUG_KMS("disabled FBC\n"); | |
166 | } | |
167 | } | |
168 | ||
169 | static bool g4x_fbc_enabled(struct drm_device *dev) | |
170 | { | |
171 | struct drm_i915_private *dev_priv = dev->dev_private; | |
172 | ||
173 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; | |
174 | } | |
175 | ||
176 | static void snb_fbc_blit_update(struct drm_device *dev) | |
177 | { | |
178 | struct drm_i915_private *dev_priv = dev->dev_private; | |
179 | u32 blt_ecoskpd; | |
180 | ||
181 | /* Make sure blitter notifies FBC of writes */ | |
182 | ||
183 | /* Blitter is part of Media powerwell on VLV. No impact of | |
184 | * his param in other platforms for now */ | |
59bad947 | 185 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA); |
7ff0ebcc RV |
186 | |
187 | blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); | |
188 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << | |
189 | GEN6_BLITTER_LOCK_SHIFT; | |
190 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
191 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY; | |
192 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
193 | blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY << | |
194 | GEN6_BLITTER_LOCK_SHIFT); | |
195 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
196 | POSTING_READ(GEN6_BLITTER_ECOSKPD); | |
197 | ||
59bad947 | 198 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA); |
7ff0ebcc RV |
199 | } |
200 | ||
201 | static void ilk_fbc_enable(struct drm_crtc *crtc) | |
202 | { | |
203 | struct drm_device *dev = crtc->dev; | |
204 | struct drm_i915_private *dev_priv = dev->dev_private; | |
205 | struct drm_framebuffer *fb = crtc->primary->fb; | |
206 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
207 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
208 | u32 dpfc_ctl; | |
209 | ||
210 | dev_priv->fbc.enabled = true; | |
211 | ||
212 | dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane); | |
213 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) | |
214 | dev_priv->fbc.threshold++; | |
215 | ||
216 | switch (dev_priv->fbc.threshold) { | |
217 | case 4: | |
218 | case 3: | |
219 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; | |
220 | break; | |
221 | case 2: | |
222 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
223 | break; | |
224 | case 1: | |
225 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
226 | break; | |
227 | } | |
228 | dpfc_ctl |= DPFC_CTL_FENCE_EN; | |
229 | if (IS_GEN5(dev)) | |
230 | dpfc_ctl |= obj->fence_reg; | |
231 | ||
232 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); | |
233 | I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID); | |
234 | /* enable it... */ | |
235 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
236 | ||
237 | if (IS_GEN6(dev)) { | |
238 | I915_WRITE(SNB_DPFC_CTL_SA, | |
239 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); | |
240 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); | |
241 | snb_fbc_blit_update(dev); | |
242 | } | |
243 | ||
244 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); | |
245 | } | |
246 | ||
247 | static void ilk_fbc_disable(struct drm_device *dev) | |
248 | { | |
249 | struct drm_i915_private *dev_priv = dev->dev_private; | |
250 | u32 dpfc_ctl; | |
251 | ||
252 | dev_priv->fbc.enabled = false; | |
253 | ||
254 | /* Disable compression */ | |
255 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
256 | if (dpfc_ctl & DPFC_CTL_EN) { | |
257 | dpfc_ctl &= ~DPFC_CTL_EN; | |
258 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); | |
259 | ||
260 | DRM_DEBUG_KMS("disabled FBC\n"); | |
261 | } | |
262 | } | |
263 | ||
264 | static bool ilk_fbc_enabled(struct drm_device *dev) | |
265 | { | |
266 | struct drm_i915_private *dev_priv = dev->dev_private; | |
267 | ||
268 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; | |
269 | } | |
270 | ||
271 | static void gen7_fbc_enable(struct drm_crtc *crtc) | |
272 | { | |
273 | struct drm_device *dev = crtc->dev; | |
274 | struct drm_i915_private *dev_priv = dev->dev_private; | |
275 | struct drm_framebuffer *fb = crtc->primary->fb; | |
276 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
277 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
278 | u32 dpfc_ctl; | |
279 | ||
280 | dev_priv->fbc.enabled = true; | |
281 | ||
282 | dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane); | |
283 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) | |
284 | dev_priv->fbc.threshold++; | |
285 | ||
286 | switch (dev_priv->fbc.threshold) { | |
287 | case 4: | |
288 | case 3: | |
289 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; | |
290 | break; | |
291 | case 2: | |
292 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
293 | break; | |
294 | case 1: | |
295 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
296 | break; | |
297 | } | |
298 | ||
299 | dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; | |
300 | ||
301 | if (dev_priv->fbc.false_color) | |
302 | dpfc_ctl |= FBC_CTL_FALSE_COLOR; | |
303 | ||
304 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
305 | ||
306 | if (IS_IVYBRIDGE(dev)) { | |
307 | /* WaFbcAsynchFlipDisableFbcQueue:ivb */ | |
308 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
309 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
310 | ILK_FBCQ_DIS); | |
311 | } else { | |
312 | /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ | |
313 | I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe), | |
314 | I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) | | |
315 | HSW_FBCQ_DIS); | |
316 | } | |
317 | ||
318 | I915_WRITE(SNB_DPFC_CTL_SA, | |
319 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); | |
320 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); | |
321 | ||
322 | snb_fbc_blit_update(dev); | |
323 | ||
324 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); | |
325 | } | |
326 | ||
94b83957 RV |
327 | /** |
328 | * intel_fbc_enabled - Is FBC enabled? | |
329 | * @dev: the drm_device | |
330 | * | |
331 | * This function is used to verify the current state of FBC. | |
332 | * FIXME: This should be tracked in the plane config eventually | |
333 | * instead of queried at runtime for most callers. | |
334 | */ | |
7ff0ebcc RV |
335 | bool intel_fbc_enabled(struct drm_device *dev) |
336 | { | |
337 | struct drm_i915_private *dev_priv = dev->dev_private; | |
338 | ||
339 | return dev_priv->fbc.enabled; | |
340 | } | |
341 | ||
342 | void bdw_fbc_sw_flush(struct drm_device *dev, u32 value) | |
343 | { | |
344 | struct drm_i915_private *dev_priv = dev->dev_private; | |
345 | ||
346 | if (!IS_GEN8(dev)) | |
347 | return; | |
348 | ||
349 | if (!intel_fbc_enabled(dev)) | |
350 | return; | |
351 | ||
352 | I915_WRITE(MSG_FBC_REND_STATE, value); | |
353 | } | |
354 | ||
355 | static void intel_fbc_work_fn(struct work_struct *__work) | |
356 | { | |
357 | struct intel_fbc_work *work = | |
358 | container_of(to_delayed_work(__work), | |
359 | struct intel_fbc_work, work); | |
360 | struct drm_device *dev = work->crtc->dev; | |
361 | struct drm_i915_private *dev_priv = dev->dev_private; | |
362 | ||
363 | mutex_lock(&dev->struct_mutex); | |
364 | if (work == dev_priv->fbc.fbc_work) { | |
365 | /* Double check that we haven't switched fb without cancelling | |
366 | * the prior work. | |
367 | */ | |
368 | if (work->crtc->primary->fb == work->fb) { | |
369 | dev_priv->display.enable_fbc(work->crtc); | |
370 | ||
371 | dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane; | |
372 | dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id; | |
373 | dev_priv->fbc.y = work->crtc->y; | |
374 | } | |
375 | ||
376 | dev_priv->fbc.fbc_work = NULL; | |
377 | } | |
378 | mutex_unlock(&dev->struct_mutex); | |
379 | ||
380 | kfree(work); | |
381 | } | |
382 | ||
383 | static void intel_fbc_cancel_work(struct drm_i915_private *dev_priv) | |
384 | { | |
385 | if (dev_priv->fbc.fbc_work == NULL) | |
386 | return; | |
387 | ||
388 | DRM_DEBUG_KMS("cancelling pending FBC enable\n"); | |
389 | ||
390 | /* Synchronisation is provided by struct_mutex and checking of | |
391 | * dev_priv->fbc.fbc_work, so we can perform the cancellation | |
392 | * entirely asynchronously. | |
393 | */ | |
394 | if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work)) | |
395 | /* tasklet was killed before being run, clean up */ | |
396 | kfree(dev_priv->fbc.fbc_work); | |
397 | ||
398 | /* Mark the work as no longer wanted so that if it does | |
399 | * wake-up (because the work was already running and waiting | |
400 | * for our mutex), it will discover that is no longer | |
401 | * necessary to run. | |
402 | */ | |
403 | dev_priv->fbc.fbc_work = NULL; | |
404 | } | |
405 | ||
406 | static void intel_fbc_enable(struct drm_crtc *crtc) | |
407 | { | |
408 | struct intel_fbc_work *work; | |
409 | struct drm_device *dev = crtc->dev; | |
410 | struct drm_i915_private *dev_priv = dev->dev_private; | |
411 | ||
412 | if (!dev_priv->display.enable_fbc) | |
413 | return; | |
414 | ||
415 | intel_fbc_cancel_work(dev_priv); | |
416 | ||
417 | work = kzalloc(sizeof(*work), GFP_KERNEL); | |
418 | if (work == NULL) { | |
419 | DRM_ERROR("Failed to allocate FBC work structure\n"); | |
420 | dev_priv->display.enable_fbc(crtc); | |
421 | return; | |
422 | } | |
423 | ||
424 | work->crtc = crtc; | |
425 | work->fb = crtc->primary->fb; | |
426 | INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); | |
427 | ||
428 | dev_priv->fbc.fbc_work = work; | |
429 | ||
430 | /* Delay the actual enabling to let pageflipping cease and the | |
431 | * display to settle before starting the compression. Note that | |
432 | * this delay also serves a second purpose: it allows for a | |
433 | * vblank to pass after disabling the FBC before we attempt | |
434 | * to modify the control registers. | |
435 | * | |
436 | * A more complicated solution would involve tracking vblanks | |
437 | * following the termination of the page-flipping sequence | |
438 | * and indeed performing the enable as a co-routine and not | |
439 | * waiting synchronously upon the vblank. | |
440 | * | |
441 | * WaFbcWaitForVBlankBeforeEnable:ilk,snb | |
442 | */ | |
443 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); | |
444 | } | |
445 | ||
94b83957 RV |
446 | /** |
447 | * intel_fbc_disable - disable FBC | |
448 | * @dev: the drm_device | |
449 | * | |
450 | * This function disables FBC. | |
451 | */ | |
7ff0ebcc RV |
452 | void intel_fbc_disable(struct drm_device *dev) |
453 | { | |
454 | struct drm_i915_private *dev_priv = dev->dev_private; | |
455 | ||
456 | intel_fbc_cancel_work(dev_priv); | |
457 | ||
458 | if (!dev_priv->display.disable_fbc) | |
459 | return; | |
460 | ||
461 | dev_priv->display.disable_fbc(dev); | |
462 | dev_priv->fbc.plane = -1; | |
463 | } | |
464 | ||
465 | static bool set_no_fbc_reason(struct drm_i915_private *dev_priv, | |
466 | enum no_fbc_reason reason) | |
467 | { | |
468 | if (dev_priv->fbc.no_fbc_reason == reason) | |
469 | return false; | |
470 | ||
471 | dev_priv->fbc.no_fbc_reason = reason; | |
472 | return true; | |
473 | } | |
474 | ||
475 | /** | |
476 | * intel_fbc_update - enable/disable FBC as needed | |
477 | * @dev: the drm_device | |
478 | * | |
479 | * Set up the framebuffer compression hardware at mode set time. We | |
480 | * enable it if possible: | |
481 | * - plane A only (on pre-965) | |
482 | * - no pixel mulitply/line duplication | |
483 | * - no alpha buffer discard | |
484 | * - no dual wide | |
485 | * - framebuffer <= max_hdisplay in width, max_vdisplay in height | |
486 | * | |
487 | * We can't assume that any compression will take place (worst case), | |
488 | * so the compressed buffer has to be the same size as the uncompressed | |
489 | * one. It also must reside (along with the line length buffer) in | |
490 | * stolen memory. | |
491 | * | |
492 | * We need to enable/disable FBC on a global basis. | |
493 | */ | |
494 | void intel_fbc_update(struct drm_device *dev) | |
495 | { | |
496 | struct drm_i915_private *dev_priv = dev->dev_private; | |
497 | struct drm_crtc *crtc = NULL, *tmp_crtc; | |
498 | struct intel_crtc *intel_crtc; | |
499 | struct drm_framebuffer *fb; | |
500 | struct drm_i915_gem_object *obj; | |
501 | const struct drm_display_mode *adjusted_mode; | |
502 | unsigned int max_width, max_height; | |
503 | ||
504 | if (!HAS_FBC(dev)) { | |
505 | set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED); | |
506 | return; | |
507 | } | |
508 | ||
509 | if (!i915.powersave) { | |
510 | if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM)) | |
511 | DRM_DEBUG_KMS("fbc disabled per module param\n"); | |
512 | return; | |
513 | } | |
514 | ||
515 | /* | |
516 | * If FBC is already on, we just have to verify that we can | |
517 | * keep it that way... | |
518 | * Need to disable if: | |
519 | * - more than one pipe is active | |
520 | * - changing FBC params (stride, fence, mode) | |
521 | * - new fb is too large to fit in compressed buffer | |
522 | * - going to an unsupported config (interlace, pixel multiply, etc.) | |
523 | */ | |
524 | for_each_crtc(dev, tmp_crtc) { | |
525 | if (intel_crtc_active(tmp_crtc) && | |
526 | to_intel_crtc(tmp_crtc)->primary_enabled) { | |
527 | if (crtc) { | |
528 | if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES)) | |
529 | DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); | |
530 | goto out_disable; | |
531 | } | |
532 | crtc = tmp_crtc; | |
533 | } | |
534 | } | |
535 | ||
536 | if (!crtc || crtc->primary->fb == NULL) { | |
537 | if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT)) | |
538 | DRM_DEBUG_KMS("no output, disabling\n"); | |
539 | goto out_disable; | |
540 | } | |
541 | ||
542 | intel_crtc = to_intel_crtc(crtc); | |
543 | fb = crtc->primary->fb; | |
544 | obj = intel_fb_obj(fb); | |
6e3c9717 | 545 | adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
7ff0ebcc RV |
546 | |
547 | if (i915.enable_fbc < 0) { | |
548 | if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT)) | |
549 | DRM_DEBUG_KMS("disabled per chip default\n"); | |
550 | goto out_disable; | |
551 | } | |
552 | if (!i915.enable_fbc) { | |
553 | if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM)) | |
554 | DRM_DEBUG_KMS("fbc disabled per module param\n"); | |
555 | goto out_disable; | |
556 | } | |
557 | if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) || | |
558 | (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) { | |
559 | if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE)) | |
560 | DRM_DEBUG_KMS("mode incompatible with compression, " | |
561 | "disabling\n"); | |
562 | goto out_disable; | |
563 | } | |
564 | ||
565 | if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) { | |
566 | max_width = 4096; | |
567 | max_height = 4096; | |
568 | } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { | |
569 | max_width = 4096; | |
570 | max_height = 2048; | |
571 | } else { | |
572 | max_width = 2048; | |
573 | max_height = 1536; | |
574 | } | |
6e3c9717 ACO |
575 | if (intel_crtc->config->pipe_src_w > max_width || |
576 | intel_crtc->config->pipe_src_h > max_height) { | |
7ff0ebcc RV |
577 | if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE)) |
578 | DRM_DEBUG_KMS("mode too large for compression, disabling\n"); | |
579 | goto out_disable; | |
580 | } | |
581 | if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) && | |
582 | intel_crtc->plane != PLANE_A) { | |
583 | if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE)) | |
584 | DRM_DEBUG_KMS("plane not A, disabling compression\n"); | |
585 | goto out_disable; | |
586 | } | |
587 | ||
588 | /* The use of a CPU fence is mandatory in order to detect writes | |
589 | * by the CPU to the scanout and trigger updates to the FBC. | |
590 | */ | |
591 | if (obj->tiling_mode != I915_TILING_X || | |
592 | obj->fence_reg == I915_FENCE_REG_NONE) { | |
593 | if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED)) | |
594 | DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n"); | |
595 | goto out_disable; | |
596 | } | |
597 | if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && | |
8e7d688b | 598 | crtc->primary->state->rotation != BIT(DRM_ROTATE_0)) { |
7ff0ebcc RV |
599 | if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE)) |
600 | DRM_DEBUG_KMS("Rotation unsupported, disabling\n"); | |
601 | goto out_disable; | |
602 | } | |
603 | ||
604 | /* If the kernel debugger is active, always disable compression */ | |
605 | if (in_dbg_master()) | |
606 | goto out_disable; | |
607 | ||
608 | if (i915_gem_stolen_setup_compression(dev, obj->base.size, | |
609 | drm_format_plane_cpp(fb->pixel_format, 0))) { | |
610 | if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL)) | |
611 | DRM_DEBUG_KMS("framebuffer too large, disabling compression\n"); | |
612 | goto out_disable; | |
613 | } | |
614 | ||
615 | /* If the scanout has not changed, don't modify the FBC settings. | |
616 | * Note that we make the fundamental assumption that the fb->obj | |
617 | * cannot be unpinned (and have its GTT offset and fence revoked) | |
618 | * without first being decoupled from the scanout and FBC disabled. | |
619 | */ | |
620 | if (dev_priv->fbc.plane == intel_crtc->plane && | |
621 | dev_priv->fbc.fb_id == fb->base.id && | |
622 | dev_priv->fbc.y == crtc->y) | |
623 | return; | |
624 | ||
625 | if (intel_fbc_enabled(dev)) { | |
626 | /* We update FBC along two paths, after changing fb/crtc | |
627 | * configuration (modeswitching) and after page-flipping | |
628 | * finishes. For the latter, we know that not only did | |
629 | * we disable the FBC at the start of the page-flip | |
630 | * sequence, but also more than one vblank has passed. | |
631 | * | |
632 | * For the former case of modeswitching, it is possible | |
633 | * to switch between two FBC valid configurations | |
634 | * instantaneously so we do need to disable the FBC | |
635 | * before we can modify its control registers. We also | |
636 | * have to wait for the next vblank for that to take | |
637 | * effect. However, since we delay enabling FBC we can | |
638 | * assume that a vblank has passed since disabling and | |
639 | * that we can safely alter the registers in the deferred | |
640 | * callback. | |
641 | * | |
642 | * In the scenario that we go from a valid to invalid | |
643 | * and then back to valid FBC configuration we have | |
644 | * no strict enforcement that a vblank occurred since | |
645 | * disabling the FBC. However, along all current pipe | |
646 | * disabling paths we do need to wait for a vblank at | |
647 | * some point. And we wait before enabling FBC anyway. | |
648 | */ | |
649 | DRM_DEBUG_KMS("disabling active FBC for update\n"); | |
650 | intel_fbc_disable(dev); | |
651 | } | |
652 | ||
653 | intel_fbc_enable(crtc); | |
654 | dev_priv->fbc.no_fbc_reason = FBC_OK; | |
655 | return; | |
656 | ||
657 | out_disable: | |
658 | /* Multiple disables should be harmless */ | |
659 | if (intel_fbc_enabled(dev)) { | |
660 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); | |
661 | intel_fbc_disable(dev); | |
662 | } | |
663 | i915_gem_stolen_cleanup_compression(dev); | |
664 | } | |
665 | ||
94b83957 RV |
666 | /** |
667 | * intel_fbc_init - Initialize FBC | |
668 | * @dev_priv: the i915 device | |
669 | * | |
670 | * This function might be called during PM init process. | |
671 | */ | |
7ff0ebcc RV |
672 | void intel_fbc_init(struct drm_i915_private *dev_priv) |
673 | { | |
674 | if (!HAS_FBC(dev_priv)) { | |
675 | dev_priv->fbc.enabled = false; | |
676 | return; | |
677 | } | |
678 | ||
679 | if (INTEL_INFO(dev_priv)->gen >= 7) { | |
680 | dev_priv->display.fbc_enabled = ilk_fbc_enabled; | |
681 | dev_priv->display.enable_fbc = gen7_fbc_enable; | |
682 | dev_priv->display.disable_fbc = ilk_fbc_disable; | |
683 | } else if (INTEL_INFO(dev_priv)->gen >= 5) { | |
684 | dev_priv->display.fbc_enabled = ilk_fbc_enabled; | |
685 | dev_priv->display.enable_fbc = ilk_fbc_enable; | |
686 | dev_priv->display.disable_fbc = ilk_fbc_disable; | |
687 | } else if (IS_GM45(dev_priv)) { | |
688 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; | |
689 | dev_priv->display.enable_fbc = g4x_fbc_enable; | |
690 | dev_priv->display.disable_fbc = g4x_fbc_disable; | |
691 | } else { | |
692 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; | |
693 | dev_priv->display.enable_fbc = i8xx_fbc_enable; | |
694 | dev_priv->display.disable_fbc = i8xx_fbc_disable; | |
695 | ||
696 | /* This value was pulled out of someone's hat */ | |
697 | I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT); | |
698 | } | |
699 | ||
700 | dev_priv->fbc.enabled = dev_priv->display.fbc_enabled(dev_priv->dev); | |
701 | } |