Commit | Line | Data |
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7ff0ebcc RV |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
94b83957 RV |
24 | /** |
25 | * DOC: Frame Buffer Compression (FBC) | |
26 | * | |
27 | * FBC tries to save memory bandwidth (and so power consumption) by | |
28 | * compressing the amount of memory used by the display. It is total | |
29 | * transparent to user space and completely handled in the kernel. | |
7ff0ebcc RV |
30 | * |
31 | * The benefits of FBC are mostly visible with solid backgrounds and | |
94b83957 RV |
32 | * variation-less patterns. It comes from keeping the memory footprint small |
33 | * and having fewer memory pages opened and accessed for refreshing the display. | |
7ff0ebcc | 34 | * |
94b83957 RV |
35 | * i915 is responsible to reserve stolen memory for FBC and configure its |
36 | * offset on proper registers. The hardware takes care of all | |
37 | * compress/decompress. However there are many known cases where we have to | |
38 | * forcibly disable it to allow proper screen updates. | |
7ff0ebcc RV |
39 | */ |
40 | ||
94b83957 RV |
41 | #include "intel_drv.h" |
42 | #include "i915_drv.h" | |
43 | ||
2db3366b PZ |
44 | /* |
45 | * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the | |
46 | * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's | |
47 | * origin so the x and y offsets can actually fit the registers. As a | |
48 | * consequence, the fence doesn't really start exactly at the display plane | |
49 | * address we program because it starts at the real start of the buffer, so we | |
50 | * have to take this into consideration here. | |
51 | */ | |
52 | static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc) | |
53 | { | |
54 | return crtc->base.y - crtc->adjusted_y; | |
55 | } | |
56 | ||
7733b49b | 57 | static void i8xx_fbc_disable(struct drm_i915_private *dev_priv) |
7ff0ebcc | 58 | { |
7ff0ebcc RV |
59 | u32 fbc_ctl; |
60 | ||
61 | dev_priv->fbc.enabled = false; | |
62 | ||
63 | /* Disable compression */ | |
64 | fbc_ctl = I915_READ(FBC_CONTROL); | |
65 | if ((fbc_ctl & FBC_CTL_EN) == 0) | |
66 | return; | |
67 | ||
68 | fbc_ctl &= ~FBC_CTL_EN; | |
69 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
70 | ||
71 | /* Wait for compressing bit to clear */ | |
72 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { | |
73 | DRM_DEBUG_KMS("FBC idle timed out\n"); | |
74 | return; | |
75 | } | |
76 | ||
77 | DRM_DEBUG_KMS("disabled FBC\n"); | |
78 | } | |
79 | ||
220285f2 | 80 | static void i8xx_fbc_enable(struct intel_crtc *crtc) |
7ff0ebcc | 81 | { |
220285f2 PZ |
82 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
83 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
7ff0ebcc | 84 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
7ff0ebcc RV |
85 | int cfb_pitch; |
86 | int i; | |
87 | u32 fbc_ctl; | |
88 | ||
89 | dev_priv->fbc.enabled = true; | |
90 | ||
60ee5cd2 JN |
91 | /* Note: fbc.threshold == 1 for i8xx */ |
92 | cfb_pitch = dev_priv->fbc.uncompressed_size / FBC_LL_SIZE; | |
7ff0ebcc RV |
93 | if (fb->pitches[0] < cfb_pitch) |
94 | cfb_pitch = fb->pitches[0]; | |
95 | ||
96 | /* FBC_CTL wants 32B or 64B units */ | |
7733b49b | 97 | if (IS_GEN2(dev_priv)) |
7ff0ebcc RV |
98 | cfb_pitch = (cfb_pitch / 32) - 1; |
99 | else | |
100 | cfb_pitch = (cfb_pitch / 64) - 1; | |
101 | ||
102 | /* Clear old tags */ | |
103 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) | |
4d110c71 | 104 | I915_WRITE(FBC_TAG(i), 0); |
7ff0ebcc | 105 | |
7733b49b | 106 | if (IS_GEN4(dev_priv)) { |
7ff0ebcc RV |
107 | u32 fbc_ctl2; |
108 | ||
109 | /* Set it up... */ | |
110 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; | |
220285f2 | 111 | fbc_ctl2 |= FBC_CTL_PLANE(crtc->plane); |
7ff0ebcc | 112 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
2db3366b | 113 | I915_WRITE(FBC_FENCE_OFF, get_crtc_fence_y_offset(crtc)); |
7ff0ebcc RV |
114 | } |
115 | ||
116 | /* enable it... */ | |
117 | fbc_ctl = I915_READ(FBC_CONTROL); | |
118 | fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT; | |
119 | fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC; | |
7733b49b | 120 | if (IS_I945GM(dev_priv)) |
7ff0ebcc RV |
121 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
122 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; | |
123 | fbc_ctl |= obj->fence_reg; | |
124 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
125 | ||
126 | DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n", | |
220285f2 | 127 | cfb_pitch, crtc->base.y, plane_name(crtc->plane)); |
7ff0ebcc RV |
128 | } |
129 | ||
7733b49b | 130 | static bool i8xx_fbc_enabled(struct drm_i915_private *dev_priv) |
7ff0ebcc | 131 | { |
7ff0ebcc RV |
132 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; |
133 | } | |
134 | ||
220285f2 | 135 | static void g4x_fbc_enable(struct intel_crtc *crtc) |
7ff0ebcc | 136 | { |
220285f2 PZ |
137 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
138 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
7ff0ebcc | 139 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
7ff0ebcc RV |
140 | u32 dpfc_ctl; |
141 | ||
142 | dev_priv->fbc.enabled = true; | |
143 | ||
220285f2 | 144 | dpfc_ctl = DPFC_CTL_PLANE(crtc->plane) | DPFC_SR_EN; |
7ff0ebcc RV |
145 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
146 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
147 | else | |
148 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
149 | dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; | |
150 | ||
2db3366b | 151 | I915_WRITE(DPFC_FENCE_YOFF, get_crtc_fence_y_offset(crtc)); |
7ff0ebcc RV |
152 | |
153 | /* enable it... */ | |
154 | I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
155 | ||
220285f2 | 156 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane)); |
7ff0ebcc RV |
157 | } |
158 | ||
7733b49b | 159 | static void g4x_fbc_disable(struct drm_i915_private *dev_priv) |
7ff0ebcc | 160 | { |
7ff0ebcc RV |
161 | u32 dpfc_ctl; |
162 | ||
163 | dev_priv->fbc.enabled = false; | |
164 | ||
165 | /* Disable compression */ | |
166 | dpfc_ctl = I915_READ(DPFC_CONTROL); | |
167 | if (dpfc_ctl & DPFC_CTL_EN) { | |
168 | dpfc_ctl &= ~DPFC_CTL_EN; | |
169 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); | |
170 | ||
171 | DRM_DEBUG_KMS("disabled FBC\n"); | |
172 | } | |
173 | } | |
174 | ||
7733b49b | 175 | static bool g4x_fbc_enabled(struct drm_i915_private *dev_priv) |
7ff0ebcc | 176 | { |
7ff0ebcc RV |
177 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; |
178 | } | |
179 | ||
dbef0f15 | 180 | static void intel_fbc_nuke(struct drm_i915_private *dev_priv) |
7ff0ebcc | 181 | { |
dbef0f15 PZ |
182 | I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE); |
183 | POSTING_READ(MSG_FBC_REND_STATE); | |
7ff0ebcc RV |
184 | } |
185 | ||
220285f2 | 186 | static void ilk_fbc_enable(struct intel_crtc *crtc) |
7ff0ebcc | 187 | { |
220285f2 PZ |
188 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
189 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
7ff0ebcc | 190 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
7ff0ebcc | 191 | u32 dpfc_ctl; |
ce65e47b | 192 | int threshold = dev_priv->fbc.threshold; |
2db3366b | 193 | unsigned int y_offset; |
7ff0ebcc RV |
194 | |
195 | dev_priv->fbc.enabled = true; | |
196 | ||
220285f2 | 197 | dpfc_ctl = DPFC_CTL_PLANE(crtc->plane); |
7ff0ebcc | 198 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
ce65e47b | 199 | threshold++; |
7ff0ebcc | 200 | |
ce65e47b | 201 | switch (threshold) { |
7ff0ebcc RV |
202 | case 4: |
203 | case 3: | |
204 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; | |
205 | break; | |
206 | case 2: | |
207 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
208 | break; | |
209 | case 1: | |
210 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
211 | break; | |
212 | } | |
213 | dpfc_ctl |= DPFC_CTL_FENCE_EN; | |
7733b49b | 214 | if (IS_GEN5(dev_priv)) |
7ff0ebcc RV |
215 | dpfc_ctl |= obj->fence_reg; |
216 | ||
2db3366b PZ |
217 | y_offset = get_crtc_fence_y_offset(crtc); |
218 | I915_WRITE(ILK_DPFC_FENCE_YOFF, y_offset); | |
7ff0ebcc RV |
219 | I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID); |
220 | /* enable it... */ | |
221 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
222 | ||
7733b49b | 223 | if (IS_GEN6(dev_priv)) { |
7ff0ebcc RV |
224 | I915_WRITE(SNB_DPFC_CTL_SA, |
225 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); | |
2db3366b | 226 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, y_offset); |
7ff0ebcc RV |
227 | } |
228 | ||
dbef0f15 PZ |
229 | intel_fbc_nuke(dev_priv); |
230 | ||
220285f2 | 231 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane)); |
7ff0ebcc RV |
232 | } |
233 | ||
7733b49b | 234 | static void ilk_fbc_disable(struct drm_i915_private *dev_priv) |
7ff0ebcc | 235 | { |
7ff0ebcc RV |
236 | u32 dpfc_ctl; |
237 | ||
238 | dev_priv->fbc.enabled = false; | |
239 | ||
240 | /* Disable compression */ | |
241 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
242 | if (dpfc_ctl & DPFC_CTL_EN) { | |
243 | dpfc_ctl &= ~DPFC_CTL_EN; | |
244 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); | |
245 | ||
246 | DRM_DEBUG_KMS("disabled FBC\n"); | |
247 | } | |
248 | } | |
249 | ||
7733b49b | 250 | static bool ilk_fbc_enabled(struct drm_i915_private *dev_priv) |
7ff0ebcc | 251 | { |
7ff0ebcc RV |
252 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; |
253 | } | |
254 | ||
220285f2 | 255 | static void gen7_fbc_enable(struct intel_crtc *crtc) |
7ff0ebcc | 256 | { |
220285f2 PZ |
257 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
258 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
7ff0ebcc | 259 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
7ff0ebcc | 260 | u32 dpfc_ctl; |
ce65e47b | 261 | int threshold = dev_priv->fbc.threshold; |
7ff0ebcc RV |
262 | |
263 | dev_priv->fbc.enabled = true; | |
264 | ||
d8514d63 | 265 | dpfc_ctl = 0; |
7733b49b | 266 | if (IS_IVYBRIDGE(dev_priv)) |
220285f2 | 267 | dpfc_ctl |= IVB_DPFC_CTL_PLANE(crtc->plane); |
d8514d63 | 268 | |
7ff0ebcc | 269 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
ce65e47b | 270 | threshold++; |
7ff0ebcc | 271 | |
ce65e47b | 272 | switch (threshold) { |
7ff0ebcc RV |
273 | case 4: |
274 | case 3: | |
275 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; | |
276 | break; | |
277 | case 2: | |
278 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
279 | break; | |
280 | case 1: | |
281 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
282 | break; | |
283 | } | |
284 | ||
285 | dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; | |
286 | ||
287 | if (dev_priv->fbc.false_color) | |
288 | dpfc_ctl |= FBC_CTL_FALSE_COLOR; | |
289 | ||
7733b49b | 290 | if (IS_IVYBRIDGE(dev_priv)) { |
7ff0ebcc RV |
291 | /* WaFbcAsynchFlipDisableFbcQueue:ivb */ |
292 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
293 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
294 | ILK_FBCQ_DIS); | |
40f4022e | 295 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
7ff0ebcc | 296 | /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ |
220285f2 PZ |
297 | I915_WRITE(CHICKEN_PIPESL_1(crtc->pipe), |
298 | I915_READ(CHICKEN_PIPESL_1(crtc->pipe)) | | |
7ff0ebcc RV |
299 | HSW_FBCQ_DIS); |
300 | } | |
301 | ||
57012be9 PZ |
302 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
303 | ||
7ff0ebcc RV |
304 | I915_WRITE(SNB_DPFC_CTL_SA, |
305 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); | |
2db3366b | 306 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, get_crtc_fence_y_offset(crtc)); |
7ff0ebcc | 307 | |
dbef0f15 | 308 | intel_fbc_nuke(dev_priv); |
7ff0ebcc | 309 | |
220285f2 | 310 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane)); |
7ff0ebcc RV |
311 | } |
312 | ||
94b83957 RV |
313 | /** |
314 | * intel_fbc_enabled - Is FBC enabled? | |
7733b49b | 315 | * @dev_priv: i915 device instance |
94b83957 RV |
316 | * |
317 | * This function is used to verify the current state of FBC. | |
318 | * FIXME: This should be tracked in the plane config eventually | |
319 | * instead of queried at runtime for most callers. | |
320 | */ | |
7733b49b | 321 | bool intel_fbc_enabled(struct drm_i915_private *dev_priv) |
7ff0ebcc | 322 | { |
7ff0ebcc RV |
323 | return dev_priv->fbc.enabled; |
324 | } | |
325 | ||
e8cb8d69 PZ |
326 | static void intel_fbc_enable(struct intel_crtc *crtc, |
327 | const struct drm_framebuffer *fb) | |
328 | { | |
329 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
330 | ||
331 | dev_priv->fbc.enable_fbc(crtc); | |
332 | ||
333 | dev_priv->fbc.crtc = crtc; | |
334 | dev_priv->fbc.fb_id = fb->base.id; | |
335 | dev_priv->fbc.y = crtc->base.y; | |
336 | } | |
337 | ||
7ff0ebcc RV |
338 | static void intel_fbc_work_fn(struct work_struct *__work) |
339 | { | |
340 | struct intel_fbc_work *work = | |
341 | container_of(to_delayed_work(__work), | |
342 | struct intel_fbc_work, work); | |
220285f2 PZ |
343 | struct drm_i915_private *dev_priv = work->crtc->base.dev->dev_private; |
344 | struct drm_framebuffer *crtc_fb = work->crtc->base.primary->fb; | |
7ff0ebcc | 345 | |
25ad93fd | 346 | mutex_lock(&dev_priv->fbc.lock); |
7ff0ebcc RV |
347 | if (work == dev_priv->fbc.fbc_work) { |
348 | /* Double check that we haven't switched fb without cancelling | |
349 | * the prior work. | |
350 | */ | |
e8cb8d69 PZ |
351 | if (crtc_fb == work->fb) |
352 | intel_fbc_enable(work->crtc, work->fb); | |
7ff0ebcc RV |
353 | |
354 | dev_priv->fbc.fbc_work = NULL; | |
355 | } | |
25ad93fd | 356 | mutex_unlock(&dev_priv->fbc.lock); |
7ff0ebcc RV |
357 | |
358 | kfree(work); | |
359 | } | |
360 | ||
361 | static void intel_fbc_cancel_work(struct drm_i915_private *dev_priv) | |
362 | { | |
25ad93fd PZ |
363 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
364 | ||
7ff0ebcc RV |
365 | if (dev_priv->fbc.fbc_work == NULL) |
366 | return; | |
367 | ||
368 | DRM_DEBUG_KMS("cancelling pending FBC enable\n"); | |
369 | ||
370 | /* Synchronisation is provided by struct_mutex and checking of | |
371 | * dev_priv->fbc.fbc_work, so we can perform the cancellation | |
372 | * entirely asynchronously. | |
373 | */ | |
374 | if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work)) | |
375 | /* tasklet was killed before being run, clean up */ | |
376 | kfree(dev_priv->fbc.fbc_work); | |
377 | ||
378 | /* Mark the work as no longer wanted so that if it does | |
379 | * wake-up (because the work was already running and waiting | |
380 | * for our mutex), it will discover that is no longer | |
381 | * necessary to run. | |
382 | */ | |
383 | dev_priv->fbc.fbc_work = NULL; | |
384 | } | |
385 | ||
e8cb8d69 | 386 | static void intel_fbc_schedule_enable(struct intel_crtc *crtc) |
7ff0ebcc RV |
387 | { |
388 | struct intel_fbc_work *work; | |
220285f2 | 389 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
7ff0ebcc | 390 | |
25ad93fd PZ |
391 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
392 | ||
7ff0ebcc RV |
393 | intel_fbc_cancel_work(dev_priv); |
394 | ||
395 | work = kzalloc(sizeof(*work), GFP_KERNEL); | |
396 | if (work == NULL) { | |
397 | DRM_ERROR("Failed to allocate FBC work structure\n"); | |
e8cb8d69 | 398 | intel_fbc_enable(crtc, crtc->base.primary->fb); |
7ff0ebcc RV |
399 | return; |
400 | } | |
401 | ||
402 | work->crtc = crtc; | |
220285f2 | 403 | work->fb = crtc->base.primary->fb; |
7ff0ebcc RV |
404 | INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); |
405 | ||
406 | dev_priv->fbc.fbc_work = work; | |
407 | ||
408 | /* Delay the actual enabling to let pageflipping cease and the | |
409 | * display to settle before starting the compression. Note that | |
410 | * this delay also serves a second purpose: it allows for a | |
411 | * vblank to pass after disabling the FBC before we attempt | |
412 | * to modify the control registers. | |
413 | * | |
414 | * A more complicated solution would involve tracking vblanks | |
415 | * following the termination of the page-flipping sequence | |
416 | * and indeed performing the enable as a co-routine and not | |
417 | * waiting synchronously upon the vblank. | |
418 | * | |
419 | * WaFbcWaitForVBlankBeforeEnable:ilk,snb | |
420 | */ | |
421 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); | |
422 | } | |
423 | ||
7733b49b | 424 | static void __intel_fbc_disable(struct drm_i915_private *dev_priv) |
25ad93fd | 425 | { |
25ad93fd PZ |
426 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
427 | ||
428 | intel_fbc_cancel_work(dev_priv); | |
429 | ||
7733b49b | 430 | dev_priv->fbc.disable_fbc(dev_priv); |
25ad93fd PZ |
431 | dev_priv->fbc.crtc = NULL; |
432 | } | |
433 | ||
94b83957 RV |
434 | /** |
435 | * intel_fbc_disable - disable FBC | |
7733b49b | 436 | * @dev_priv: i915 device instance |
94b83957 RV |
437 | * |
438 | * This function disables FBC. | |
439 | */ | |
7733b49b | 440 | void intel_fbc_disable(struct drm_i915_private *dev_priv) |
7ff0ebcc | 441 | { |
ff2a3117 | 442 | if (!dev_priv->fbc.enable_fbc) |
0bf73c36 PZ |
443 | return; |
444 | ||
25ad93fd | 445 | mutex_lock(&dev_priv->fbc.lock); |
7733b49b | 446 | __intel_fbc_disable(dev_priv); |
25ad93fd PZ |
447 | mutex_unlock(&dev_priv->fbc.lock); |
448 | } | |
7ff0ebcc | 449 | |
25ad93fd PZ |
450 | /* |
451 | * intel_fbc_disable_crtc - disable FBC if it's associated with crtc | |
452 | * @crtc: the CRTC | |
453 | * | |
454 | * This function disables FBC if it's associated with the provided CRTC. | |
455 | */ | |
456 | void intel_fbc_disable_crtc(struct intel_crtc *crtc) | |
457 | { | |
7733b49b | 458 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
7ff0ebcc | 459 | |
ff2a3117 | 460 | if (!dev_priv->fbc.enable_fbc) |
0bf73c36 PZ |
461 | return; |
462 | ||
25ad93fd PZ |
463 | mutex_lock(&dev_priv->fbc.lock); |
464 | if (dev_priv->fbc.crtc == crtc) | |
7733b49b | 465 | __intel_fbc_disable(dev_priv); |
25ad93fd | 466 | mutex_unlock(&dev_priv->fbc.lock); |
7ff0ebcc RV |
467 | } |
468 | ||
2e8144a5 PZ |
469 | const char *intel_no_fbc_reason_str(enum no_fbc_reason reason) |
470 | { | |
471 | switch (reason) { | |
472 | case FBC_OK: | |
473 | return "FBC enabled but currently disabled in hardware"; | |
474 | case FBC_UNSUPPORTED: | |
475 | return "unsupported by this chipset"; | |
476 | case FBC_NO_OUTPUT: | |
477 | return "no output"; | |
478 | case FBC_STOLEN_TOO_SMALL: | |
479 | return "not enough stolen memory"; | |
480 | case FBC_UNSUPPORTED_MODE: | |
481 | return "mode incompatible with compression"; | |
482 | case FBC_MODE_TOO_LARGE: | |
483 | return "mode too large for compression"; | |
484 | case FBC_BAD_PLANE: | |
485 | return "FBC unsupported on plane"; | |
486 | case FBC_NOT_TILED: | |
487 | return "framebuffer not tiled or fenced"; | |
488 | case FBC_MULTIPLE_PIPES: | |
489 | return "more than one pipe active"; | |
490 | case FBC_MODULE_PARAM: | |
491 | return "disabled per module param"; | |
492 | case FBC_CHIP_DEFAULT: | |
493 | return "disabled per chip default"; | |
494 | case FBC_ROTATION: | |
495 | return "rotation unsupported"; | |
89351085 PZ |
496 | case FBC_IN_DBG_MASTER: |
497 | return "Kernel debugger is active"; | |
adf70c65 PZ |
498 | case FBC_BAD_STRIDE: |
499 | return "framebuffer stride not supported"; | |
7b24c9a6 PZ |
500 | case FBC_PIXEL_RATE: |
501 | return "pixel rate is too big"; | |
b9e831dc PZ |
502 | case FBC_PIXEL_FORMAT: |
503 | return "pixel format is invalid"; | |
2e8144a5 PZ |
504 | default: |
505 | MISSING_CASE(reason); | |
506 | return "unknown reason"; | |
507 | } | |
508 | } | |
509 | ||
510 | static void set_no_fbc_reason(struct drm_i915_private *dev_priv, | |
7ff0ebcc RV |
511 | enum no_fbc_reason reason) |
512 | { | |
513 | if (dev_priv->fbc.no_fbc_reason == reason) | |
2e8144a5 | 514 | return; |
7ff0ebcc RV |
515 | |
516 | dev_priv->fbc.no_fbc_reason = reason; | |
2e8144a5 | 517 | DRM_DEBUG_KMS("Disabling FBC: %s\n", intel_no_fbc_reason_str(reason)); |
7ff0ebcc RV |
518 | } |
519 | ||
95106753 PZ |
520 | static struct drm_crtc *intel_fbc_find_crtc(struct drm_i915_private *dev_priv) |
521 | { | |
95106753 | 522 | struct drm_crtc *crtc = NULL, *tmp_crtc; |
68b92147 | 523 | enum pipe pipe; |
232fd934 | 524 | bool pipe_a_only = false; |
68b92147 PZ |
525 | |
526 | if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) | |
527 | pipe_a_only = true; | |
528 | ||
529 | for_each_pipe(dev_priv, pipe) { | |
530 | tmp_crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
95106753 | 531 | |
95106753 | 532 | if (intel_crtc_active(tmp_crtc) && |
232fd934 | 533 | to_intel_plane_state(tmp_crtc->primary->state)->visible) |
95106753 | 534 | crtc = tmp_crtc; |
68b92147 PZ |
535 | |
536 | if (pipe_a_only) | |
537 | break; | |
95106753 PZ |
538 | } |
539 | ||
8df5dd57 | 540 | if (!crtc || crtc->primary->fb == NULL) |
95106753 | 541 | return NULL; |
95106753 PZ |
542 | |
543 | return crtc; | |
544 | } | |
545 | ||
232fd934 PZ |
546 | static bool multiple_pipes_ok(struct drm_i915_private *dev_priv) |
547 | { | |
548 | enum pipe pipe; | |
549 | int n_pipes = 0; | |
550 | struct drm_crtc *crtc; | |
551 | ||
552 | if (INTEL_INFO(dev_priv)->gen > 4) | |
553 | return true; | |
554 | ||
555 | for_each_pipe(dev_priv, pipe) { | |
556 | crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
557 | ||
558 | if (intel_crtc_active(crtc) && | |
559 | to_intel_plane_state(crtc->primary->state)->visible) | |
560 | n_pipes++; | |
561 | } | |
562 | ||
563 | return (n_pipes < 2); | |
564 | } | |
565 | ||
7733b49b | 566 | static int find_compression_threshold(struct drm_i915_private *dev_priv, |
fc786728 PZ |
567 | struct drm_mm_node *node, |
568 | int size, | |
569 | int fb_cpp) | |
570 | { | |
fc786728 PZ |
571 | int compression_threshold = 1; |
572 | int ret; | |
a9da512b PZ |
573 | u64 end; |
574 | ||
575 | /* The FBC hardware for BDW/SKL doesn't have access to the stolen | |
576 | * reserved range size, so it always assumes the maximum (8mb) is used. | |
577 | * If we enable FBC using a CFB on that memory range we'll get FIFO | |
578 | * underruns, even if that range is not reserved by the BIOS. */ | |
579 | if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv)) | |
580 | end = dev_priv->gtt.stolen_size - 8 * 1024 * 1024; | |
581 | else | |
582 | end = dev_priv->gtt.stolen_usable_size; | |
fc786728 PZ |
583 | |
584 | /* HACK: This code depends on what we will do in *_enable_fbc. If that | |
585 | * code changes, this code needs to change as well. | |
586 | * | |
587 | * The enable_fbc code will attempt to use one of our 2 compression | |
588 | * thresholds, therefore, in that case, we only have 1 resort. | |
589 | */ | |
590 | ||
591 | /* Try to over-allocate to reduce reallocations and fragmentation. */ | |
a9da512b PZ |
592 | ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1, |
593 | 4096, 0, end); | |
fc786728 PZ |
594 | if (ret == 0) |
595 | return compression_threshold; | |
596 | ||
597 | again: | |
598 | /* HW's ability to limit the CFB is 1:4 */ | |
599 | if (compression_threshold > 4 || | |
600 | (fb_cpp == 2 && compression_threshold == 2)) | |
601 | return 0; | |
602 | ||
a9da512b PZ |
603 | ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1, |
604 | 4096, 0, end); | |
7733b49b | 605 | if (ret && INTEL_INFO(dev_priv)->gen <= 4) { |
fc786728 PZ |
606 | return 0; |
607 | } else if (ret) { | |
608 | compression_threshold <<= 1; | |
609 | goto again; | |
610 | } else { | |
611 | return compression_threshold; | |
612 | } | |
613 | } | |
614 | ||
7733b49b PZ |
615 | static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv, int size, |
616 | int fb_cpp) | |
fc786728 | 617 | { |
fc786728 PZ |
618 | struct drm_mm_node *uninitialized_var(compressed_llb); |
619 | int ret; | |
620 | ||
7733b49b | 621 | ret = find_compression_threshold(dev_priv, &dev_priv->fbc.compressed_fb, |
fc786728 PZ |
622 | size, fb_cpp); |
623 | if (!ret) | |
624 | goto err_llb; | |
625 | else if (ret > 1) { | |
626 | DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n"); | |
627 | ||
628 | } | |
629 | ||
630 | dev_priv->fbc.threshold = ret; | |
631 | ||
632 | if (INTEL_INFO(dev_priv)->gen >= 5) | |
633 | I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start); | |
7733b49b | 634 | else if (IS_GM45(dev_priv)) { |
fc786728 PZ |
635 | I915_WRITE(DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start); |
636 | } else { | |
637 | compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL); | |
638 | if (!compressed_llb) | |
639 | goto err_fb; | |
640 | ||
641 | ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb, | |
642 | 4096, 4096); | |
643 | if (ret) | |
644 | goto err_fb; | |
645 | ||
646 | dev_priv->fbc.compressed_llb = compressed_llb; | |
647 | ||
648 | I915_WRITE(FBC_CFB_BASE, | |
649 | dev_priv->mm.stolen_base + dev_priv->fbc.compressed_fb.start); | |
650 | I915_WRITE(FBC_LL_BASE, | |
651 | dev_priv->mm.stolen_base + compressed_llb->start); | |
652 | } | |
653 | ||
654 | dev_priv->fbc.uncompressed_size = size; | |
655 | ||
b8bf5d7f PZ |
656 | DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n", |
657 | dev_priv->fbc.compressed_fb.size, | |
658 | dev_priv->fbc.threshold); | |
fc786728 PZ |
659 | |
660 | return 0; | |
661 | ||
662 | err_fb: | |
663 | kfree(compressed_llb); | |
664 | i915_gem_stolen_remove_node(dev_priv, &dev_priv->fbc.compressed_fb); | |
665 | err_llb: | |
666 | pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size); | |
667 | return -ENOSPC; | |
668 | } | |
669 | ||
7733b49b | 670 | static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) |
fc786728 | 671 | { |
fc786728 PZ |
672 | if (dev_priv->fbc.uncompressed_size == 0) |
673 | return; | |
674 | ||
675 | i915_gem_stolen_remove_node(dev_priv, &dev_priv->fbc.compressed_fb); | |
676 | ||
677 | if (dev_priv->fbc.compressed_llb) { | |
678 | i915_gem_stolen_remove_node(dev_priv, | |
679 | dev_priv->fbc.compressed_llb); | |
680 | kfree(dev_priv->fbc.compressed_llb); | |
681 | } | |
682 | ||
683 | dev_priv->fbc.uncompressed_size = 0; | |
684 | } | |
685 | ||
7733b49b | 686 | void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) |
25ad93fd | 687 | { |
ff2a3117 | 688 | if (!dev_priv->fbc.enable_fbc) |
0bf73c36 PZ |
689 | return; |
690 | ||
25ad93fd | 691 | mutex_lock(&dev_priv->fbc.lock); |
7733b49b | 692 | __intel_fbc_cleanup_cfb(dev_priv); |
25ad93fd PZ |
693 | mutex_unlock(&dev_priv->fbc.lock); |
694 | } | |
695 | ||
7733b49b PZ |
696 | static int intel_fbc_setup_cfb(struct drm_i915_private *dev_priv, int size, |
697 | int fb_cpp) | |
fc786728 | 698 | { |
fc786728 PZ |
699 | if (size <= dev_priv->fbc.uncompressed_size) |
700 | return 0; | |
701 | ||
702 | /* Release any current block */ | |
7733b49b | 703 | __intel_fbc_cleanup_cfb(dev_priv); |
fc786728 | 704 | |
7733b49b | 705 | return intel_fbc_alloc_cfb(dev_priv, size, fb_cpp); |
fc786728 PZ |
706 | } |
707 | ||
adf70c65 PZ |
708 | static bool stride_is_valid(struct drm_i915_private *dev_priv, |
709 | unsigned int stride) | |
710 | { | |
711 | /* These should have been caught earlier. */ | |
712 | WARN_ON(stride < 512); | |
713 | WARN_ON((stride & (64 - 1)) != 0); | |
714 | ||
715 | /* Below are the additional FBC restrictions. */ | |
716 | ||
717 | if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv)) | |
718 | return stride == 4096 || stride == 8192; | |
719 | ||
720 | if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048) | |
721 | return false; | |
722 | ||
723 | if (stride > 16384) | |
724 | return false; | |
725 | ||
726 | return true; | |
727 | } | |
728 | ||
b9e831dc PZ |
729 | static bool pixel_format_is_valid(struct drm_framebuffer *fb) |
730 | { | |
731 | struct drm_device *dev = fb->dev; | |
732 | struct drm_i915_private *dev_priv = dev->dev_private; | |
733 | ||
734 | switch (fb->pixel_format) { | |
735 | case DRM_FORMAT_XRGB8888: | |
736 | case DRM_FORMAT_XBGR8888: | |
737 | return true; | |
738 | case DRM_FORMAT_XRGB1555: | |
739 | case DRM_FORMAT_RGB565: | |
740 | /* 16bpp not supported on gen2 */ | |
741 | if (IS_GEN2(dev)) | |
742 | return false; | |
743 | /* WaFbcOnly1to1Ratio:ctg */ | |
744 | if (IS_G4X(dev_priv)) | |
745 | return false; | |
746 | return true; | |
747 | default: | |
748 | return false; | |
749 | } | |
750 | } | |
751 | ||
7ff0ebcc | 752 | /** |
25ad93fd | 753 | * __intel_fbc_update - enable/disable FBC as needed, unlocked |
7733b49b | 754 | * @dev_priv: i915 device instance |
7ff0ebcc RV |
755 | * |
756 | * Set up the framebuffer compression hardware at mode set time. We | |
757 | * enable it if possible: | |
758 | * - plane A only (on pre-965) | |
759 | * - no pixel mulitply/line duplication | |
760 | * - no alpha buffer discard | |
761 | * - no dual wide | |
762 | * - framebuffer <= max_hdisplay in width, max_vdisplay in height | |
763 | * | |
764 | * We can't assume that any compression will take place (worst case), | |
765 | * so the compressed buffer has to be the same size as the uncompressed | |
766 | * one. It also must reside (along with the line length buffer) in | |
767 | * stolen memory. | |
768 | * | |
769 | * We need to enable/disable FBC on a global basis. | |
770 | */ | |
7733b49b | 771 | static void __intel_fbc_update(struct drm_i915_private *dev_priv) |
7ff0ebcc | 772 | { |
95106753 | 773 | struct drm_crtc *crtc = NULL; |
7ff0ebcc RV |
774 | struct intel_crtc *intel_crtc; |
775 | struct drm_framebuffer *fb; | |
776 | struct drm_i915_gem_object *obj; | |
777 | const struct drm_display_mode *adjusted_mode; | |
778 | unsigned int max_width, max_height; | |
779 | ||
25ad93fd PZ |
780 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
781 | ||
bd49234b | 782 | /* disable framebuffer compression in vGPU */ |
7733b49b | 783 | if (intel_vgpu_active(dev_priv->dev)) |
bd49234b YZ |
784 | i915.enable_fbc = 0; |
785 | ||
7cc65746 | 786 | if (i915.enable_fbc < 0) { |
2e8144a5 | 787 | set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT); |
7cc65746 PZ |
788 | goto out_disable; |
789 | } | |
790 | ||
ab585dea | 791 | if (!i915.enable_fbc) { |
2e8144a5 | 792 | set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM); |
7cc65746 | 793 | goto out_disable; |
7ff0ebcc RV |
794 | } |
795 | ||
796 | /* | |
797 | * If FBC is already on, we just have to verify that we can | |
798 | * keep it that way... | |
799 | * Need to disable if: | |
800 | * - more than one pipe is active | |
801 | * - changing FBC params (stride, fence, mode) | |
802 | * - new fb is too large to fit in compressed buffer | |
803 | * - going to an unsupported config (interlace, pixel multiply, etc.) | |
804 | */ | |
95106753 | 805 | crtc = intel_fbc_find_crtc(dev_priv); |
8df5dd57 PZ |
806 | if (!crtc) { |
807 | set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT); | |
7ff0ebcc | 808 | goto out_disable; |
8df5dd57 | 809 | } |
7ff0ebcc | 810 | |
232fd934 PZ |
811 | if (!multiple_pipes_ok(dev_priv)) { |
812 | set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES); | |
813 | goto out_disable; | |
814 | } | |
815 | ||
7ff0ebcc RV |
816 | intel_crtc = to_intel_crtc(crtc); |
817 | fb = crtc->primary->fb; | |
818 | obj = intel_fb_obj(fb); | |
6e3c9717 | 819 | adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
7ff0ebcc | 820 | |
7ff0ebcc RV |
821 | if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) || |
822 | (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) { | |
2e8144a5 | 823 | set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE); |
7ff0ebcc RV |
824 | goto out_disable; |
825 | } | |
826 | ||
7733b49b | 827 | if (INTEL_INFO(dev_priv)->gen >= 8 || IS_HASWELL(dev_priv)) { |
7ff0ebcc RV |
828 | max_width = 4096; |
829 | max_height = 4096; | |
7733b49b | 830 | } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { |
7ff0ebcc RV |
831 | max_width = 4096; |
832 | max_height = 2048; | |
833 | } else { | |
834 | max_width = 2048; | |
835 | max_height = 1536; | |
836 | } | |
6e3c9717 ACO |
837 | if (intel_crtc->config->pipe_src_w > max_width || |
838 | intel_crtc->config->pipe_src_h > max_height) { | |
2e8144a5 | 839 | set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE); |
7ff0ebcc RV |
840 | goto out_disable; |
841 | } | |
7733b49b | 842 | if ((INTEL_INFO(dev_priv)->gen < 4 || HAS_DDI(dev_priv)) && |
7ff0ebcc | 843 | intel_crtc->plane != PLANE_A) { |
2e8144a5 | 844 | set_no_fbc_reason(dev_priv, FBC_BAD_PLANE); |
7ff0ebcc RV |
845 | goto out_disable; |
846 | } | |
847 | ||
848 | /* The use of a CPU fence is mandatory in order to detect writes | |
849 | * by the CPU to the scanout and trigger updates to the FBC. | |
850 | */ | |
851 | if (obj->tiling_mode != I915_TILING_X || | |
852 | obj->fence_reg == I915_FENCE_REG_NONE) { | |
2e8144a5 | 853 | set_no_fbc_reason(dev_priv, FBC_NOT_TILED); |
7ff0ebcc RV |
854 | goto out_disable; |
855 | } | |
7733b49b | 856 | if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) && |
8e7d688b | 857 | crtc->primary->state->rotation != BIT(DRM_ROTATE_0)) { |
2e8144a5 | 858 | set_no_fbc_reason(dev_priv, FBC_ROTATION); |
7ff0ebcc RV |
859 | goto out_disable; |
860 | } | |
861 | ||
adf70c65 PZ |
862 | if (!stride_is_valid(dev_priv, fb->pitches[0])) { |
863 | set_no_fbc_reason(dev_priv, FBC_BAD_STRIDE); | |
864 | goto out_disable; | |
865 | } | |
866 | ||
b9e831dc PZ |
867 | if (!pixel_format_is_valid(fb)) { |
868 | set_no_fbc_reason(dev_priv, FBC_PIXEL_FORMAT); | |
869 | goto out_disable; | |
870 | } | |
871 | ||
7ff0ebcc | 872 | /* If the kernel debugger is active, always disable compression */ |
89351085 PZ |
873 | if (in_dbg_master()) { |
874 | set_no_fbc_reason(dev_priv, FBC_IN_DBG_MASTER); | |
7ff0ebcc | 875 | goto out_disable; |
89351085 | 876 | } |
7ff0ebcc | 877 | |
7b24c9a6 PZ |
878 | /* WaFbcExceedCdClockThreshold:hsw,bdw */ |
879 | if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) && | |
880 | ilk_pipe_pixel_rate(intel_crtc->config) >= | |
881 | dev_priv->cdclk_freq * 95 / 100) { | |
882 | set_no_fbc_reason(dev_priv, FBC_PIXEL_RATE); | |
883 | goto out_disable; | |
884 | } | |
885 | ||
7733b49b | 886 | if (intel_fbc_setup_cfb(dev_priv, obj->base.size, |
fc786728 | 887 | drm_format_plane_cpp(fb->pixel_format, 0))) { |
2e8144a5 | 888 | set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL); |
7ff0ebcc RV |
889 | goto out_disable; |
890 | } | |
891 | ||
892 | /* If the scanout has not changed, don't modify the FBC settings. | |
893 | * Note that we make the fundamental assumption that the fb->obj | |
894 | * cannot be unpinned (and have its GTT offset and fence revoked) | |
895 | * without first being decoupled from the scanout and FBC disabled. | |
896 | */ | |
e35fef21 | 897 | if (dev_priv->fbc.crtc == intel_crtc && |
7ff0ebcc RV |
898 | dev_priv->fbc.fb_id == fb->base.id && |
899 | dev_priv->fbc.y == crtc->y) | |
900 | return; | |
901 | ||
7733b49b | 902 | if (intel_fbc_enabled(dev_priv)) { |
7ff0ebcc RV |
903 | /* We update FBC along two paths, after changing fb/crtc |
904 | * configuration (modeswitching) and after page-flipping | |
905 | * finishes. For the latter, we know that not only did | |
906 | * we disable the FBC at the start of the page-flip | |
907 | * sequence, but also more than one vblank has passed. | |
908 | * | |
909 | * For the former case of modeswitching, it is possible | |
910 | * to switch between two FBC valid configurations | |
911 | * instantaneously so we do need to disable the FBC | |
912 | * before we can modify its control registers. We also | |
913 | * have to wait for the next vblank for that to take | |
914 | * effect. However, since we delay enabling FBC we can | |
915 | * assume that a vblank has passed since disabling and | |
916 | * that we can safely alter the registers in the deferred | |
917 | * callback. | |
918 | * | |
919 | * In the scenario that we go from a valid to invalid | |
920 | * and then back to valid FBC configuration we have | |
921 | * no strict enforcement that a vblank occurred since | |
922 | * disabling the FBC. However, along all current pipe | |
923 | * disabling paths we do need to wait for a vblank at | |
924 | * some point. And we wait before enabling FBC anyway. | |
925 | */ | |
926 | DRM_DEBUG_KMS("disabling active FBC for update\n"); | |
7733b49b | 927 | __intel_fbc_disable(dev_priv); |
7ff0ebcc RV |
928 | } |
929 | ||
e8cb8d69 | 930 | intel_fbc_schedule_enable(intel_crtc); |
7ff0ebcc RV |
931 | dev_priv->fbc.no_fbc_reason = FBC_OK; |
932 | return; | |
933 | ||
934 | out_disable: | |
935 | /* Multiple disables should be harmless */ | |
7733b49b | 936 | if (intel_fbc_enabled(dev_priv)) { |
7ff0ebcc | 937 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); |
7733b49b | 938 | __intel_fbc_disable(dev_priv); |
7ff0ebcc | 939 | } |
7733b49b | 940 | __intel_fbc_cleanup_cfb(dev_priv); |
25ad93fd PZ |
941 | } |
942 | ||
943 | /* | |
944 | * intel_fbc_update - enable/disable FBC as needed | |
7733b49b | 945 | * @dev_priv: i915 device instance |
25ad93fd PZ |
946 | * |
947 | * This function reevaluates the overall state and enables or disables FBC. | |
948 | */ | |
7733b49b | 949 | void intel_fbc_update(struct drm_i915_private *dev_priv) |
25ad93fd | 950 | { |
ff2a3117 | 951 | if (!dev_priv->fbc.enable_fbc) |
0bf73c36 PZ |
952 | return; |
953 | ||
25ad93fd | 954 | mutex_lock(&dev_priv->fbc.lock); |
7733b49b | 955 | __intel_fbc_update(dev_priv); |
25ad93fd | 956 | mutex_unlock(&dev_priv->fbc.lock); |
7ff0ebcc RV |
957 | } |
958 | ||
dbef0f15 PZ |
959 | void intel_fbc_invalidate(struct drm_i915_private *dev_priv, |
960 | unsigned int frontbuffer_bits, | |
961 | enum fb_op_origin origin) | |
962 | { | |
dbef0f15 PZ |
963 | unsigned int fbc_bits; |
964 | ||
ff2a3117 | 965 | if (!dev_priv->fbc.enable_fbc) |
0bf73c36 PZ |
966 | return; |
967 | ||
dbef0f15 PZ |
968 | if (origin == ORIGIN_GTT) |
969 | return; | |
970 | ||
25ad93fd PZ |
971 | mutex_lock(&dev_priv->fbc.lock); |
972 | ||
dbef0f15 PZ |
973 | if (dev_priv->fbc.enabled) |
974 | fbc_bits = INTEL_FRONTBUFFER_PRIMARY(dev_priv->fbc.crtc->pipe); | |
975 | else if (dev_priv->fbc.fbc_work) | |
976 | fbc_bits = INTEL_FRONTBUFFER_PRIMARY( | |
220285f2 | 977 | dev_priv->fbc.fbc_work->crtc->pipe); |
dbef0f15 PZ |
978 | else |
979 | fbc_bits = dev_priv->fbc.possible_framebuffer_bits; | |
980 | ||
981 | dev_priv->fbc.busy_bits |= (fbc_bits & frontbuffer_bits); | |
982 | ||
983 | if (dev_priv->fbc.busy_bits) | |
7733b49b | 984 | __intel_fbc_disable(dev_priv); |
25ad93fd PZ |
985 | |
986 | mutex_unlock(&dev_priv->fbc.lock); | |
dbef0f15 PZ |
987 | } |
988 | ||
989 | void intel_fbc_flush(struct drm_i915_private *dev_priv, | |
6f4551fe | 990 | unsigned int frontbuffer_bits, enum fb_op_origin origin) |
dbef0f15 | 991 | { |
ff2a3117 | 992 | if (!dev_priv->fbc.enable_fbc) |
0bf73c36 PZ |
993 | return; |
994 | ||
6f4551fe PZ |
995 | if (origin == ORIGIN_GTT) |
996 | return; | |
25ad93fd | 997 | |
6f4551fe | 998 | mutex_lock(&dev_priv->fbc.lock); |
dbef0f15 PZ |
999 | |
1000 | dev_priv->fbc.busy_bits &= ~frontbuffer_bits; | |
1001 | ||
6f4551fe PZ |
1002 | if (!dev_priv->fbc.busy_bits) { |
1003 | __intel_fbc_disable(dev_priv); | |
7733b49b | 1004 | __intel_fbc_update(dev_priv); |
6f4551fe | 1005 | } |
25ad93fd | 1006 | |
25ad93fd | 1007 | mutex_unlock(&dev_priv->fbc.lock); |
dbef0f15 PZ |
1008 | } |
1009 | ||
94b83957 RV |
1010 | /** |
1011 | * intel_fbc_init - Initialize FBC | |
1012 | * @dev_priv: the i915 device | |
1013 | * | |
1014 | * This function might be called during PM init process. | |
1015 | */ | |
7ff0ebcc RV |
1016 | void intel_fbc_init(struct drm_i915_private *dev_priv) |
1017 | { | |
dbef0f15 PZ |
1018 | enum pipe pipe; |
1019 | ||
25ad93fd PZ |
1020 | mutex_init(&dev_priv->fbc.lock); |
1021 | ||
7ff0ebcc RV |
1022 | if (!HAS_FBC(dev_priv)) { |
1023 | dev_priv->fbc.enabled = false; | |
104618b3 | 1024 | dev_priv->fbc.no_fbc_reason = FBC_UNSUPPORTED; |
7ff0ebcc RV |
1025 | return; |
1026 | } | |
1027 | ||
dbef0f15 PZ |
1028 | for_each_pipe(dev_priv, pipe) { |
1029 | dev_priv->fbc.possible_framebuffer_bits |= | |
1030 | INTEL_FRONTBUFFER_PRIMARY(pipe); | |
1031 | ||
1032 | if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) | |
1033 | break; | |
1034 | } | |
1035 | ||
7ff0ebcc | 1036 | if (INTEL_INFO(dev_priv)->gen >= 7) { |
ff2a3117 PZ |
1037 | dev_priv->fbc.fbc_enabled = ilk_fbc_enabled; |
1038 | dev_priv->fbc.enable_fbc = gen7_fbc_enable; | |
1039 | dev_priv->fbc.disable_fbc = ilk_fbc_disable; | |
7ff0ebcc | 1040 | } else if (INTEL_INFO(dev_priv)->gen >= 5) { |
ff2a3117 PZ |
1041 | dev_priv->fbc.fbc_enabled = ilk_fbc_enabled; |
1042 | dev_priv->fbc.enable_fbc = ilk_fbc_enable; | |
1043 | dev_priv->fbc.disable_fbc = ilk_fbc_disable; | |
7ff0ebcc | 1044 | } else if (IS_GM45(dev_priv)) { |
ff2a3117 PZ |
1045 | dev_priv->fbc.fbc_enabled = g4x_fbc_enabled; |
1046 | dev_priv->fbc.enable_fbc = g4x_fbc_enable; | |
1047 | dev_priv->fbc.disable_fbc = g4x_fbc_disable; | |
7ff0ebcc | 1048 | } else { |
ff2a3117 PZ |
1049 | dev_priv->fbc.fbc_enabled = i8xx_fbc_enabled; |
1050 | dev_priv->fbc.enable_fbc = i8xx_fbc_enable; | |
1051 | dev_priv->fbc.disable_fbc = i8xx_fbc_disable; | |
7ff0ebcc RV |
1052 | |
1053 | /* This value was pulled out of someone's hat */ | |
1054 | I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT); | |
1055 | } | |
1056 | ||
7733b49b | 1057 | dev_priv->fbc.enabled = dev_priv->fbc.fbc_enabled(dev_priv); |
7ff0ebcc | 1058 | } |