Commit | Line | Data |
---|---|---|
7ff0ebcc RV |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
94b83957 RV |
24 | /** |
25 | * DOC: Frame Buffer Compression (FBC) | |
26 | * | |
27 | * FBC tries to save memory bandwidth (and so power consumption) by | |
28 | * compressing the amount of memory used by the display. It is total | |
29 | * transparent to user space and completely handled in the kernel. | |
7ff0ebcc RV |
30 | * |
31 | * The benefits of FBC are mostly visible with solid backgrounds and | |
94b83957 RV |
32 | * variation-less patterns. It comes from keeping the memory footprint small |
33 | * and having fewer memory pages opened and accessed for refreshing the display. | |
7ff0ebcc | 34 | * |
94b83957 RV |
35 | * i915 is responsible to reserve stolen memory for FBC and configure its |
36 | * offset on proper registers. The hardware takes care of all | |
37 | * compress/decompress. However there are many known cases where we have to | |
38 | * forcibly disable it to allow proper screen updates. | |
7ff0ebcc RV |
39 | */ |
40 | ||
94b83957 RV |
41 | #include "intel_drv.h" |
42 | #include "i915_drv.h" | |
43 | ||
9f218336 PZ |
44 | static inline bool fbc_supported(struct drm_i915_private *dev_priv) |
45 | { | |
0e631adc | 46 | return dev_priv->fbc.activate != NULL; |
9f218336 PZ |
47 | } |
48 | ||
57105022 PZ |
49 | static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv) |
50 | { | |
51 | return IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8; | |
52 | } | |
53 | ||
e6cd6dc1 PZ |
54 | static inline bool fbc_on_plane_a_only(struct drm_i915_private *dev_priv) |
55 | { | |
56 | return INTEL_INFO(dev_priv)->gen < 4; | |
57 | } | |
58 | ||
2db3366b PZ |
59 | /* |
60 | * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the | |
61 | * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's | |
62 | * origin so the x and y offsets can actually fit the registers. As a | |
63 | * consequence, the fence doesn't really start exactly at the display plane | |
64 | * address we program because it starts at the real start of the buffer, so we | |
65 | * have to take this into consideration here. | |
66 | */ | |
67 | static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc) | |
68 | { | |
69 | return crtc->base.y - crtc->adjusted_y; | |
70 | } | |
71 | ||
c5ecd469 PZ |
72 | /* |
73 | * For SKL+, the plane source size used by the hardware is based on the value we | |
74 | * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value | |
75 | * we wrote to PIPESRC. | |
76 | */ | |
77 | static void intel_fbc_get_plane_source_size(struct intel_crtc *crtc, | |
78 | int *width, int *height) | |
79 | { | |
80 | struct intel_plane_state *plane_state = | |
81 | to_intel_plane_state(crtc->base.primary->state); | |
82 | int w, h; | |
83 | ||
84 | if (intel_rotation_90_or_270(plane_state->base.rotation)) { | |
85 | w = drm_rect_height(&plane_state->src) >> 16; | |
86 | h = drm_rect_width(&plane_state->src) >> 16; | |
87 | } else { | |
88 | w = drm_rect_width(&plane_state->src) >> 16; | |
89 | h = drm_rect_height(&plane_state->src) >> 16; | |
90 | } | |
91 | ||
92 | if (width) | |
93 | *width = w; | |
94 | if (height) | |
95 | *height = h; | |
96 | } | |
97 | ||
98 | static int intel_fbc_calculate_cfb_size(struct intel_crtc *crtc, | |
99 | struct drm_framebuffer *fb) | |
100 | { | |
101 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
102 | int lines; | |
103 | ||
104 | intel_fbc_get_plane_source_size(crtc, NULL, &lines); | |
105 | if (INTEL_INFO(dev_priv)->gen >= 7) | |
106 | lines = min(lines, 2048); | |
107 | ||
108 | /* Hardware needs the full buffer stride, not just the active area. */ | |
109 | return lines * fb->pitches[0]; | |
110 | } | |
111 | ||
0e631adc | 112 | static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv) |
7ff0ebcc | 113 | { |
7ff0ebcc RV |
114 | u32 fbc_ctl; |
115 | ||
0e631adc | 116 | dev_priv->fbc.active = false; |
7ff0ebcc RV |
117 | |
118 | /* Disable compression */ | |
119 | fbc_ctl = I915_READ(FBC_CONTROL); | |
120 | if ((fbc_ctl & FBC_CTL_EN) == 0) | |
121 | return; | |
122 | ||
123 | fbc_ctl &= ~FBC_CTL_EN; | |
124 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
125 | ||
126 | /* Wait for compressing bit to clear */ | |
127 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { | |
128 | DRM_DEBUG_KMS("FBC idle timed out\n"); | |
129 | return; | |
130 | } | |
131 | ||
0e631adc | 132 | DRM_DEBUG_KMS("deactivated FBC\n"); |
7ff0ebcc RV |
133 | } |
134 | ||
0e631adc | 135 | static void i8xx_fbc_activate(struct intel_crtc *crtc) |
7ff0ebcc | 136 | { |
220285f2 PZ |
137 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
138 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
7ff0ebcc | 139 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
7ff0ebcc RV |
140 | int cfb_pitch; |
141 | int i; | |
142 | u32 fbc_ctl; | |
143 | ||
0e631adc | 144 | dev_priv->fbc.active = true; |
7ff0ebcc | 145 | |
60ee5cd2 JN |
146 | /* Note: fbc.threshold == 1 for i8xx */ |
147 | cfb_pitch = dev_priv->fbc.uncompressed_size / FBC_LL_SIZE; | |
7ff0ebcc RV |
148 | if (fb->pitches[0] < cfb_pitch) |
149 | cfb_pitch = fb->pitches[0]; | |
150 | ||
151 | /* FBC_CTL wants 32B or 64B units */ | |
7733b49b | 152 | if (IS_GEN2(dev_priv)) |
7ff0ebcc RV |
153 | cfb_pitch = (cfb_pitch / 32) - 1; |
154 | else | |
155 | cfb_pitch = (cfb_pitch / 64) - 1; | |
156 | ||
157 | /* Clear old tags */ | |
158 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) | |
4d110c71 | 159 | I915_WRITE(FBC_TAG(i), 0); |
7ff0ebcc | 160 | |
7733b49b | 161 | if (IS_GEN4(dev_priv)) { |
7ff0ebcc RV |
162 | u32 fbc_ctl2; |
163 | ||
164 | /* Set it up... */ | |
165 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; | |
220285f2 | 166 | fbc_ctl2 |= FBC_CTL_PLANE(crtc->plane); |
7ff0ebcc | 167 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
2db3366b | 168 | I915_WRITE(FBC_FENCE_OFF, get_crtc_fence_y_offset(crtc)); |
7ff0ebcc RV |
169 | } |
170 | ||
171 | /* enable it... */ | |
172 | fbc_ctl = I915_READ(FBC_CONTROL); | |
173 | fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT; | |
174 | fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC; | |
7733b49b | 175 | if (IS_I945GM(dev_priv)) |
7ff0ebcc RV |
176 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
177 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; | |
178 | fbc_ctl |= obj->fence_reg; | |
179 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
180 | ||
0e631adc | 181 | DRM_DEBUG_KMS("activated FBC, pitch %d, yoff %d, plane %c\n", |
220285f2 | 182 | cfb_pitch, crtc->base.y, plane_name(crtc->plane)); |
7ff0ebcc RV |
183 | } |
184 | ||
0e631adc | 185 | static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv) |
7ff0ebcc | 186 | { |
7ff0ebcc RV |
187 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; |
188 | } | |
189 | ||
0e631adc | 190 | static void g4x_fbc_activate(struct intel_crtc *crtc) |
7ff0ebcc | 191 | { |
220285f2 PZ |
192 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
193 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
7ff0ebcc | 194 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
7ff0ebcc RV |
195 | u32 dpfc_ctl; |
196 | ||
0e631adc | 197 | dev_priv->fbc.active = true; |
7ff0ebcc | 198 | |
220285f2 | 199 | dpfc_ctl = DPFC_CTL_PLANE(crtc->plane) | DPFC_SR_EN; |
7ff0ebcc RV |
200 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
201 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
202 | else | |
203 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
204 | dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; | |
205 | ||
2db3366b | 206 | I915_WRITE(DPFC_FENCE_YOFF, get_crtc_fence_y_offset(crtc)); |
7ff0ebcc RV |
207 | |
208 | /* enable it... */ | |
209 | I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
210 | ||
0e631adc | 211 | DRM_DEBUG_KMS("activated fbc on plane %c\n", plane_name(crtc->plane)); |
7ff0ebcc RV |
212 | } |
213 | ||
0e631adc | 214 | static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv) |
7ff0ebcc | 215 | { |
7ff0ebcc RV |
216 | u32 dpfc_ctl; |
217 | ||
0e631adc | 218 | dev_priv->fbc.active = false; |
7ff0ebcc RV |
219 | |
220 | /* Disable compression */ | |
221 | dpfc_ctl = I915_READ(DPFC_CONTROL); | |
222 | if (dpfc_ctl & DPFC_CTL_EN) { | |
223 | dpfc_ctl &= ~DPFC_CTL_EN; | |
224 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); | |
225 | ||
0e631adc | 226 | DRM_DEBUG_KMS("deactivated FBC\n"); |
7ff0ebcc RV |
227 | } |
228 | } | |
229 | ||
0e631adc | 230 | static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv) |
7ff0ebcc | 231 | { |
7ff0ebcc RV |
232 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; |
233 | } | |
234 | ||
d5ce4164 PZ |
235 | /* This function forces a CFB recompression through the nuke operation. */ |
236 | static void intel_fbc_recompress(struct drm_i915_private *dev_priv) | |
7ff0ebcc | 237 | { |
dbef0f15 PZ |
238 | I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE); |
239 | POSTING_READ(MSG_FBC_REND_STATE); | |
7ff0ebcc RV |
240 | } |
241 | ||
0e631adc | 242 | static void ilk_fbc_activate(struct intel_crtc *crtc) |
7ff0ebcc | 243 | { |
220285f2 PZ |
244 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
245 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
7ff0ebcc | 246 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
7ff0ebcc | 247 | u32 dpfc_ctl; |
ce65e47b | 248 | int threshold = dev_priv->fbc.threshold; |
2db3366b | 249 | unsigned int y_offset; |
7ff0ebcc | 250 | |
0e631adc | 251 | dev_priv->fbc.active = true; |
7ff0ebcc | 252 | |
220285f2 | 253 | dpfc_ctl = DPFC_CTL_PLANE(crtc->plane); |
7ff0ebcc | 254 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
ce65e47b | 255 | threshold++; |
7ff0ebcc | 256 | |
ce65e47b | 257 | switch (threshold) { |
7ff0ebcc RV |
258 | case 4: |
259 | case 3: | |
260 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; | |
261 | break; | |
262 | case 2: | |
263 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
264 | break; | |
265 | case 1: | |
266 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
267 | break; | |
268 | } | |
269 | dpfc_ctl |= DPFC_CTL_FENCE_EN; | |
7733b49b | 270 | if (IS_GEN5(dev_priv)) |
7ff0ebcc RV |
271 | dpfc_ctl |= obj->fence_reg; |
272 | ||
2db3366b PZ |
273 | y_offset = get_crtc_fence_y_offset(crtc); |
274 | I915_WRITE(ILK_DPFC_FENCE_YOFF, y_offset); | |
7ff0ebcc RV |
275 | I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID); |
276 | /* enable it... */ | |
277 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
278 | ||
7733b49b | 279 | if (IS_GEN6(dev_priv)) { |
7ff0ebcc RV |
280 | I915_WRITE(SNB_DPFC_CTL_SA, |
281 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); | |
2db3366b | 282 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, y_offset); |
7ff0ebcc RV |
283 | } |
284 | ||
d5ce4164 | 285 | intel_fbc_recompress(dev_priv); |
dbef0f15 | 286 | |
0e631adc | 287 | DRM_DEBUG_KMS("activated fbc on plane %c\n", plane_name(crtc->plane)); |
7ff0ebcc RV |
288 | } |
289 | ||
0e631adc | 290 | static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv) |
7ff0ebcc | 291 | { |
7ff0ebcc RV |
292 | u32 dpfc_ctl; |
293 | ||
0e631adc | 294 | dev_priv->fbc.active = false; |
7ff0ebcc RV |
295 | |
296 | /* Disable compression */ | |
297 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
298 | if (dpfc_ctl & DPFC_CTL_EN) { | |
299 | dpfc_ctl &= ~DPFC_CTL_EN; | |
300 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); | |
301 | ||
0e631adc | 302 | DRM_DEBUG_KMS("deactivated FBC\n"); |
7ff0ebcc RV |
303 | } |
304 | } | |
305 | ||
0e631adc | 306 | static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv) |
7ff0ebcc | 307 | { |
7ff0ebcc RV |
308 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; |
309 | } | |
310 | ||
0e631adc | 311 | static void gen7_fbc_activate(struct intel_crtc *crtc) |
7ff0ebcc | 312 | { |
220285f2 PZ |
313 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
314 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
7ff0ebcc | 315 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
7ff0ebcc | 316 | u32 dpfc_ctl; |
ce65e47b | 317 | int threshold = dev_priv->fbc.threshold; |
7ff0ebcc | 318 | |
0e631adc | 319 | dev_priv->fbc.active = true; |
7ff0ebcc | 320 | |
d8514d63 | 321 | dpfc_ctl = 0; |
7733b49b | 322 | if (IS_IVYBRIDGE(dev_priv)) |
220285f2 | 323 | dpfc_ctl |= IVB_DPFC_CTL_PLANE(crtc->plane); |
d8514d63 | 324 | |
7ff0ebcc | 325 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
ce65e47b | 326 | threshold++; |
7ff0ebcc | 327 | |
ce65e47b | 328 | switch (threshold) { |
7ff0ebcc RV |
329 | case 4: |
330 | case 3: | |
331 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; | |
332 | break; | |
333 | case 2: | |
334 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
335 | break; | |
336 | case 1: | |
337 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
338 | break; | |
339 | } | |
340 | ||
341 | dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; | |
342 | ||
343 | if (dev_priv->fbc.false_color) | |
344 | dpfc_ctl |= FBC_CTL_FALSE_COLOR; | |
345 | ||
7733b49b | 346 | if (IS_IVYBRIDGE(dev_priv)) { |
7ff0ebcc RV |
347 | /* WaFbcAsynchFlipDisableFbcQueue:ivb */ |
348 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
349 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
350 | ILK_FBCQ_DIS); | |
40f4022e | 351 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
7ff0ebcc | 352 | /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ |
220285f2 PZ |
353 | I915_WRITE(CHICKEN_PIPESL_1(crtc->pipe), |
354 | I915_READ(CHICKEN_PIPESL_1(crtc->pipe)) | | |
7ff0ebcc RV |
355 | HSW_FBCQ_DIS); |
356 | } | |
357 | ||
57012be9 PZ |
358 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
359 | ||
7ff0ebcc RV |
360 | I915_WRITE(SNB_DPFC_CTL_SA, |
361 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); | |
2db3366b | 362 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, get_crtc_fence_y_offset(crtc)); |
7ff0ebcc | 363 | |
d5ce4164 | 364 | intel_fbc_recompress(dev_priv); |
7ff0ebcc | 365 | |
0e631adc | 366 | DRM_DEBUG_KMS("activated fbc on plane %c\n", plane_name(crtc->plane)); |
7ff0ebcc RV |
367 | } |
368 | ||
94b83957 | 369 | /** |
0e631adc | 370 | * intel_fbc_is_active - Is FBC active? |
7733b49b | 371 | * @dev_priv: i915 device instance |
94b83957 RV |
372 | * |
373 | * This function is used to verify the current state of FBC. | |
374 | * FIXME: This should be tracked in the plane config eventually | |
375 | * instead of queried at runtime for most callers. | |
376 | */ | |
0e631adc | 377 | bool intel_fbc_is_active(struct drm_i915_private *dev_priv) |
7ff0ebcc | 378 | { |
0e631adc | 379 | return dev_priv->fbc.active; |
7ff0ebcc RV |
380 | } |
381 | ||
0e631adc | 382 | static void intel_fbc_activate(const struct drm_framebuffer *fb) |
e8cb8d69 | 383 | { |
e9c5fd26 PZ |
384 | struct drm_i915_private *dev_priv = fb->dev->dev_private; |
385 | struct intel_crtc *crtc = dev_priv->fbc.crtc; | |
e8cb8d69 | 386 | |
0e631adc | 387 | dev_priv->fbc.activate(crtc); |
e8cb8d69 | 388 | |
e8cb8d69 PZ |
389 | dev_priv->fbc.fb_id = fb->base.id; |
390 | dev_priv->fbc.y = crtc->base.y; | |
391 | } | |
392 | ||
7ff0ebcc RV |
393 | static void intel_fbc_work_fn(struct work_struct *__work) |
394 | { | |
128d7356 PZ |
395 | struct drm_i915_private *dev_priv = |
396 | container_of(__work, struct drm_i915_private, fbc.work.work); | |
397 | struct intel_fbc_work *work = &dev_priv->fbc.work; | |
398 | struct intel_crtc *crtc = dev_priv->fbc.crtc; | |
399 | int delay_ms = 50; | |
400 | ||
401 | retry: | |
402 | /* Delay the actual enabling to let pageflipping cease and the | |
403 | * display to settle before starting the compression. Note that | |
404 | * this delay also serves a second purpose: it allows for a | |
405 | * vblank to pass after disabling the FBC before we attempt | |
406 | * to modify the control registers. | |
407 | * | |
408 | * A more complicated solution would involve tracking vblanks | |
409 | * following the termination of the page-flipping sequence | |
410 | * and indeed performing the enable as a co-routine and not | |
411 | * waiting synchronously upon the vblank. | |
412 | * | |
413 | * WaFbcWaitForVBlankBeforeEnable:ilk,snb | |
414 | */ | |
415 | wait_remaining_ms_from_jiffies(work->enable_jiffies, delay_ms); | |
7ff0ebcc | 416 | |
25ad93fd | 417 | mutex_lock(&dev_priv->fbc.lock); |
7ff0ebcc | 418 | |
128d7356 PZ |
419 | /* Were we cancelled? */ |
420 | if (!work->scheduled) | |
421 | goto out; | |
422 | ||
423 | /* Were we delayed again while this function was sleeping? */ | |
424 | if (time_after(work->enable_jiffies + msecs_to_jiffies(delay_ms), | |
425 | jiffies)) { | |
426 | mutex_unlock(&dev_priv->fbc.lock); | |
427 | goto retry; | |
7ff0ebcc | 428 | } |
7ff0ebcc | 429 | |
128d7356 PZ |
430 | if (crtc->base.primary->fb == work->fb) |
431 | intel_fbc_activate(work->fb); | |
432 | ||
433 | work->scheduled = false; | |
434 | ||
435 | out: | |
436 | mutex_unlock(&dev_priv->fbc.lock); | |
7ff0ebcc RV |
437 | } |
438 | ||
439 | static void intel_fbc_cancel_work(struct drm_i915_private *dev_priv) | |
440 | { | |
25ad93fd | 441 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
128d7356 | 442 | dev_priv->fbc.work.scheduled = false; |
7ff0ebcc RV |
443 | } |
444 | ||
0e631adc | 445 | static void intel_fbc_schedule_activation(struct intel_crtc *crtc) |
7ff0ebcc | 446 | { |
220285f2 | 447 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
128d7356 | 448 | struct intel_fbc_work *work = &dev_priv->fbc.work; |
7ff0ebcc | 449 | |
25ad93fd PZ |
450 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
451 | ||
128d7356 PZ |
452 | /* It is useless to call intel_fbc_cancel_work() in this function since |
453 | * we're not releasing fbc.lock, so it won't have an opportunity to grab | |
454 | * it to discover that it was cancelled. So we just update the expected | |
455 | * jiffy count. */ | |
220285f2 | 456 | work->fb = crtc->base.primary->fb; |
128d7356 PZ |
457 | work->scheduled = true; |
458 | work->enable_jiffies = jiffies; | |
7ff0ebcc | 459 | |
128d7356 | 460 | schedule_work(&work->work); |
7ff0ebcc RV |
461 | } |
462 | ||
d029bcad | 463 | static void __intel_fbc_deactivate(struct drm_i915_private *dev_priv) |
25ad93fd | 464 | { |
25ad93fd PZ |
465 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
466 | ||
467 | intel_fbc_cancel_work(dev_priv); | |
468 | ||
0e631adc PZ |
469 | if (dev_priv->fbc.active) |
470 | dev_priv->fbc.deactivate(dev_priv); | |
754d1133 PZ |
471 | } |
472 | ||
25ad93fd | 473 | /* |
d029bcad | 474 | * intel_fbc_deactivate - deactivate FBC if it's associated with crtc |
25ad93fd PZ |
475 | * @crtc: the CRTC |
476 | * | |
d029bcad | 477 | * This function deactivates FBC if it's associated with the provided CRTC. |
25ad93fd | 478 | */ |
d029bcad | 479 | void intel_fbc_deactivate(struct intel_crtc *crtc) |
25ad93fd | 480 | { |
7733b49b | 481 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
7ff0ebcc | 482 | |
9f218336 | 483 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
484 | return; |
485 | ||
25ad93fd PZ |
486 | mutex_lock(&dev_priv->fbc.lock); |
487 | if (dev_priv->fbc.crtc == crtc) | |
d029bcad | 488 | __intel_fbc_deactivate(dev_priv); |
25ad93fd | 489 | mutex_unlock(&dev_priv->fbc.lock); |
7ff0ebcc RV |
490 | } |
491 | ||
2e8144a5 | 492 | static void set_no_fbc_reason(struct drm_i915_private *dev_priv, |
bf6189c6 | 493 | const char *reason) |
7ff0ebcc RV |
494 | { |
495 | if (dev_priv->fbc.no_fbc_reason == reason) | |
2e8144a5 | 496 | return; |
7ff0ebcc RV |
497 | |
498 | dev_priv->fbc.no_fbc_reason = reason; | |
bf6189c6 | 499 | DRM_DEBUG_KMS("Disabling FBC: %s\n", reason); |
7ff0ebcc RV |
500 | } |
501 | ||
d029bcad | 502 | static bool crtc_can_fbc(struct intel_crtc *crtc) |
30c58d58 PZ |
503 | { |
504 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
505 | ||
506 | if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A) | |
507 | return false; | |
508 | ||
e6cd6dc1 PZ |
509 | if (fbc_on_plane_a_only(dev_priv) && crtc->plane != PLANE_A) |
510 | return false; | |
511 | ||
d029bcad PZ |
512 | return true; |
513 | } | |
514 | ||
515 | static bool crtc_is_valid(struct intel_crtc *crtc) | |
516 | { | |
30c58d58 PZ |
517 | if (!intel_crtc_active(&crtc->base)) |
518 | return false; | |
519 | ||
520 | if (!to_intel_plane_state(crtc->base.primary->state)->visible) | |
521 | return false; | |
522 | ||
523 | return true; | |
524 | } | |
525 | ||
232fd934 PZ |
526 | static bool multiple_pipes_ok(struct drm_i915_private *dev_priv) |
527 | { | |
528 | enum pipe pipe; | |
529 | int n_pipes = 0; | |
530 | struct drm_crtc *crtc; | |
531 | ||
532 | if (INTEL_INFO(dev_priv)->gen > 4) | |
533 | return true; | |
534 | ||
535 | for_each_pipe(dev_priv, pipe) { | |
536 | crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
537 | ||
538 | if (intel_crtc_active(crtc) && | |
539 | to_intel_plane_state(crtc->primary->state)->visible) | |
540 | n_pipes++; | |
541 | } | |
542 | ||
543 | return (n_pipes < 2); | |
544 | } | |
545 | ||
7733b49b | 546 | static int find_compression_threshold(struct drm_i915_private *dev_priv, |
fc786728 PZ |
547 | struct drm_mm_node *node, |
548 | int size, | |
549 | int fb_cpp) | |
550 | { | |
fc786728 PZ |
551 | int compression_threshold = 1; |
552 | int ret; | |
a9da512b PZ |
553 | u64 end; |
554 | ||
555 | /* The FBC hardware for BDW/SKL doesn't have access to the stolen | |
556 | * reserved range size, so it always assumes the maximum (8mb) is used. | |
557 | * If we enable FBC using a CFB on that memory range we'll get FIFO | |
558 | * underruns, even if that range is not reserved by the BIOS. */ | |
ef11bdb3 RV |
559 | if (IS_BROADWELL(dev_priv) || |
560 | IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) | |
a9da512b PZ |
561 | end = dev_priv->gtt.stolen_size - 8 * 1024 * 1024; |
562 | else | |
563 | end = dev_priv->gtt.stolen_usable_size; | |
fc786728 PZ |
564 | |
565 | /* HACK: This code depends on what we will do in *_enable_fbc. If that | |
566 | * code changes, this code needs to change as well. | |
567 | * | |
568 | * The enable_fbc code will attempt to use one of our 2 compression | |
569 | * thresholds, therefore, in that case, we only have 1 resort. | |
570 | */ | |
571 | ||
572 | /* Try to over-allocate to reduce reallocations and fragmentation. */ | |
a9da512b PZ |
573 | ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1, |
574 | 4096, 0, end); | |
fc786728 PZ |
575 | if (ret == 0) |
576 | return compression_threshold; | |
577 | ||
578 | again: | |
579 | /* HW's ability to limit the CFB is 1:4 */ | |
580 | if (compression_threshold > 4 || | |
581 | (fb_cpp == 2 && compression_threshold == 2)) | |
582 | return 0; | |
583 | ||
a9da512b PZ |
584 | ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1, |
585 | 4096, 0, end); | |
7733b49b | 586 | if (ret && INTEL_INFO(dev_priv)->gen <= 4) { |
fc786728 PZ |
587 | return 0; |
588 | } else if (ret) { | |
589 | compression_threshold <<= 1; | |
590 | goto again; | |
591 | } else { | |
592 | return compression_threshold; | |
593 | } | |
594 | } | |
595 | ||
c5ecd469 | 596 | static int intel_fbc_alloc_cfb(struct intel_crtc *crtc) |
fc786728 | 597 | { |
c5ecd469 PZ |
598 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
599 | struct drm_framebuffer *fb = crtc->base.primary->state->fb; | |
fc786728 | 600 | struct drm_mm_node *uninitialized_var(compressed_llb); |
c5ecd469 PZ |
601 | int size, fb_cpp, ret; |
602 | ||
603 | WARN_ON(drm_mm_node_allocated(&dev_priv->fbc.compressed_fb)); | |
604 | ||
605 | size = intel_fbc_calculate_cfb_size(crtc, fb); | |
606 | fb_cpp = drm_format_plane_cpp(fb->pixel_format, 0); | |
fc786728 | 607 | |
7733b49b | 608 | ret = find_compression_threshold(dev_priv, &dev_priv->fbc.compressed_fb, |
fc786728 PZ |
609 | size, fb_cpp); |
610 | if (!ret) | |
611 | goto err_llb; | |
612 | else if (ret > 1) { | |
613 | DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n"); | |
614 | ||
615 | } | |
616 | ||
617 | dev_priv->fbc.threshold = ret; | |
618 | ||
619 | if (INTEL_INFO(dev_priv)->gen >= 5) | |
620 | I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start); | |
7733b49b | 621 | else if (IS_GM45(dev_priv)) { |
fc786728 PZ |
622 | I915_WRITE(DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start); |
623 | } else { | |
624 | compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL); | |
625 | if (!compressed_llb) | |
626 | goto err_fb; | |
627 | ||
628 | ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb, | |
629 | 4096, 4096); | |
630 | if (ret) | |
631 | goto err_fb; | |
632 | ||
633 | dev_priv->fbc.compressed_llb = compressed_llb; | |
634 | ||
635 | I915_WRITE(FBC_CFB_BASE, | |
636 | dev_priv->mm.stolen_base + dev_priv->fbc.compressed_fb.start); | |
637 | I915_WRITE(FBC_LL_BASE, | |
638 | dev_priv->mm.stolen_base + compressed_llb->start); | |
639 | } | |
640 | ||
641 | dev_priv->fbc.uncompressed_size = size; | |
642 | ||
b8bf5d7f PZ |
643 | DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n", |
644 | dev_priv->fbc.compressed_fb.size, | |
645 | dev_priv->fbc.threshold); | |
fc786728 PZ |
646 | |
647 | return 0; | |
648 | ||
649 | err_fb: | |
650 | kfree(compressed_llb); | |
651 | i915_gem_stolen_remove_node(dev_priv, &dev_priv->fbc.compressed_fb); | |
652 | err_llb: | |
653 | pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size); | |
654 | return -ENOSPC; | |
655 | } | |
656 | ||
7733b49b | 657 | static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) |
fc786728 | 658 | { |
fc786728 PZ |
659 | if (dev_priv->fbc.uncompressed_size == 0) |
660 | return; | |
661 | ||
662 | i915_gem_stolen_remove_node(dev_priv, &dev_priv->fbc.compressed_fb); | |
663 | ||
664 | if (dev_priv->fbc.compressed_llb) { | |
665 | i915_gem_stolen_remove_node(dev_priv, | |
666 | dev_priv->fbc.compressed_llb); | |
667 | kfree(dev_priv->fbc.compressed_llb); | |
668 | } | |
669 | ||
670 | dev_priv->fbc.uncompressed_size = 0; | |
671 | } | |
672 | ||
7733b49b | 673 | void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) |
25ad93fd | 674 | { |
9f218336 | 675 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
676 | return; |
677 | ||
25ad93fd | 678 | mutex_lock(&dev_priv->fbc.lock); |
7733b49b | 679 | __intel_fbc_cleanup_cfb(dev_priv); |
25ad93fd PZ |
680 | mutex_unlock(&dev_priv->fbc.lock); |
681 | } | |
682 | ||
adf70c65 PZ |
683 | static bool stride_is_valid(struct drm_i915_private *dev_priv, |
684 | unsigned int stride) | |
685 | { | |
686 | /* These should have been caught earlier. */ | |
687 | WARN_ON(stride < 512); | |
688 | WARN_ON((stride & (64 - 1)) != 0); | |
689 | ||
690 | /* Below are the additional FBC restrictions. */ | |
691 | ||
692 | if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv)) | |
693 | return stride == 4096 || stride == 8192; | |
694 | ||
695 | if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048) | |
696 | return false; | |
697 | ||
698 | if (stride > 16384) | |
699 | return false; | |
700 | ||
701 | return true; | |
702 | } | |
703 | ||
b9e831dc PZ |
704 | static bool pixel_format_is_valid(struct drm_framebuffer *fb) |
705 | { | |
706 | struct drm_device *dev = fb->dev; | |
707 | struct drm_i915_private *dev_priv = dev->dev_private; | |
708 | ||
709 | switch (fb->pixel_format) { | |
710 | case DRM_FORMAT_XRGB8888: | |
711 | case DRM_FORMAT_XBGR8888: | |
712 | return true; | |
713 | case DRM_FORMAT_XRGB1555: | |
714 | case DRM_FORMAT_RGB565: | |
715 | /* 16bpp not supported on gen2 */ | |
716 | if (IS_GEN2(dev)) | |
717 | return false; | |
718 | /* WaFbcOnly1to1Ratio:ctg */ | |
719 | if (IS_G4X(dev_priv)) | |
720 | return false; | |
721 | return true; | |
722 | default: | |
723 | return false; | |
724 | } | |
725 | } | |
726 | ||
856312ae PZ |
727 | /* |
728 | * For some reason, the hardware tracking starts looking at whatever we | |
729 | * programmed as the display plane base address register. It does not look at | |
730 | * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y} | |
731 | * variables instead of just looking at the pipe/plane size. | |
732 | */ | |
733 | static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc) | |
3c5f174e PZ |
734 | { |
735 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
856312ae | 736 | unsigned int effective_w, effective_h, max_w, max_h; |
3c5f174e PZ |
737 | |
738 | if (INTEL_INFO(dev_priv)->gen >= 8 || IS_HASWELL(dev_priv)) { | |
739 | max_w = 4096; | |
740 | max_h = 4096; | |
741 | } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { | |
742 | max_w = 4096; | |
743 | max_h = 2048; | |
744 | } else { | |
745 | max_w = 2048; | |
746 | max_h = 1536; | |
747 | } | |
748 | ||
856312ae PZ |
749 | intel_fbc_get_plane_source_size(crtc, &effective_w, &effective_h); |
750 | effective_w += crtc->adjusted_x; | |
751 | effective_h += crtc->adjusted_y; | |
752 | ||
753 | return effective_w <= max_w && effective_h <= max_h; | |
3c5f174e PZ |
754 | } |
755 | ||
7ff0ebcc | 756 | /** |
d029bcad | 757 | * __intel_fbc_update - activate/deactivate FBC as needed, unlocked |
754d1133 | 758 | * @crtc: the CRTC that triggered the update |
7ff0ebcc | 759 | * |
d029bcad PZ |
760 | * This function completely reevaluates the status of FBC, then activates, |
761 | * deactivates or maintains it on the same state. | |
7ff0ebcc | 762 | */ |
754d1133 | 763 | static void __intel_fbc_update(struct intel_crtc *crtc) |
7ff0ebcc | 764 | { |
754d1133 | 765 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
7ff0ebcc RV |
766 | struct drm_framebuffer *fb; |
767 | struct drm_i915_gem_object *obj; | |
768 | const struct drm_display_mode *adjusted_mode; | |
7ff0ebcc | 769 | |
25ad93fd PZ |
770 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
771 | ||
754d1133 PZ |
772 | if (!multiple_pipes_ok(dev_priv)) { |
773 | set_no_fbc_reason(dev_priv, "more than one pipe active"); | |
774 | goto out_disable; | |
775 | } | |
776 | ||
d029bcad | 777 | if (!dev_priv->fbc.enabled || dev_priv->fbc.crtc != crtc) |
754d1133 PZ |
778 | return; |
779 | ||
754d1133 | 780 | if (!crtc_is_valid(crtc)) { |
bf6189c6 | 781 | set_no_fbc_reason(dev_priv, "no output"); |
7ff0ebcc | 782 | goto out_disable; |
8df5dd57 | 783 | } |
7ff0ebcc | 784 | |
45b32a29 | 785 | fb = crtc->base.primary->fb; |
7ff0ebcc | 786 | obj = intel_fb_obj(fb); |
45b32a29 | 787 | adjusted_mode = &crtc->config->base.adjusted_mode; |
7ff0ebcc | 788 | |
7ff0ebcc RV |
789 | if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) || |
790 | (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) { | |
bf6189c6 | 791 | set_no_fbc_reason(dev_priv, "incompatible mode"); |
7ff0ebcc RV |
792 | goto out_disable; |
793 | } | |
794 | ||
45b32a29 | 795 | if (!intel_fbc_hw_tracking_covers_screen(crtc)) { |
bf6189c6 | 796 | set_no_fbc_reason(dev_priv, "mode too large for compression"); |
7ff0ebcc RV |
797 | goto out_disable; |
798 | } | |
3c5f174e | 799 | |
7ff0ebcc RV |
800 | /* The use of a CPU fence is mandatory in order to detect writes |
801 | * by the CPU to the scanout and trigger updates to the FBC. | |
802 | */ | |
803 | if (obj->tiling_mode != I915_TILING_X || | |
804 | obj->fence_reg == I915_FENCE_REG_NONE) { | |
bf6189c6 | 805 | set_no_fbc_reason(dev_priv, "framebuffer not tiled or fenced"); |
7ff0ebcc RV |
806 | goto out_disable; |
807 | } | |
7733b49b | 808 | if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) && |
45b32a29 | 809 | crtc->base.primary->state->rotation != BIT(DRM_ROTATE_0)) { |
bf6189c6 | 810 | set_no_fbc_reason(dev_priv, "rotation unsupported"); |
7ff0ebcc RV |
811 | goto out_disable; |
812 | } | |
813 | ||
adf70c65 | 814 | if (!stride_is_valid(dev_priv, fb->pitches[0])) { |
bf6189c6 | 815 | set_no_fbc_reason(dev_priv, "framebuffer stride not supported"); |
adf70c65 PZ |
816 | goto out_disable; |
817 | } | |
818 | ||
b9e831dc | 819 | if (!pixel_format_is_valid(fb)) { |
bf6189c6 | 820 | set_no_fbc_reason(dev_priv, "pixel format is invalid"); |
b9e831dc PZ |
821 | goto out_disable; |
822 | } | |
823 | ||
7b24c9a6 PZ |
824 | /* WaFbcExceedCdClockThreshold:hsw,bdw */ |
825 | if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) && | |
45b32a29 | 826 | ilk_pipe_pixel_rate(crtc->config) >= |
7b24c9a6 | 827 | dev_priv->cdclk_freq * 95 / 100) { |
bf6189c6 | 828 | set_no_fbc_reason(dev_priv, "pixel rate is too big"); |
7b24c9a6 PZ |
829 | goto out_disable; |
830 | } | |
831 | ||
c5ecd469 PZ |
832 | /* It is possible for the required CFB size change without a |
833 | * crtc->disable + crtc->enable since it is possible to change the | |
834 | * stride without triggering a full modeset. Since we try to | |
835 | * over-allocate the CFB, there's a chance we may keep FBC enabled even | |
836 | * if this happens, but if we exceed the current CFB size we'll have to | |
837 | * disable FBC. Notice that it would be possible to disable FBC, wait | |
838 | * for a frame, free the stolen node, then try to reenable FBC in case | |
839 | * we didn't get any invalidate/deactivate calls, but this would require | |
840 | * a lot of tracking just for a specific case. If we conclude it's an | |
841 | * important case, we can implement it later. */ | |
842 | if (intel_fbc_calculate_cfb_size(crtc, fb) > | |
843 | dev_priv->fbc.compressed_fb.size * dev_priv->fbc.threshold) { | |
844 | set_no_fbc_reason(dev_priv, "CFB requirements changed"); | |
7ff0ebcc RV |
845 | goto out_disable; |
846 | } | |
847 | ||
848 | /* If the scanout has not changed, don't modify the FBC settings. | |
849 | * Note that we make the fundamental assumption that the fb->obj | |
850 | * cannot be unpinned (and have its GTT offset and fence revoked) | |
851 | * without first being decoupled from the scanout and FBC disabled. | |
852 | */ | |
45b32a29 | 853 | if (dev_priv->fbc.crtc == crtc && |
7ff0ebcc | 854 | dev_priv->fbc.fb_id == fb->base.id && |
754d1133 | 855 | dev_priv->fbc.y == crtc->base.y && |
0e631adc | 856 | dev_priv->fbc.active) |
7ff0ebcc RV |
857 | return; |
858 | ||
0e631adc | 859 | if (intel_fbc_is_active(dev_priv)) { |
7ff0ebcc RV |
860 | /* We update FBC along two paths, after changing fb/crtc |
861 | * configuration (modeswitching) and after page-flipping | |
862 | * finishes. For the latter, we know that not only did | |
863 | * we disable the FBC at the start of the page-flip | |
864 | * sequence, but also more than one vblank has passed. | |
865 | * | |
866 | * For the former case of modeswitching, it is possible | |
867 | * to switch between two FBC valid configurations | |
868 | * instantaneously so we do need to disable the FBC | |
869 | * before we can modify its control registers. We also | |
870 | * have to wait for the next vblank for that to take | |
871 | * effect. However, since we delay enabling FBC we can | |
872 | * assume that a vblank has passed since disabling and | |
873 | * that we can safely alter the registers in the deferred | |
874 | * callback. | |
875 | * | |
876 | * In the scenario that we go from a valid to invalid | |
877 | * and then back to valid FBC configuration we have | |
878 | * no strict enforcement that a vblank occurred since | |
879 | * disabling the FBC. However, along all current pipe | |
880 | * disabling paths we do need to wait for a vblank at | |
881 | * some point. And we wait before enabling FBC anyway. | |
882 | */ | |
d029bcad PZ |
883 | DRM_DEBUG_KMS("deactivating FBC for update\n"); |
884 | __intel_fbc_deactivate(dev_priv); | |
7ff0ebcc RV |
885 | } |
886 | ||
0e631adc | 887 | intel_fbc_schedule_activation(crtc); |
793af070 | 888 | dev_priv->fbc.no_fbc_reason = "FBC enabled (not necessarily active)"; |
7ff0ebcc RV |
889 | return; |
890 | ||
891 | out_disable: | |
892 | /* Multiple disables should be harmless */ | |
0e631adc | 893 | if (intel_fbc_is_active(dev_priv)) { |
d029bcad PZ |
894 | DRM_DEBUG_KMS("unsupported config, deactivating FBC\n"); |
895 | __intel_fbc_deactivate(dev_priv); | |
7ff0ebcc | 896 | } |
25ad93fd PZ |
897 | } |
898 | ||
899 | /* | |
d029bcad | 900 | * intel_fbc_update - activate/deactivate FBC as needed |
754d1133 | 901 | * @crtc: the CRTC that triggered the update |
25ad93fd | 902 | * |
d029bcad | 903 | * This function reevaluates the overall state and activates or deactivates FBC. |
25ad93fd | 904 | */ |
754d1133 | 905 | void intel_fbc_update(struct intel_crtc *crtc) |
25ad93fd | 906 | { |
754d1133 PZ |
907 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
908 | ||
9f218336 | 909 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
910 | return; |
911 | ||
25ad93fd | 912 | mutex_lock(&dev_priv->fbc.lock); |
754d1133 | 913 | __intel_fbc_update(crtc); |
25ad93fd | 914 | mutex_unlock(&dev_priv->fbc.lock); |
7ff0ebcc RV |
915 | } |
916 | ||
dbef0f15 PZ |
917 | void intel_fbc_invalidate(struct drm_i915_private *dev_priv, |
918 | unsigned int frontbuffer_bits, | |
919 | enum fb_op_origin origin) | |
920 | { | |
dbef0f15 PZ |
921 | unsigned int fbc_bits; |
922 | ||
9f218336 | 923 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
924 | return; |
925 | ||
dbef0f15 PZ |
926 | if (origin == ORIGIN_GTT) |
927 | return; | |
928 | ||
25ad93fd PZ |
929 | mutex_lock(&dev_priv->fbc.lock); |
930 | ||
d029bcad | 931 | if (dev_priv->fbc.enabled) |
dbef0f15 | 932 | fbc_bits = INTEL_FRONTBUFFER_PRIMARY(dev_priv->fbc.crtc->pipe); |
dbef0f15 PZ |
933 | else |
934 | fbc_bits = dev_priv->fbc.possible_framebuffer_bits; | |
935 | ||
936 | dev_priv->fbc.busy_bits |= (fbc_bits & frontbuffer_bits); | |
937 | ||
938 | if (dev_priv->fbc.busy_bits) | |
d029bcad | 939 | __intel_fbc_deactivate(dev_priv); |
25ad93fd PZ |
940 | |
941 | mutex_unlock(&dev_priv->fbc.lock); | |
dbef0f15 PZ |
942 | } |
943 | ||
944 | void intel_fbc_flush(struct drm_i915_private *dev_priv, | |
6f4551fe | 945 | unsigned int frontbuffer_bits, enum fb_op_origin origin) |
dbef0f15 | 946 | { |
9f218336 | 947 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
948 | return; |
949 | ||
6f4551fe PZ |
950 | if (origin == ORIGIN_GTT) |
951 | return; | |
25ad93fd | 952 | |
6f4551fe | 953 | mutex_lock(&dev_priv->fbc.lock); |
dbef0f15 PZ |
954 | |
955 | dev_priv->fbc.busy_bits &= ~frontbuffer_bits; | |
956 | ||
d029bcad PZ |
957 | if (!dev_priv->fbc.busy_bits && dev_priv->fbc.enabled) { |
958 | __intel_fbc_deactivate(dev_priv); | |
754d1133 | 959 | __intel_fbc_update(dev_priv->fbc.crtc); |
6f4551fe | 960 | } |
25ad93fd | 961 | |
25ad93fd | 962 | mutex_unlock(&dev_priv->fbc.lock); |
dbef0f15 PZ |
963 | } |
964 | ||
d029bcad PZ |
965 | /** |
966 | * intel_fbc_enable: tries to enable FBC on the CRTC | |
967 | * @crtc: the CRTC | |
968 | * | |
969 | * This function checks if it's possible to enable FBC on the following CRTC, | |
970 | * then enables it. Notice that it doesn't activate FBC. | |
971 | */ | |
972 | void intel_fbc_enable(struct intel_crtc *crtc) | |
973 | { | |
974 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
975 | ||
976 | if (!fbc_supported(dev_priv)) | |
977 | return; | |
978 | ||
979 | mutex_lock(&dev_priv->fbc.lock); | |
980 | ||
981 | if (dev_priv->fbc.enabled) { | |
982 | WARN_ON(dev_priv->fbc.crtc == crtc); | |
983 | goto out; | |
984 | } | |
985 | ||
986 | WARN_ON(dev_priv->fbc.active); | |
987 | WARN_ON(dev_priv->fbc.crtc != NULL); | |
988 | ||
989 | if (intel_vgpu_active(dev_priv->dev)) { | |
990 | set_no_fbc_reason(dev_priv, "VGPU is active"); | |
991 | goto out; | |
992 | } | |
993 | ||
994 | if (i915.enable_fbc < 0) { | |
995 | set_no_fbc_reason(dev_priv, "disabled per chip default"); | |
996 | goto out; | |
997 | } | |
998 | ||
999 | if (!i915.enable_fbc) { | |
1000 | set_no_fbc_reason(dev_priv, "disabled per module param"); | |
1001 | goto out; | |
1002 | } | |
1003 | ||
1004 | if (!crtc_can_fbc(crtc)) { | |
1005 | set_no_fbc_reason(dev_priv, "no enabled pipes can have FBC"); | |
1006 | goto out; | |
1007 | } | |
1008 | ||
c5ecd469 PZ |
1009 | if (intel_fbc_alloc_cfb(crtc)) { |
1010 | set_no_fbc_reason(dev_priv, "not enough stolen memory"); | |
1011 | goto out; | |
1012 | } | |
1013 | ||
d029bcad PZ |
1014 | DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc->pipe)); |
1015 | dev_priv->fbc.no_fbc_reason = "FBC enabled but not active yet\n"; | |
1016 | ||
1017 | dev_priv->fbc.enabled = true; | |
1018 | dev_priv->fbc.crtc = crtc; | |
1019 | out: | |
1020 | mutex_unlock(&dev_priv->fbc.lock); | |
1021 | } | |
1022 | ||
1023 | /** | |
1024 | * __intel_fbc_disable - disable FBC | |
1025 | * @dev_priv: i915 device instance | |
1026 | * | |
1027 | * This is the low level function that actually disables FBC. Callers should | |
1028 | * grab the FBC lock. | |
1029 | */ | |
1030 | static void __intel_fbc_disable(struct drm_i915_private *dev_priv) | |
1031 | { | |
1032 | struct intel_crtc *crtc = dev_priv->fbc.crtc; | |
1033 | ||
1034 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); | |
1035 | WARN_ON(!dev_priv->fbc.enabled); | |
1036 | WARN_ON(dev_priv->fbc.active); | |
1037 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1038 | ||
1039 | DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc->pipe)); | |
1040 | ||
c5ecd469 PZ |
1041 | __intel_fbc_cleanup_cfb(dev_priv); |
1042 | ||
d029bcad PZ |
1043 | dev_priv->fbc.enabled = false; |
1044 | dev_priv->fbc.crtc = NULL; | |
1045 | } | |
1046 | ||
1047 | /** | |
1048 | * intel_fbc_disable_crtc - disable FBC if it's associated with crtc | |
1049 | * @crtc: the CRTC | |
1050 | * | |
1051 | * This function disables FBC if it's associated with the provided CRTC. | |
1052 | */ | |
1053 | void intel_fbc_disable_crtc(struct intel_crtc *crtc) | |
1054 | { | |
1055 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1056 | ||
1057 | if (!fbc_supported(dev_priv)) | |
1058 | return; | |
1059 | ||
1060 | mutex_lock(&dev_priv->fbc.lock); | |
1061 | if (dev_priv->fbc.crtc == crtc) { | |
1062 | WARN_ON(!dev_priv->fbc.enabled); | |
1063 | WARN_ON(dev_priv->fbc.active); | |
1064 | __intel_fbc_disable(dev_priv); | |
1065 | } | |
1066 | mutex_unlock(&dev_priv->fbc.lock); | |
1067 | } | |
1068 | ||
1069 | /** | |
1070 | * intel_fbc_disable - globally disable FBC | |
1071 | * @dev_priv: i915 device instance | |
1072 | * | |
1073 | * This function disables FBC regardless of which CRTC is associated with it. | |
1074 | */ | |
1075 | void intel_fbc_disable(struct drm_i915_private *dev_priv) | |
1076 | { | |
1077 | if (!fbc_supported(dev_priv)) | |
1078 | return; | |
1079 | ||
1080 | mutex_lock(&dev_priv->fbc.lock); | |
1081 | if (dev_priv->fbc.enabled) | |
1082 | __intel_fbc_disable(dev_priv); | |
1083 | mutex_unlock(&dev_priv->fbc.lock); | |
1084 | } | |
1085 | ||
94b83957 RV |
1086 | /** |
1087 | * intel_fbc_init - Initialize FBC | |
1088 | * @dev_priv: the i915 device | |
1089 | * | |
1090 | * This function might be called during PM init process. | |
1091 | */ | |
7ff0ebcc RV |
1092 | void intel_fbc_init(struct drm_i915_private *dev_priv) |
1093 | { | |
dbef0f15 PZ |
1094 | enum pipe pipe; |
1095 | ||
128d7356 | 1096 | INIT_WORK(&dev_priv->fbc.work.work, intel_fbc_work_fn); |
25ad93fd | 1097 | mutex_init(&dev_priv->fbc.lock); |
d029bcad | 1098 | dev_priv->fbc.enabled = false; |
0e631adc | 1099 | dev_priv->fbc.active = false; |
128d7356 | 1100 | dev_priv->fbc.work.scheduled = false; |
25ad93fd | 1101 | |
7ff0ebcc | 1102 | if (!HAS_FBC(dev_priv)) { |
bf6189c6 | 1103 | dev_priv->fbc.no_fbc_reason = "unsupported by this chipset"; |
7ff0ebcc RV |
1104 | return; |
1105 | } | |
1106 | ||
dbef0f15 PZ |
1107 | for_each_pipe(dev_priv, pipe) { |
1108 | dev_priv->fbc.possible_framebuffer_bits |= | |
1109 | INTEL_FRONTBUFFER_PRIMARY(pipe); | |
1110 | ||
57105022 | 1111 | if (fbc_on_pipe_a_only(dev_priv)) |
dbef0f15 PZ |
1112 | break; |
1113 | } | |
1114 | ||
7ff0ebcc | 1115 | if (INTEL_INFO(dev_priv)->gen >= 7) { |
0e631adc PZ |
1116 | dev_priv->fbc.is_active = ilk_fbc_is_active; |
1117 | dev_priv->fbc.activate = gen7_fbc_activate; | |
1118 | dev_priv->fbc.deactivate = ilk_fbc_deactivate; | |
7ff0ebcc | 1119 | } else if (INTEL_INFO(dev_priv)->gen >= 5) { |
0e631adc PZ |
1120 | dev_priv->fbc.is_active = ilk_fbc_is_active; |
1121 | dev_priv->fbc.activate = ilk_fbc_activate; | |
1122 | dev_priv->fbc.deactivate = ilk_fbc_deactivate; | |
7ff0ebcc | 1123 | } else if (IS_GM45(dev_priv)) { |
0e631adc PZ |
1124 | dev_priv->fbc.is_active = g4x_fbc_is_active; |
1125 | dev_priv->fbc.activate = g4x_fbc_activate; | |
1126 | dev_priv->fbc.deactivate = g4x_fbc_deactivate; | |
7ff0ebcc | 1127 | } else { |
0e631adc PZ |
1128 | dev_priv->fbc.is_active = i8xx_fbc_is_active; |
1129 | dev_priv->fbc.activate = i8xx_fbc_activate; | |
1130 | dev_priv->fbc.deactivate = i8xx_fbc_deactivate; | |
7ff0ebcc RV |
1131 | |
1132 | /* This value was pulled out of someone's hat */ | |
1133 | I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT); | |
1134 | } | |
1135 | ||
b07ea0fa | 1136 | /* We still don't have any sort of hardware state readout for FBC, so |
0e631adc PZ |
1137 | * deactivate it in case the BIOS activated it to make sure software |
1138 | * matches the hardware state. */ | |
1139 | if (dev_priv->fbc.is_active(dev_priv)) | |
1140 | dev_priv->fbc.deactivate(dev_priv); | |
7ff0ebcc | 1141 | } |