Commit | Line | Data |
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7ff0ebcc RV |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
94b83957 RV |
24 | /** |
25 | * DOC: Frame Buffer Compression (FBC) | |
26 | * | |
27 | * FBC tries to save memory bandwidth (and so power consumption) by | |
28 | * compressing the amount of memory used by the display. It is total | |
29 | * transparent to user space and completely handled in the kernel. | |
7ff0ebcc RV |
30 | * |
31 | * The benefits of FBC are mostly visible with solid backgrounds and | |
94b83957 RV |
32 | * variation-less patterns. It comes from keeping the memory footprint small |
33 | * and having fewer memory pages opened and accessed for refreshing the display. | |
7ff0ebcc | 34 | * |
94b83957 RV |
35 | * i915 is responsible to reserve stolen memory for FBC and configure its |
36 | * offset on proper registers. The hardware takes care of all | |
37 | * compress/decompress. However there are many known cases where we have to | |
38 | * forcibly disable it to allow proper screen updates. | |
7ff0ebcc RV |
39 | */ |
40 | ||
94b83957 RV |
41 | #include "intel_drv.h" |
42 | #include "i915_drv.h" | |
43 | ||
9f218336 PZ |
44 | static inline bool fbc_supported(struct drm_i915_private *dev_priv) |
45 | { | |
46 | return dev_priv->fbc.enable_fbc != NULL; | |
47 | } | |
48 | ||
2db3366b PZ |
49 | /* |
50 | * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the | |
51 | * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's | |
52 | * origin so the x and y offsets can actually fit the registers. As a | |
53 | * consequence, the fence doesn't really start exactly at the display plane | |
54 | * address we program because it starts at the real start of the buffer, so we | |
55 | * have to take this into consideration here. | |
56 | */ | |
57 | static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc) | |
58 | { | |
59 | return crtc->base.y - crtc->adjusted_y; | |
60 | } | |
61 | ||
7733b49b | 62 | static void i8xx_fbc_disable(struct drm_i915_private *dev_priv) |
7ff0ebcc | 63 | { |
7ff0ebcc RV |
64 | u32 fbc_ctl; |
65 | ||
66 | dev_priv->fbc.enabled = false; | |
67 | ||
68 | /* Disable compression */ | |
69 | fbc_ctl = I915_READ(FBC_CONTROL); | |
70 | if ((fbc_ctl & FBC_CTL_EN) == 0) | |
71 | return; | |
72 | ||
73 | fbc_ctl &= ~FBC_CTL_EN; | |
74 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
75 | ||
76 | /* Wait for compressing bit to clear */ | |
77 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { | |
78 | DRM_DEBUG_KMS("FBC idle timed out\n"); | |
79 | return; | |
80 | } | |
81 | ||
82 | DRM_DEBUG_KMS("disabled FBC\n"); | |
83 | } | |
84 | ||
220285f2 | 85 | static void i8xx_fbc_enable(struct intel_crtc *crtc) |
7ff0ebcc | 86 | { |
220285f2 PZ |
87 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
88 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
7ff0ebcc | 89 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
7ff0ebcc RV |
90 | int cfb_pitch; |
91 | int i; | |
92 | u32 fbc_ctl; | |
93 | ||
94 | dev_priv->fbc.enabled = true; | |
95 | ||
60ee5cd2 JN |
96 | /* Note: fbc.threshold == 1 for i8xx */ |
97 | cfb_pitch = dev_priv->fbc.uncompressed_size / FBC_LL_SIZE; | |
7ff0ebcc RV |
98 | if (fb->pitches[0] < cfb_pitch) |
99 | cfb_pitch = fb->pitches[0]; | |
100 | ||
101 | /* FBC_CTL wants 32B or 64B units */ | |
7733b49b | 102 | if (IS_GEN2(dev_priv)) |
7ff0ebcc RV |
103 | cfb_pitch = (cfb_pitch / 32) - 1; |
104 | else | |
105 | cfb_pitch = (cfb_pitch / 64) - 1; | |
106 | ||
107 | /* Clear old tags */ | |
108 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) | |
4d110c71 | 109 | I915_WRITE(FBC_TAG(i), 0); |
7ff0ebcc | 110 | |
7733b49b | 111 | if (IS_GEN4(dev_priv)) { |
7ff0ebcc RV |
112 | u32 fbc_ctl2; |
113 | ||
114 | /* Set it up... */ | |
115 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; | |
220285f2 | 116 | fbc_ctl2 |= FBC_CTL_PLANE(crtc->plane); |
7ff0ebcc | 117 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
2db3366b | 118 | I915_WRITE(FBC_FENCE_OFF, get_crtc_fence_y_offset(crtc)); |
7ff0ebcc RV |
119 | } |
120 | ||
121 | /* enable it... */ | |
122 | fbc_ctl = I915_READ(FBC_CONTROL); | |
123 | fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT; | |
124 | fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC; | |
7733b49b | 125 | if (IS_I945GM(dev_priv)) |
7ff0ebcc RV |
126 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
127 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; | |
128 | fbc_ctl |= obj->fence_reg; | |
129 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
130 | ||
131 | DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n", | |
220285f2 | 132 | cfb_pitch, crtc->base.y, plane_name(crtc->plane)); |
7ff0ebcc RV |
133 | } |
134 | ||
7733b49b | 135 | static bool i8xx_fbc_enabled(struct drm_i915_private *dev_priv) |
7ff0ebcc | 136 | { |
7ff0ebcc RV |
137 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; |
138 | } | |
139 | ||
220285f2 | 140 | static void g4x_fbc_enable(struct intel_crtc *crtc) |
7ff0ebcc | 141 | { |
220285f2 PZ |
142 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
143 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
7ff0ebcc | 144 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
7ff0ebcc RV |
145 | u32 dpfc_ctl; |
146 | ||
147 | dev_priv->fbc.enabled = true; | |
148 | ||
220285f2 | 149 | dpfc_ctl = DPFC_CTL_PLANE(crtc->plane) | DPFC_SR_EN; |
7ff0ebcc RV |
150 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
151 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
152 | else | |
153 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
154 | dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; | |
155 | ||
2db3366b | 156 | I915_WRITE(DPFC_FENCE_YOFF, get_crtc_fence_y_offset(crtc)); |
7ff0ebcc RV |
157 | |
158 | /* enable it... */ | |
159 | I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
160 | ||
220285f2 | 161 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane)); |
7ff0ebcc RV |
162 | } |
163 | ||
7733b49b | 164 | static void g4x_fbc_disable(struct drm_i915_private *dev_priv) |
7ff0ebcc | 165 | { |
7ff0ebcc RV |
166 | u32 dpfc_ctl; |
167 | ||
168 | dev_priv->fbc.enabled = false; | |
169 | ||
170 | /* Disable compression */ | |
171 | dpfc_ctl = I915_READ(DPFC_CONTROL); | |
172 | if (dpfc_ctl & DPFC_CTL_EN) { | |
173 | dpfc_ctl &= ~DPFC_CTL_EN; | |
174 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); | |
175 | ||
176 | DRM_DEBUG_KMS("disabled FBC\n"); | |
177 | } | |
178 | } | |
179 | ||
7733b49b | 180 | static bool g4x_fbc_enabled(struct drm_i915_private *dev_priv) |
7ff0ebcc | 181 | { |
7ff0ebcc RV |
182 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; |
183 | } | |
184 | ||
dbef0f15 | 185 | static void intel_fbc_nuke(struct drm_i915_private *dev_priv) |
7ff0ebcc | 186 | { |
dbef0f15 PZ |
187 | I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE); |
188 | POSTING_READ(MSG_FBC_REND_STATE); | |
7ff0ebcc RV |
189 | } |
190 | ||
220285f2 | 191 | static void ilk_fbc_enable(struct intel_crtc *crtc) |
7ff0ebcc | 192 | { |
220285f2 PZ |
193 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
194 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
7ff0ebcc | 195 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
7ff0ebcc | 196 | u32 dpfc_ctl; |
ce65e47b | 197 | int threshold = dev_priv->fbc.threshold; |
2db3366b | 198 | unsigned int y_offset; |
7ff0ebcc RV |
199 | |
200 | dev_priv->fbc.enabled = true; | |
201 | ||
220285f2 | 202 | dpfc_ctl = DPFC_CTL_PLANE(crtc->plane); |
7ff0ebcc | 203 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
ce65e47b | 204 | threshold++; |
7ff0ebcc | 205 | |
ce65e47b | 206 | switch (threshold) { |
7ff0ebcc RV |
207 | case 4: |
208 | case 3: | |
209 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; | |
210 | break; | |
211 | case 2: | |
212 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
213 | break; | |
214 | case 1: | |
215 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
216 | break; | |
217 | } | |
218 | dpfc_ctl |= DPFC_CTL_FENCE_EN; | |
7733b49b | 219 | if (IS_GEN5(dev_priv)) |
7ff0ebcc RV |
220 | dpfc_ctl |= obj->fence_reg; |
221 | ||
2db3366b PZ |
222 | y_offset = get_crtc_fence_y_offset(crtc); |
223 | I915_WRITE(ILK_DPFC_FENCE_YOFF, y_offset); | |
7ff0ebcc RV |
224 | I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID); |
225 | /* enable it... */ | |
226 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
227 | ||
7733b49b | 228 | if (IS_GEN6(dev_priv)) { |
7ff0ebcc RV |
229 | I915_WRITE(SNB_DPFC_CTL_SA, |
230 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); | |
2db3366b | 231 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, y_offset); |
7ff0ebcc RV |
232 | } |
233 | ||
dbef0f15 PZ |
234 | intel_fbc_nuke(dev_priv); |
235 | ||
220285f2 | 236 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane)); |
7ff0ebcc RV |
237 | } |
238 | ||
7733b49b | 239 | static void ilk_fbc_disable(struct drm_i915_private *dev_priv) |
7ff0ebcc | 240 | { |
7ff0ebcc RV |
241 | u32 dpfc_ctl; |
242 | ||
243 | dev_priv->fbc.enabled = false; | |
244 | ||
245 | /* Disable compression */ | |
246 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
247 | if (dpfc_ctl & DPFC_CTL_EN) { | |
248 | dpfc_ctl &= ~DPFC_CTL_EN; | |
249 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); | |
250 | ||
251 | DRM_DEBUG_KMS("disabled FBC\n"); | |
252 | } | |
253 | } | |
254 | ||
7733b49b | 255 | static bool ilk_fbc_enabled(struct drm_i915_private *dev_priv) |
7ff0ebcc | 256 | { |
7ff0ebcc RV |
257 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; |
258 | } | |
259 | ||
220285f2 | 260 | static void gen7_fbc_enable(struct intel_crtc *crtc) |
7ff0ebcc | 261 | { |
220285f2 PZ |
262 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
263 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
7ff0ebcc | 264 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
7ff0ebcc | 265 | u32 dpfc_ctl; |
ce65e47b | 266 | int threshold = dev_priv->fbc.threshold; |
7ff0ebcc RV |
267 | |
268 | dev_priv->fbc.enabled = true; | |
269 | ||
d8514d63 | 270 | dpfc_ctl = 0; |
7733b49b | 271 | if (IS_IVYBRIDGE(dev_priv)) |
220285f2 | 272 | dpfc_ctl |= IVB_DPFC_CTL_PLANE(crtc->plane); |
d8514d63 | 273 | |
7ff0ebcc | 274 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
ce65e47b | 275 | threshold++; |
7ff0ebcc | 276 | |
ce65e47b | 277 | switch (threshold) { |
7ff0ebcc RV |
278 | case 4: |
279 | case 3: | |
280 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; | |
281 | break; | |
282 | case 2: | |
283 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
284 | break; | |
285 | case 1: | |
286 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
287 | break; | |
288 | } | |
289 | ||
290 | dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; | |
291 | ||
292 | if (dev_priv->fbc.false_color) | |
293 | dpfc_ctl |= FBC_CTL_FALSE_COLOR; | |
294 | ||
7733b49b | 295 | if (IS_IVYBRIDGE(dev_priv)) { |
7ff0ebcc RV |
296 | /* WaFbcAsynchFlipDisableFbcQueue:ivb */ |
297 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
298 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
299 | ILK_FBCQ_DIS); | |
40f4022e | 300 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
7ff0ebcc | 301 | /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ |
220285f2 PZ |
302 | I915_WRITE(CHICKEN_PIPESL_1(crtc->pipe), |
303 | I915_READ(CHICKEN_PIPESL_1(crtc->pipe)) | | |
7ff0ebcc RV |
304 | HSW_FBCQ_DIS); |
305 | } | |
306 | ||
57012be9 PZ |
307 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
308 | ||
7ff0ebcc RV |
309 | I915_WRITE(SNB_DPFC_CTL_SA, |
310 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); | |
2db3366b | 311 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, get_crtc_fence_y_offset(crtc)); |
7ff0ebcc | 312 | |
dbef0f15 | 313 | intel_fbc_nuke(dev_priv); |
7ff0ebcc | 314 | |
220285f2 | 315 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane)); |
7ff0ebcc RV |
316 | } |
317 | ||
94b83957 RV |
318 | /** |
319 | * intel_fbc_enabled - Is FBC enabled? | |
7733b49b | 320 | * @dev_priv: i915 device instance |
94b83957 RV |
321 | * |
322 | * This function is used to verify the current state of FBC. | |
323 | * FIXME: This should be tracked in the plane config eventually | |
324 | * instead of queried at runtime for most callers. | |
325 | */ | |
7733b49b | 326 | bool intel_fbc_enabled(struct drm_i915_private *dev_priv) |
7ff0ebcc | 327 | { |
7ff0ebcc RV |
328 | return dev_priv->fbc.enabled; |
329 | } | |
330 | ||
e8cb8d69 PZ |
331 | static void intel_fbc_enable(struct intel_crtc *crtc, |
332 | const struct drm_framebuffer *fb) | |
333 | { | |
334 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
335 | ||
336 | dev_priv->fbc.enable_fbc(crtc); | |
337 | ||
338 | dev_priv->fbc.crtc = crtc; | |
339 | dev_priv->fbc.fb_id = fb->base.id; | |
340 | dev_priv->fbc.y = crtc->base.y; | |
341 | } | |
342 | ||
7ff0ebcc RV |
343 | static void intel_fbc_work_fn(struct work_struct *__work) |
344 | { | |
345 | struct intel_fbc_work *work = | |
346 | container_of(to_delayed_work(__work), | |
347 | struct intel_fbc_work, work); | |
220285f2 PZ |
348 | struct drm_i915_private *dev_priv = work->crtc->base.dev->dev_private; |
349 | struct drm_framebuffer *crtc_fb = work->crtc->base.primary->fb; | |
7ff0ebcc | 350 | |
25ad93fd | 351 | mutex_lock(&dev_priv->fbc.lock); |
7ff0ebcc RV |
352 | if (work == dev_priv->fbc.fbc_work) { |
353 | /* Double check that we haven't switched fb without cancelling | |
354 | * the prior work. | |
355 | */ | |
e8cb8d69 PZ |
356 | if (crtc_fb == work->fb) |
357 | intel_fbc_enable(work->crtc, work->fb); | |
7ff0ebcc RV |
358 | |
359 | dev_priv->fbc.fbc_work = NULL; | |
360 | } | |
25ad93fd | 361 | mutex_unlock(&dev_priv->fbc.lock); |
7ff0ebcc RV |
362 | |
363 | kfree(work); | |
364 | } | |
365 | ||
366 | static void intel_fbc_cancel_work(struct drm_i915_private *dev_priv) | |
367 | { | |
25ad93fd PZ |
368 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
369 | ||
7ff0ebcc RV |
370 | if (dev_priv->fbc.fbc_work == NULL) |
371 | return; | |
372 | ||
373 | DRM_DEBUG_KMS("cancelling pending FBC enable\n"); | |
374 | ||
375 | /* Synchronisation is provided by struct_mutex and checking of | |
376 | * dev_priv->fbc.fbc_work, so we can perform the cancellation | |
377 | * entirely asynchronously. | |
378 | */ | |
379 | if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work)) | |
380 | /* tasklet was killed before being run, clean up */ | |
381 | kfree(dev_priv->fbc.fbc_work); | |
382 | ||
383 | /* Mark the work as no longer wanted so that if it does | |
384 | * wake-up (because the work was already running and waiting | |
385 | * for our mutex), it will discover that is no longer | |
386 | * necessary to run. | |
387 | */ | |
388 | dev_priv->fbc.fbc_work = NULL; | |
389 | } | |
390 | ||
e8cb8d69 | 391 | static void intel_fbc_schedule_enable(struct intel_crtc *crtc) |
7ff0ebcc RV |
392 | { |
393 | struct intel_fbc_work *work; | |
220285f2 | 394 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
7ff0ebcc | 395 | |
25ad93fd PZ |
396 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
397 | ||
7ff0ebcc RV |
398 | intel_fbc_cancel_work(dev_priv); |
399 | ||
400 | work = kzalloc(sizeof(*work), GFP_KERNEL); | |
401 | if (work == NULL) { | |
402 | DRM_ERROR("Failed to allocate FBC work structure\n"); | |
e8cb8d69 | 403 | intel_fbc_enable(crtc, crtc->base.primary->fb); |
7ff0ebcc RV |
404 | return; |
405 | } | |
406 | ||
407 | work->crtc = crtc; | |
220285f2 | 408 | work->fb = crtc->base.primary->fb; |
7ff0ebcc RV |
409 | INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); |
410 | ||
411 | dev_priv->fbc.fbc_work = work; | |
412 | ||
413 | /* Delay the actual enabling to let pageflipping cease and the | |
414 | * display to settle before starting the compression. Note that | |
415 | * this delay also serves a second purpose: it allows for a | |
416 | * vblank to pass after disabling the FBC before we attempt | |
417 | * to modify the control registers. | |
418 | * | |
419 | * A more complicated solution would involve tracking vblanks | |
420 | * following the termination of the page-flipping sequence | |
421 | * and indeed performing the enable as a co-routine and not | |
422 | * waiting synchronously upon the vblank. | |
423 | * | |
424 | * WaFbcWaitForVBlankBeforeEnable:ilk,snb | |
425 | */ | |
426 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); | |
427 | } | |
428 | ||
7733b49b | 429 | static void __intel_fbc_disable(struct drm_i915_private *dev_priv) |
25ad93fd | 430 | { |
25ad93fd PZ |
431 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
432 | ||
433 | intel_fbc_cancel_work(dev_priv); | |
434 | ||
7733b49b | 435 | dev_priv->fbc.disable_fbc(dev_priv); |
25ad93fd PZ |
436 | dev_priv->fbc.crtc = NULL; |
437 | } | |
438 | ||
94b83957 RV |
439 | /** |
440 | * intel_fbc_disable - disable FBC | |
7733b49b | 441 | * @dev_priv: i915 device instance |
94b83957 RV |
442 | * |
443 | * This function disables FBC. | |
444 | */ | |
7733b49b | 445 | void intel_fbc_disable(struct drm_i915_private *dev_priv) |
7ff0ebcc | 446 | { |
9f218336 | 447 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
448 | return; |
449 | ||
25ad93fd | 450 | mutex_lock(&dev_priv->fbc.lock); |
7733b49b | 451 | __intel_fbc_disable(dev_priv); |
25ad93fd PZ |
452 | mutex_unlock(&dev_priv->fbc.lock); |
453 | } | |
7ff0ebcc | 454 | |
25ad93fd PZ |
455 | /* |
456 | * intel_fbc_disable_crtc - disable FBC if it's associated with crtc | |
457 | * @crtc: the CRTC | |
458 | * | |
459 | * This function disables FBC if it's associated with the provided CRTC. | |
460 | */ | |
461 | void intel_fbc_disable_crtc(struct intel_crtc *crtc) | |
462 | { | |
7733b49b | 463 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
7ff0ebcc | 464 | |
9f218336 | 465 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
466 | return; |
467 | ||
25ad93fd PZ |
468 | mutex_lock(&dev_priv->fbc.lock); |
469 | if (dev_priv->fbc.crtc == crtc) | |
7733b49b | 470 | __intel_fbc_disable(dev_priv); |
25ad93fd | 471 | mutex_unlock(&dev_priv->fbc.lock); |
7ff0ebcc RV |
472 | } |
473 | ||
2e8144a5 | 474 | static void set_no_fbc_reason(struct drm_i915_private *dev_priv, |
bf6189c6 | 475 | const char *reason) |
7ff0ebcc RV |
476 | { |
477 | if (dev_priv->fbc.no_fbc_reason == reason) | |
2e8144a5 | 478 | return; |
7ff0ebcc RV |
479 | |
480 | dev_priv->fbc.no_fbc_reason = reason; | |
bf6189c6 | 481 | DRM_DEBUG_KMS("Disabling FBC: %s\n", reason); |
7ff0ebcc RV |
482 | } |
483 | ||
95106753 PZ |
484 | static struct drm_crtc *intel_fbc_find_crtc(struct drm_i915_private *dev_priv) |
485 | { | |
95106753 | 486 | struct drm_crtc *crtc = NULL, *tmp_crtc; |
68b92147 | 487 | enum pipe pipe; |
232fd934 | 488 | bool pipe_a_only = false; |
68b92147 PZ |
489 | |
490 | if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) | |
491 | pipe_a_only = true; | |
492 | ||
493 | for_each_pipe(dev_priv, pipe) { | |
494 | tmp_crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
95106753 | 495 | |
95106753 | 496 | if (intel_crtc_active(tmp_crtc) && |
232fd934 | 497 | to_intel_plane_state(tmp_crtc->primary->state)->visible) |
95106753 | 498 | crtc = tmp_crtc; |
68b92147 PZ |
499 | |
500 | if (pipe_a_only) | |
501 | break; | |
95106753 PZ |
502 | } |
503 | ||
8df5dd57 | 504 | if (!crtc || crtc->primary->fb == NULL) |
95106753 | 505 | return NULL; |
95106753 PZ |
506 | |
507 | return crtc; | |
508 | } | |
509 | ||
232fd934 PZ |
510 | static bool multiple_pipes_ok(struct drm_i915_private *dev_priv) |
511 | { | |
512 | enum pipe pipe; | |
513 | int n_pipes = 0; | |
514 | struct drm_crtc *crtc; | |
515 | ||
516 | if (INTEL_INFO(dev_priv)->gen > 4) | |
517 | return true; | |
518 | ||
519 | for_each_pipe(dev_priv, pipe) { | |
520 | crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
521 | ||
522 | if (intel_crtc_active(crtc) && | |
523 | to_intel_plane_state(crtc->primary->state)->visible) | |
524 | n_pipes++; | |
525 | } | |
526 | ||
527 | return (n_pipes < 2); | |
528 | } | |
529 | ||
7733b49b | 530 | static int find_compression_threshold(struct drm_i915_private *dev_priv, |
fc786728 PZ |
531 | struct drm_mm_node *node, |
532 | int size, | |
533 | int fb_cpp) | |
534 | { | |
fc786728 PZ |
535 | int compression_threshold = 1; |
536 | int ret; | |
a9da512b PZ |
537 | u64 end; |
538 | ||
539 | /* The FBC hardware for BDW/SKL doesn't have access to the stolen | |
540 | * reserved range size, so it always assumes the maximum (8mb) is used. | |
541 | * If we enable FBC using a CFB on that memory range we'll get FIFO | |
542 | * underruns, even if that range is not reserved by the BIOS. */ | |
ef11bdb3 RV |
543 | if (IS_BROADWELL(dev_priv) || |
544 | IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) | |
a9da512b PZ |
545 | end = dev_priv->gtt.stolen_size - 8 * 1024 * 1024; |
546 | else | |
547 | end = dev_priv->gtt.stolen_usable_size; | |
fc786728 PZ |
548 | |
549 | /* HACK: This code depends on what we will do in *_enable_fbc. If that | |
550 | * code changes, this code needs to change as well. | |
551 | * | |
552 | * The enable_fbc code will attempt to use one of our 2 compression | |
553 | * thresholds, therefore, in that case, we only have 1 resort. | |
554 | */ | |
555 | ||
556 | /* Try to over-allocate to reduce reallocations and fragmentation. */ | |
a9da512b PZ |
557 | ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1, |
558 | 4096, 0, end); | |
fc786728 PZ |
559 | if (ret == 0) |
560 | return compression_threshold; | |
561 | ||
562 | again: | |
563 | /* HW's ability to limit the CFB is 1:4 */ | |
564 | if (compression_threshold > 4 || | |
565 | (fb_cpp == 2 && compression_threshold == 2)) | |
566 | return 0; | |
567 | ||
a9da512b PZ |
568 | ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1, |
569 | 4096, 0, end); | |
7733b49b | 570 | if (ret && INTEL_INFO(dev_priv)->gen <= 4) { |
fc786728 PZ |
571 | return 0; |
572 | } else if (ret) { | |
573 | compression_threshold <<= 1; | |
574 | goto again; | |
575 | } else { | |
576 | return compression_threshold; | |
577 | } | |
578 | } | |
579 | ||
7733b49b PZ |
580 | static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv, int size, |
581 | int fb_cpp) | |
fc786728 | 582 | { |
fc786728 PZ |
583 | struct drm_mm_node *uninitialized_var(compressed_llb); |
584 | int ret; | |
585 | ||
7733b49b | 586 | ret = find_compression_threshold(dev_priv, &dev_priv->fbc.compressed_fb, |
fc786728 PZ |
587 | size, fb_cpp); |
588 | if (!ret) | |
589 | goto err_llb; | |
590 | else if (ret > 1) { | |
591 | DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n"); | |
592 | ||
593 | } | |
594 | ||
595 | dev_priv->fbc.threshold = ret; | |
596 | ||
597 | if (INTEL_INFO(dev_priv)->gen >= 5) | |
598 | I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start); | |
7733b49b | 599 | else if (IS_GM45(dev_priv)) { |
fc786728 PZ |
600 | I915_WRITE(DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start); |
601 | } else { | |
602 | compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL); | |
603 | if (!compressed_llb) | |
604 | goto err_fb; | |
605 | ||
606 | ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb, | |
607 | 4096, 4096); | |
608 | if (ret) | |
609 | goto err_fb; | |
610 | ||
611 | dev_priv->fbc.compressed_llb = compressed_llb; | |
612 | ||
613 | I915_WRITE(FBC_CFB_BASE, | |
614 | dev_priv->mm.stolen_base + dev_priv->fbc.compressed_fb.start); | |
615 | I915_WRITE(FBC_LL_BASE, | |
616 | dev_priv->mm.stolen_base + compressed_llb->start); | |
617 | } | |
618 | ||
619 | dev_priv->fbc.uncompressed_size = size; | |
620 | ||
b8bf5d7f PZ |
621 | DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n", |
622 | dev_priv->fbc.compressed_fb.size, | |
623 | dev_priv->fbc.threshold); | |
fc786728 PZ |
624 | |
625 | return 0; | |
626 | ||
627 | err_fb: | |
628 | kfree(compressed_llb); | |
629 | i915_gem_stolen_remove_node(dev_priv, &dev_priv->fbc.compressed_fb); | |
630 | err_llb: | |
631 | pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size); | |
632 | return -ENOSPC; | |
633 | } | |
634 | ||
7733b49b | 635 | static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) |
fc786728 | 636 | { |
fc786728 PZ |
637 | if (dev_priv->fbc.uncompressed_size == 0) |
638 | return; | |
639 | ||
640 | i915_gem_stolen_remove_node(dev_priv, &dev_priv->fbc.compressed_fb); | |
641 | ||
642 | if (dev_priv->fbc.compressed_llb) { | |
643 | i915_gem_stolen_remove_node(dev_priv, | |
644 | dev_priv->fbc.compressed_llb); | |
645 | kfree(dev_priv->fbc.compressed_llb); | |
646 | } | |
647 | ||
648 | dev_priv->fbc.uncompressed_size = 0; | |
649 | } | |
650 | ||
7733b49b | 651 | void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) |
25ad93fd | 652 | { |
9f218336 | 653 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
654 | return; |
655 | ||
25ad93fd | 656 | mutex_lock(&dev_priv->fbc.lock); |
7733b49b | 657 | __intel_fbc_cleanup_cfb(dev_priv); |
25ad93fd PZ |
658 | mutex_unlock(&dev_priv->fbc.lock); |
659 | } | |
660 | ||
c4ffd409 PZ |
661 | /* |
662 | * For SKL+, the plane source size used by the hardware is based on the value we | |
663 | * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value | |
664 | * we wrote to PIPESRC. | |
665 | */ | |
666 | static void intel_fbc_get_plane_source_size(struct intel_crtc *crtc, | |
667 | int *width, int *height) | |
fc786728 | 668 | { |
c4ffd409 PZ |
669 | struct intel_plane_state *plane_state = |
670 | to_intel_plane_state(crtc->base.primary->state); | |
671 | int w, h; | |
672 | ||
673 | if (intel_rotation_90_or_270(plane_state->base.rotation)) { | |
674 | w = drm_rect_height(&plane_state->src) >> 16; | |
675 | h = drm_rect_width(&plane_state->src) >> 16; | |
676 | } else { | |
677 | w = drm_rect_width(&plane_state->src) >> 16; | |
678 | h = drm_rect_height(&plane_state->src) >> 16; | |
679 | } | |
680 | ||
681 | if (width) | |
682 | *width = w; | |
683 | if (height) | |
684 | *height = h; | |
685 | } | |
686 | ||
687 | static int intel_fbc_calculate_cfb_size(struct intel_crtc *crtc) | |
688 | { | |
689 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
690 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
691 | int lines; | |
692 | ||
693 | intel_fbc_get_plane_source_size(crtc, NULL, &lines); | |
694 | if (INTEL_INFO(dev_priv)->gen >= 7) | |
695 | lines = min(lines, 2048); | |
696 | ||
697 | return lines * fb->pitches[0]; | |
698 | } | |
699 | ||
700 | static int intel_fbc_setup_cfb(struct intel_crtc *crtc) | |
701 | { | |
702 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
703 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
704 | int size, cpp; | |
705 | ||
706 | size = intel_fbc_calculate_cfb_size(crtc); | |
707 | cpp = drm_format_plane_cpp(fb->pixel_format, 0); | |
708 | ||
fc786728 PZ |
709 | if (size <= dev_priv->fbc.uncompressed_size) |
710 | return 0; | |
711 | ||
712 | /* Release any current block */ | |
7733b49b | 713 | __intel_fbc_cleanup_cfb(dev_priv); |
fc786728 | 714 | |
c4ffd409 | 715 | return intel_fbc_alloc_cfb(dev_priv, size, cpp); |
fc786728 PZ |
716 | } |
717 | ||
adf70c65 PZ |
718 | static bool stride_is_valid(struct drm_i915_private *dev_priv, |
719 | unsigned int stride) | |
720 | { | |
721 | /* These should have been caught earlier. */ | |
722 | WARN_ON(stride < 512); | |
723 | WARN_ON((stride & (64 - 1)) != 0); | |
724 | ||
725 | /* Below are the additional FBC restrictions. */ | |
726 | ||
727 | if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv)) | |
728 | return stride == 4096 || stride == 8192; | |
729 | ||
730 | if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048) | |
731 | return false; | |
732 | ||
733 | if (stride > 16384) | |
734 | return false; | |
735 | ||
736 | return true; | |
737 | } | |
738 | ||
b9e831dc PZ |
739 | static bool pixel_format_is_valid(struct drm_framebuffer *fb) |
740 | { | |
741 | struct drm_device *dev = fb->dev; | |
742 | struct drm_i915_private *dev_priv = dev->dev_private; | |
743 | ||
744 | switch (fb->pixel_format) { | |
745 | case DRM_FORMAT_XRGB8888: | |
746 | case DRM_FORMAT_XBGR8888: | |
747 | return true; | |
748 | case DRM_FORMAT_XRGB1555: | |
749 | case DRM_FORMAT_RGB565: | |
750 | /* 16bpp not supported on gen2 */ | |
751 | if (IS_GEN2(dev)) | |
752 | return false; | |
753 | /* WaFbcOnly1to1Ratio:ctg */ | |
754 | if (IS_G4X(dev_priv)) | |
755 | return false; | |
756 | return true; | |
757 | default: | |
758 | return false; | |
759 | } | |
760 | } | |
761 | ||
856312ae PZ |
762 | /* |
763 | * For some reason, the hardware tracking starts looking at whatever we | |
764 | * programmed as the display plane base address register. It does not look at | |
765 | * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y} | |
766 | * variables instead of just looking at the pipe/plane size. | |
767 | */ | |
768 | static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc) | |
3c5f174e PZ |
769 | { |
770 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
856312ae | 771 | unsigned int effective_w, effective_h, max_w, max_h; |
3c5f174e PZ |
772 | |
773 | if (INTEL_INFO(dev_priv)->gen >= 8 || IS_HASWELL(dev_priv)) { | |
774 | max_w = 4096; | |
775 | max_h = 4096; | |
776 | } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { | |
777 | max_w = 4096; | |
778 | max_h = 2048; | |
779 | } else { | |
780 | max_w = 2048; | |
781 | max_h = 1536; | |
782 | } | |
783 | ||
856312ae PZ |
784 | intel_fbc_get_plane_source_size(crtc, &effective_w, &effective_h); |
785 | effective_w += crtc->adjusted_x; | |
786 | effective_h += crtc->adjusted_y; | |
787 | ||
788 | return effective_w <= max_w && effective_h <= max_h; | |
3c5f174e PZ |
789 | } |
790 | ||
7ff0ebcc | 791 | /** |
25ad93fd | 792 | * __intel_fbc_update - enable/disable FBC as needed, unlocked |
7733b49b | 793 | * @dev_priv: i915 device instance |
7ff0ebcc RV |
794 | * |
795 | * Set up the framebuffer compression hardware at mode set time. We | |
796 | * enable it if possible: | |
797 | * - plane A only (on pre-965) | |
798 | * - no pixel mulitply/line duplication | |
799 | * - no alpha buffer discard | |
800 | * - no dual wide | |
801 | * - framebuffer <= max_hdisplay in width, max_vdisplay in height | |
802 | * | |
803 | * We can't assume that any compression will take place (worst case), | |
804 | * so the compressed buffer has to be the same size as the uncompressed | |
805 | * one. It also must reside (along with the line length buffer) in | |
806 | * stolen memory. | |
807 | * | |
808 | * We need to enable/disable FBC on a global basis. | |
809 | */ | |
7733b49b | 810 | static void __intel_fbc_update(struct drm_i915_private *dev_priv) |
7ff0ebcc | 811 | { |
95106753 | 812 | struct drm_crtc *crtc = NULL; |
7ff0ebcc RV |
813 | struct intel_crtc *intel_crtc; |
814 | struct drm_framebuffer *fb; | |
815 | struct drm_i915_gem_object *obj; | |
816 | const struct drm_display_mode *adjusted_mode; | |
7ff0ebcc | 817 | |
25ad93fd PZ |
818 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
819 | ||
bd49234b | 820 | /* disable framebuffer compression in vGPU */ |
7733b49b | 821 | if (intel_vgpu_active(dev_priv->dev)) |
bd49234b YZ |
822 | i915.enable_fbc = 0; |
823 | ||
7cc65746 | 824 | if (i915.enable_fbc < 0) { |
bf6189c6 | 825 | set_no_fbc_reason(dev_priv, "disabled per chip default"); |
7cc65746 PZ |
826 | goto out_disable; |
827 | } | |
828 | ||
ab585dea | 829 | if (!i915.enable_fbc) { |
bf6189c6 | 830 | set_no_fbc_reason(dev_priv, "disabled per module param"); |
7cc65746 | 831 | goto out_disable; |
7ff0ebcc RV |
832 | } |
833 | ||
834 | /* | |
835 | * If FBC is already on, we just have to verify that we can | |
836 | * keep it that way... | |
837 | * Need to disable if: | |
838 | * - more than one pipe is active | |
839 | * - changing FBC params (stride, fence, mode) | |
840 | * - new fb is too large to fit in compressed buffer | |
841 | * - going to an unsupported config (interlace, pixel multiply, etc.) | |
842 | */ | |
95106753 | 843 | crtc = intel_fbc_find_crtc(dev_priv); |
8df5dd57 | 844 | if (!crtc) { |
bf6189c6 | 845 | set_no_fbc_reason(dev_priv, "no output"); |
7ff0ebcc | 846 | goto out_disable; |
8df5dd57 | 847 | } |
7ff0ebcc | 848 | |
232fd934 | 849 | if (!multiple_pipes_ok(dev_priv)) { |
bf6189c6 | 850 | set_no_fbc_reason(dev_priv, "more than one pipe active"); |
232fd934 PZ |
851 | goto out_disable; |
852 | } | |
853 | ||
7ff0ebcc RV |
854 | intel_crtc = to_intel_crtc(crtc); |
855 | fb = crtc->primary->fb; | |
856 | obj = intel_fb_obj(fb); | |
6e3c9717 | 857 | adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
7ff0ebcc | 858 | |
7ff0ebcc RV |
859 | if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) || |
860 | (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) { | |
bf6189c6 | 861 | set_no_fbc_reason(dev_priv, "incompatible mode"); |
7ff0ebcc RV |
862 | goto out_disable; |
863 | } | |
864 | ||
856312ae | 865 | if (!intel_fbc_hw_tracking_covers_screen(intel_crtc)) { |
bf6189c6 | 866 | set_no_fbc_reason(dev_priv, "mode too large for compression"); |
7ff0ebcc RV |
867 | goto out_disable; |
868 | } | |
3c5f174e | 869 | |
7733b49b | 870 | if ((INTEL_INFO(dev_priv)->gen < 4 || HAS_DDI(dev_priv)) && |
7ff0ebcc | 871 | intel_crtc->plane != PLANE_A) { |
bf6189c6 | 872 | set_no_fbc_reason(dev_priv, "FBC unsupported on plane"); |
7ff0ebcc RV |
873 | goto out_disable; |
874 | } | |
875 | ||
876 | /* The use of a CPU fence is mandatory in order to detect writes | |
877 | * by the CPU to the scanout and trigger updates to the FBC. | |
878 | */ | |
879 | if (obj->tiling_mode != I915_TILING_X || | |
880 | obj->fence_reg == I915_FENCE_REG_NONE) { | |
bf6189c6 | 881 | set_no_fbc_reason(dev_priv, "framebuffer not tiled or fenced"); |
7ff0ebcc RV |
882 | goto out_disable; |
883 | } | |
7733b49b | 884 | if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) && |
8e7d688b | 885 | crtc->primary->state->rotation != BIT(DRM_ROTATE_0)) { |
bf6189c6 | 886 | set_no_fbc_reason(dev_priv, "rotation unsupported"); |
7ff0ebcc RV |
887 | goto out_disable; |
888 | } | |
889 | ||
adf70c65 | 890 | if (!stride_is_valid(dev_priv, fb->pitches[0])) { |
bf6189c6 | 891 | set_no_fbc_reason(dev_priv, "framebuffer stride not supported"); |
adf70c65 PZ |
892 | goto out_disable; |
893 | } | |
894 | ||
b9e831dc | 895 | if (!pixel_format_is_valid(fb)) { |
bf6189c6 | 896 | set_no_fbc_reason(dev_priv, "pixel format is invalid"); |
b9e831dc PZ |
897 | goto out_disable; |
898 | } | |
899 | ||
7ff0ebcc | 900 | /* If the kernel debugger is active, always disable compression */ |
89351085 | 901 | if (in_dbg_master()) { |
bf6189c6 | 902 | set_no_fbc_reason(dev_priv, "Kernel debugger is active"); |
7ff0ebcc | 903 | goto out_disable; |
89351085 | 904 | } |
7ff0ebcc | 905 | |
7b24c9a6 PZ |
906 | /* WaFbcExceedCdClockThreshold:hsw,bdw */ |
907 | if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) && | |
908 | ilk_pipe_pixel_rate(intel_crtc->config) >= | |
909 | dev_priv->cdclk_freq * 95 / 100) { | |
bf6189c6 | 910 | set_no_fbc_reason(dev_priv, "pixel rate is too big"); |
7b24c9a6 PZ |
911 | goto out_disable; |
912 | } | |
913 | ||
c4ffd409 | 914 | if (intel_fbc_setup_cfb(intel_crtc)) { |
bf6189c6 | 915 | set_no_fbc_reason(dev_priv, "not enough stolen memory"); |
7ff0ebcc RV |
916 | goto out_disable; |
917 | } | |
918 | ||
919 | /* If the scanout has not changed, don't modify the FBC settings. | |
920 | * Note that we make the fundamental assumption that the fb->obj | |
921 | * cannot be unpinned (and have its GTT offset and fence revoked) | |
922 | * without first being decoupled from the scanout and FBC disabled. | |
923 | */ | |
e35fef21 | 924 | if (dev_priv->fbc.crtc == intel_crtc && |
7ff0ebcc RV |
925 | dev_priv->fbc.fb_id == fb->base.id && |
926 | dev_priv->fbc.y == crtc->y) | |
927 | return; | |
928 | ||
7733b49b | 929 | if (intel_fbc_enabled(dev_priv)) { |
7ff0ebcc RV |
930 | /* We update FBC along two paths, after changing fb/crtc |
931 | * configuration (modeswitching) and after page-flipping | |
932 | * finishes. For the latter, we know that not only did | |
933 | * we disable the FBC at the start of the page-flip | |
934 | * sequence, but also more than one vblank has passed. | |
935 | * | |
936 | * For the former case of modeswitching, it is possible | |
937 | * to switch between two FBC valid configurations | |
938 | * instantaneously so we do need to disable the FBC | |
939 | * before we can modify its control registers. We also | |
940 | * have to wait for the next vblank for that to take | |
941 | * effect. However, since we delay enabling FBC we can | |
942 | * assume that a vblank has passed since disabling and | |
943 | * that we can safely alter the registers in the deferred | |
944 | * callback. | |
945 | * | |
946 | * In the scenario that we go from a valid to invalid | |
947 | * and then back to valid FBC configuration we have | |
948 | * no strict enforcement that a vblank occurred since | |
949 | * disabling the FBC. However, along all current pipe | |
950 | * disabling paths we do need to wait for a vblank at | |
951 | * some point. And we wait before enabling FBC anyway. | |
952 | */ | |
953 | DRM_DEBUG_KMS("disabling active FBC for update\n"); | |
7733b49b | 954 | __intel_fbc_disable(dev_priv); |
7ff0ebcc RV |
955 | } |
956 | ||
e8cb8d69 | 957 | intel_fbc_schedule_enable(intel_crtc); |
793af070 | 958 | dev_priv->fbc.no_fbc_reason = "FBC enabled (not necessarily active)"; |
7ff0ebcc RV |
959 | return; |
960 | ||
961 | out_disable: | |
962 | /* Multiple disables should be harmless */ | |
7733b49b | 963 | if (intel_fbc_enabled(dev_priv)) { |
7ff0ebcc | 964 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); |
7733b49b | 965 | __intel_fbc_disable(dev_priv); |
7ff0ebcc | 966 | } |
7733b49b | 967 | __intel_fbc_cleanup_cfb(dev_priv); |
25ad93fd PZ |
968 | } |
969 | ||
970 | /* | |
971 | * intel_fbc_update - enable/disable FBC as needed | |
7733b49b | 972 | * @dev_priv: i915 device instance |
25ad93fd PZ |
973 | * |
974 | * This function reevaluates the overall state and enables or disables FBC. | |
975 | */ | |
7733b49b | 976 | void intel_fbc_update(struct drm_i915_private *dev_priv) |
25ad93fd | 977 | { |
9f218336 | 978 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
979 | return; |
980 | ||
25ad93fd | 981 | mutex_lock(&dev_priv->fbc.lock); |
7733b49b | 982 | __intel_fbc_update(dev_priv); |
25ad93fd | 983 | mutex_unlock(&dev_priv->fbc.lock); |
7ff0ebcc RV |
984 | } |
985 | ||
dbef0f15 PZ |
986 | void intel_fbc_invalidate(struct drm_i915_private *dev_priv, |
987 | unsigned int frontbuffer_bits, | |
988 | enum fb_op_origin origin) | |
989 | { | |
dbef0f15 PZ |
990 | unsigned int fbc_bits; |
991 | ||
9f218336 | 992 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
993 | return; |
994 | ||
dbef0f15 PZ |
995 | if (origin == ORIGIN_GTT) |
996 | return; | |
997 | ||
25ad93fd PZ |
998 | mutex_lock(&dev_priv->fbc.lock); |
999 | ||
dbef0f15 PZ |
1000 | if (dev_priv->fbc.enabled) |
1001 | fbc_bits = INTEL_FRONTBUFFER_PRIMARY(dev_priv->fbc.crtc->pipe); | |
1002 | else if (dev_priv->fbc.fbc_work) | |
1003 | fbc_bits = INTEL_FRONTBUFFER_PRIMARY( | |
220285f2 | 1004 | dev_priv->fbc.fbc_work->crtc->pipe); |
dbef0f15 PZ |
1005 | else |
1006 | fbc_bits = dev_priv->fbc.possible_framebuffer_bits; | |
1007 | ||
1008 | dev_priv->fbc.busy_bits |= (fbc_bits & frontbuffer_bits); | |
1009 | ||
1010 | if (dev_priv->fbc.busy_bits) | |
7733b49b | 1011 | __intel_fbc_disable(dev_priv); |
25ad93fd PZ |
1012 | |
1013 | mutex_unlock(&dev_priv->fbc.lock); | |
dbef0f15 PZ |
1014 | } |
1015 | ||
1016 | void intel_fbc_flush(struct drm_i915_private *dev_priv, | |
6f4551fe | 1017 | unsigned int frontbuffer_bits, enum fb_op_origin origin) |
dbef0f15 | 1018 | { |
9f218336 | 1019 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
1020 | return; |
1021 | ||
6f4551fe PZ |
1022 | if (origin == ORIGIN_GTT) |
1023 | return; | |
25ad93fd | 1024 | |
6f4551fe | 1025 | mutex_lock(&dev_priv->fbc.lock); |
dbef0f15 PZ |
1026 | |
1027 | dev_priv->fbc.busy_bits &= ~frontbuffer_bits; | |
1028 | ||
6f4551fe PZ |
1029 | if (!dev_priv->fbc.busy_bits) { |
1030 | __intel_fbc_disable(dev_priv); | |
7733b49b | 1031 | __intel_fbc_update(dev_priv); |
6f4551fe | 1032 | } |
25ad93fd | 1033 | |
25ad93fd | 1034 | mutex_unlock(&dev_priv->fbc.lock); |
dbef0f15 PZ |
1035 | } |
1036 | ||
94b83957 RV |
1037 | /** |
1038 | * intel_fbc_init - Initialize FBC | |
1039 | * @dev_priv: the i915 device | |
1040 | * | |
1041 | * This function might be called during PM init process. | |
1042 | */ | |
7ff0ebcc RV |
1043 | void intel_fbc_init(struct drm_i915_private *dev_priv) |
1044 | { | |
dbef0f15 PZ |
1045 | enum pipe pipe; |
1046 | ||
25ad93fd PZ |
1047 | mutex_init(&dev_priv->fbc.lock); |
1048 | ||
7ff0ebcc RV |
1049 | if (!HAS_FBC(dev_priv)) { |
1050 | dev_priv->fbc.enabled = false; | |
bf6189c6 | 1051 | dev_priv->fbc.no_fbc_reason = "unsupported by this chipset"; |
7ff0ebcc RV |
1052 | return; |
1053 | } | |
1054 | ||
dbef0f15 PZ |
1055 | for_each_pipe(dev_priv, pipe) { |
1056 | dev_priv->fbc.possible_framebuffer_bits |= | |
1057 | INTEL_FRONTBUFFER_PRIMARY(pipe); | |
1058 | ||
1059 | if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) | |
1060 | break; | |
1061 | } | |
1062 | ||
7ff0ebcc | 1063 | if (INTEL_INFO(dev_priv)->gen >= 7) { |
ff2a3117 PZ |
1064 | dev_priv->fbc.fbc_enabled = ilk_fbc_enabled; |
1065 | dev_priv->fbc.enable_fbc = gen7_fbc_enable; | |
1066 | dev_priv->fbc.disable_fbc = ilk_fbc_disable; | |
7ff0ebcc | 1067 | } else if (INTEL_INFO(dev_priv)->gen >= 5) { |
ff2a3117 PZ |
1068 | dev_priv->fbc.fbc_enabled = ilk_fbc_enabled; |
1069 | dev_priv->fbc.enable_fbc = ilk_fbc_enable; | |
1070 | dev_priv->fbc.disable_fbc = ilk_fbc_disable; | |
7ff0ebcc | 1071 | } else if (IS_GM45(dev_priv)) { |
ff2a3117 PZ |
1072 | dev_priv->fbc.fbc_enabled = g4x_fbc_enabled; |
1073 | dev_priv->fbc.enable_fbc = g4x_fbc_enable; | |
1074 | dev_priv->fbc.disable_fbc = g4x_fbc_disable; | |
7ff0ebcc | 1075 | } else { |
ff2a3117 PZ |
1076 | dev_priv->fbc.fbc_enabled = i8xx_fbc_enabled; |
1077 | dev_priv->fbc.enable_fbc = i8xx_fbc_enable; | |
1078 | dev_priv->fbc.disable_fbc = i8xx_fbc_disable; | |
7ff0ebcc RV |
1079 | |
1080 | /* This value was pulled out of someone's hat */ | |
1081 | I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT); | |
1082 | } | |
1083 | ||
7733b49b | 1084 | dev_priv->fbc.enabled = dev_priv->fbc.fbc_enabled(dev_priv); |
7ff0ebcc | 1085 | } |