Commit | Line | Data |
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7ff0ebcc RV |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
94b83957 RV |
24 | /** |
25 | * DOC: Frame Buffer Compression (FBC) | |
26 | * | |
27 | * FBC tries to save memory bandwidth (and so power consumption) by | |
28 | * compressing the amount of memory used by the display. It is total | |
29 | * transparent to user space and completely handled in the kernel. | |
7ff0ebcc RV |
30 | * |
31 | * The benefits of FBC are mostly visible with solid backgrounds and | |
94b83957 RV |
32 | * variation-less patterns. It comes from keeping the memory footprint small |
33 | * and having fewer memory pages opened and accessed for refreshing the display. | |
7ff0ebcc | 34 | * |
94b83957 RV |
35 | * i915 is responsible to reserve stolen memory for FBC and configure its |
36 | * offset on proper registers. The hardware takes care of all | |
37 | * compress/decompress. However there are many known cases where we have to | |
38 | * forcibly disable it to allow proper screen updates. | |
7ff0ebcc RV |
39 | */ |
40 | ||
94b83957 RV |
41 | #include "intel_drv.h" |
42 | #include "i915_drv.h" | |
43 | ||
7733b49b | 44 | static void i8xx_fbc_disable(struct drm_i915_private *dev_priv) |
7ff0ebcc | 45 | { |
7ff0ebcc RV |
46 | u32 fbc_ctl; |
47 | ||
48 | dev_priv->fbc.enabled = false; | |
49 | ||
50 | /* Disable compression */ | |
51 | fbc_ctl = I915_READ(FBC_CONTROL); | |
52 | if ((fbc_ctl & FBC_CTL_EN) == 0) | |
53 | return; | |
54 | ||
55 | fbc_ctl &= ~FBC_CTL_EN; | |
56 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
57 | ||
58 | /* Wait for compressing bit to clear */ | |
59 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { | |
60 | DRM_DEBUG_KMS("FBC idle timed out\n"); | |
61 | return; | |
62 | } | |
63 | ||
64 | DRM_DEBUG_KMS("disabled FBC\n"); | |
65 | } | |
66 | ||
220285f2 | 67 | static void i8xx_fbc_enable(struct intel_crtc *crtc) |
7ff0ebcc | 68 | { |
220285f2 PZ |
69 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
70 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
7ff0ebcc | 71 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
7ff0ebcc RV |
72 | int cfb_pitch; |
73 | int i; | |
74 | u32 fbc_ctl; | |
75 | ||
76 | dev_priv->fbc.enabled = true; | |
77 | ||
60ee5cd2 JN |
78 | /* Note: fbc.threshold == 1 for i8xx */ |
79 | cfb_pitch = dev_priv->fbc.uncompressed_size / FBC_LL_SIZE; | |
7ff0ebcc RV |
80 | if (fb->pitches[0] < cfb_pitch) |
81 | cfb_pitch = fb->pitches[0]; | |
82 | ||
83 | /* FBC_CTL wants 32B or 64B units */ | |
7733b49b | 84 | if (IS_GEN2(dev_priv)) |
7ff0ebcc RV |
85 | cfb_pitch = (cfb_pitch / 32) - 1; |
86 | else | |
87 | cfb_pitch = (cfb_pitch / 64) - 1; | |
88 | ||
89 | /* Clear old tags */ | |
90 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) | |
91 | I915_WRITE(FBC_TAG + (i * 4), 0); | |
92 | ||
7733b49b | 93 | if (IS_GEN4(dev_priv)) { |
7ff0ebcc RV |
94 | u32 fbc_ctl2; |
95 | ||
96 | /* Set it up... */ | |
97 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; | |
220285f2 | 98 | fbc_ctl2 |= FBC_CTL_PLANE(crtc->plane); |
7ff0ebcc | 99 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
220285f2 | 100 | I915_WRITE(FBC_FENCE_OFF, crtc->base.y); |
7ff0ebcc RV |
101 | } |
102 | ||
103 | /* enable it... */ | |
104 | fbc_ctl = I915_READ(FBC_CONTROL); | |
105 | fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT; | |
106 | fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC; | |
7733b49b | 107 | if (IS_I945GM(dev_priv)) |
7ff0ebcc RV |
108 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
109 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; | |
110 | fbc_ctl |= obj->fence_reg; | |
111 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
112 | ||
113 | DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n", | |
220285f2 | 114 | cfb_pitch, crtc->base.y, plane_name(crtc->plane)); |
7ff0ebcc RV |
115 | } |
116 | ||
7733b49b | 117 | static bool i8xx_fbc_enabled(struct drm_i915_private *dev_priv) |
7ff0ebcc | 118 | { |
7ff0ebcc RV |
119 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; |
120 | } | |
121 | ||
220285f2 | 122 | static void g4x_fbc_enable(struct intel_crtc *crtc) |
7ff0ebcc | 123 | { |
220285f2 PZ |
124 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
125 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
7ff0ebcc | 126 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
7ff0ebcc RV |
127 | u32 dpfc_ctl; |
128 | ||
129 | dev_priv->fbc.enabled = true; | |
130 | ||
220285f2 | 131 | dpfc_ctl = DPFC_CTL_PLANE(crtc->plane) | DPFC_SR_EN; |
7ff0ebcc RV |
132 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
133 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
134 | else | |
135 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
136 | dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; | |
137 | ||
220285f2 | 138 | I915_WRITE(DPFC_FENCE_YOFF, crtc->base.y); |
7ff0ebcc RV |
139 | |
140 | /* enable it... */ | |
141 | I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
142 | ||
220285f2 | 143 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane)); |
7ff0ebcc RV |
144 | } |
145 | ||
7733b49b | 146 | static void g4x_fbc_disable(struct drm_i915_private *dev_priv) |
7ff0ebcc | 147 | { |
7ff0ebcc RV |
148 | u32 dpfc_ctl; |
149 | ||
150 | dev_priv->fbc.enabled = false; | |
151 | ||
152 | /* Disable compression */ | |
153 | dpfc_ctl = I915_READ(DPFC_CONTROL); | |
154 | if (dpfc_ctl & DPFC_CTL_EN) { | |
155 | dpfc_ctl &= ~DPFC_CTL_EN; | |
156 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); | |
157 | ||
158 | DRM_DEBUG_KMS("disabled FBC\n"); | |
159 | } | |
160 | } | |
161 | ||
7733b49b | 162 | static bool g4x_fbc_enabled(struct drm_i915_private *dev_priv) |
7ff0ebcc | 163 | { |
7ff0ebcc RV |
164 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; |
165 | } | |
166 | ||
dbef0f15 | 167 | static void intel_fbc_nuke(struct drm_i915_private *dev_priv) |
7ff0ebcc | 168 | { |
dbef0f15 PZ |
169 | I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE); |
170 | POSTING_READ(MSG_FBC_REND_STATE); | |
7ff0ebcc RV |
171 | } |
172 | ||
220285f2 | 173 | static void ilk_fbc_enable(struct intel_crtc *crtc) |
7ff0ebcc | 174 | { |
220285f2 PZ |
175 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
176 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
7ff0ebcc | 177 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
7ff0ebcc | 178 | u32 dpfc_ctl; |
ce65e47b | 179 | int threshold = dev_priv->fbc.threshold; |
7ff0ebcc RV |
180 | |
181 | dev_priv->fbc.enabled = true; | |
182 | ||
220285f2 | 183 | dpfc_ctl = DPFC_CTL_PLANE(crtc->plane); |
7ff0ebcc | 184 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
ce65e47b | 185 | threshold++; |
7ff0ebcc | 186 | |
ce65e47b | 187 | switch (threshold) { |
7ff0ebcc RV |
188 | case 4: |
189 | case 3: | |
190 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; | |
191 | break; | |
192 | case 2: | |
193 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
194 | break; | |
195 | case 1: | |
196 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
197 | break; | |
198 | } | |
199 | dpfc_ctl |= DPFC_CTL_FENCE_EN; | |
7733b49b | 200 | if (IS_GEN5(dev_priv)) |
7ff0ebcc RV |
201 | dpfc_ctl |= obj->fence_reg; |
202 | ||
220285f2 | 203 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->base.y); |
7ff0ebcc RV |
204 | I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID); |
205 | /* enable it... */ | |
206 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
207 | ||
7733b49b | 208 | if (IS_GEN6(dev_priv)) { |
7ff0ebcc RV |
209 | I915_WRITE(SNB_DPFC_CTL_SA, |
210 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); | |
220285f2 | 211 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->base.y); |
7ff0ebcc RV |
212 | } |
213 | ||
dbef0f15 PZ |
214 | intel_fbc_nuke(dev_priv); |
215 | ||
220285f2 | 216 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane)); |
7ff0ebcc RV |
217 | } |
218 | ||
7733b49b | 219 | static void ilk_fbc_disable(struct drm_i915_private *dev_priv) |
7ff0ebcc | 220 | { |
7ff0ebcc RV |
221 | u32 dpfc_ctl; |
222 | ||
223 | dev_priv->fbc.enabled = false; | |
224 | ||
225 | /* Disable compression */ | |
226 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
227 | if (dpfc_ctl & DPFC_CTL_EN) { | |
228 | dpfc_ctl &= ~DPFC_CTL_EN; | |
229 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); | |
230 | ||
231 | DRM_DEBUG_KMS("disabled FBC\n"); | |
232 | } | |
233 | } | |
234 | ||
7733b49b | 235 | static bool ilk_fbc_enabled(struct drm_i915_private *dev_priv) |
7ff0ebcc | 236 | { |
7ff0ebcc RV |
237 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; |
238 | } | |
239 | ||
220285f2 | 240 | static void gen7_fbc_enable(struct intel_crtc *crtc) |
7ff0ebcc | 241 | { |
220285f2 PZ |
242 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
243 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
7ff0ebcc | 244 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
7ff0ebcc | 245 | u32 dpfc_ctl; |
ce65e47b | 246 | int threshold = dev_priv->fbc.threshold; |
7ff0ebcc RV |
247 | |
248 | dev_priv->fbc.enabled = true; | |
249 | ||
d8514d63 | 250 | dpfc_ctl = 0; |
7733b49b | 251 | if (IS_IVYBRIDGE(dev_priv)) |
220285f2 | 252 | dpfc_ctl |= IVB_DPFC_CTL_PLANE(crtc->plane); |
d8514d63 | 253 | |
7ff0ebcc | 254 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
ce65e47b | 255 | threshold++; |
7ff0ebcc | 256 | |
ce65e47b | 257 | switch (threshold) { |
7ff0ebcc RV |
258 | case 4: |
259 | case 3: | |
260 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; | |
261 | break; | |
262 | case 2: | |
263 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
264 | break; | |
265 | case 1: | |
266 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
267 | break; | |
268 | } | |
269 | ||
270 | dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; | |
271 | ||
272 | if (dev_priv->fbc.false_color) | |
273 | dpfc_ctl |= FBC_CTL_FALSE_COLOR; | |
274 | ||
275 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
276 | ||
7733b49b | 277 | if (IS_IVYBRIDGE(dev_priv)) { |
7ff0ebcc RV |
278 | /* WaFbcAsynchFlipDisableFbcQueue:ivb */ |
279 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
280 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
281 | ILK_FBCQ_DIS); | |
282 | } else { | |
283 | /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ | |
220285f2 PZ |
284 | I915_WRITE(CHICKEN_PIPESL_1(crtc->pipe), |
285 | I915_READ(CHICKEN_PIPESL_1(crtc->pipe)) | | |
7ff0ebcc RV |
286 | HSW_FBCQ_DIS); |
287 | } | |
288 | ||
289 | I915_WRITE(SNB_DPFC_CTL_SA, | |
290 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); | |
220285f2 | 291 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->base.y); |
7ff0ebcc | 292 | |
dbef0f15 | 293 | intel_fbc_nuke(dev_priv); |
7ff0ebcc | 294 | |
220285f2 | 295 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(crtc->plane)); |
7ff0ebcc RV |
296 | } |
297 | ||
94b83957 RV |
298 | /** |
299 | * intel_fbc_enabled - Is FBC enabled? | |
7733b49b | 300 | * @dev_priv: i915 device instance |
94b83957 RV |
301 | * |
302 | * This function is used to verify the current state of FBC. | |
303 | * FIXME: This should be tracked in the plane config eventually | |
304 | * instead of queried at runtime for most callers. | |
305 | */ | |
7733b49b | 306 | bool intel_fbc_enabled(struct drm_i915_private *dev_priv) |
7ff0ebcc | 307 | { |
7ff0ebcc RV |
308 | return dev_priv->fbc.enabled; |
309 | } | |
310 | ||
e8cb8d69 PZ |
311 | static void intel_fbc_enable(struct intel_crtc *crtc, |
312 | const struct drm_framebuffer *fb) | |
313 | { | |
314 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
315 | ||
316 | dev_priv->fbc.enable_fbc(crtc); | |
317 | ||
318 | dev_priv->fbc.crtc = crtc; | |
319 | dev_priv->fbc.fb_id = fb->base.id; | |
320 | dev_priv->fbc.y = crtc->base.y; | |
321 | } | |
322 | ||
7ff0ebcc RV |
323 | static void intel_fbc_work_fn(struct work_struct *__work) |
324 | { | |
325 | struct intel_fbc_work *work = | |
326 | container_of(to_delayed_work(__work), | |
327 | struct intel_fbc_work, work); | |
220285f2 PZ |
328 | struct drm_i915_private *dev_priv = work->crtc->base.dev->dev_private; |
329 | struct drm_framebuffer *crtc_fb = work->crtc->base.primary->fb; | |
7ff0ebcc | 330 | |
25ad93fd | 331 | mutex_lock(&dev_priv->fbc.lock); |
7ff0ebcc RV |
332 | if (work == dev_priv->fbc.fbc_work) { |
333 | /* Double check that we haven't switched fb without cancelling | |
334 | * the prior work. | |
335 | */ | |
e8cb8d69 PZ |
336 | if (crtc_fb == work->fb) |
337 | intel_fbc_enable(work->crtc, work->fb); | |
7ff0ebcc RV |
338 | |
339 | dev_priv->fbc.fbc_work = NULL; | |
340 | } | |
25ad93fd | 341 | mutex_unlock(&dev_priv->fbc.lock); |
7ff0ebcc RV |
342 | |
343 | kfree(work); | |
344 | } | |
345 | ||
346 | static void intel_fbc_cancel_work(struct drm_i915_private *dev_priv) | |
347 | { | |
25ad93fd PZ |
348 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
349 | ||
7ff0ebcc RV |
350 | if (dev_priv->fbc.fbc_work == NULL) |
351 | return; | |
352 | ||
353 | DRM_DEBUG_KMS("cancelling pending FBC enable\n"); | |
354 | ||
355 | /* Synchronisation is provided by struct_mutex and checking of | |
356 | * dev_priv->fbc.fbc_work, so we can perform the cancellation | |
357 | * entirely asynchronously. | |
358 | */ | |
359 | if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work)) | |
360 | /* tasklet was killed before being run, clean up */ | |
361 | kfree(dev_priv->fbc.fbc_work); | |
362 | ||
363 | /* Mark the work as no longer wanted so that if it does | |
364 | * wake-up (because the work was already running and waiting | |
365 | * for our mutex), it will discover that is no longer | |
366 | * necessary to run. | |
367 | */ | |
368 | dev_priv->fbc.fbc_work = NULL; | |
369 | } | |
370 | ||
e8cb8d69 | 371 | static void intel_fbc_schedule_enable(struct intel_crtc *crtc) |
7ff0ebcc RV |
372 | { |
373 | struct intel_fbc_work *work; | |
220285f2 | 374 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
7ff0ebcc | 375 | |
25ad93fd PZ |
376 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
377 | ||
7ff0ebcc RV |
378 | intel_fbc_cancel_work(dev_priv); |
379 | ||
380 | work = kzalloc(sizeof(*work), GFP_KERNEL); | |
381 | if (work == NULL) { | |
382 | DRM_ERROR("Failed to allocate FBC work structure\n"); | |
e8cb8d69 | 383 | intel_fbc_enable(crtc, crtc->base.primary->fb); |
7ff0ebcc RV |
384 | return; |
385 | } | |
386 | ||
387 | work->crtc = crtc; | |
220285f2 | 388 | work->fb = crtc->base.primary->fb; |
7ff0ebcc RV |
389 | INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); |
390 | ||
391 | dev_priv->fbc.fbc_work = work; | |
392 | ||
393 | /* Delay the actual enabling to let pageflipping cease and the | |
394 | * display to settle before starting the compression. Note that | |
395 | * this delay also serves a second purpose: it allows for a | |
396 | * vblank to pass after disabling the FBC before we attempt | |
397 | * to modify the control registers. | |
398 | * | |
399 | * A more complicated solution would involve tracking vblanks | |
400 | * following the termination of the page-flipping sequence | |
401 | * and indeed performing the enable as a co-routine and not | |
402 | * waiting synchronously upon the vblank. | |
403 | * | |
404 | * WaFbcWaitForVBlankBeforeEnable:ilk,snb | |
405 | */ | |
406 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); | |
407 | } | |
408 | ||
7733b49b | 409 | static void __intel_fbc_disable(struct drm_i915_private *dev_priv) |
25ad93fd | 410 | { |
25ad93fd PZ |
411 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
412 | ||
413 | intel_fbc_cancel_work(dev_priv); | |
414 | ||
7733b49b | 415 | dev_priv->fbc.disable_fbc(dev_priv); |
25ad93fd PZ |
416 | dev_priv->fbc.crtc = NULL; |
417 | } | |
418 | ||
94b83957 RV |
419 | /** |
420 | * intel_fbc_disable - disable FBC | |
7733b49b | 421 | * @dev_priv: i915 device instance |
94b83957 RV |
422 | * |
423 | * This function disables FBC. | |
424 | */ | |
7733b49b | 425 | void intel_fbc_disable(struct drm_i915_private *dev_priv) |
7ff0ebcc | 426 | { |
ff2a3117 | 427 | if (!dev_priv->fbc.enable_fbc) |
0bf73c36 PZ |
428 | return; |
429 | ||
25ad93fd | 430 | mutex_lock(&dev_priv->fbc.lock); |
7733b49b | 431 | __intel_fbc_disable(dev_priv); |
25ad93fd PZ |
432 | mutex_unlock(&dev_priv->fbc.lock); |
433 | } | |
7ff0ebcc | 434 | |
25ad93fd PZ |
435 | /* |
436 | * intel_fbc_disable_crtc - disable FBC if it's associated with crtc | |
437 | * @crtc: the CRTC | |
438 | * | |
439 | * This function disables FBC if it's associated with the provided CRTC. | |
440 | */ | |
441 | void intel_fbc_disable_crtc(struct intel_crtc *crtc) | |
442 | { | |
7733b49b | 443 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
7ff0ebcc | 444 | |
ff2a3117 | 445 | if (!dev_priv->fbc.enable_fbc) |
0bf73c36 PZ |
446 | return; |
447 | ||
25ad93fd PZ |
448 | mutex_lock(&dev_priv->fbc.lock); |
449 | if (dev_priv->fbc.crtc == crtc) | |
7733b49b | 450 | __intel_fbc_disable(dev_priv); |
25ad93fd | 451 | mutex_unlock(&dev_priv->fbc.lock); |
7ff0ebcc RV |
452 | } |
453 | ||
2e8144a5 PZ |
454 | const char *intel_no_fbc_reason_str(enum no_fbc_reason reason) |
455 | { | |
456 | switch (reason) { | |
457 | case FBC_OK: | |
458 | return "FBC enabled but currently disabled in hardware"; | |
459 | case FBC_UNSUPPORTED: | |
460 | return "unsupported by this chipset"; | |
461 | case FBC_NO_OUTPUT: | |
462 | return "no output"; | |
463 | case FBC_STOLEN_TOO_SMALL: | |
464 | return "not enough stolen memory"; | |
465 | case FBC_UNSUPPORTED_MODE: | |
466 | return "mode incompatible with compression"; | |
467 | case FBC_MODE_TOO_LARGE: | |
468 | return "mode too large for compression"; | |
469 | case FBC_BAD_PLANE: | |
470 | return "FBC unsupported on plane"; | |
471 | case FBC_NOT_TILED: | |
472 | return "framebuffer not tiled or fenced"; | |
473 | case FBC_MULTIPLE_PIPES: | |
474 | return "more than one pipe active"; | |
475 | case FBC_MODULE_PARAM: | |
476 | return "disabled per module param"; | |
477 | case FBC_CHIP_DEFAULT: | |
478 | return "disabled per chip default"; | |
479 | case FBC_ROTATION: | |
480 | return "rotation unsupported"; | |
89351085 PZ |
481 | case FBC_IN_DBG_MASTER: |
482 | return "Kernel debugger is active"; | |
adf70c65 PZ |
483 | case FBC_BAD_STRIDE: |
484 | return "framebuffer stride not supported"; | |
7b24c9a6 PZ |
485 | case FBC_PIXEL_RATE: |
486 | return "pixel rate is too big"; | |
2e8144a5 PZ |
487 | default: |
488 | MISSING_CASE(reason); | |
489 | return "unknown reason"; | |
490 | } | |
491 | } | |
492 | ||
493 | static void set_no_fbc_reason(struct drm_i915_private *dev_priv, | |
7ff0ebcc RV |
494 | enum no_fbc_reason reason) |
495 | { | |
496 | if (dev_priv->fbc.no_fbc_reason == reason) | |
2e8144a5 | 497 | return; |
7ff0ebcc RV |
498 | |
499 | dev_priv->fbc.no_fbc_reason = reason; | |
2e8144a5 | 500 | DRM_DEBUG_KMS("Disabling FBC: %s\n", intel_no_fbc_reason_str(reason)); |
7ff0ebcc RV |
501 | } |
502 | ||
95106753 PZ |
503 | static struct drm_crtc *intel_fbc_find_crtc(struct drm_i915_private *dev_priv) |
504 | { | |
95106753 | 505 | struct drm_crtc *crtc = NULL, *tmp_crtc; |
68b92147 | 506 | enum pipe pipe; |
232fd934 | 507 | bool pipe_a_only = false; |
68b92147 PZ |
508 | |
509 | if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) | |
510 | pipe_a_only = true; | |
511 | ||
512 | for_each_pipe(dev_priv, pipe) { | |
513 | tmp_crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
95106753 | 514 | |
95106753 | 515 | if (intel_crtc_active(tmp_crtc) && |
232fd934 | 516 | to_intel_plane_state(tmp_crtc->primary->state)->visible) |
95106753 | 517 | crtc = tmp_crtc; |
68b92147 PZ |
518 | |
519 | if (pipe_a_only) | |
520 | break; | |
95106753 PZ |
521 | } |
522 | ||
8df5dd57 | 523 | if (!crtc || crtc->primary->fb == NULL) |
95106753 | 524 | return NULL; |
95106753 PZ |
525 | |
526 | return crtc; | |
527 | } | |
528 | ||
232fd934 PZ |
529 | static bool multiple_pipes_ok(struct drm_i915_private *dev_priv) |
530 | { | |
531 | enum pipe pipe; | |
532 | int n_pipes = 0; | |
533 | struct drm_crtc *crtc; | |
534 | ||
535 | if (INTEL_INFO(dev_priv)->gen > 4) | |
536 | return true; | |
537 | ||
538 | for_each_pipe(dev_priv, pipe) { | |
539 | crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
540 | ||
541 | if (intel_crtc_active(crtc) && | |
542 | to_intel_plane_state(crtc->primary->state)->visible) | |
543 | n_pipes++; | |
544 | } | |
545 | ||
546 | return (n_pipes < 2); | |
547 | } | |
548 | ||
7733b49b | 549 | static int find_compression_threshold(struct drm_i915_private *dev_priv, |
fc786728 PZ |
550 | struct drm_mm_node *node, |
551 | int size, | |
552 | int fb_cpp) | |
553 | { | |
fc786728 PZ |
554 | int compression_threshold = 1; |
555 | int ret; | |
a9da512b PZ |
556 | u64 end; |
557 | ||
558 | /* The FBC hardware for BDW/SKL doesn't have access to the stolen | |
559 | * reserved range size, so it always assumes the maximum (8mb) is used. | |
560 | * If we enable FBC using a CFB on that memory range we'll get FIFO | |
561 | * underruns, even if that range is not reserved by the BIOS. */ | |
562 | if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv)) | |
563 | end = dev_priv->gtt.stolen_size - 8 * 1024 * 1024; | |
564 | else | |
565 | end = dev_priv->gtt.stolen_usable_size; | |
fc786728 PZ |
566 | |
567 | /* HACK: This code depends on what we will do in *_enable_fbc. If that | |
568 | * code changes, this code needs to change as well. | |
569 | * | |
570 | * The enable_fbc code will attempt to use one of our 2 compression | |
571 | * thresholds, therefore, in that case, we only have 1 resort. | |
572 | */ | |
573 | ||
574 | /* Try to over-allocate to reduce reallocations and fragmentation. */ | |
a9da512b PZ |
575 | ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1, |
576 | 4096, 0, end); | |
fc786728 PZ |
577 | if (ret == 0) |
578 | return compression_threshold; | |
579 | ||
580 | again: | |
581 | /* HW's ability to limit the CFB is 1:4 */ | |
582 | if (compression_threshold > 4 || | |
583 | (fb_cpp == 2 && compression_threshold == 2)) | |
584 | return 0; | |
585 | ||
a9da512b PZ |
586 | ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1, |
587 | 4096, 0, end); | |
7733b49b | 588 | if (ret && INTEL_INFO(dev_priv)->gen <= 4) { |
fc786728 PZ |
589 | return 0; |
590 | } else if (ret) { | |
591 | compression_threshold <<= 1; | |
592 | goto again; | |
593 | } else { | |
594 | return compression_threshold; | |
595 | } | |
596 | } | |
597 | ||
7733b49b PZ |
598 | static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv, int size, |
599 | int fb_cpp) | |
fc786728 | 600 | { |
fc786728 PZ |
601 | struct drm_mm_node *uninitialized_var(compressed_llb); |
602 | int ret; | |
603 | ||
7733b49b | 604 | ret = find_compression_threshold(dev_priv, &dev_priv->fbc.compressed_fb, |
fc786728 PZ |
605 | size, fb_cpp); |
606 | if (!ret) | |
607 | goto err_llb; | |
608 | else if (ret > 1) { | |
609 | DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n"); | |
610 | ||
611 | } | |
612 | ||
613 | dev_priv->fbc.threshold = ret; | |
614 | ||
615 | if (INTEL_INFO(dev_priv)->gen >= 5) | |
616 | I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start); | |
7733b49b | 617 | else if (IS_GM45(dev_priv)) { |
fc786728 PZ |
618 | I915_WRITE(DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start); |
619 | } else { | |
620 | compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL); | |
621 | if (!compressed_llb) | |
622 | goto err_fb; | |
623 | ||
624 | ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb, | |
625 | 4096, 4096); | |
626 | if (ret) | |
627 | goto err_fb; | |
628 | ||
629 | dev_priv->fbc.compressed_llb = compressed_llb; | |
630 | ||
631 | I915_WRITE(FBC_CFB_BASE, | |
632 | dev_priv->mm.stolen_base + dev_priv->fbc.compressed_fb.start); | |
633 | I915_WRITE(FBC_LL_BASE, | |
634 | dev_priv->mm.stolen_base + compressed_llb->start); | |
635 | } | |
636 | ||
637 | dev_priv->fbc.uncompressed_size = size; | |
638 | ||
b8bf5d7f PZ |
639 | DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n", |
640 | dev_priv->fbc.compressed_fb.size, | |
641 | dev_priv->fbc.threshold); | |
fc786728 PZ |
642 | |
643 | return 0; | |
644 | ||
645 | err_fb: | |
646 | kfree(compressed_llb); | |
647 | i915_gem_stolen_remove_node(dev_priv, &dev_priv->fbc.compressed_fb); | |
648 | err_llb: | |
649 | pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size); | |
650 | return -ENOSPC; | |
651 | } | |
652 | ||
7733b49b | 653 | static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) |
fc786728 | 654 | { |
fc786728 PZ |
655 | if (dev_priv->fbc.uncompressed_size == 0) |
656 | return; | |
657 | ||
658 | i915_gem_stolen_remove_node(dev_priv, &dev_priv->fbc.compressed_fb); | |
659 | ||
660 | if (dev_priv->fbc.compressed_llb) { | |
661 | i915_gem_stolen_remove_node(dev_priv, | |
662 | dev_priv->fbc.compressed_llb); | |
663 | kfree(dev_priv->fbc.compressed_llb); | |
664 | } | |
665 | ||
666 | dev_priv->fbc.uncompressed_size = 0; | |
667 | } | |
668 | ||
7733b49b | 669 | void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) |
25ad93fd | 670 | { |
ff2a3117 | 671 | if (!dev_priv->fbc.enable_fbc) |
0bf73c36 PZ |
672 | return; |
673 | ||
25ad93fd | 674 | mutex_lock(&dev_priv->fbc.lock); |
7733b49b | 675 | __intel_fbc_cleanup_cfb(dev_priv); |
25ad93fd PZ |
676 | mutex_unlock(&dev_priv->fbc.lock); |
677 | } | |
678 | ||
7733b49b PZ |
679 | static int intel_fbc_setup_cfb(struct drm_i915_private *dev_priv, int size, |
680 | int fb_cpp) | |
fc786728 | 681 | { |
fc786728 PZ |
682 | if (size <= dev_priv->fbc.uncompressed_size) |
683 | return 0; | |
684 | ||
685 | /* Release any current block */ | |
7733b49b | 686 | __intel_fbc_cleanup_cfb(dev_priv); |
fc786728 | 687 | |
7733b49b | 688 | return intel_fbc_alloc_cfb(dev_priv, size, fb_cpp); |
fc786728 PZ |
689 | } |
690 | ||
adf70c65 PZ |
691 | static bool stride_is_valid(struct drm_i915_private *dev_priv, |
692 | unsigned int stride) | |
693 | { | |
694 | /* These should have been caught earlier. */ | |
695 | WARN_ON(stride < 512); | |
696 | WARN_ON((stride & (64 - 1)) != 0); | |
697 | ||
698 | /* Below are the additional FBC restrictions. */ | |
699 | ||
700 | if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv)) | |
701 | return stride == 4096 || stride == 8192; | |
702 | ||
703 | if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048) | |
704 | return false; | |
705 | ||
706 | if (stride > 16384) | |
707 | return false; | |
708 | ||
709 | return true; | |
710 | } | |
711 | ||
7ff0ebcc | 712 | /** |
25ad93fd | 713 | * __intel_fbc_update - enable/disable FBC as needed, unlocked |
7733b49b | 714 | * @dev_priv: i915 device instance |
7ff0ebcc RV |
715 | * |
716 | * Set up the framebuffer compression hardware at mode set time. We | |
717 | * enable it if possible: | |
718 | * - plane A only (on pre-965) | |
719 | * - no pixel mulitply/line duplication | |
720 | * - no alpha buffer discard | |
721 | * - no dual wide | |
722 | * - framebuffer <= max_hdisplay in width, max_vdisplay in height | |
723 | * | |
724 | * We can't assume that any compression will take place (worst case), | |
725 | * so the compressed buffer has to be the same size as the uncompressed | |
726 | * one. It also must reside (along with the line length buffer) in | |
727 | * stolen memory. | |
728 | * | |
729 | * We need to enable/disable FBC on a global basis. | |
730 | */ | |
7733b49b | 731 | static void __intel_fbc_update(struct drm_i915_private *dev_priv) |
7ff0ebcc | 732 | { |
95106753 | 733 | struct drm_crtc *crtc = NULL; |
7ff0ebcc RV |
734 | struct intel_crtc *intel_crtc; |
735 | struct drm_framebuffer *fb; | |
736 | struct drm_i915_gem_object *obj; | |
737 | const struct drm_display_mode *adjusted_mode; | |
738 | unsigned int max_width, max_height; | |
739 | ||
25ad93fd PZ |
740 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
741 | ||
bd49234b | 742 | /* disable framebuffer compression in vGPU */ |
7733b49b | 743 | if (intel_vgpu_active(dev_priv->dev)) |
bd49234b YZ |
744 | i915.enable_fbc = 0; |
745 | ||
7cc65746 | 746 | if (i915.enable_fbc < 0) { |
2e8144a5 | 747 | set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT); |
7cc65746 PZ |
748 | goto out_disable; |
749 | } | |
750 | ||
ab585dea | 751 | if (!i915.enable_fbc) { |
2e8144a5 | 752 | set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM); |
7cc65746 | 753 | goto out_disable; |
7ff0ebcc RV |
754 | } |
755 | ||
756 | /* | |
757 | * If FBC is already on, we just have to verify that we can | |
758 | * keep it that way... | |
759 | * Need to disable if: | |
760 | * - more than one pipe is active | |
761 | * - changing FBC params (stride, fence, mode) | |
762 | * - new fb is too large to fit in compressed buffer | |
763 | * - going to an unsupported config (interlace, pixel multiply, etc.) | |
764 | */ | |
95106753 | 765 | crtc = intel_fbc_find_crtc(dev_priv); |
8df5dd57 PZ |
766 | if (!crtc) { |
767 | set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT); | |
7ff0ebcc | 768 | goto out_disable; |
8df5dd57 | 769 | } |
7ff0ebcc | 770 | |
232fd934 PZ |
771 | if (!multiple_pipes_ok(dev_priv)) { |
772 | set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES); | |
773 | goto out_disable; | |
774 | } | |
775 | ||
7ff0ebcc RV |
776 | intel_crtc = to_intel_crtc(crtc); |
777 | fb = crtc->primary->fb; | |
778 | obj = intel_fb_obj(fb); | |
6e3c9717 | 779 | adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
7ff0ebcc | 780 | |
7ff0ebcc RV |
781 | if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) || |
782 | (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) { | |
2e8144a5 | 783 | set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE); |
7ff0ebcc RV |
784 | goto out_disable; |
785 | } | |
786 | ||
7733b49b | 787 | if (INTEL_INFO(dev_priv)->gen >= 8 || IS_HASWELL(dev_priv)) { |
7ff0ebcc RV |
788 | max_width = 4096; |
789 | max_height = 4096; | |
7733b49b | 790 | } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { |
7ff0ebcc RV |
791 | max_width = 4096; |
792 | max_height = 2048; | |
793 | } else { | |
794 | max_width = 2048; | |
795 | max_height = 1536; | |
796 | } | |
6e3c9717 ACO |
797 | if (intel_crtc->config->pipe_src_w > max_width || |
798 | intel_crtc->config->pipe_src_h > max_height) { | |
2e8144a5 | 799 | set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE); |
7ff0ebcc RV |
800 | goto out_disable; |
801 | } | |
7733b49b | 802 | if ((INTEL_INFO(dev_priv)->gen < 4 || HAS_DDI(dev_priv)) && |
7ff0ebcc | 803 | intel_crtc->plane != PLANE_A) { |
2e8144a5 | 804 | set_no_fbc_reason(dev_priv, FBC_BAD_PLANE); |
7ff0ebcc RV |
805 | goto out_disable; |
806 | } | |
807 | ||
808 | /* The use of a CPU fence is mandatory in order to detect writes | |
809 | * by the CPU to the scanout and trigger updates to the FBC. | |
810 | */ | |
811 | if (obj->tiling_mode != I915_TILING_X || | |
812 | obj->fence_reg == I915_FENCE_REG_NONE) { | |
2e8144a5 | 813 | set_no_fbc_reason(dev_priv, FBC_NOT_TILED); |
7ff0ebcc RV |
814 | goto out_disable; |
815 | } | |
7733b49b | 816 | if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) && |
8e7d688b | 817 | crtc->primary->state->rotation != BIT(DRM_ROTATE_0)) { |
2e8144a5 | 818 | set_no_fbc_reason(dev_priv, FBC_ROTATION); |
7ff0ebcc RV |
819 | goto out_disable; |
820 | } | |
821 | ||
adf70c65 PZ |
822 | if (!stride_is_valid(dev_priv, fb->pitches[0])) { |
823 | set_no_fbc_reason(dev_priv, FBC_BAD_STRIDE); | |
824 | goto out_disable; | |
825 | } | |
826 | ||
7ff0ebcc | 827 | /* If the kernel debugger is active, always disable compression */ |
89351085 PZ |
828 | if (in_dbg_master()) { |
829 | set_no_fbc_reason(dev_priv, FBC_IN_DBG_MASTER); | |
7ff0ebcc | 830 | goto out_disable; |
89351085 | 831 | } |
7ff0ebcc | 832 | |
7b24c9a6 PZ |
833 | /* WaFbcExceedCdClockThreshold:hsw,bdw */ |
834 | if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) && | |
835 | ilk_pipe_pixel_rate(intel_crtc->config) >= | |
836 | dev_priv->cdclk_freq * 95 / 100) { | |
837 | set_no_fbc_reason(dev_priv, FBC_PIXEL_RATE); | |
838 | goto out_disable; | |
839 | } | |
840 | ||
7733b49b | 841 | if (intel_fbc_setup_cfb(dev_priv, obj->base.size, |
fc786728 | 842 | drm_format_plane_cpp(fb->pixel_format, 0))) { |
2e8144a5 | 843 | set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL); |
7ff0ebcc RV |
844 | goto out_disable; |
845 | } | |
846 | ||
847 | /* If the scanout has not changed, don't modify the FBC settings. | |
848 | * Note that we make the fundamental assumption that the fb->obj | |
849 | * cannot be unpinned (and have its GTT offset and fence revoked) | |
850 | * without first being decoupled from the scanout and FBC disabled. | |
851 | */ | |
e35fef21 | 852 | if (dev_priv->fbc.crtc == intel_crtc && |
7ff0ebcc RV |
853 | dev_priv->fbc.fb_id == fb->base.id && |
854 | dev_priv->fbc.y == crtc->y) | |
855 | return; | |
856 | ||
7733b49b | 857 | if (intel_fbc_enabled(dev_priv)) { |
7ff0ebcc RV |
858 | /* We update FBC along two paths, after changing fb/crtc |
859 | * configuration (modeswitching) and after page-flipping | |
860 | * finishes. For the latter, we know that not only did | |
861 | * we disable the FBC at the start of the page-flip | |
862 | * sequence, but also more than one vblank has passed. | |
863 | * | |
864 | * For the former case of modeswitching, it is possible | |
865 | * to switch between two FBC valid configurations | |
866 | * instantaneously so we do need to disable the FBC | |
867 | * before we can modify its control registers. We also | |
868 | * have to wait for the next vblank for that to take | |
869 | * effect. However, since we delay enabling FBC we can | |
870 | * assume that a vblank has passed since disabling and | |
871 | * that we can safely alter the registers in the deferred | |
872 | * callback. | |
873 | * | |
874 | * In the scenario that we go from a valid to invalid | |
875 | * and then back to valid FBC configuration we have | |
876 | * no strict enforcement that a vblank occurred since | |
877 | * disabling the FBC. However, along all current pipe | |
878 | * disabling paths we do need to wait for a vblank at | |
879 | * some point. And we wait before enabling FBC anyway. | |
880 | */ | |
881 | DRM_DEBUG_KMS("disabling active FBC for update\n"); | |
7733b49b | 882 | __intel_fbc_disable(dev_priv); |
7ff0ebcc RV |
883 | } |
884 | ||
e8cb8d69 | 885 | intel_fbc_schedule_enable(intel_crtc); |
7ff0ebcc RV |
886 | dev_priv->fbc.no_fbc_reason = FBC_OK; |
887 | return; | |
888 | ||
889 | out_disable: | |
890 | /* Multiple disables should be harmless */ | |
7733b49b | 891 | if (intel_fbc_enabled(dev_priv)) { |
7ff0ebcc | 892 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); |
7733b49b | 893 | __intel_fbc_disable(dev_priv); |
7ff0ebcc | 894 | } |
7733b49b | 895 | __intel_fbc_cleanup_cfb(dev_priv); |
25ad93fd PZ |
896 | } |
897 | ||
898 | /* | |
899 | * intel_fbc_update - enable/disable FBC as needed | |
7733b49b | 900 | * @dev_priv: i915 device instance |
25ad93fd PZ |
901 | * |
902 | * This function reevaluates the overall state and enables or disables FBC. | |
903 | */ | |
7733b49b | 904 | void intel_fbc_update(struct drm_i915_private *dev_priv) |
25ad93fd | 905 | { |
ff2a3117 | 906 | if (!dev_priv->fbc.enable_fbc) |
0bf73c36 PZ |
907 | return; |
908 | ||
25ad93fd | 909 | mutex_lock(&dev_priv->fbc.lock); |
7733b49b | 910 | __intel_fbc_update(dev_priv); |
25ad93fd | 911 | mutex_unlock(&dev_priv->fbc.lock); |
7ff0ebcc RV |
912 | } |
913 | ||
dbef0f15 PZ |
914 | void intel_fbc_invalidate(struct drm_i915_private *dev_priv, |
915 | unsigned int frontbuffer_bits, | |
916 | enum fb_op_origin origin) | |
917 | { | |
dbef0f15 PZ |
918 | unsigned int fbc_bits; |
919 | ||
ff2a3117 | 920 | if (!dev_priv->fbc.enable_fbc) |
0bf73c36 PZ |
921 | return; |
922 | ||
dbef0f15 PZ |
923 | if (origin == ORIGIN_GTT) |
924 | return; | |
925 | ||
25ad93fd PZ |
926 | mutex_lock(&dev_priv->fbc.lock); |
927 | ||
dbef0f15 PZ |
928 | if (dev_priv->fbc.enabled) |
929 | fbc_bits = INTEL_FRONTBUFFER_PRIMARY(dev_priv->fbc.crtc->pipe); | |
930 | else if (dev_priv->fbc.fbc_work) | |
931 | fbc_bits = INTEL_FRONTBUFFER_PRIMARY( | |
220285f2 | 932 | dev_priv->fbc.fbc_work->crtc->pipe); |
dbef0f15 PZ |
933 | else |
934 | fbc_bits = dev_priv->fbc.possible_framebuffer_bits; | |
935 | ||
936 | dev_priv->fbc.busy_bits |= (fbc_bits & frontbuffer_bits); | |
937 | ||
938 | if (dev_priv->fbc.busy_bits) | |
7733b49b | 939 | __intel_fbc_disable(dev_priv); |
25ad93fd PZ |
940 | |
941 | mutex_unlock(&dev_priv->fbc.lock); | |
dbef0f15 PZ |
942 | } |
943 | ||
944 | void intel_fbc_flush(struct drm_i915_private *dev_priv, | |
6f4551fe | 945 | unsigned int frontbuffer_bits, enum fb_op_origin origin) |
dbef0f15 | 946 | { |
ff2a3117 | 947 | if (!dev_priv->fbc.enable_fbc) |
0bf73c36 PZ |
948 | return; |
949 | ||
6f4551fe PZ |
950 | if (origin == ORIGIN_GTT) |
951 | return; | |
25ad93fd | 952 | |
6f4551fe | 953 | mutex_lock(&dev_priv->fbc.lock); |
dbef0f15 PZ |
954 | |
955 | dev_priv->fbc.busy_bits &= ~frontbuffer_bits; | |
956 | ||
6f4551fe PZ |
957 | if (!dev_priv->fbc.busy_bits) { |
958 | __intel_fbc_disable(dev_priv); | |
7733b49b | 959 | __intel_fbc_update(dev_priv); |
6f4551fe | 960 | } |
25ad93fd | 961 | |
25ad93fd | 962 | mutex_unlock(&dev_priv->fbc.lock); |
dbef0f15 PZ |
963 | } |
964 | ||
94b83957 RV |
965 | /** |
966 | * intel_fbc_init - Initialize FBC | |
967 | * @dev_priv: the i915 device | |
968 | * | |
969 | * This function might be called during PM init process. | |
970 | */ | |
7ff0ebcc RV |
971 | void intel_fbc_init(struct drm_i915_private *dev_priv) |
972 | { | |
dbef0f15 PZ |
973 | enum pipe pipe; |
974 | ||
25ad93fd PZ |
975 | mutex_init(&dev_priv->fbc.lock); |
976 | ||
7ff0ebcc RV |
977 | if (!HAS_FBC(dev_priv)) { |
978 | dev_priv->fbc.enabled = false; | |
104618b3 | 979 | dev_priv->fbc.no_fbc_reason = FBC_UNSUPPORTED; |
7ff0ebcc RV |
980 | return; |
981 | } | |
982 | ||
dbef0f15 PZ |
983 | for_each_pipe(dev_priv, pipe) { |
984 | dev_priv->fbc.possible_framebuffer_bits |= | |
985 | INTEL_FRONTBUFFER_PRIMARY(pipe); | |
986 | ||
987 | if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) | |
988 | break; | |
989 | } | |
990 | ||
7ff0ebcc | 991 | if (INTEL_INFO(dev_priv)->gen >= 7) { |
ff2a3117 PZ |
992 | dev_priv->fbc.fbc_enabled = ilk_fbc_enabled; |
993 | dev_priv->fbc.enable_fbc = gen7_fbc_enable; | |
994 | dev_priv->fbc.disable_fbc = ilk_fbc_disable; | |
7ff0ebcc | 995 | } else if (INTEL_INFO(dev_priv)->gen >= 5) { |
ff2a3117 PZ |
996 | dev_priv->fbc.fbc_enabled = ilk_fbc_enabled; |
997 | dev_priv->fbc.enable_fbc = ilk_fbc_enable; | |
998 | dev_priv->fbc.disable_fbc = ilk_fbc_disable; | |
7ff0ebcc | 999 | } else if (IS_GM45(dev_priv)) { |
ff2a3117 PZ |
1000 | dev_priv->fbc.fbc_enabled = g4x_fbc_enabled; |
1001 | dev_priv->fbc.enable_fbc = g4x_fbc_enable; | |
1002 | dev_priv->fbc.disable_fbc = g4x_fbc_disable; | |
7ff0ebcc | 1003 | } else { |
ff2a3117 PZ |
1004 | dev_priv->fbc.fbc_enabled = i8xx_fbc_enabled; |
1005 | dev_priv->fbc.enable_fbc = i8xx_fbc_enable; | |
1006 | dev_priv->fbc.disable_fbc = i8xx_fbc_disable; | |
7ff0ebcc RV |
1007 | |
1008 | /* This value was pulled out of someone's hat */ | |
1009 | I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT); | |
1010 | } | |
1011 | ||
7733b49b | 1012 | dev_priv->fbc.enabled = dev_priv->fbc.fbc_enabled(dev_priv); |
7ff0ebcc | 1013 | } |