Commit | Line | Data |
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7ff0ebcc RV |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
94b83957 RV |
24 | /** |
25 | * DOC: Frame Buffer Compression (FBC) | |
26 | * | |
27 | * FBC tries to save memory bandwidth (and so power consumption) by | |
28 | * compressing the amount of memory used by the display. It is total | |
29 | * transparent to user space and completely handled in the kernel. | |
7ff0ebcc RV |
30 | * |
31 | * The benefits of FBC are mostly visible with solid backgrounds and | |
94b83957 RV |
32 | * variation-less patterns. It comes from keeping the memory footprint small |
33 | * and having fewer memory pages opened and accessed for refreshing the display. | |
7ff0ebcc | 34 | * |
94b83957 RV |
35 | * i915 is responsible to reserve stolen memory for FBC and configure its |
36 | * offset on proper registers. The hardware takes care of all | |
37 | * compress/decompress. However there are many known cases where we have to | |
38 | * forcibly disable it to allow proper screen updates. | |
7ff0ebcc RV |
39 | */ |
40 | ||
94b83957 RV |
41 | #include "intel_drv.h" |
42 | #include "i915_drv.h" | |
43 | ||
9f218336 PZ |
44 | static inline bool fbc_supported(struct drm_i915_private *dev_priv) |
45 | { | |
0e631adc | 46 | return dev_priv->fbc.activate != NULL; |
9f218336 PZ |
47 | } |
48 | ||
57105022 PZ |
49 | static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv) |
50 | { | |
51 | return IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8; | |
52 | } | |
53 | ||
2db3366b PZ |
54 | /* |
55 | * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the | |
56 | * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's | |
57 | * origin so the x and y offsets can actually fit the registers. As a | |
58 | * consequence, the fence doesn't really start exactly at the display plane | |
59 | * address we program because it starts at the real start of the buffer, so we | |
60 | * have to take this into consideration here. | |
61 | */ | |
62 | static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc) | |
63 | { | |
64 | return crtc->base.y - crtc->adjusted_y; | |
65 | } | |
66 | ||
0e631adc | 67 | static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv) |
7ff0ebcc | 68 | { |
7ff0ebcc RV |
69 | u32 fbc_ctl; |
70 | ||
0e631adc | 71 | dev_priv->fbc.active = false; |
7ff0ebcc RV |
72 | |
73 | /* Disable compression */ | |
74 | fbc_ctl = I915_READ(FBC_CONTROL); | |
75 | if ((fbc_ctl & FBC_CTL_EN) == 0) | |
76 | return; | |
77 | ||
78 | fbc_ctl &= ~FBC_CTL_EN; | |
79 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
80 | ||
81 | /* Wait for compressing bit to clear */ | |
82 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { | |
83 | DRM_DEBUG_KMS("FBC idle timed out\n"); | |
84 | return; | |
85 | } | |
86 | ||
0e631adc | 87 | DRM_DEBUG_KMS("deactivated FBC\n"); |
7ff0ebcc RV |
88 | } |
89 | ||
0e631adc | 90 | static void i8xx_fbc_activate(struct intel_crtc *crtc) |
7ff0ebcc | 91 | { |
220285f2 PZ |
92 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
93 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
7ff0ebcc | 94 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
7ff0ebcc RV |
95 | int cfb_pitch; |
96 | int i; | |
97 | u32 fbc_ctl; | |
98 | ||
0e631adc | 99 | dev_priv->fbc.active = true; |
7ff0ebcc | 100 | |
60ee5cd2 JN |
101 | /* Note: fbc.threshold == 1 for i8xx */ |
102 | cfb_pitch = dev_priv->fbc.uncompressed_size / FBC_LL_SIZE; | |
7ff0ebcc RV |
103 | if (fb->pitches[0] < cfb_pitch) |
104 | cfb_pitch = fb->pitches[0]; | |
105 | ||
106 | /* FBC_CTL wants 32B or 64B units */ | |
7733b49b | 107 | if (IS_GEN2(dev_priv)) |
7ff0ebcc RV |
108 | cfb_pitch = (cfb_pitch / 32) - 1; |
109 | else | |
110 | cfb_pitch = (cfb_pitch / 64) - 1; | |
111 | ||
112 | /* Clear old tags */ | |
113 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) | |
4d110c71 | 114 | I915_WRITE(FBC_TAG(i), 0); |
7ff0ebcc | 115 | |
7733b49b | 116 | if (IS_GEN4(dev_priv)) { |
7ff0ebcc RV |
117 | u32 fbc_ctl2; |
118 | ||
119 | /* Set it up... */ | |
120 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; | |
220285f2 | 121 | fbc_ctl2 |= FBC_CTL_PLANE(crtc->plane); |
7ff0ebcc | 122 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
2db3366b | 123 | I915_WRITE(FBC_FENCE_OFF, get_crtc_fence_y_offset(crtc)); |
7ff0ebcc RV |
124 | } |
125 | ||
126 | /* enable it... */ | |
127 | fbc_ctl = I915_READ(FBC_CONTROL); | |
128 | fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT; | |
129 | fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC; | |
7733b49b | 130 | if (IS_I945GM(dev_priv)) |
7ff0ebcc RV |
131 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
132 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; | |
133 | fbc_ctl |= obj->fence_reg; | |
134 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
135 | ||
0e631adc | 136 | DRM_DEBUG_KMS("activated FBC, pitch %d, yoff %d, plane %c\n", |
220285f2 | 137 | cfb_pitch, crtc->base.y, plane_name(crtc->plane)); |
7ff0ebcc RV |
138 | } |
139 | ||
0e631adc | 140 | static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv) |
7ff0ebcc | 141 | { |
7ff0ebcc RV |
142 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; |
143 | } | |
144 | ||
0e631adc | 145 | static void g4x_fbc_activate(struct intel_crtc *crtc) |
7ff0ebcc | 146 | { |
220285f2 PZ |
147 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
148 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
7ff0ebcc | 149 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
7ff0ebcc RV |
150 | u32 dpfc_ctl; |
151 | ||
0e631adc | 152 | dev_priv->fbc.active = true; |
7ff0ebcc | 153 | |
220285f2 | 154 | dpfc_ctl = DPFC_CTL_PLANE(crtc->plane) | DPFC_SR_EN; |
7ff0ebcc RV |
155 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
156 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
157 | else | |
158 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
159 | dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; | |
160 | ||
2db3366b | 161 | I915_WRITE(DPFC_FENCE_YOFF, get_crtc_fence_y_offset(crtc)); |
7ff0ebcc RV |
162 | |
163 | /* enable it... */ | |
164 | I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
165 | ||
0e631adc | 166 | DRM_DEBUG_KMS("activated fbc on plane %c\n", plane_name(crtc->plane)); |
7ff0ebcc RV |
167 | } |
168 | ||
0e631adc | 169 | static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv) |
7ff0ebcc | 170 | { |
7ff0ebcc RV |
171 | u32 dpfc_ctl; |
172 | ||
0e631adc | 173 | dev_priv->fbc.active = false; |
7ff0ebcc RV |
174 | |
175 | /* Disable compression */ | |
176 | dpfc_ctl = I915_READ(DPFC_CONTROL); | |
177 | if (dpfc_ctl & DPFC_CTL_EN) { | |
178 | dpfc_ctl &= ~DPFC_CTL_EN; | |
179 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); | |
180 | ||
0e631adc | 181 | DRM_DEBUG_KMS("deactivated FBC\n"); |
7ff0ebcc RV |
182 | } |
183 | } | |
184 | ||
0e631adc | 185 | static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv) |
7ff0ebcc | 186 | { |
7ff0ebcc RV |
187 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; |
188 | } | |
189 | ||
d5ce4164 PZ |
190 | /* This function forces a CFB recompression through the nuke operation. */ |
191 | static void intel_fbc_recompress(struct drm_i915_private *dev_priv) | |
7ff0ebcc | 192 | { |
dbef0f15 PZ |
193 | I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE); |
194 | POSTING_READ(MSG_FBC_REND_STATE); | |
7ff0ebcc RV |
195 | } |
196 | ||
0e631adc | 197 | static void ilk_fbc_activate(struct intel_crtc *crtc) |
7ff0ebcc | 198 | { |
220285f2 PZ |
199 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
200 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
7ff0ebcc | 201 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
7ff0ebcc | 202 | u32 dpfc_ctl; |
ce65e47b | 203 | int threshold = dev_priv->fbc.threshold; |
2db3366b | 204 | unsigned int y_offset; |
7ff0ebcc | 205 | |
0e631adc | 206 | dev_priv->fbc.active = true; |
7ff0ebcc | 207 | |
220285f2 | 208 | dpfc_ctl = DPFC_CTL_PLANE(crtc->plane); |
7ff0ebcc | 209 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
ce65e47b | 210 | threshold++; |
7ff0ebcc | 211 | |
ce65e47b | 212 | switch (threshold) { |
7ff0ebcc RV |
213 | case 4: |
214 | case 3: | |
215 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; | |
216 | break; | |
217 | case 2: | |
218 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
219 | break; | |
220 | case 1: | |
221 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
222 | break; | |
223 | } | |
224 | dpfc_ctl |= DPFC_CTL_FENCE_EN; | |
7733b49b | 225 | if (IS_GEN5(dev_priv)) |
7ff0ebcc RV |
226 | dpfc_ctl |= obj->fence_reg; |
227 | ||
2db3366b PZ |
228 | y_offset = get_crtc_fence_y_offset(crtc); |
229 | I915_WRITE(ILK_DPFC_FENCE_YOFF, y_offset); | |
7ff0ebcc RV |
230 | I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID); |
231 | /* enable it... */ | |
232 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
233 | ||
7733b49b | 234 | if (IS_GEN6(dev_priv)) { |
7ff0ebcc RV |
235 | I915_WRITE(SNB_DPFC_CTL_SA, |
236 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); | |
2db3366b | 237 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, y_offset); |
7ff0ebcc RV |
238 | } |
239 | ||
d5ce4164 | 240 | intel_fbc_recompress(dev_priv); |
dbef0f15 | 241 | |
0e631adc | 242 | DRM_DEBUG_KMS("activated fbc on plane %c\n", plane_name(crtc->plane)); |
7ff0ebcc RV |
243 | } |
244 | ||
0e631adc | 245 | static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv) |
7ff0ebcc | 246 | { |
7ff0ebcc RV |
247 | u32 dpfc_ctl; |
248 | ||
0e631adc | 249 | dev_priv->fbc.active = false; |
7ff0ebcc RV |
250 | |
251 | /* Disable compression */ | |
252 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
253 | if (dpfc_ctl & DPFC_CTL_EN) { | |
254 | dpfc_ctl &= ~DPFC_CTL_EN; | |
255 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); | |
256 | ||
0e631adc | 257 | DRM_DEBUG_KMS("deactivated FBC\n"); |
7ff0ebcc RV |
258 | } |
259 | } | |
260 | ||
0e631adc | 261 | static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv) |
7ff0ebcc | 262 | { |
7ff0ebcc RV |
263 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; |
264 | } | |
265 | ||
0e631adc | 266 | static void gen7_fbc_activate(struct intel_crtc *crtc) |
7ff0ebcc | 267 | { |
220285f2 PZ |
268 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
269 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
7ff0ebcc | 270 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
7ff0ebcc | 271 | u32 dpfc_ctl; |
ce65e47b | 272 | int threshold = dev_priv->fbc.threshold; |
7ff0ebcc | 273 | |
0e631adc | 274 | dev_priv->fbc.active = true; |
7ff0ebcc | 275 | |
d8514d63 | 276 | dpfc_ctl = 0; |
7733b49b | 277 | if (IS_IVYBRIDGE(dev_priv)) |
220285f2 | 278 | dpfc_ctl |= IVB_DPFC_CTL_PLANE(crtc->plane); |
d8514d63 | 279 | |
7ff0ebcc | 280 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
ce65e47b | 281 | threshold++; |
7ff0ebcc | 282 | |
ce65e47b | 283 | switch (threshold) { |
7ff0ebcc RV |
284 | case 4: |
285 | case 3: | |
286 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; | |
287 | break; | |
288 | case 2: | |
289 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
290 | break; | |
291 | case 1: | |
292 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
293 | break; | |
294 | } | |
295 | ||
296 | dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; | |
297 | ||
298 | if (dev_priv->fbc.false_color) | |
299 | dpfc_ctl |= FBC_CTL_FALSE_COLOR; | |
300 | ||
7733b49b | 301 | if (IS_IVYBRIDGE(dev_priv)) { |
7ff0ebcc RV |
302 | /* WaFbcAsynchFlipDisableFbcQueue:ivb */ |
303 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
304 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
305 | ILK_FBCQ_DIS); | |
40f4022e | 306 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
7ff0ebcc | 307 | /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ |
220285f2 PZ |
308 | I915_WRITE(CHICKEN_PIPESL_1(crtc->pipe), |
309 | I915_READ(CHICKEN_PIPESL_1(crtc->pipe)) | | |
7ff0ebcc RV |
310 | HSW_FBCQ_DIS); |
311 | } | |
312 | ||
57012be9 PZ |
313 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
314 | ||
7ff0ebcc RV |
315 | I915_WRITE(SNB_DPFC_CTL_SA, |
316 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); | |
2db3366b | 317 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, get_crtc_fence_y_offset(crtc)); |
7ff0ebcc | 318 | |
d5ce4164 | 319 | intel_fbc_recompress(dev_priv); |
7ff0ebcc | 320 | |
0e631adc | 321 | DRM_DEBUG_KMS("activated fbc on plane %c\n", plane_name(crtc->plane)); |
7ff0ebcc RV |
322 | } |
323 | ||
94b83957 | 324 | /** |
0e631adc | 325 | * intel_fbc_is_active - Is FBC active? |
7733b49b | 326 | * @dev_priv: i915 device instance |
94b83957 RV |
327 | * |
328 | * This function is used to verify the current state of FBC. | |
329 | * FIXME: This should be tracked in the plane config eventually | |
330 | * instead of queried at runtime for most callers. | |
331 | */ | |
0e631adc | 332 | bool intel_fbc_is_active(struct drm_i915_private *dev_priv) |
7ff0ebcc | 333 | { |
0e631adc | 334 | return dev_priv->fbc.active; |
7ff0ebcc RV |
335 | } |
336 | ||
0e631adc | 337 | static void intel_fbc_activate(const struct drm_framebuffer *fb) |
e8cb8d69 | 338 | { |
e9c5fd26 PZ |
339 | struct drm_i915_private *dev_priv = fb->dev->dev_private; |
340 | struct intel_crtc *crtc = dev_priv->fbc.crtc; | |
e8cb8d69 | 341 | |
0e631adc | 342 | dev_priv->fbc.activate(crtc); |
e8cb8d69 | 343 | |
e8cb8d69 PZ |
344 | dev_priv->fbc.fb_id = fb->base.id; |
345 | dev_priv->fbc.y = crtc->base.y; | |
346 | } | |
347 | ||
7ff0ebcc RV |
348 | static void intel_fbc_work_fn(struct work_struct *__work) |
349 | { | |
350 | struct intel_fbc_work *work = | |
351 | container_of(to_delayed_work(__work), | |
352 | struct intel_fbc_work, work); | |
e9c5fd26 PZ |
353 | struct drm_i915_private *dev_priv = work->fb->dev->dev_private; |
354 | struct drm_framebuffer *crtc_fb = dev_priv->fbc.crtc->base.primary->fb; | |
7ff0ebcc | 355 | |
25ad93fd | 356 | mutex_lock(&dev_priv->fbc.lock); |
7ff0ebcc RV |
357 | if (work == dev_priv->fbc.fbc_work) { |
358 | /* Double check that we haven't switched fb without cancelling | |
359 | * the prior work. | |
360 | */ | |
e8cb8d69 | 361 | if (crtc_fb == work->fb) |
0e631adc | 362 | intel_fbc_activate(work->fb); |
7ff0ebcc RV |
363 | |
364 | dev_priv->fbc.fbc_work = NULL; | |
365 | } | |
25ad93fd | 366 | mutex_unlock(&dev_priv->fbc.lock); |
7ff0ebcc RV |
367 | |
368 | kfree(work); | |
369 | } | |
370 | ||
371 | static void intel_fbc_cancel_work(struct drm_i915_private *dev_priv) | |
372 | { | |
25ad93fd PZ |
373 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
374 | ||
7ff0ebcc RV |
375 | if (dev_priv->fbc.fbc_work == NULL) |
376 | return; | |
377 | ||
7ff0ebcc RV |
378 | /* Synchronisation is provided by struct_mutex and checking of |
379 | * dev_priv->fbc.fbc_work, so we can perform the cancellation | |
380 | * entirely asynchronously. | |
381 | */ | |
382 | if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work)) | |
383 | /* tasklet was killed before being run, clean up */ | |
384 | kfree(dev_priv->fbc.fbc_work); | |
385 | ||
386 | /* Mark the work as no longer wanted so that if it does | |
387 | * wake-up (because the work was already running and waiting | |
388 | * for our mutex), it will discover that is no longer | |
389 | * necessary to run. | |
390 | */ | |
391 | dev_priv->fbc.fbc_work = NULL; | |
392 | } | |
393 | ||
0e631adc | 394 | static void intel_fbc_schedule_activation(struct intel_crtc *crtc) |
7ff0ebcc RV |
395 | { |
396 | struct intel_fbc_work *work; | |
220285f2 | 397 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
7ff0ebcc | 398 | |
25ad93fd PZ |
399 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
400 | ||
7ff0ebcc RV |
401 | intel_fbc_cancel_work(dev_priv); |
402 | ||
403 | work = kzalloc(sizeof(*work), GFP_KERNEL); | |
404 | if (work == NULL) { | |
405 | DRM_ERROR("Failed to allocate FBC work structure\n"); | |
0e631adc | 406 | intel_fbc_activate(crtc->base.primary->fb); |
7ff0ebcc RV |
407 | return; |
408 | } | |
409 | ||
220285f2 | 410 | work->fb = crtc->base.primary->fb; |
7ff0ebcc RV |
411 | INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); |
412 | ||
413 | dev_priv->fbc.fbc_work = work; | |
414 | ||
415 | /* Delay the actual enabling to let pageflipping cease and the | |
416 | * display to settle before starting the compression. Note that | |
417 | * this delay also serves a second purpose: it allows for a | |
418 | * vblank to pass after disabling the FBC before we attempt | |
419 | * to modify the control registers. | |
420 | * | |
421 | * A more complicated solution would involve tracking vblanks | |
422 | * following the termination of the page-flipping sequence | |
423 | * and indeed performing the enable as a co-routine and not | |
424 | * waiting synchronously upon the vblank. | |
425 | * | |
426 | * WaFbcWaitForVBlankBeforeEnable:ilk,snb | |
427 | */ | |
428 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); | |
429 | } | |
430 | ||
d029bcad | 431 | static void __intel_fbc_deactivate(struct drm_i915_private *dev_priv) |
25ad93fd | 432 | { |
25ad93fd PZ |
433 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
434 | ||
435 | intel_fbc_cancel_work(dev_priv); | |
436 | ||
0e631adc PZ |
437 | if (dev_priv->fbc.active) |
438 | dev_priv->fbc.deactivate(dev_priv); | |
754d1133 PZ |
439 | } |
440 | ||
25ad93fd | 441 | /* |
d029bcad | 442 | * intel_fbc_deactivate - deactivate FBC if it's associated with crtc |
25ad93fd PZ |
443 | * @crtc: the CRTC |
444 | * | |
d029bcad | 445 | * This function deactivates FBC if it's associated with the provided CRTC. |
25ad93fd | 446 | */ |
d029bcad | 447 | void intel_fbc_deactivate(struct intel_crtc *crtc) |
25ad93fd | 448 | { |
7733b49b | 449 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
7ff0ebcc | 450 | |
9f218336 | 451 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
452 | return; |
453 | ||
25ad93fd PZ |
454 | mutex_lock(&dev_priv->fbc.lock); |
455 | if (dev_priv->fbc.crtc == crtc) | |
d029bcad | 456 | __intel_fbc_deactivate(dev_priv); |
25ad93fd | 457 | mutex_unlock(&dev_priv->fbc.lock); |
7ff0ebcc RV |
458 | } |
459 | ||
2e8144a5 | 460 | static void set_no_fbc_reason(struct drm_i915_private *dev_priv, |
bf6189c6 | 461 | const char *reason) |
7ff0ebcc RV |
462 | { |
463 | if (dev_priv->fbc.no_fbc_reason == reason) | |
2e8144a5 | 464 | return; |
7ff0ebcc RV |
465 | |
466 | dev_priv->fbc.no_fbc_reason = reason; | |
bf6189c6 | 467 | DRM_DEBUG_KMS("Disabling FBC: %s\n", reason); |
7ff0ebcc RV |
468 | } |
469 | ||
d029bcad | 470 | static bool crtc_can_fbc(struct intel_crtc *crtc) |
30c58d58 PZ |
471 | { |
472 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
473 | ||
474 | if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A) | |
475 | return false; | |
476 | ||
d029bcad PZ |
477 | return true; |
478 | } | |
479 | ||
480 | static bool crtc_is_valid(struct intel_crtc *crtc) | |
481 | { | |
30c58d58 PZ |
482 | if (!intel_crtc_active(&crtc->base)) |
483 | return false; | |
484 | ||
485 | if (!to_intel_plane_state(crtc->base.primary->state)->visible) | |
486 | return false; | |
487 | ||
488 | return true; | |
489 | } | |
490 | ||
232fd934 PZ |
491 | static bool multiple_pipes_ok(struct drm_i915_private *dev_priv) |
492 | { | |
493 | enum pipe pipe; | |
494 | int n_pipes = 0; | |
495 | struct drm_crtc *crtc; | |
496 | ||
497 | if (INTEL_INFO(dev_priv)->gen > 4) | |
498 | return true; | |
499 | ||
500 | for_each_pipe(dev_priv, pipe) { | |
501 | crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
502 | ||
503 | if (intel_crtc_active(crtc) && | |
504 | to_intel_plane_state(crtc->primary->state)->visible) | |
505 | n_pipes++; | |
506 | } | |
507 | ||
508 | return (n_pipes < 2); | |
509 | } | |
510 | ||
7733b49b | 511 | static int find_compression_threshold(struct drm_i915_private *dev_priv, |
fc786728 PZ |
512 | struct drm_mm_node *node, |
513 | int size, | |
514 | int fb_cpp) | |
515 | { | |
fc786728 PZ |
516 | int compression_threshold = 1; |
517 | int ret; | |
a9da512b PZ |
518 | u64 end; |
519 | ||
520 | /* The FBC hardware for BDW/SKL doesn't have access to the stolen | |
521 | * reserved range size, so it always assumes the maximum (8mb) is used. | |
522 | * If we enable FBC using a CFB on that memory range we'll get FIFO | |
523 | * underruns, even if that range is not reserved by the BIOS. */ | |
ef11bdb3 RV |
524 | if (IS_BROADWELL(dev_priv) || |
525 | IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) | |
a9da512b PZ |
526 | end = dev_priv->gtt.stolen_size - 8 * 1024 * 1024; |
527 | else | |
528 | end = dev_priv->gtt.stolen_usable_size; | |
fc786728 PZ |
529 | |
530 | /* HACK: This code depends on what we will do in *_enable_fbc. If that | |
531 | * code changes, this code needs to change as well. | |
532 | * | |
533 | * The enable_fbc code will attempt to use one of our 2 compression | |
534 | * thresholds, therefore, in that case, we only have 1 resort. | |
535 | */ | |
536 | ||
537 | /* Try to over-allocate to reduce reallocations and fragmentation. */ | |
a9da512b PZ |
538 | ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1, |
539 | 4096, 0, end); | |
fc786728 PZ |
540 | if (ret == 0) |
541 | return compression_threshold; | |
542 | ||
543 | again: | |
544 | /* HW's ability to limit the CFB is 1:4 */ | |
545 | if (compression_threshold > 4 || | |
546 | (fb_cpp == 2 && compression_threshold == 2)) | |
547 | return 0; | |
548 | ||
a9da512b PZ |
549 | ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1, |
550 | 4096, 0, end); | |
7733b49b | 551 | if (ret && INTEL_INFO(dev_priv)->gen <= 4) { |
fc786728 PZ |
552 | return 0; |
553 | } else if (ret) { | |
554 | compression_threshold <<= 1; | |
555 | goto again; | |
556 | } else { | |
557 | return compression_threshold; | |
558 | } | |
559 | } | |
560 | ||
7733b49b PZ |
561 | static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv, int size, |
562 | int fb_cpp) | |
fc786728 | 563 | { |
fc786728 PZ |
564 | struct drm_mm_node *uninitialized_var(compressed_llb); |
565 | int ret; | |
566 | ||
7733b49b | 567 | ret = find_compression_threshold(dev_priv, &dev_priv->fbc.compressed_fb, |
fc786728 PZ |
568 | size, fb_cpp); |
569 | if (!ret) | |
570 | goto err_llb; | |
571 | else if (ret > 1) { | |
572 | DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n"); | |
573 | ||
574 | } | |
575 | ||
576 | dev_priv->fbc.threshold = ret; | |
577 | ||
578 | if (INTEL_INFO(dev_priv)->gen >= 5) | |
579 | I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start); | |
7733b49b | 580 | else if (IS_GM45(dev_priv)) { |
fc786728 PZ |
581 | I915_WRITE(DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start); |
582 | } else { | |
583 | compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL); | |
584 | if (!compressed_llb) | |
585 | goto err_fb; | |
586 | ||
587 | ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb, | |
588 | 4096, 4096); | |
589 | if (ret) | |
590 | goto err_fb; | |
591 | ||
592 | dev_priv->fbc.compressed_llb = compressed_llb; | |
593 | ||
594 | I915_WRITE(FBC_CFB_BASE, | |
595 | dev_priv->mm.stolen_base + dev_priv->fbc.compressed_fb.start); | |
596 | I915_WRITE(FBC_LL_BASE, | |
597 | dev_priv->mm.stolen_base + compressed_llb->start); | |
598 | } | |
599 | ||
600 | dev_priv->fbc.uncompressed_size = size; | |
601 | ||
b8bf5d7f PZ |
602 | DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n", |
603 | dev_priv->fbc.compressed_fb.size, | |
604 | dev_priv->fbc.threshold); | |
fc786728 PZ |
605 | |
606 | return 0; | |
607 | ||
608 | err_fb: | |
609 | kfree(compressed_llb); | |
610 | i915_gem_stolen_remove_node(dev_priv, &dev_priv->fbc.compressed_fb); | |
611 | err_llb: | |
612 | pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size); | |
613 | return -ENOSPC; | |
614 | } | |
615 | ||
7733b49b | 616 | static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) |
fc786728 | 617 | { |
fc786728 PZ |
618 | if (dev_priv->fbc.uncompressed_size == 0) |
619 | return; | |
620 | ||
621 | i915_gem_stolen_remove_node(dev_priv, &dev_priv->fbc.compressed_fb); | |
622 | ||
623 | if (dev_priv->fbc.compressed_llb) { | |
624 | i915_gem_stolen_remove_node(dev_priv, | |
625 | dev_priv->fbc.compressed_llb); | |
626 | kfree(dev_priv->fbc.compressed_llb); | |
627 | } | |
628 | ||
629 | dev_priv->fbc.uncompressed_size = 0; | |
630 | } | |
631 | ||
7733b49b | 632 | void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) |
25ad93fd | 633 | { |
9f218336 | 634 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
635 | return; |
636 | ||
25ad93fd | 637 | mutex_lock(&dev_priv->fbc.lock); |
7733b49b | 638 | __intel_fbc_cleanup_cfb(dev_priv); |
25ad93fd PZ |
639 | mutex_unlock(&dev_priv->fbc.lock); |
640 | } | |
641 | ||
c4ffd409 PZ |
642 | /* |
643 | * For SKL+, the plane source size used by the hardware is based on the value we | |
644 | * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value | |
645 | * we wrote to PIPESRC. | |
646 | */ | |
647 | static void intel_fbc_get_plane_source_size(struct intel_crtc *crtc, | |
648 | int *width, int *height) | |
fc786728 | 649 | { |
c4ffd409 PZ |
650 | struct intel_plane_state *plane_state = |
651 | to_intel_plane_state(crtc->base.primary->state); | |
652 | int w, h; | |
653 | ||
654 | if (intel_rotation_90_or_270(plane_state->base.rotation)) { | |
655 | w = drm_rect_height(&plane_state->src) >> 16; | |
656 | h = drm_rect_width(&plane_state->src) >> 16; | |
657 | } else { | |
658 | w = drm_rect_width(&plane_state->src) >> 16; | |
659 | h = drm_rect_height(&plane_state->src) >> 16; | |
660 | } | |
661 | ||
662 | if (width) | |
663 | *width = w; | |
664 | if (height) | |
665 | *height = h; | |
666 | } | |
667 | ||
668 | static int intel_fbc_calculate_cfb_size(struct intel_crtc *crtc) | |
669 | { | |
670 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
671 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
672 | int lines; | |
673 | ||
674 | intel_fbc_get_plane_source_size(crtc, NULL, &lines); | |
675 | if (INTEL_INFO(dev_priv)->gen >= 7) | |
676 | lines = min(lines, 2048); | |
677 | ||
850bfaab | 678 | /* Hardware needs the full buffer stride, not just the active area. */ |
c4ffd409 PZ |
679 | return lines * fb->pitches[0]; |
680 | } | |
681 | ||
682 | static int intel_fbc_setup_cfb(struct intel_crtc *crtc) | |
683 | { | |
684 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
685 | struct drm_framebuffer *fb = crtc->base.primary->fb; | |
686 | int size, cpp; | |
687 | ||
688 | size = intel_fbc_calculate_cfb_size(crtc); | |
689 | cpp = drm_format_plane_cpp(fb->pixel_format, 0); | |
690 | ||
90d5234f PZ |
691 | if (drm_mm_node_allocated(&dev_priv->fbc.compressed_fb) && |
692 | size <= dev_priv->fbc.compressed_fb.size * dev_priv->fbc.threshold) | |
fc786728 PZ |
693 | return 0; |
694 | ||
695 | /* Release any current block */ | |
7733b49b | 696 | __intel_fbc_cleanup_cfb(dev_priv); |
fc786728 | 697 | |
c4ffd409 | 698 | return intel_fbc_alloc_cfb(dev_priv, size, cpp); |
fc786728 PZ |
699 | } |
700 | ||
adf70c65 PZ |
701 | static bool stride_is_valid(struct drm_i915_private *dev_priv, |
702 | unsigned int stride) | |
703 | { | |
704 | /* These should have been caught earlier. */ | |
705 | WARN_ON(stride < 512); | |
706 | WARN_ON((stride & (64 - 1)) != 0); | |
707 | ||
708 | /* Below are the additional FBC restrictions. */ | |
709 | ||
710 | if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv)) | |
711 | return stride == 4096 || stride == 8192; | |
712 | ||
713 | if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048) | |
714 | return false; | |
715 | ||
716 | if (stride > 16384) | |
717 | return false; | |
718 | ||
719 | return true; | |
720 | } | |
721 | ||
b9e831dc PZ |
722 | static bool pixel_format_is_valid(struct drm_framebuffer *fb) |
723 | { | |
724 | struct drm_device *dev = fb->dev; | |
725 | struct drm_i915_private *dev_priv = dev->dev_private; | |
726 | ||
727 | switch (fb->pixel_format) { | |
728 | case DRM_FORMAT_XRGB8888: | |
729 | case DRM_FORMAT_XBGR8888: | |
730 | return true; | |
731 | case DRM_FORMAT_XRGB1555: | |
732 | case DRM_FORMAT_RGB565: | |
733 | /* 16bpp not supported on gen2 */ | |
734 | if (IS_GEN2(dev)) | |
735 | return false; | |
736 | /* WaFbcOnly1to1Ratio:ctg */ | |
737 | if (IS_G4X(dev_priv)) | |
738 | return false; | |
739 | return true; | |
740 | default: | |
741 | return false; | |
742 | } | |
743 | } | |
744 | ||
856312ae PZ |
745 | /* |
746 | * For some reason, the hardware tracking starts looking at whatever we | |
747 | * programmed as the display plane base address register. It does not look at | |
748 | * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y} | |
749 | * variables instead of just looking at the pipe/plane size. | |
750 | */ | |
751 | static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc) | |
3c5f174e PZ |
752 | { |
753 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
856312ae | 754 | unsigned int effective_w, effective_h, max_w, max_h; |
3c5f174e PZ |
755 | |
756 | if (INTEL_INFO(dev_priv)->gen >= 8 || IS_HASWELL(dev_priv)) { | |
757 | max_w = 4096; | |
758 | max_h = 4096; | |
759 | } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { | |
760 | max_w = 4096; | |
761 | max_h = 2048; | |
762 | } else { | |
763 | max_w = 2048; | |
764 | max_h = 1536; | |
765 | } | |
766 | ||
856312ae PZ |
767 | intel_fbc_get_plane_source_size(crtc, &effective_w, &effective_h); |
768 | effective_w += crtc->adjusted_x; | |
769 | effective_h += crtc->adjusted_y; | |
770 | ||
771 | return effective_w <= max_w && effective_h <= max_h; | |
3c5f174e PZ |
772 | } |
773 | ||
7ff0ebcc | 774 | /** |
d029bcad | 775 | * __intel_fbc_update - activate/deactivate FBC as needed, unlocked |
754d1133 | 776 | * @crtc: the CRTC that triggered the update |
7ff0ebcc | 777 | * |
d029bcad PZ |
778 | * This function completely reevaluates the status of FBC, then activates, |
779 | * deactivates or maintains it on the same state. | |
7ff0ebcc | 780 | */ |
754d1133 | 781 | static void __intel_fbc_update(struct intel_crtc *crtc) |
7ff0ebcc | 782 | { |
754d1133 | 783 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
7ff0ebcc RV |
784 | struct drm_framebuffer *fb; |
785 | struct drm_i915_gem_object *obj; | |
786 | const struct drm_display_mode *adjusted_mode; | |
7ff0ebcc | 787 | |
25ad93fd PZ |
788 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); |
789 | ||
754d1133 PZ |
790 | if (!multiple_pipes_ok(dev_priv)) { |
791 | set_no_fbc_reason(dev_priv, "more than one pipe active"); | |
792 | goto out_disable; | |
793 | } | |
794 | ||
d029bcad | 795 | if (!dev_priv->fbc.enabled || dev_priv->fbc.crtc != crtc) |
754d1133 PZ |
796 | return; |
797 | ||
754d1133 | 798 | if (!crtc_is_valid(crtc)) { |
bf6189c6 | 799 | set_no_fbc_reason(dev_priv, "no output"); |
7ff0ebcc | 800 | goto out_disable; |
8df5dd57 | 801 | } |
7ff0ebcc | 802 | |
45b32a29 | 803 | fb = crtc->base.primary->fb; |
7ff0ebcc | 804 | obj = intel_fb_obj(fb); |
45b32a29 | 805 | adjusted_mode = &crtc->config->base.adjusted_mode; |
7ff0ebcc | 806 | |
7ff0ebcc RV |
807 | if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) || |
808 | (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) { | |
bf6189c6 | 809 | set_no_fbc_reason(dev_priv, "incompatible mode"); |
7ff0ebcc RV |
810 | goto out_disable; |
811 | } | |
812 | ||
45b32a29 | 813 | if (!intel_fbc_hw_tracking_covers_screen(crtc)) { |
bf6189c6 | 814 | set_no_fbc_reason(dev_priv, "mode too large for compression"); |
7ff0ebcc RV |
815 | goto out_disable; |
816 | } | |
3c5f174e | 817 | |
7733b49b | 818 | if ((INTEL_INFO(dev_priv)->gen < 4 || HAS_DDI(dev_priv)) && |
45b32a29 | 819 | crtc->plane != PLANE_A) { |
bf6189c6 | 820 | set_no_fbc_reason(dev_priv, "FBC unsupported on plane"); |
7ff0ebcc RV |
821 | goto out_disable; |
822 | } | |
823 | ||
824 | /* The use of a CPU fence is mandatory in order to detect writes | |
825 | * by the CPU to the scanout and trigger updates to the FBC. | |
826 | */ | |
827 | if (obj->tiling_mode != I915_TILING_X || | |
828 | obj->fence_reg == I915_FENCE_REG_NONE) { | |
bf6189c6 | 829 | set_no_fbc_reason(dev_priv, "framebuffer not tiled or fenced"); |
7ff0ebcc RV |
830 | goto out_disable; |
831 | } | |
7733b49b | 832 | if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) && |
45b32a29 | 833 | crtc->base.primary->state->rotation != BIT(DRM_ROTATE_0)) { |
bf6189c6 | 834 | set_no_fbc_reason(dev_priv, "rotation unsupported"); |
7ff0ebcc RV |
835 | goto out_disable; |
836 | } | |
837 | ||
adf70c65 | 838 | if (!stride_is_valid(dev_priv, fb->pitches[0])) { |
bf6189c6 | 839 | set_no_fbc_reason(dev_priv, "framebuffer stride not supported"); |
adf70c65 PZ |
840 | goto out_disable; |
841 | } | |
842 | ||
b9e831dc | 843 | if (!pixel_format_is_valid(fb)) { |
bf6189c6 | 844 | set_no_fbc_reason(dev_priv, "pixel format is invalid"); |
b9e831dc PZ |
845 | goto out_disable; |
846 | } | |
847 | ||
7b24c9a6 PZ |
848 | /* WaFbcExceedCdClockThreshold:hsw,bdw */ |
849 | if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) && | |
45b32a29 | 850 | ilk_pipe_pixel_rate(crtc->config) >= |
7b24c9a6 | 851 | dev_priv->cdclk_freq * 95 / 100) { |
bf6189c6 | 852 | set_no_fbc_reason(dev_priv, "pixel rate is too big"); |
7b24c9a6 PZ |
853 | goto out_disable; |
854 | } | |
855 | ||
45b32a29 | 856 | if (intel_fbc_setup_cfb(crtc)) { |
bf6189c6 | 857 | set_no_fbc_reason(dev_priv, "not enough stolen memory"); |
7ff0ebcc RV |
858 | goto out_disable; |
859 | } | |
860 | ||
861 | /* If the scanout has not changed, don't modify the FBC settings. | |
862 | * Note that we make the fundamental assumption that the fb->obj | |
863 | * cannot be unpinned (and have its GTT offset and fence revoked) | |
864 | * without first being decoupled from the scanout and FBC disabled. | |
865 | */ | |
45b32a29 | 866 | if (dev_priv->fbc.crtc == crtc && |
7ff0ebcc | 867 | dev_priv->fbc.fb_id == fb->base.id && |
754d1133 | 868 | dev_priv->fbc.y == crtc->base.y && |
0e631adc | 869 | dev_priv->fbc.active) |
7ff0ebcc RV |
870 | return; |
871 | ||
0e631adc | 872 | if (intel_fbc_is_active(dev_priv)) { |
7ff0ebcc RV |
873 | /* We update FBC along two paths, after changing fb/crtc |
874 | * configuration (modeswitching) and after page-flipping | |
875 | * finishes. For the latter, we know that not only did | |
876 | * we disable the FBC at the start of the page-flip | |
877 | * sequence, but also more than one vblank has passed. | |
878 | * | |
879 | * For the former case of modeswitching, it is possible | |
880 | * to switch between two FBC valid configurations | |
881 | * instantaneously so we do need to disable the FBC | |
882 | * before we can modify its control registers. We also | |
883 | * have to wait for the next vblank for that to take | |
884 | * effect. However, since we delay enabling FBC we can | |
885 | * assume that a vblank has passed since disabling and | |
886 | * that we can safely alter the registers in the deferred | |
887 | * callback. | |
888 | * | |
889 | * In the scenario that we go from a valid to invalid | |
890 | * and then back to valid FBC configuration we have | |
891 | * no strict enforcement that a vblank occurred since | |
892 | * disabling the FBC. However, along all current pipe | |
893 | * disabling paths we do need to wait for a vblank at | |
894 | * some point. And we wait before enabling FBC anyway. | |
895 | */ | |
d029bcad PZ |
896 | DRM_DEBUG_KMS("deactivating FBC for update\n"); |
897 | __intel_fbc_deactivate(dev_priv); | |
7ff0ebcc RV |
898 | } |
899 | ||
0e631adc | 900 | intel_fbc_schedule_activation(crtc); |
793af070 | 901 | dev_priv->fbc.no_fbc_reason = "FBC enabled (not necessarily active)"; |
7ff0ebcc RV |
902 | return; |
903 | ||
904 | out_disable: | |
905 | /* Multiple disables should be harmless */ | |
0e631adc | 906 | if (intel_fbc_is_active(dev_priv)) { |
d029bcad PZ |
907 | DRM_DEBUG_KMS("unsupported config, deactivating FBC\n"); |
908 | __intel_fbc_deactivate(dev_priv); | |
7ff0ebcc | 909 | } |
7733b49b | 910 | __intel_fbc_cleanup_cfb(dev_priv); |
25ad93fd PZ |
911 | } |
912 | ||
913 | /* | |
d029bcad | 914 | * intel_fbc_update - activate/deactivate FBC as needed |
754d1133 | 915 | * @crtc: the CRTC that triggered the update |
25ad93fd | 916 | * |
d029bcad | 917 | * This function reevaluates the overall state and activates or deactivates FBC. |
25ad93fd | 918 | */ |
754d1133 | 919 | void intel_fbc_update(struct intel_crtc *crtc) |
25ad93fd | 920 | { |
754d1133 PZ |
921 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
922 | ||
9f218336 | 923 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
924 | return; |
925 | ||
25ad93fd | 926 | mutex_lock(&dev_priv->fbc.lock); |
754d1133 | 927 | __intel_fbc_update(crtc); |
25ad93fd | 928 | mutex_unlock(&dev_priv->fbc.lock); |
7ff0ebcc RV |
929 | } |
930 | ||
dbef0f15 PZ |
931 | void intel_fbc_invalidate(struct drm_i915_private *dev_priv, |
932 | unsigned int frontbuffer_bits, | |
933 | enum fb_op_origin origin) | |
934 | { | |
dbef0f15 PZ |
935 | unsigned int fbc_bits; |
936 | ||
9f218336 | 937 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
938 | return; |
939 | ||
dbef0f15 PZ |
940 | if (origin == ORIGIN_GTT) |
941 | return; | |
942 | ||
25ad93fd PZ |
943 | mutex_lock(&dev_priv->fbc.lock); |
944 | ||
d029bcad | 945 | if (dev_priv->fbc.enabled) |
dbef0f15 | 946 | fbc_bits = INTEL_FRONTBUFFER_PRIMARY(dev_priv->fbc.crtc->pipe); |
dbef0f15 PZ |
947 | else |
948 | fbc_bits = dev_priv->fbc.possible_framebuffer_bits; | |
949 | ||
950 | dev_priv->fbc.busy_bits |= (fbc_bits & frontbuffer_bits); | |
951 | ||
952 | if (dev_priv->fbc.busy_bits) | |
d029bcad | 953 | __intel_fbc_deactivate(dev_priv); |
25ad93fd PZ |
954 | |
955 | mutex_unlock(&dev_priv->fbc.lock); | |
dbef0f15 PZ |
956 | } |
957 | ||
958 | void intel_fbc_flush(struct drm_i915_private *dev_priv, | |
6f4551fe | 959 | unsigned int frontbuffer_bits, enum fb_op_origin origin) |
dbef0f15 | 960 | { |
9f218336 | 961 | if (!fbc_supported(dev_priv)) |
0bf73c36 PZ |
962 | return; |
963 | ||
6f4551fe PZ |
964 | if (origin == ORIGIN_GTT) |
965 | return; | |
25ad93fd | 966 | |
6f4551fe | 967 | mutex_lock(&dev_priv->fbc.lock); |
dbef0f15 PZ |
968 | |
969 | dev_priv->fbc.busy_bits &= ~frontbuffer_bits; | |
970 | ||
d029bcad PZ |
971 | if (!dev_priv->fbc.busy_bits && dev_priv->fbc.enabled) { |
972 | __intel_fbc_deactivate(dev_priv); | |
754d1133 | 973 | __intel_fbc_update(dev_priv->fbc.crtc); |
6f4551fe | 974 | } |
25ad93fd | 975 | |
25ad93fd | 976 | mutex_unlock(&dev_priv->fbc.lock); |
dbef0f15 PZ |
977 | } |
978 | ||
d029bcad PZ |
979 | /** |
980 | * intel_fbc_enable: tries to enable FBC on the CRTC | |
981 | * @crtc: the CRTC | |
982 | * | |
983 | * This function checks if it's possible to enable FBC on the following CRTC, | |
984 | * then enables it. Notice that it doesn't activate FBC. | |
985 | */ | |
986 | void intel_fbc_enable(struct intel_crtc *crtc) | |
987 | { | |
988 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
989 | ||
990 | if (!fbc_supported(dev_priv)) | |
991 | return; | |
992 | ||
993 | mutex_lock(&dev_priv->fbc.lock); | |
994 | ||
995 | if (dev_priv->fbc.enabled) { | |
996 | WARN_ON(dev_priv->fbc.crtc == crtc); | |
997 | goto out; | |
998 | } | |
999 | ||
1000 | WARN_ON(dev_priv->fbc.active); | |
1001 | WARN_ON(dev_priv->fbc.crtc != NULL); | |
1002 | ||
1003 | if (intel_vgpu_active(dev_priv->dev)) { | |
1004 | set_no_fbc_reason(dev_priv, "VGPU is active"); | |
1005 | goto out; | |
1006 | } | |
1007 | ||
1008 | if (i915.enable_fbc < 0) { | |
1009 | set_no_fbc_reason(dev_priv, "disabled per chip default"); | |
1010 | goto out; | |
1011 | } | |
1012 | ||
1013 | if (!i915.enable_fbc) { | |
1014 | set_no_fbc_reason(dev_priv, "disabled per module param"); | |
1015 | goto out; | |
1016 | } | |
1017 | ||
1018 | if (!crtc_can_fbc(crtc)) { | |
1019 | set_no_fbc_reason(dev_priv, "no enabled pipes can have FBC"); | |
1020 | goto out; | |
1021 | } | |
1022 | ||
1023 | DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc->pipe)); | |
1024 | dev_priv->fbc.no_fbc_reason = "FBC enabled but not active yet\n"; | |
1025 | ||
1026 | dev_priv->fbc.enabled = true; | |
1027 | dev_priv->fbc.crtc = crtc; | |
1028 | out: | |
1029 | mutex_unlock(&dev_priv->fbc.lock); | |
1030 | } | |
1031 | ||
1032 | /** | |
1033 | * __intel_fbc_disable - disable FBC | |
1034 | * @dev_priv: i915 device instance | |
1035 | * | |
1036 | * This is the low level function that actually disables FBC. Callers should | |
1037 | * grab the FBC lock. | |
1038 | */ | |
1039 | static void __intel_fbc_disable(struct drm_i915_private *dev_priv) | |
1040 | { | |
1041 | struct intel_crtc *crtc = dev_priv->fbc.crtc; | |
1042 | ||
1043 | WARN_ON(!mutex_is_locked(&dev_priv->fbc.lock)); | |
1044 | WARN_ON(!dev_priv->fbc.enabled); | |
1045 | WARN_ON(dev_priv->fbc.active); | |
1046 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1047 | ||
1048 | DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc->pipe)); | |
1049 | ||
1050 | dev_priv->fbc.enabled = false; | |
1051 | dev_priv->fbc.crtc = NULL; | |
1052 | } | |
1053 | ||
1054 | /** | |
1055 | * intel_fbc_disable_crtc - disable FBC if it's associated with crtc | |
1056 | * @crtc: the CRTC | |
1057 | * | |
1058 | * This function disables FBC if it's associated with the provided CRTC. | |
1059 | */ | |
1060 | void intel_fbc_disable_crtc(struct intel_crtc *crtc) | |
1061 | { | |
1062 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1063 | ||
1064 | if (!fbc_supported(dev_priv)) | |
1065 | return; | |
1066 | ||
1067 | mutex_lock(&dev_priv->fbc.lock); | |
1068 | if (dev_priv->fbc.crtc == crtc) { | |
1069 | WARN_ON(!dev_priv->fbc.enabled); | |
1070 | WARN_ON(dev_priv->fbc.active); | |
1071 | __intel_fbc_disable(dev_priv); | |
1072 | } | |
1073 | mutex_unlock(&dev_priv->fbc.lock); | |
1074 | } | |
1075 | ||
1076 | /** | |
1077 | * intel_fbc_disable - globally disable FBC | |
1078 | * @dev_priv: i915 device instance | |
1079 | * | |
1080 | * This function disables FBC regardless of which CRTC is associated with it. | |
1081 | */ | |
1082 | void intel_fbc_disable(struct drm_i915_private *dev_priv) | |
1083 | { | |
1084 | if (!fbc_supported(dev_priv)) | |
1085 | return; | |
1086 | ||
1087 | mutex_lock(&dev_priv->fbc.lock); | |
1088 | if (dev_priv->fbc.enabled) | |
1089 | __intel_fbc_disable(dev_priv); | |
1090 | mutex_unlock(&dev_priv->fbc.lock); | |
1091 | } | |
1092 | ||
94b83957 RV |
1093 | /** |
1094 | * intel_fbc_init - Initialize FBC | |
1095 | * @dev_priv: the i915 device | |
1096 | * | |
1097 | * This function might be called during PM init process. | |
1098 | */ | |
7ff0ebcc RV |
1099 | void intel_fbc_init(struct drm_i915_private *dev_priv) |
1100 | { | |
dbef0f15 PZ |
1101 | enum pipe pipe; |
1102 | ||
25ad93fd | 1103 | mutex_init(&dev_priv->fbc.lock); |
d029bcad | 1104 | dev_priv->fbc.enabled = false; |
0e631adc | 1105 | dev_priv->fbc.active = false; |
25ad93fd | 1106 | |
7ff0ebcc | 1107 | if (!HAS_FBC(dev_priv)) { |
bf6189c6 | 1108 | dev_priv->fbc.no_fbc_reason = "unsupported by this chipset"; |
7ff0ebcc RV |
1109 | return; |
1110 | } | |
1111 | ||
dbef0f15 PZ |
1112 | for_each_pipe(dev_priv, pipe) { |
1113 | dev_priv->fbc.possible_framebuffer_bits |= | |
1114 | INTEL_FRONTBUFFER_PRIMARY(pipe); | |
1115 | ||
57105022 | 1116 | if (fbc_on_pipe_a_only(dev_priv)) |
dbef0f15 PZ |
1117 | break; |
1118 | } | |
1119 | ||
7ff0ebcc | 1120 | if (INTEL_INFO(dev_priv)->gen >= 7) { |
0e631adc PZ |
1121 | dev_priv->fbc.is_active = ilk_fbc_is_active; |
1122 | dev_priv->fbc.activate = gen7_fbc_activate; | |
1123 | dev_priv->fbc.deactivate = ilk_fbc_deactivate; | |
7ff0ebcc | 1124 | } else if (INTEL_INFO(dev_priv)->gen >= 5) { |
0e631adc PZ |
1125 | dev_priv->fbc.is_active = ilk_fbc_is_active; |
1126 | dev_priv->fbc.activate = ilk_fbc_activate; | |
1127 | dev_priv->fbc.deactivate = ilk_fbc_deactivate; | |
7ff0ebcc | 1128 | } else if (IS_GM45(dev_priv)) { |
0e631adc PZ |
1129 | dev_priv->fbc.is_active = g4x_fbc_is_active; |
1130 | dev_priv->fbc.activate = g4x_fbc_activate; | |
1131 | dev_priv->fbc.deactivate = g4x_fbc_deactivate; | |
7ff0ebcc | 1132 | } else { |
0e631adc PZ |
1133 | dev_priv->fbc.is_active = i8xx_fbc_is_active; |
1134 | dev_priv->fbc.activate = i8xx_fbc_activate; | |
1135 | dev_priv->fbc.deactivate = i8xx_fbc_deactivate; | |
7ff0ebcc RV |
1136 | |
1137 | /* This value was pulled out of someone's hat */ | |
1138 | I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT); | |
1139 | } | |
1140 | ||
b07ea0fa | 1141 | /* We still don't have any sort of hardware state readout for FBC, so |
0e631adc PZ |
1142 | * deactivate it in case the BIOS activated it to make sure software |
1143 | * matches the hardware state. */ | |
1144 | if (dev_priv->fbc.is_active(dev_priv)) | |
1145 | dev_priv->fbc.deactivate(dev_priv); | |
7ff0ebcc | 1146 | } |